1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 39 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 40 #define RTW89_HTC_VARIANT_HE 3 41 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 42 #define RTW89_HTC_VARIANT_HE_CID_OM 1 43 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 44 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 45 46 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 47 enum htc_om_channel_width { 48 HTC_OM_CHANNEL_WIDTH_20 = 0, 49 HTC_OM_CHANNEL_WIDTH_40 = 1, 50 HTC_OM_CHANNEL_WIDTH_80 = 2, 51 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 52 }; 53 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 54 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 55 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 56 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 57 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 58 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 59 60 #define RTW89_TF_PAD GENMASK(11, 0) 61 #define RTW89_TF_BASIC_USER_INFO_SZ 6 62 63 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 64 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 65 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 66 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 67 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 68 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 69 70 enum rtw89_subband { 71 RTW89_CH_2G = 0, 72 RTW89_CH_5G_BAND_1 = 1, 73 /* RTW89_CH_5G_BAND_2 = 2, unused */ 74 RTW89_CH_5G_BAND_3 = 3, 75 RTW89_CH_5G_BAND_4 = 4, 76 77 RTW89_CH_6G_BAND_IDX0, /* Low */ 78 RTW89_CH_6G_BAND_IDX1, /* Low */ 79 RTW89_CH_6G_BAND_IDX2, /* Mid */ 80 RTW89_CH_6G_BAND_IDX3, /* Mid */ 81 RTW89_CH_6G_BAND_IDX4, /* High */ 82 RTW89_CH_6G_BAND_IDX5, /* High */ 83 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 84 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 85 86 RTW89_SUBBAND_NR, 87 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 88 }; 89 90 enum rtw89_gain_offset { 91 RTW89_GAIN_OFFSET_2G_CCK, 92 RTW89_GAIN_OFFSET_2G_OFDM, 93 RTW89_GAIN_OFFSET_5G_LOW, 94 RTW89_GAIN_OFFSET_5G_MID, 95 RTW89_GAIN_OFFSET_5G_HIGH, 96 97 RTW89_GAIN_OFFSET_NR, 98 }; 99 100 enum rtw89_hci_type { 101 RTW89_HCI_TYPE_PCIE, 102 RTW89_HCI_TYPE_USB, 103 RTW89_HCI_TYPE_SDIO, 104 }; 105 106 enum rtw89_core_chip_id { 107 RTL8852A, 108 RTL8852B, 109 RTL8852C, 110 }; 111 112 enum rtw89_cv { 113 CHIP_CAV, 114 CHIP_CBV, 115 CHIP_CCV, 116 CHIP_CDV, 117 CHIP_CEV, 118 CHIP_CFV, 119 CHIP_CV_MAX, 120 CHIP_CV_INVALID = CHIP_CV_MAX, 121 }; 122 123 enum rtw89_core_tx_type { 124 RTW89_CORE_TX_TYPE_DATA, 125 RTW89_CORE_TX_TYPE_MGMT, 126 RTW89_CORE_TX_TYPE_FWCMD, 127 }; 128 129 enum rtw89_core_rx_type { 130 RTW89_CORE_RX_TYPE_WIFI = 0, 131 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 132 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 133 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 134 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 135 RTW89_CORE_RX_TYPE_SS2FW = 5, 136 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 137 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 138 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 139 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 140 RTW89_CORE_RX_TYPE_C2H = 10, 141 RTW89_CORE_RX_TYPE_CSI = 11, 142 RTW89_CORE_RX_TYPE_CQI = 12, 143 RTW89_CORE_RX_TYPE_H2C = 13, 144 RTW89_CORE_RX_TYPE_FWDL = 14, 145 }; 146 147 enum rtw89_txq_flags { 148 RTW89_TXQ_F_AMPDU = 0, 149 RTW89_TXQ_F_BLOCK_BA = 1, 150 RTW89_TXQ_F_FORBID_BA = 2, 151 }; 152 153 enum rtw89_net_type { 154 RTW89_NET_TYPE_NO_LINK = 0, 155 RTW89_NET_TYPE_AD_HOC = 1, 156 RTW89_NET_TYPE_INFRA = 2, 157 RTW89_NET_TYPE_AP_MODE = 3, 158 }; 159 160 enum rtw89_wifi_role { 161 RTW89_WIFI_ROLE_NONE, 162 RTW89_WIFI_ROLE_STATION, 163 RTW89_WIFI_ROLE_AP, 164 RTW89_WIFI_ROLE_AP_VLAN, 165 RTW89_WIFI_ROLE_ADHOC, 166 RTW89_WIFI_ROLE_ADHOC_MASTER, 167 RTW89_WIFI_ROLE_MESH_POINT, 168 RTW89_WIFI_ROLE_MONITOR, 169 RTW89_WIFI_ROLE_P2P_DEVICE, 170 RTW89_WIFI_ROLE_P2P_CLIENT, 171 RTW89_WIFI_ROLE_P2P_GO, 172 RTW89_WIFI_ROLE_NAN, 173 RTW89_WIFI_ROLE_MLME_MAX 174 }; 175 176 enum rtw89_upd_mode { 177 RTW89_ROLE_CREATE, 178 RTW89_ROLE_REMOVE, 179 RTW89_ROLE_TYPE_CHANGE, 180 RTW89_ROLE_INFO_CHANGE, 181 RTW89_ROLE_CON_DISCONN, 182 RTW89_ROLE_BAND_SW, 183 RTW89_ROLE_FW_RESTORE, 184 }; 185 186 enum rtw89_self_role { 187 RTW89_SELF_ROLE_CLIENT, 188 RTW89_SELF_ROLE_AP, 189 RTW89_SELF_ROLE_AP_CLIENT 190 }; 191 192 enum rtw89_msk_sO_el { 193 RTW89_NO_MSK, 194 RTW89_SMA, 195 RTW89_TMA, 196 RTW89_BSSID 197 }; 198 199 enum rtw89_sch_tx_sel { 200 RTW89_SCH_TX_SEL_ALL, 201 RTW89_SCH_TX_SEL_HIQ, 202 RTW89_SCH_TX_SEL_MG0, 203 RTW89_SCH_TX_SEL_MACID, 204 }; 205 206 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 207 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 208 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 209 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 210 */ 211 enum rtw89_add_cam_sec_mode { 212 RTW89_ADDR_CAM_SEC_NONE = 0, 213 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 214 RTW89_ADDR_CAM_SEC_NORMAL = 2, 215 RTW89_ADDR_CAM_SEC_4GROUP = 3, 216 }; 217 218 enum rtw89_sec_key_type { 219 RTW89_SEC_KEY_TYPE_NONE = 0, 220 RTW89_SEC_KEY_TYPE_WEP40 = 1, 221 RTW89_SEC_KEY_TYPE_WEP104 = 2, 222 RTW89_SEC_KEY_TYPE_TKIP = 3, 223 RTW89_SEC_KEY_TYPE_WAPI = 4, 224 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 225 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 226 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 227 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 228 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 229 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 230 }; 231 232 enum rtw89_port { 233 RTW89_PORT_0 = 0, 234 RTW89_PORT_1 = 1, 235 RTW89_PORT_2 = 2, 236 RTW89_PORT_3 = 3, 237 RTW89_PORT_4 = 4, 238 RTW89_PORT_NUM 239 }; 240 241 enum rtw89_band { 242 RTW89_BAND_2G = 0, 243 RTW89_BAND_5G = 1, 244 RTW89_BAND_6G = 2, 245 RTW89_BAND_MAX, 246 }; 247 248 enum rtw89_hw_rate { 249 RTW89_HW_RATE_CCK1 = 0x0, 250 RTW89_HW_RATE_CCK2 = 0x1, 251 RTW89_HW_RATE_CCK5_5 = 0x2, 252 RTW89_HW_RATE_CCK11 = 0x3, 253 RTW89_HW_RATE_OFDM6 = 0x4, 254 RTW89_HW_RATE_OFDM9 = 0x5, 255 RTW89_HW_RATE_OFDM12 = 0x6, 256 RTW89_HW_RATE_OFDM18 = 0x7, 257 RTW89_HW_RATE_OFDM24 = 0x8, 258 RTW89_HW_RATE_OFDM36 = 0x9, 259 RTW89_HW_RATE_OFDM48 = 0xA, 260 RTW89_HW_RATE_OFDM54 = 0xB, 261 RTW89_HW_RATE_MCS0 = 0x80, 262 RTW89_HW_RATE_MCS1 = 0x81, 263 RTW89_HW_RATE_MCS2 = 0x82, 264 RTW89_HW_RATE_MCS3 = 0x83, 265 RTW89_HW_RATE_MCS4 = 0x84, 266 RTW89_HW_RATE_MCS5 = 0x85, 267 RTW89_HW_RATE_MCS6 = 0x86, 268 RTW89_HW_RATE_MCS7 = 0x87, 269 RTW89_HW_RATE_MCS8 = 0x88, 270 RTW89_HW_RATE_MCS9 = 0x89, 271 RTW89_HW_RATE_MCS10 = 0x8A, 272 RTW89_HW_RATE_MCS11 = 0x8B, 273 RTW89_HW_RATE_MCS12 = 0x8C, 274 RTW89_HW_RATE_MCS13 = 0x8D, 275 RTW89_HW_RATE_MCS14 = 0x8E, 276 RTW89_HW_RATE_MCS15 = 0x8F, 277 RTW89_HW_RATE_MCS16 = 0x90, 278 RTW89_HW_RATE_MCS17 = 0x91, 279 RTW89_HW_RATE_MCS18 = 0x92, 280 RTW89_HW_RATE_MCS19 = 0x93, 281 RTW89_HW_RATE_MCS20 = 0x94, 282 RTW89_HW_RATE_MCS21 = 0x95, 283 RTW89_HW_RATE_MCS22 = 0x96, 284 RTW89_HW_RATE_MCS23 = 0x97, 285 RTW89_HW_RATE_MCS24 = 0x98, 286 RTW89_HW_RATE_MCS25 = 0x99, 287 RTW89_HW_RATE_MCS26 = 0x9A, 288 RTW89_HW_RATE_MCS27 = 0x9B, 289 RTW89_HW_RATE_MCS28 = 0x9C, 290 RTW89_HW_RATE_MCS29 = 0x9D, 291 RTW89_HW_RATE_MCS30 = 0x9E, 292 RTW89_HW_RATE_MCS31 = 0x9F, 293 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 294 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 295 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 296 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 297 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 298 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 299 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 300 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 301 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 302 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 303 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 304 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 305 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 306 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 307 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 308 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 309 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 310 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 311 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 312 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 313 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 314 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 315 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 316 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 317 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 318 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 319 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 320 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 321 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 322 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 323 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 324 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 325 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 326 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 327 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 328 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 329 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 330 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 331 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 332 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 333 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 334 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 335 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 336 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 337 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 338 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 339 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 340 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 341 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 342 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 343 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 344 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 345 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 346 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 347 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 348 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 349 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 350 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 351 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 352 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 353 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 354 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 355 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 356 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 357 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 358 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 359 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 360 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 361 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 362 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 363 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 364 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 365 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 366 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 367 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 368 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 369 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 370 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 371 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 372 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 373 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 374 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 375 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 376 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 377 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 378 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 379 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 380 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 381 RTW89_HW_RATE_NR, 382 383 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 384 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 385 }; 386 387 /* 2G channels, 388 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 389 */ 390 #define RTW89_2G_CH_NUM 14 391 392 /* 5G channels, 393 * 36, 38, 40, 42, 44, 46, 48, 50, 394 * 52, 54, 56, 58, 60, 62, 64, 395 * 100, 102, 104, 106, 108, 110, 112, 114, 396 * 116, 118, 120, 122, 124, 126, 128, 130, 397 * 132, 134, 136, 138, 140, 142, 144, 398 * 149, 151, 153, 155, 157, 159, 161, 163, 399 * 165, 167, 169, 171, 173, 175, 177 400 */ 401 #define RTW89_5G_CH_NUM 53 402 403 /* 6G channels, 404 * 1, 3, 5, 7, 9, 11, 13, 15, 405 * 17, 19, 21, 23, 25, 27, 29, 33, 406 * 35, 37, 39, 41, 43, 45, 47, 49, 407 * 51, 53, 55, 57, 59, 61, 65, 67, 408 * 69, 71, 73, 75, 77, 79, 81, 83, 409 * 85, 87, 89, 91, 93, 97, 99, 101, 410 * 103, 105, 107, 109, 111, 113, 115, 117, 411 * 119, 121, 123, 125, 129, 131, 133, 135, 412 * 137, 139, 141, 143, 145, 147, 149, 151, 413 * 153, 155, 157, 161, 163, 165, 167, 169, 414 * 171, 173, 175, 177, 179, 181, 183, 185, 415 * 187, 189, 193, 195, 197, 199, 201, 203, 416 * 205, 207, 209, 211, 213, 215, 217, 219, 417 * 221, 225, 227, 229, 231, 233, 235, 237, 418 * 239, 241, 243, 245, 247, 249, 251, 253, 419 */ 420 #define RTW89_6G_CH_NUM 120 421 422 enum rtw89_rate_section { 423 RTW89_RS_CCK, 424 RTW89_RS_OFDM, 425 RTW89_RS_MCS, /* for HT/VHT/HE */ 426 RTW89_RS_HEDCM, 427 RTW89_RS_OFFSET, 428 RTW89_RS_MAX, 429 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 430 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 431 }; 432 433 enum rtw89_rate_max { 434 RTW89_RATE_CCK_MAX = 4, 435 RTW89_RATE_OFDM_MAX = 8, 436 RTW89_RATE_MCS_MAX = 12, 437 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 438 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 439 }; 440 441 enum rtw89_nss { 442 RTW89_NSS_1 = 0, 443 RTW89_NSS_2 = 1, 444 /* HE DCM only support 1ss and 2ss */ 445 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 446 RTW89_NSS_3 = 2, 447 RTW89_NSS_4 = 3, 448 RTW89_NSS_MAX, 449 }; 450 451 enum rtw89_ntx { 452 RTW89_1TX = 0, 453 RTW89_2TX = 1, 454 RTW89_NTX_NUM, 455 }; 456 457 enum rtw89_beamforming_type { 458 RTW89_NONBF = 0, 459 RTW89_BF = 1, 460 RTW89_BF_NUM, 461 }; 462 463 enum rtw89_regulation_type { 464 RTW89_WW = 0, 465 RTW89_ETSI = 1, 466 RTW89_FCC = 2, 467 RTW89_MKK = 3, 468 RTW89_NA = 4, 469 RTW89_IC = 5, 470 RTW89_KCC = 6, 471 RTW89_ACMA = 7, 472 RTW89_NCC = 8, 473 RTW89_MEXICO = 9, 474 RTW89_CHILE = 10, 475 RTW89_UKRAINE = 11, 476 RTW89_CN = 12, 477 RTW89_QATAR = 13, 478 RTW89_UK = 14, 479 RTW89_REGD_NUM, 480 }; 481 482 enum rtw89_fw_pkt_ofld_type { 483 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 484 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 485 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 486 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 487 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 488 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 489 RTW89_PKT_OFLD_TYPE_NDP = 6, 490 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 491 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 492 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 493 RTW89_PKT_OFLD_TYPE_NUM, 494 }; 495 496 struct rtw89_txpwr_byrate { 497 s8 cck[RTW89_RATE_CCK_MAX]; 498 s8 ofdm[RTW89_RATE_OFDM_MAX]; 499 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 500 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 501 s8 offset[RTW89_RATE_OFFSET_MAX]; 502 }; 503 504 enum rtw89_bandwidth_section_num { 505 RTW89_BW20_SEC_NUM = 8, 506 RTW89_BW40_SEC_NUM = 4, 507 RTW89_BW80_SEC_NUM = 2, 508 }; 509 510 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 511 512 struct rtw89_txpwr_limit { 513 s8 cck_20m[RTW89_BF_NUM]; 514 s8 cck_40m[RTW89_BF_NUM]; 515 s8 ofdm[RTW89_BF_NUM]; 516 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 517 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 518 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 519 s8 mcs_160m[RTW89_BF_NUM]; 520 s8 mcs_40m_0p5[RTW89_BF_NUM]; 521 s8 mcs_40m_2p5[RTW89_BF_NUM]; 522 }; 523 524 #define RTW89_RU_SEC_NUM 8 525 526 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 527 528 struct rtw89_txpwr_limit_ru { 529 s8 ru26[RTW89_RU_SEC_NUM]; 530 s8 ru52[RTW89_RU_SEC_NUM]; 531 s8 ru106[RTW89_RU_SEC_NUM]; 532 }; 533 534 struct rtw89_rate_desc { 535 enum rtw89_nss nss; 536 enum rtw89_rate_section rs; 537 u8 idx; 538 }; 539 540 #define PHY_STS_HDR_LEN 8 541 #define RF_PATH_MAX 4 542 #define RTW89_MAX_PPDU_CNT 8 543 struct rtw89_rx_phy_ppdu { 544 u8 *buf; 545 u32 len; 546 u8 rssi_avg; 547 u8 rssi[RF_PATH_MAX]; 548 u8 mac_id; 549 u8 chan_idx; 550 u8 ie; 551 u16 rate; 552 bool to_self; 553 bool valid; 554 }; 555 556 enum rtw89_mac_idx { 557 RTW89_MAC_0 = 0, 558 RTW89_MAC_1 = 1, 559 }; 560 561 enum rtw89_phy_idx { 562 RTW89_PHY_0 = 0, 563 RTW89_PHY_1 = 1, 564 RTW89_PHY_MAX 565 }; 566 567 enum rtw89_sub_entity_idx { 568 RTW89_SUB_ENTITY_0 = 0, 569 570 NUM_OF_RTW89_SUB_ENTITY, 571 }; 572 573 enum rtw89_rf_path { 574 RF_PATH_A = 0, 575 RF_PATH_B = 1, 576 RF_PATH_C = 2, 577 RF_PATH_D = 3, 578 RF_PATH_AB, 579 RF_PATH_AC, 580 RF_PATH_AD, 581 RF_PATH_BC, 582 RF_PATH_BD, 583 RF_PATH_CD, 584 RF_PATH_ABC, 585 RF_PATH_ABD, 586 RF_PATH_ACD, 587 RF_PATH_BCD, 588 RF_PATH_ABCD, 589 }; 590 591 enum rtw89_rf_path_bit { 592 RF_A = BIT(0), 593 RF_B = BIT(1), 594 RF_C = BIT(2), 595 RF_D = BIT(3), 596 597 RF_AB = (RF_A | RF_B), 598 RF_AC = (RF_A | RF_C), 599 RF_AD = (RF_A | RF_D), 600 RF_BC = (RF_B | RF_C), 601 RF_BD = (RF_B | RF_D), 602 RF_CD = (RF_C | RF_D), 603 604 RF_ABC = (RF_A | RF_B | RF_C), 605 RF_ABD = (RF_A | RF_B | RF_D), 606 RF_ACD = (RF_A | RF_C | RF_D), 607 RF_BCD = (RF_B | RF_C | RF_D), 608 609 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 610 }; 611 612 enum rtw89_bandwidth { 613 RTW89_CHANNEL_WIDTH_20 = 0, 614 RTW89_CHANNEL_WIDTH_40 = 1, 615 RTW89_CHANNEL_WIDTH_80 = 2, 616 RTW89_CHANNEL_WIDTH_160 = 3, 617 RTW89_CHANNEL_WIDTH_80_80 = 4, 618 RTW89_CHANNEL_WIDTH_5 = 5, 619 RTW89_CHANNEL_WIDTH_10 = 6, 620 }; 621 622 enum rtw89_ps_mode { 623 RTW89_PS_MODE_NONE = 0, 624 RTW89_PS_MODE_RFOFF = 1, 625 RTW89_PS_MODE_CLK_GATED = 2, 626 RTW89_PS_MODE_PWR_GATED = 3, 627 }; 628 629 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 630 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 631 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 632 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 633 634 enum rtw89_ru_bandwidth { 635 RTW89_RU26 = 0, 636 RTW89_RU52 = 1, 637 RTW89_RU106 = 2, 638 RTW89_RU_NUM, 639 }; 640 641 enum rtw89_sc_offset { 642 RTW89_SC_DONT_CARE = 0, 643 RTW89_SC_20_UPPER = 1, 644 RTW89_SC_20_LOWER = 2, 645 RTW89_SC_20_UPMOST = 3, 646 RTW89_SC_20_LOWEST = 4, 647 RTW89_SC_20_UP2X = 5, 648 RTW89_SC_20_LOW2X = 6, 649 RTW89_SC_20_UP3X = 7, 650 RTW89_SC_20_LOW3X = 8, 651 RTW89_SC_40_UPPER = 9, 652 RTW89_SC_40_LOWER = 10, 653 }; 654 655 enum rtw89_wow_flags { 656 RTW89_WOW_FLAG_EN_MAGIC_PKT, 657 RTW89_WOW_FLAG_EN_REKEY_PKT, 658 RTW89_WOW_FLAG_EN_DISCONNECT, 659 RTW89_WOW_FLAG_NUM, 660 }; 661 662 struct rtw89_chan { 663 u8 channel; 664 u8 primary_channel; 665 enum rtw89_band band_type; 666 enum rtw89_bandwidth band_width; 667 668 /* The follow-up are derived from the above. We must ensure that it 669 * is assigned correctly in rtw89_chan_create() if new one is added. 670 */ 671 u32 freq; 672 enum rtw89_subband subband_type; 673 enum rtw89_sc_offset pri_ch_idx; 674 }; 675 676 struct rtw89_chan_rcd { 677 u8 prev_primary_channel; 678 enum rtw89_band prev_band_type; 679 }; 680 681 struct rtw89_channel_help_params { 682 u32 tx_en; 683 }; 684 685 struct rtw89_port_reg { 686 u32 port_cfg; 687 u32 tbtt_prohib; 688 u32 bcn_area; 689 u32 bcn_early; 690 u32 tbtt_early; 691 u32 tbtt_agg; 692 u32 bcn_space; 693 u32 bcn_forcetx; 694 u32 bcn_err_cnt; 695 u32 bcn_err_flag; 696 u32 dtim_ctrl; 697 u32 tbtt_shift; 698 u32 bcn_cnt_tmr; 699 u32 tsftr_l; 700 u32 tsftr_h; 701 }; 702 703 struct rtw89_txwd_body { 704 __le32 dword0; 705 __le32 dword1; 706 __le32 dword2; 707 __le32 dword3; 708 __le32 dword4; 709 __le32 dword5; 710 } __packed; 711 712 struct rtw89_txwd_body_v1 { 713 __le32 dword0; 714 __le32 dword1; 715 __le32 dword2; 716 __le32 dword3; 717 __le32 dword4; 718 __le32 dword5; 719 __le32 dword6; 720 __le32 dword7; 721 } __packed; 722 723 struct rtw89_txwd_info { 724 __le32 dword0; 725 __le32 dword1; 726 __le32 dword2; 727 __le32 dword3; 728 __le32 dword4; 729 __le32 dword5; 730 } __packed; 731 732 struct rtw89_rx_desc_info { 733 u16 pkt_size; 734 u8 pkt_type; 735 u8 drv_info_size; 736 u8 shift; 737 u8 wl_hd_iv_len; 738 bool long_rxdesc; 739 bool bb_sel; 740 bool mac_info_valid; 741 u16 data_rate; 742 u8 gi_ltf; 743 u8 bw; 744 u32 free_run_cnt; 745 u8 user_id; 746 bool sr_en; 747 u8 ppdu_cnt; 748 u8 ppdu_type; 749 bool icv_err; 750 bool crc32_err; 751 bool hw_dec; 752 bool sw_dec; 753 bool addr1_match; 754 u8 frag; 755 u16 seq; 756 u8 frame_type; 757 u8 rx_pl_id; 758 bool addr_cam_valid; 759 u8 addr_cam_id; 760 u8 sec_cam_id; 761 u8 mac_id; 762 u16 offset; 763 bool ready; 764 }; 765 766 struct rtw89_rxdesc_short { 767 __le32 dword0; 768 __le32 dword1; 769 __le32 dword2; 770 __le32 dword3; 771 } __packed; 772 773 struct rtw89_rxdesc_long { 774 __le32 dword0; 775 __le32 dword1; 776 __le32 dword2; 777 __le32 dword3; 778 __le32 dword4; 779 __le32 dword5; 780 __le32 dword6; 781 __le32 dword7; 782 } __packed; 783 784 struct rtw89_tx_desc_info { 785 u16 pkt_size; 786 u8 wp_offset; 787 u8 mac_id; 788 u8 qsel; 789 u8 ch_dma; 790 u8 hdr_llc_len; 791 bool is_bmc; 792 bool en_wd_info; 793 bool wd_page; 794 bool use_rate; 795 bool dis_data_fb; 796 bool tid_indicate; 797 bool agg_en; 798 bool bk; 799 u8 ampdu_density; 800 u8 ampdu_num; 801 bool sec_en; 802 u8 addr_info_nr; 803 u8 sec_keyid; 804 u8 sec_type; 805 u8 sec_cam_idx; 806 u8 sec_seq[6]; 807 u16 data_rate; 808 u16 data_retry_lowest_rate; 809 bool fw_dl; 810 u16 seq; 811 bool a_ctrl_bsr; 812 u8 hw_ssn_sel; 813 #define RTW89_MGMT_HW_SSN_SEL 1 814 u8 hw_seq_mode; 815 #define RTW89_MGMT_HW_SEQ_MODE 1 816 bool hiq; 817 u8 port; 818 }; 819 820 struct rtw89_core_tx_request { 821 enum rtw89_core_tx_type tx_type; 822 823 struct sk_buff *skb; 824 struct ieee80211_vif *vif; 825 struct ieee80211_sta *sta; 826 struct rtw89_tx_desc_info desc_info; 827 }; 828 829 struct rtw89_txq { 830 struct list_head list; 831 unsigned long flags; 832 int wait_cnt; 833 }; 834 835 struct rtw89_mac_ax_gnt { 836 u8 gnt_bt_sw_en; 837 u8 gnt_bt; 838 u8 gnt_wl_sw_en; 839 u8 gnt_wl; 840 } __packed; 841 842 #define RTW89_MAC_AX_COEX_GNT_NR 2 843 struct rtw89_mac_ax_coex_gnt { 844 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 845 }; 846 847 enum rtw89_btc_ncnt { 848 BTC_NCNT_POWER_ON = 0x0, 849 BTC_NCNT_POWER_OFF, 850 BTC_NCNT_INIT_COEX, 851 BTC_NCNT_SCAN_START, 852 BTC_NCNT_SCAN_FINISH, 853 BTC_NCNT_SPECIAL_PACKET, 854 BTC_NCNT_SWITCH_BAND, 855 BTC_NCNT_RFK_TIMEOUT, 856 BTC_NCNT_SHOW_COEX_INFO, 857 BTC_NCNT_ROLE_INFO, 858 BTC_NCNT_CONTROL, 859 BTC_NCNT_RADIO_STATE, 860 BTC_NCNT_CUSTOMERIZE, 861 BTC_NCNT_WL_RFK, 862 BTC_NCNT_WL_STA, 863 BTC_NCNT_FWINFO, 864 BTC_NCNT_TIMER, 865 BTC_NCNT_NUM 866 }; 867 868 enum rtw89_btc_btinfo { 869 BTC_BTINFO_L0 = 0, 870 BTC_BTINFO_L1, 871 BTC_BTINFO_L2, 872 BTC_BTINFO_L3, 873 BTC_BTINFO_H0, 874 BTC_BTINFO_H1, 875 BTC_BTINFO_H2, 876 BTC_BTINFO_H3, 877 BTC_BTINFO_MAX 878 }; 879 880 enum rtw89_btc_dcnt { 881 BTC_DCNT_RUN = 0x0, 882 BTC_DCNT_CX_RUNINFO, 883 BTC_DCNT_RPT, 884 BTC_DCNT_RPT_FREEZE, 885 BTC_DCNT_CYCLE, 886 BTC_DCNT_CYCLE_FREEZE, 887 BTC_DCNT_W1, 888 BTC_DCNT_W1_FREEZE, 889 BTC_DCNT_B1, 890 BTC_DCNT_B1_FREEZE, 891 BTC_DCNT_TDMA_NONSYNC, 892 BTC_DCNT_SLOT_NONSYNC, 893 BTC_DCNT_BTCNT_FREEZE, 894 BTC_DCNT_WL_SLOT_DRIFT, 895 BTC_DCNT_BT_SLOT_DRIFT, 896 BTC_DCNT_WL_STA_LAST, 897 BTC_DCNT_NUM, 898 }; 899 900 enum rtw89_btc_wl_state_cnt { 901 BTC_WCNT_SCANAP = 0x0, 902 BTC_WCNT_DHCP, 903 BTC_WCNT_EAPOL, 904 BTC_WCNT_ARP, 905 BTC_WCNT_SCBDUPDATE, 906 BTC_WCNT_RFK_REQ, 907 BTC_WCNT_RFK_GO, 908 BTC_WCNT_RFK_REJECT, 909 BTC_WCNT_RFK_TIMEOUT, 910 BTC_WCNT_CH_UPDATE, 911 BTC_WCNT_NUM 912 }; 913 914 enum rtw89_btc_bt_state_cnt { 915 BTC_BCNT_RETRY = 0x0, 916 BTC_BCNT_REINIT, 917 BTC_BCNT_REENABLE, 918 BTC_BCNT_SCBDREAD, 919 BTC_BCNT_RELINK, 920 BTC_BCNT_IGNOWL, 921 BTC_BCNT_INQPAG, 922 BTC_BCNT_INQ, 923 BTC_BCNT_PAGE, 924 BTC_BCNT_ROLESW, 925 BTC_BCNT_AFH, 926 BTC_BCNT_INFOUPDATE, 927 BTC_BCNT_INFOSAME, 928 BTC_BCNT_SCBDUPDATE, 929 BTC_BCNT_HIPRI_TX, 930 BTC_BCNT_HIPRI_RX, 931 BTC_BCNT_LOPRI_TX, 932 BTC_BCNT_LOPRI_RX, 933 BTC_BCNT_POLUT, 934 BTC_BCNT_RATECHG, 935 BTC_BCNT_NUM 936 }; 937 938 enum rtw89_btc_bt_profile { 939 BTC_BT_NOPROFILE = 0, 940 BTC_BT_HFP = BIT(0), 941 BTC_BT_HID = BIT(1), 942 BTC_BT_A2DP = BIT(2), 943 BTC_BT_PAN = BIT(3), 944 BTC_PROFILE_MAX = 4, 945 }; 946 947 struct rtw89_btc_ant_info { 948 u8 type; /* shared, dedicated */ 949 u8 num; 950 u8 isolation; 951 952 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 953 u8 diversity: 1; 954 }; 955 956 enum rtw89_tfc_dir { 957 RTW89_TFC_UL, 958 RTW89_TFC_DL, 959 }; 960 961 struct rtw89_btc_wl_smap { 962 u32 busy: 1; 963 u32 scan: 1; 964 u32 connecting: 1; 965 u32 roaming: 1; 966 u32 _4way: 1; 967 u32 rf_off: 1; 968 u32 lps: 2; 969 u32 ips: 1; 970 u32 init_ok: 1; 971 u32 traffic_dir : 2; 972 u32 rf_off_pre: 1; 973 u32 lps_pre: 2; 974 }; 975 976 enum rtw89_tfc_lv { 977 RTW89_TFC_IDLE, 978 RTW89_TFC_ULTRA_LOW, 979 RTW89_TFC_LOW, 980 RTW89_TFC_MID, 981 RTW89_TFC_HIGH, 982 }; 983 984 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 985 DECLARE_EWMA(tp, 10, 2); 986 987 struct rtw89_traffic_stats { 988 /* units in bytes */ 989 u64 tx_unicast; 990 u64 rx_unicast; 991 u32 tx_avg_len; 992 u32 rx_avg_len; 993 994 /* count for packets */ 995 u64 tx_cnt; 996 u64 rx_cnt; 997 998 /* units in Mbps */ 999 u32 tx_throughput; 1000 u32 rx_throughput; 1001 u32 tx_throughput_raw; 1002 u32 rx_throughput_raw; 1003 1004 u32 rx_tf_acc; 1005 u32 rx_tf_periodic; 1006 1007 enum rtw89_tfc_lv tx_tfc_lv; 1008 enum rtw89_tfc_lv rx_tfc_lv; 1009 struct ewma_tp tx_ewma_tp; 1010 struct ewma_tp rx_ewma_tp; 1011 1012 u16 tx_rate; 1013 u16 rx_rate; 1014 }; 1015 1016 struct rtw89_btc_statistic { 1017 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1018 struct rtw89_traffic_stats traffic; 1019 }; 1020 1021 #define BTC_WL_RSSI_THMAX 4 1022 1023 struct rtw89_btc_wl_link_info { 1024 struct rtw89_btc_statistic stat; 1025 enum rtw89_tfc_dir dir; 1026 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1027 u8 mac_addr[ETH_ALEN]; 1028 u8 busy; 1029 u8 ch; 1030 u8 bw; 1031 u8 band; 1032 u8 role; 1033 u8 pid; 1034 u8 phy; 1035 u8 dtim_period; 1036 u8 mode; 1037 1038 u8 mac_id; 1039 u8 tx_retry; 1040 1041 u32 bcn_period; 1042 u32 busy_t; 1043 u32 tx_time; 1044 u32 client_cnt; 1045 u32 rx_rate_drop_cnt; 1046 1047 u32 active: 1; 1048 u32 noa: 1; 1049 u32 client_ps: 1; 1050 u32 connected: 2; 1051 }; 1052 1053 union rtw89_btc_wl_state_map { 1054 u32 val; 1055 struct rtw89_btc_wl_smap map; 1056 }; 1057 1058 struct rtw89_btc_bt_hfp_desc { 1059 u32 exist: 1; 1060 u32 type: 2; 1061 u32 rsvd: 29; 1062 }; 1063 1064 struct rtw89_btc_bt_hid_desc { 1065 u32 exist: 1; 1066 u32 slot_info: 2; 1067 u32 pair_cnt: 2; 1068 u32 type: 8; 1069 u32 rsvd: 19; 1070 }; 1071 1072 struct rtw89_btc_bt_a2dp_desc { 1073 u8 exist: 1; 1074 u8 exist_last: 1; 1075 u8 play_latency: 1; 1076 u8 type: 3; 1077 u8 active: 1; 1078 u8 sink: 1; 1079 1080 u8 bitpool; 1081 u16 vendor_id; 1082 u32 device_name; 1083 u32 flush_time; 1084 }; 1085 1086 struct rtw89_btc_bt_pan_desc { 1087 u32 exist: 1; 1088 u32 type: 1; 1089 u32 active: 1; 1090 u32 rsvd: 29; 1091 }; 1092 1093 struct rtw89_btc_bt_rfk_info { 1094 u32 run: 1; 1095 u32 req: 1; 1096 u32 timeout: 1; 1097 u32 rsvd: 29; 1098 }; 1099 1100 union rtw89_btc_bt_rfk_info_map { 1101 u32 val; 1102 struct rtw89_btc_bt_rfk_info map; 1103 }; 1104 1105 struct rtw89_btc_bt_ver_info { 1106 u32 fw_coex; /* match with which coex_ver */ 1107 u32 fw; 1108 }; 1109 1110 struct rtw89_btc_bool_sta_chg { 1111 u32 now: 1; 1112 u32 last: 1; 1113 u32 remain: 1; 1114 u32 srvd: 29; 1115 }; 1116 1117 struct rtw89_btc_u8_sta_chg { 1118 u8 now; 1119 u8 last; 1120 u8 remain; 1121 u8 rsvd; 1122 }; 1123 1124 struct rtw89_btc_wl_scan_info { 1125 u8 band[RTW89_PHY_MAX]; 1126 u8 phy_map; 1127 u8 rsvd; 1128 }; 1129 1130 struct rtw89_btc_wl_dbcc_info { 1131 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1132 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1133 u8 real_band[RTW89_PHY_MAX]; 1134 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1135 }; 1136 1137 struct rtw89_btc_wl_active_role { 1138 u8 connected: 1; 1139 u8 pid: 3; 1140 u8 phy: 1; 1141 u8 noa: 1; 1142 u8 band: 2; 1143 1144 u8 client_ps: 1; 1145 u8 bw: 7; 1146 1147 u8 role; 1148 u8 ch; 1149 1150 u16 tx_lvl; 1151 u16 rx_lvl; 1152 u16 tx_rate; 1153 u16 rx_rate; 1154 }; 1155 1156 struct rtw89_btc_wl_active_role_v1 { 1157 u8 connected: 1; 1158 u8 pid: 3; 1159 u8 phy: 1; 1160 u8 noa: 1; 1161 u8 band: 2; 1162 1163 u8 client_ps: 1; 1164 u8 bw: 7; 1165 1166 u8 role; 1167 u8 ch; 1168 1169 u16 tx_lvl; 1170 u16 rx_lvl; 1171 u16 tx_rate; 1172 u16 rx_rate; 1173 1174 u32 noa_duration; /* ms */ 1175 }; 1176 1177 struct rtw89_btc_wl_role_info_bpos { 1178 u16 none: 1; 1179 u16 station: 1; 1180 u16 ap: 1; 1181 u16 vap: 1; 1182 u16 adhoc: 1; 1183 u16 adhoc_master: 1; 1184 u16 mesh: 1; 1185 u16 moniter: 1; 1186 u16 p2p_device: 1; 1187 u16 p2p_gc: 1; 1188 u16 p2p_go: 1; 1189 u16 nan: 1; 1190 }; 1191 1192 struct rtw89_btc_wl_scc_ctrl { 1193 u8 null_role1; 1194 u8 null_role2; 1195 u8 ebt_null; /* if tx null at EBT slot */ 1196 }; 1197 1198 union rtw89_btc_wl_role_info_map { 1199 u16 val; 1200 struct rtw89_btc_wl_role_info_bpos role; 1201 }; 1202 1203 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1204 u8 connect_cnt; 1205 u8 link_mode; 1206 union rtw89_btc_wl_role_info_map role_map; 1207 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1208 }; 1209 1210 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1211 u8 connect_cnt; 1212 u8 link_mode; 1213 union rtw89_btc_wl_role_info_map role_map; 1214 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1215 u32 mrole_type; /* btc_wl_mrole_type */ 1216 u32 mrole_noa_duration; /* ms */ 1217 1218 u32 dbcc_en: 1; 1219 u32 dbcc_chg: 1; 1220 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1221 u32 link_mode_chg: 1; 1222 u32 rsvd: 27; 1223 }; 1224 1225 struct rtw89_btc_wl_ver_info { 1226 u32 fw_coex; /* match with which coex_ver */ 1227 u32 fw; 1228 u32 mac; 1229 u32 bb; 1230 u32 rf; 1231 }; 1232 1233 struct rtw89_btc_wl_afh_info { 1234 u8 en; 1235 u8 ch; 1236 u8 bw; 1237 u8 rsvd; 1238 } __packed; 1239 1240 struct rtw89_btc_wl_rfk_info { 1241 u32 state: 2; 1242 u32 path_map: 4; 1243 u32 phy_map: 2; 1244 u32 band: 2; 1245 u32 type: 8; 1246 u32 rsvd: 14; 1247 }; 1248 1249 struct rtw89_btc_bt_smap { 1250 u32 connect: 1; 1251 u32 ble_connect: 1; 1252 u32 acl_busy: 1; 1253 u32 sco_busy: 1; 1254 u32 mesh_busy: 1; 1255 u32 inq_pag: 1; 1256 }; 1257 1258 union rtw89_btc_bt_state_map { 1259 u32 val; 1260 struct rtw89_btc_bt_smap map; 1261 }; 1262 1263 #define BTC_BT_RSSI_THMAX 4 1264 #define BTC_BT_AFH_GROUP 12 1265 1266 struct rtw89_btc_bt_link_info { 1267 struct rtw89_btc_u8_sta_chg profile_cnt; 1268 struct rtw89_btc_bool_sta_chg multi_link; 1269 struct rtw89_btc_bool_sta_chg relink; 1270 struct rtw89_btc_bt_hfp_desc hfp_desc; 1271 struct rtw89_btc_bt_hid_desc hid_desc; 1272 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1273 struct rtw89_btc_bt_pan_desc pan_desc; 1274 union rtw89_btc_bt_state_map status; 1275 1276 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1277 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1278 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1279 u8 afh_map[BTC_BT_AFH_GROUP]; 1280 1281 u32 role_sw: 1; 1282 u32 slave_role: 1; 1283 u32 afh_update: 1; 1284 u32 cqddr: 1; 1285 u32 rssi: 8; 1286 u32 tx_3m: 1; 1287 u32 rsvd: 19; 1288 }; 1289 1290 struct rtw89_btc_3rdcx_info { 1291 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1292 u8 hw_coex; 1293 u16 rsvd; 1294 }; 1295 1296 struct rtw89_btc_dm_emap { 1297 u32 init: 1; 1298 u32 pta_owner: 1; 1299 u32 wl_rfk_timeout: 1; 1300 u32 bt_rfk_timeout: 1; 1301 1302 u32 wl_fw_hang: 1; 1303 u32 offload_mismatch: 1; 1304 u32 cycle_hang: 1; 1305 u32 w1_hang: 1; 1306 1307 u32 b1_hang: 1; 1308 u32 tdma_no_sync: 1; 1309 u32 wl_slot_drift: 1; 1310 }; 1311 1312 union rtw89_btc_dm_error_map { 1313 u32 val; 1314 struct rtw89_btc_dm_emap map; 1315 }; 1316 1317 struct rtw89_btc_rf_para { 1318 u32 tx_pwr_freerun; 1319 u32 rx_gain_freerun; 1320 u32 tx_pwr_perpkt; 1321 u32 rx_gain_perpkt; 1322 }; 1323 1324 struct rtw89_btc_wl_info { 1325 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1326 struct rtw89_btc_wl_rfk_info rfk_info; 1327 struct rtw89_btc_wl_ver_info ver_info; 1328 struct rtw89_btc_wl_afh_info afh_info; 1329 struct rtw89_btc_wl_role_info role_info; 1330 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1331 struct rtw89_btc_wl_scan_info scan_info; 1332 struct rtw89_btc_wl_dbcc_info dbcc_info; 1333 struct rtw89_btc_rf_para rf_para; 1334 union rtw89_btc_wl_state_map status; 1335 1336 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1337 u8 rssi_level; 1338 1339 bool scbd_change; 1340 u32 scbd; 1341 }; 1342 1343 struct rtw89_btc_module { 1344 struct rtw89_btc_ant_info ant; 1345 u8 rfe_type; 1346 u8 cv; 1347 1348 u8 bt_solo: 1; 1349 u8 bt_pos: 1; 1350 u8 switch_type: 1; 1351 1352 u8 rsvd; 1353 }; 1354 1355 #define RTW89_BTC_DM_MAXSTEP 30 1356 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1357 1358 struct rtw89_btc_dm_step { 1359 u16 step[RTW89_BTC_DM_MAXSTEP]; 1360 u8 step_pos; 1361 bool step_ov; 1362 }; 1363 1364 struct rtw89_btc_init_info { 1365 struct rtw89_btc_module module; 1366 u8 wl_guard_ch; 1367 1368 u8 wl_only: 1; 1369 u8 wl_init_ok: 1; 1370 u8 dbcc_en: 1; 1371 u8 cx_other: 1; 1372 u8 bt_only: 1; 1373 1374 u16 rsvd; 1375 }; 1376 1377 struct rtw89_btc_wl_tx_limit_para { 1378 u16 enable; 1379 u32 tx_time; /* unit: us */ 1380 u16 tx_retry; 1381 }; 1382 1383 struct rtw89_btc_bt_scan_info { 1384 u16 win; 1385 u16 intvl; 1386 u32 enable: 1; 1387 u32 interlace: 1; 1388 u32 rsvd: 30; 1389 }; 1390 1391 enum rtw89_btc_bt_scan_type { 1392 BTC_SCAN_INQ = 0, 1393 BTC_SCAN_PAGE, 1394 BTC_SCAN_BLE, 1395 BTC_SCAN_INIT, 1396 BTC_SCAN_TV, 1397 BTC_SCAN_ADV, 1398 BTC_SCAN_MAX1, 1399 }; 1400 1401 struct rtw89_btc_bt_info { 1402 struct rtw89_btc_bt_link_info link_info; 1403 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1404 struct rtw89_btc_bt_ver_info ver_info; 1405 struct rtw89_btc_bool_sta_chg enable; 1406 struct rtw89_btc_bool_sta_chg inq_pag; 1407 struct rtw89_btc_rf_para rf_para; 1408 union rtw89_btc_bt_rfk_info_map rfk_info; 1409 1410 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1411 1412 u32 scbd; 1413 u32 feature; 1414 1415 u32 mbx_avl: 1; 1416 u32 whql_test: 1; 1417 u32 igno_wl: 1; 1418 u32 reinit: 1; 1419 u32 ble_scan_en: 1; 1420 u32 btg_type: 1; 1421 u32 inq: 1; 1422 u32 pag: 1; 1423 u32 run_patch_code: 1; 1424 u32 hi_lna_rx: 1; 1425 u32 scan_rx_low_pri: 1; 1426 u32 rsvd: 21; 1427 }; 1428 1429 struct rtw89_btc_cx { 1430 struct rtw89_btc_wl_info wl; 1431 struct rtw89_btc_bt_info bt; 1432 struct rtw89_btc_3rdcx_info other; 1433 u32 state_map; 1434 u32 cnt_bt[BTC_BCNT_NUM]; 1435 u32 cnt_wl[BTC_WCNT_NUM]; 1436 }; 1437 1438 struct rtw89_btc_fbtc_tdma { 1439 u8 type; /* chip_info::fcxtdma_ver */ 1440 u8 rxflctrl; 1441 u8 txpause; 1442 u8 wtgle_n; 1443 u8 leak_n; 1444 u8 ext_ctrl; 1445 u8 rxflctrl_role; 1446 u8 option_ctrl; 1447 } __packed; 1448 1449 struct rtw89_btc_fbtc_tdma_v1 { 1450 u8 fver; /* chip_info::fcxtdma_ver */ 1451 u8 rsvd; 1452 __le16 rsvd1; 1453 struct rtw89_btc_fbtc_tdma tdma; 1454 } __packed; 1455 1456 #define CXMREG_MAX 30 1457 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1458 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1459 1460 enum rtw89_btc_bt_sta_counter { 1461 BTC_BCNT_RFK_REQ = 0, 1462 BTC_BCNT_RFK_GO = 1, 1463 BTC_BCNT_RFK_REJECT = 2, 1464 BTC_BCNT_RFK_FAIL = 3, 1465 BTC_BCNT_RFK_TIMEOUT = 4, 1466 BTC_BCNT_HI_TX = 5, 1467 BTC_BCNT_HI_RX = 6, 1468 BTC_BCNT_LO_TX = 7, 1469 BTC_BCNT_LO_RX = 8, 1470 BTC_BCNT_POLLUTED = 9, 1471 BTC_BCNT_STA_MAX 1472 }; 1473 1474 struct rtw89_btc_fbtc_rpt_ctrl { 1475 u16 fver; /* chip_info::fcxbtcrpt_ver */ 1476 u16 rpt_cnt; /* tmr counters */ 1477 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1478 u32 wl_fw_cx_offload; 1479 u32 wl_fw_ver; 1480 u32 rpt_enable; 1481 u32 rpt_para; /* ms */ 1482 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1483 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1484 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1485 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1486 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1487 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1488 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1489 u32 c2h_cnt; /* fw send c2h counter */ 1490 u32 h2c_cnt; /* fw recv h2c counter */ 1491 } __packed; 1492 1493 struct rtw89_btc_fbtc_rpt_ctrl_info { 1494 __le32 cnt; /* fw report counter */ 1495 __le32 en; /* report map */ 1496 __le32 para; /* not used */ 1497 1498 __le32 cnt_c2h; /* fw send c2h counter */ 1499 __le32 cnt_h2c; /* fw recv h2c counter */ 1500 __le32 len_c2h; /* The total length of the last C2H */ 1501 1502 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1503 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1504 } __packed; 1505 1506 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1507 __le32 cx_ver; /* match which driver's coex version */ 1508 __le32 cx_offload; 1509 __le32 fw_ver; 1510 } __packed; 1511 1512 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1513 __le32 cnt_empty; /* a2dp empty count */ 1514 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1515 __le32 cnt_tx; 1516 __le32 cnt_ack; 1517 __le32 cnt_nack; 1518 } __packed; 1519 1520 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1521 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1522 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1523 __le32 cnt_recv; /* fw recv mailbox counter */ 1524 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1525 } __packed; 1526 1527 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1528 u8 fver; 1529 u8 rsvd; 1530 __le16 rsvd1; 1531 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1532 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1533 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1534 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1535 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1536 } __packed; 1537 1538 enum rtw89_fbtc_ext_ctrl_type { 1539 CXECTL_OFF = 0x0, /* tdma off */ 1540 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1541 CXECTL_EXT = 0x2, 1542 CXECTL_MAX 1543 }; 1544 1545 union rtw89_btc_fbtc_rxflct { 1546 u8 val; 1547 u8 type: 3; 1548 u8 tgln_n: 5; 1549 }; 1550 1551 enum rtw89_btc_cxst_state { 1552 CXST_OFF = 0x0, 1553 CXST_B2W = 0x1, 1554 CXST_W1 = 0x2, 1555 CXST_W2 = 0x3, 1556 CXST_W2B = 0x4, 1557 CXST_B1 = 0x5, 1558 CXST_B2 = 0x6, 1559 CXST_B3 = 0x7, 1560 CXST_B4 = 0x8, 1561 CXST_LK = 0x9, 1562 CXST_BLK = 0xa, 1563 CXST_E2G = 0xb, 1564 CXST_E5G = 0xc, 1565 CXST_EBT = 0xd, 1566 CXST_ENULL = 0xe, 1567 CXST_WLK = 0xf, 1568 CXST_W1FDD = 0x10, 1569 CXST_B1FDD = 0x11, 1570 CXST_MAX = 0x12, 1571 }; 1572 1573 enum { 1574 CXBCN_ALL = 0x0, 1575 CXBCN_ALL_OK, 1576 CXBCN_BT_SLOT, 1577 CXBCN_BT_OK, 1578 CXBCN_MAX 1579 }; 1580 1581 enum btc_slot_type { 1582 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1583 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1584 CXSTYPE_NUM, 1585 }; 1586 1587 enum { /* TIME */ 1588 CXT_BT = 0x0, 1589 CXT_WL = 0x1, 1590 CXT_MAX 1591 }; 1592 1593 enum { /* TIME-A2DP */ 1594 CXT_FLCTRL_OFF = 0x0, 1595 CXT_FLCTRL_ON = 0x1, 1596 CXT_FLCTRL_MAX 1597 }; 1598 1599 enum { /* STEP TYPE */ 1600 CXSTEP_NONE = 0x0, 1601 CXSTEP_EVNT = 0x1, 1602 CXSTEP_SLOT = 0x2, 1603 CXSTEP_MAX, 1604 }; 1605 1606 #define BTC_DBG_MAX1 32 1607 struct rtw89_btc_fbtc_gpio_dbg { 1608 u8 fver; /* chip_info::fcxgpiodbg_ver */ 1609 u8 rsvd; 1610 u16 rsvd2; 1611 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1612 u32 pre_state; /* the debug signal is 1 or 0 */ 1613 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1614 } __packed; 1615 1616 struct rtw89_btc_fbtc_mreg_val { 1617 u8 fver; /* chip_info::fcxmreg_ver */ 1618 u8 reg_num; 1619 __le16 rsvd; 1620 __le32 mreg_val[CXMREG_MAX]; 1621 } __packed; 1622 1623 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1624 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1625 .offset = cpu_to_le32(__offset), } 1626 1627 struct rtw89_btc_fbtc_mreg { 1628 __le16 type; 1629 __le16 bytes; 1630 __le32 offset; 1631 } __packed; 1632 1633 struct rtw89_btc_fbtc_slot { 1634 __le16 dur; 1635 __le32 cxtbl; 1636 __le16 cxtype; 1637 } __packed; 1638 1639 struct rtw89_btc_fbtc_slots { 1640 u8 fver; /* chip_info::fcxslots_ver */ 1641 u8 tbl_num; 1642 __le16 rsvd; 1643 __le32 update_map; 1644 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1645 } __packed; 1646 1647 struct rtw89_btc_fbtc_step { 1648 u8 type; 1649 u8 val; 1650 __le16 difft; 1651 } __packed; 1652 1653 struct rtw89_btc_fbtc_steps { 1654 u8 fver; /* chip_info::fcxstep_ver */ 1655 u8 rsvd; 1656 __le16 cnt; 1657 __le16 pos_old; 1658 __le16 pos_new; 1659 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1660 } __packed; 1661 1662 struct rtw89_btc_fbtc_steps_v1 { 1663 u8 fver; 1664 u8 en; 1665 __le16 rsvd; 1666 __le32 cnt; 1667 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1668 } __packed; 1669 1670 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1671 u8 fver; /* chip_info::fcxcysta_ver */ 1672 u8 rsvd; 1673 __le16 cycles; /* total cycle number */ 1674 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1675 __le16 a2dpept; /* a2dp empty cnt */ 1676 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1677 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1678 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1679 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1680 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1681 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1682 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1683 __le16 tmax_a2dpept; /* max a2dp empty time */ 1684 __le16 tavg_lk; /* avg leak-slot time */ 1685 __le16 tmax_lk; /* max leak-slot time */ 1686 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1687 __le32 bcn_cnt[CXBCN_MAX]; 1688 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1689 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1690 __le32 skip_cnt; 1691 __le32 exception; 1692 __le32 except_cnt; 1693 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1694 } __packed; 1695 1696 struct rtw89_btc_fbtc_fdd_try_info { 1697 __le16 cycles[CXT_FLCTRL_MAX]; 1698 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1699 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1700 } __packed; 1701 1702 struct rtw89_btc_fbtc_cycle_time_info { 1703 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1704 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1705 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1706 } __packed; 1707 1708 struct rtw89_btc_fbtc_a2dp_trx_stat { 1709 u8 empty_cnt; 1710 u8 retry_cnt; 1711 u8 tx_rate; 1712 u8 tx_cnt; 1713 u8 ack_cnt; 1714 u8 nack_cnt; 1715 u8 rsvd1; 1716 u8 rsvd2; 1717 } __packed; 1718 1719 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1720 __le16 cnt; /* a2dp empty cnt */ 1721 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1722 __le16 tavg; /* avg a2dp empty time */ 1723 __le16 tmax; /* max a2dp empty time */ 1724 } __packed; 1725 1726 struct rtw89_btc_fbtc_cycle_leak_info { 1727 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1728 __le16 tavg; /* avg leak-slot time */ 1729 __le16 tmax; /* max leak-slot time */ 1730 } __packed; 1731 1732 struct rtw89_btc_fbtc_cysta_v1 { /* statistics for cycles */ 1733 u8 fver; 1734 u8 rsvd; 1735 __le16 cycles; /* total cycle number */ 1736 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 1737 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 1738 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 1739 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 1740 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 1741 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 1742 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1743 __le32 bcn_cnt[CXBCN_MAX]; 1744 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 1745 __le32 skip_cnt; 1746 __le32 except_cnt; 1747 __le32 except_map; 1748 } __packed; 1749 1750 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1751 u8 fver; /* chip_info::fcxnullsta_ver */ 1752 u8 rsvd; 1753 __le16 rsvd2; 1754 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1755 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1756 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1757 } __packed; 1758 1759 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 1760 u8 fver; /* chip_info::fcxnullsta_ver */ 1761 u8 rsvd; 1762 __le16 rsvd2; 1763 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1764 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1765 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 1766 } __packed; 1767 1768 struct rtw89_btc_fbtc_btver { 1769 u8 fver; /* chip_info::fcxbtver_ver */ 1770 u8 rsvd; 1771 __le16 rsvd2; 1772 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1773 __le32 fw_ver; 1774 __le32 feature; 1775 } __packed; 1776 1777 struct rtw89_btc_fbtc_btscan { 1778 u8 fver; /* chip_info::fcxbtscan_ver */ 1779 u8 rsvd; 1780 __le16 rsvd2; 1781 u8 scan[6]; 1782 } __packed; 1783 1784 struct rtw89_btc_fbtc_btafh { 1785 u8 fver; /* chip_info::fcxbtafh_ver */ 1786 u8 rsvd; 1787 __le16 rsvd2; 1788 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1789 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1790 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1791 } __packed; 1792 1793 struct rtw89_btc_fbtc_btdevinfo { 1794 u8 fver; /* chip_info::fcxbtdevinfo_ver */ 1795 u8 rsvd; 1796 __le16 vendor_id; 1797 __le32 dev_name; /* only 24 bits valid */ 1798 __le32 flush_time; 1799 } __packed; 1800 1801 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1802 struct rtw89_btc_rf_trx_para { 1803 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1804 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1805 u8 bt_tx_power; /* decrease Tx power (dB) */ 1806 u8 bt_rx_gain; /* LNA constrain level */ 1807 }; 1808 1809 struct rtw89_btc_dm { 1810 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1811 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1812 struct rtw89_btc_fbtc_tdma tdma; 1813 struct rtw89_btc_fbtc_tdma tdma_now; 1814 struct rtw89_mac_ax_coex_gnt gnt; 1815 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1816 struct rtw89_btc_rf_trx_para rf_trx_para; 1817 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1818 struct rtw89_btc_dm_step dm_step; 1819 struct rtw89_btc_wl_scc_ctrl wl_scc; 1820 union rtw89_btc_dm_error_map error; 1821 u32 cnt_dm[BTC_DCNT_NUM]; 1822 u32 cnt_notify[BTC_NCNT_NUM]; 1823 1824 u32 update_slot_map; 1825 u32 set_ant_path; 1826 1827 u32 wl_only: 1; 1828 u32 wl_fw_cx_offload: 1; 1829 u32 freerun: 1; 1830 u32 wl_ps_ctrl: 2; 1831 u32 wl_mimo_ps: 1; 1832 u32 leak_ap: 1; 1833 u32 noisy_level: 3; 1834 u32 coex_info_map: 8; 1835 u32 bt_only: 1; 1836 u32 wl_btg_rx: 1; 1837 u32 trx_para_level: 8; 1838 u32 wl_stb_chg: 1; 1839 u32 pta_owner: 1; 1840 u32 tdma_instant_excute: 1; 1841 u32 rsvd: 1; 1842 1843 u16 slot_dur[CXST_MAX]; 1844 1845 u8 run_reason; 1846 u8 run_action; 1847 }; 1848 1849 struct rtw89_btc_ctrl { 1850 u32 manual: 1; 1851 u32 igno_bt: 1; 1852 u32 always_freerun: 1; 1853 u32 trace_step: 16; 1854 u32 rsvd: 12; 1855 }; 1856 1857 struct rtw89_btc_dbg { 1858 /* cmd "rb" */ 1859 bool rb_done; 1860 u32 rb_val; 1861 }; 1862 1863 enum rtw89_btc_btf_fw_event { 1864 BTF_EVNT_RPT = 0, 1865 BTF_EVNT_BT_INFO = 1, 1866 BTF_EVNT_BT_SCBD = 2, 1867 BTF_EVNT_BT_REG = 3, 1868 BTF_EVNT_CX_RUNINFO = 4, 1869 BTF_EVNT_BT_PSD = 5, 1870 BTF_EVNT_BUF_OVERFLOW, 1871 BTF_EVNT_C2H_LOOPBACK, 1872 BTF_EVNT_MAX, 1873 }; 1874 1875 enum btf_fw_event_report { 1876 BTC_RPT_TYPE_CTRL = 0x0, 1877 BTC_RPT_TYPE_TDMA, 1878 BTC_RPT_TYPE_SLOT, 1879 BTC_RPT_TYPE_CYSTA, 1880 BTC_RPT_TYPE_STEP, 1881 BTC_RPT_TYPE_NULLSTA, 1882 BTC_RPT_TYPE_MREG, 1883 BTC_RPT_TYPE_GPIO_DBG, 1884 BTC_RPT_TYPE_BT_VER, 1885 BTC_RPT_TYPE_BT_SCAN, 1886 BTC_RPT_TYPE_BT_AFH, 1887 BTC_RPT_TYPE_BT_DEVICE, 1888 BTC_RPT_TYPE_TEST, 1889 BTC_RPT_TYPE_MAX = 31 1890 }; 1891 1892 enum rtw_btc_btf_reg_type { 1893 REG_MAC = 0x0, 1894 REG_BB = 0x1, 1895 REG_RF = 0x2, 1896 REG_BT_RF = 0x3, 1897 REG_BT_MODEM = 0x4, 1898 REG_BT_BLUEWIZE = 0x5, 1899 REG_BT_VENDOR = 0x6, 1900 REG_BT_LE = 0x7, 1901 REG_MAX_TYPE, 1902 }; 1903 1904 struct rtw89_btc_rpt_cmn_info { 1905 u32 rx_cnt; 1906 u32 rx_len; 1907 u32 req_len; /* expected rsp len */ 1908 u8 req_fver; /* expected rsp fver */ 1909 u8 rsp_fver; /* fver from fw */ 1910 u8 valid; 1911 } __packed; 1912 1913 struct rtw89_btc_report_ctrl_state { 1914 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1915 union { 1916 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw for 52A*/ 1917 struct rtw89_btc_fbtc_rpt_ctrl_v1 finfo_v1; /* info from fw for 52C*/ 1918 }; 1919 }; 1920 1921 struct rtw89_btc_rpt_fbtc_tdma { 1922 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1923 union { 1924 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1925 struct rtw89_btc_fbtc_tdma_v1 finfo_v1; /* info from fw for 52C*/ 1926 }; 1927 }; 1928 1929 struct rtw89_btc_rpt_fbtc_slots { 1930 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1931 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1932 }; 1933 1934 struct rtw89_btc_rpt_fbtc_cysta { 1935 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1936 union { 1937 struct rtw89_btc_fbtc_cysta finfo; /* info from fw for 52A*/ 1938 struct rtw89_btc_fbtc_cysta_v1 finfo_v1; /* info from fw for 52C*/ 1939 }; 1940 }; 1941 1942 struct rtw89_btc_rpt_fbtc_step { 1943 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1944 union { 1945 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1946 struct rtw89_btc_fbtc_steps_v1 finfo_v1; /* info from fw */ 1947 }; 1948 }; 1949 1950 struct rtw89_btc_rpt_fbtc_nullsta { 1951 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1952 union { 1953 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1954 struct rtw89_btc_fbtc_cynullsta_v1 finfo_v1; /* info from fw */ 1955 }; 1956 }; 1957 1958 struct rtw89_btc_rpt_fbtc_mreg { 1959 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1960 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1961 }; 1962 1963 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1964 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1965 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1966 }; 1967 1968 struct rtw89_btc_rpt_fbtc_btver { 1969 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1970 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1971 }; 1972 1973 struct rtw89_btc_rpt_fbtc_btscan { 1974 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1975 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1976 }; 1977 1978 struct rtw89_btc_rpt_fbtc_btafh { 1979 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1980 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1981 }; 1982 1983 struct rtw89_btc_rpt_fbtc_btdev { 1984 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1985 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1986 }; 1987 1988 enum rtw89_btc_btfre_type { 1989 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1990 BTFRE_UNDEF_TYPE, 1991 BTFRE_EXCEPTION, 1992 BTFRE_MAX, 1993 }; 1994 1995 struct rtw89_btc_btf_fwinfo { 1996 u32 cnt_c2h; 1997 u32 cnt_h2c; 1998 u32 cnt_h2c_fail; 1999 u32 event[BTF_EVNT_MAX]; 2000 2001 u32 err[BTFRE_MAX]; 2002 u32 len_mismch; 2003 u32 fver_mismch; 2004 u32 rpt_en_map; 2005 2006 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2007 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2008 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2009 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2010 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2011 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2012 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2013 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2014 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2015 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2016 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2017 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2018 }; 2019 2020 #define RTW89_BTC_POLICY_MAXLEN 512 2021 2022 struct rtw89_btc { 2023 struct rtw89_btc_cx cx; 2024 struct rtw89_btc_dm dm; 2025 struct rtw89_btc_ctrl ctrl; 2026 struct rtw89_btc_module mdinfo; 2027 struct rtw89_btc_btf_fwinfo fwinfo; 2028 struct rtw89_btc_dbg dbg; 2029 2030 struct work_struct eapol_notify_work; 2031 struct work_struct arp_notify_work; 2032 struct work_struct dhcp_notify_work; 2033 struct work_struct icmp_notify_work; 2034 2035 u32 bt_req_len; 2036 2037 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2038 u16 policy_len; 2039 u16 policy_type; 2040 bool bt_req_en; 2041 bool update_policy_force; 2042 bool lps; 2043 }; 2044 2045 enum rtw89_ra_mode { 2046 RTW89_RA_MODE_CCK = BIT(0), 2047 RTW89_RA_MODE_OFDM = BIT(1), 2048 RTW89_RA_MODE_HT = BIT(2), 2049 RTW89_RA_MODE_VHT = BIT(3), 2050 RTW89_RA_MODE_HE = BIT(4), 2051 }; 2052 2053 enum rtw89_ra_report_mode { 2054 RTW89_RA_RPT_MODE_LEGACY, 2055 RTW89_RA_RPT_MODE_HT, 2056 RTW89_RA_RPT_MODE_VHT, 2057 RTW89_RA_RPT_MODE_HE, 2058 }; 2059 2060 enum rtw89_dig_noisy_level { 2061 RTW89_DIG_NOISY_LEVEL0 = -1, 2062 RTW89_DIG_NOISY_LEVEL1 = 0, 2063 RTW89_DIG_NOISY_LEVEL2 = 1, 2064 RTW89_DIG_NOISY_LEVEL3 = 2, 2065 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2066 }; 2067 2068 enum rtw89_gi_ltf { 2069 RTW89_GILTF_LGI_4XHE32 = 0, 2070 RTW89_GILTF_SGI_4XHE08 = 1, 2071 RTW89_GILTF_2XHE16 = 2, 2072 RTW89_GILTF_2XHE08 = 3, 2073 RTW89_GILTF_1XHE16 = 4, 2074 RTW89_GILTF_1XHE08 = 5, 2075 RTW89_GILTF_MAX 2076 }; 2077 2078 enum rtw89_rx_frame_type { 2079 RTW89_RX_TYPE_MGNT = 0, 2080 RTW89_RX_TYPE_CTRL = 1, 2081 RTW89_RX_TYPE_DATA = 2, 2082 RTW89_RX_TYPE_RSVD = 3, 2083 }; 2084 2085 struct rtw89_ra_info { 2086 u8 is_dis_ra:1; 2087 /* Bit0 : CCK 2088 * Bit1 : OFDM 2089 * Bit2 : HT 2090 * Bit3 : VHT 2091 * Bit4 : HE 2092 */ 2093 u8 mode_ctrl:5; 2094 u8 bw_cap:2; 2095 u8 macid; 2096 u8 dcm_cap:1; 2097 u8 er_cap:1; 2098 u8 init_rate_lv:2; 2099 u8 upd_all:1; 2100 u8 en_sgi:1; 2101 u8 ldpc_cap:1; 2102 u8 stbc_cap:1; 2103 u8 ss_num:3; 2104 u8 giltf:3; 2105 u8 upd_bw_nss_mask:1; 2106 u8 upd_mask:1; 2107 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2108 /* BFee CSI */ 2109 u8 band_num; 2110 u8 ra_csi_rate_en:1; 2111 u8 fixed_csi_rate_en:1; 2112 u8 cr_tbl_sel:1; 2113 u8 fix_giltf_en:1; 2114 u8 fix_giltf:3; 2115 u8 rsvd2:1; 2116 u8 csi_mcs_ss_idx; 2117 u8 csi_mode:2; 2118 u8 csi_gi_ltf:3; 2119 u8 csi_bw:3; 2120 }; 2121 2122 #define RTW89_PPDU_MAX_USR 4 2123 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2124 #define RTW89_PPDU_MAC_INFO_SIZE 8 2125 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2126 2127 #define RTW89_MAX_RX_AGG_NUM 64 2128 #define RTW89_MAX_TX_AGG_NUM 128 2129 2130 struct rtw89_ampdu_params { 2131 u16 agg_num; 2132 bool amsdu; 2133 }; 2134 2135 struct rtw89_ra_report { 2136 struct rate_info txrate; 2137 u32 bit_rate; 2138 u16 hw_rate; 2139 bool might_fallback_legacy; 2140 }; 2141 2142 DECLARE_EWMA(rssi, 10, 16); 2143 2144 struct rtw89_ba_cam_entry { 2145 struct list_head list; 2146 u8 tid; 2147 }; 2148 2149 #define RTW89_MAX_ADDR_CAM_NUM 128 2150 #define RTW89_MAX_BSSID_CAM_NUM 20 2151 #define RTW89_MAX_SEC_CAM_NUM 128 2152 #define RTW89_MAX_BA_CAM_NUM 8 2153 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2154 2155 struct rtw89_addr_cam_entry { 2156 u8 addr_cam_idx; 2157 u8 offset; 2158 u8 len; 2159 u8 valid : 1; 2160 u8 addr_mask : 6; 2161 u8 wapi : 1; 2162 u8 mask_sel : 2; 2163 u8 bssid_cam_idx: 6; 2164 2165 u8 sec_ent_mode; 2166 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2167 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2168 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2169 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2170 }; 2171 2172 struct rtw89_bssid_cam_entry { 2173 u8 bssid[ETH_ALEN]; 2174 u8 phy_idx; 2175 u8 bssid_cam_idx; 2176 u8 offset; 2177 u8 len; 2178 u8 valid : 1; 2179 u8 num; 2180 }; 2181 2182 struct rtw89_sec_cam_entry { 2183 u8 sec_cam_idx; 2184 u8 offset; 2185 u8 len; 2186 u8 type : 4; 2187 u8 ext_key : 1; 2188 u8 spp_mode : 1; 2189 /* 256 bits */ 2190 u8 key[32]; 2191 }; 2192 2193 struct rtw89_sta { 2194 u8 mac_id; 2195 bool disassoc; 2196 struct rtw89_dev *rtwdev; 2197 struct rtw89_vif *rtwvif; 2198 struct rtw89_ra_info ra; 2199 struct rtw89_ra_report ra_report; 2200 int max_agg_wait; 2201 u8 prev_rssi; 2202 struct ewma_rssi avg_rssi; 2203 struct ewma_rssi rssi[RF_PATH_MAX]; 2204 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2205 struct ieee80211_rx_status rx_status; 2206 u16 rx_hw_rate; 2207 __le32 htc_template; 2208 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2209 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2210 struct list_head ba_cam_list; 2211 2212 bool use_cfg_mask; 2213 struct cfg80211_bitrate_mask mask; 2214 2215 bool cctl_tx_time; 2216 u32 ampdu_max_time:4; 2217 bool cctl_tx_retry_limit; 2218 u32 data_tx_cnt_lmt:6; 2219 }; 2220 2221 struct rtw89_efuse { 2222 bool valid; 2223 bool power_k_valid; 2224 u8 xtal_cap; 2225 u8 addr[ETH_ALEN]; 2226 u8 rfe_type; 2227 char country_code[2]; 2228 }; 2229 2230 struct rtw89_phy_rate_pattern { 2231 u64 ra_mask; 2232 u16 rate; 2233 u8 ra_mode; 2234 bool enable; 2235 }; 2236 2237 #define RTW89_P2P_MAX_NOA_NUM 2 2238 2239 struct rtw89_vif { 2240 struct list_head list; 2241 struct rtw89_dev *rtwdev; 2242 u8 mac_id; 2243 u8 port; 2244 u8 mac_addr[ETH_ALEN]; 2245 u8 bssid[ETH_ALEN]; 2246 u8 phy_idx; 2247 u8 mac_idx; 2248 u8 net_type; 2249 u8 wifi_role; 2250 u8 self_role; 2251 u8 wmm; 2252 u8 bcn_hit_cond; 2253 u8 hit_rule; 2254 u8 last_noa_nr; 2255 bool trigger; 2256 bool lsig_txop; 2257 u8 tgt_ind; 2258 u8 frm_tgt_ind; 2259 bool wowlan_pattern; 2260 bool wowlan_uc; 2261 bool wowlan_magic; 2262 bool is_hesta; 2263 bool last_a_ctrl; 2264 struct work_struct update_beacon_work; 2265 struct rtw89_addr_cam_entry addr_cam; 2266 struct rtw89_bssid_cam_entry bssid_cam; 2267 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2268 struct rtw89_traffic_stats stats; 2269 struct rtw89_phy_rate_pattern rate_pattern; 2270 struct cfg80211_scan_request *scan_req; 2271 struct ieee80211_scan_ies *scan_ies; 2272 }; 2273 2274 enum rtw89_lv1_rcvy_step { 2275 RTW89_LV1_RCVY_STEP_1, 2276 RTW89_LV1_RCVY_STEP_2, 2277 }; 2278 2279 struct rtw89_hci_ops { 2280 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2281 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2282 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2283 void (*reset)(struct rtw89_dev *rtwdev); 2284 int (*start)(struct rtw89_dev *rtwdev); 2285 void (*stop)(struct rtw89_dev *rtwdev); 2286 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2287 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2288 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2289 2290 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2291 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2292 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2293 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2294 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2295 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2296 2297 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2298 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2299 int (*deinit)(struct rtw89_dev *rtwdev); 2300 2301 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2302 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2303 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2304 int (*napi_poll)(struct napi_struct *napi, int budget); 2305 2306 /* Deal with locks inside recovery_start and recovery_complete callbacks 2307 * by hci instance, and handle things which need to consider under SER. 2308 * e.g. turn on/off interrupts except for the one for halt notification. 2309 */ 2310 void (*recovery_start)(struct rtw89_dev *rtwdev); 2311 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2312 2313 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 2314 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 2315 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 2316 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 2317 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 2318 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 2319 void (*disable_intr)(struct rtw89_dev *rtwdev); 2320 void (*enable_intr)(struct rtw89_dev *rtwdev); 2321 int (*rst_bdram)(struct rtw89_dev *rtwdev); 2322 }; 2323 2324 struct rtw89_hci_info { 2325 const struct rtw89_hci_ops *ops; 2326 enum rtw89_hci_type type; 2327 u32 rpwm_addr; 2328 u32 cpwm_addr; 2329 bool paused; 2330 }; 2331 2332 struct rtw89_chip_ops { 2333 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2334 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2335 void (*bb_reset)(struct rtw89_dev *rtwdev, 2336 enum rtw89_phy_idx phy_idx); 2337 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2338 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2339 u32 addr, u32 mask); 2340 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2341 u32 addr, u32 mask, u32 data); 2342 void (*set_channel)(struct rtw89_dev *rtwdev, 2343 const struct rtw89_chan *chan, 2344 enum rtw89_mac_idx mac_idx, 2345 enum rtw89_phy_idx phy_idx); 2346 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2347 struct rtw89_channel_help_params *p, 2348 const struct rtw89_chan *chan, 2349 enum rtw89_mac_idx mac_idx, 2350 enum rtw89_phy_idx phy_idx); 2351 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2352 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2353 void (*fem_setup)(struct rtw89_dev *rtwdev); 2354 void (*rfk_init)(struct rtw89_dev *rtwdev); 2355 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2356 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2357 enum rtw89_phy_idx phy_idx); 2358 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2359 void (*rfk_track)(struct rtw89_dev *rtwdev); 2360 void (*power_trim)(struct rtw89_dev *rtwdev); 2361 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2362 const struct rtw89_chan *chan, 2363 enum rtw89_phy_idx phy_idx); 2364 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2365 enum rtw89_phy_idx phy_idx); 2366 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2367 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2368 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2369 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2370 struct rtw89_rx_phy_ppdu *phy_ppdu, 2371 struct ieee80211_rx_status *status); 2372 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2373 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2374 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2375 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2376 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2377 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2378 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2379 struct rtw89_tx_desc_info *desc_info, 2380 void *txdesc); 2381 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2382 struct rtw89_tx_desc_info *desc_info, 2383 void *txdesc); 2384 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2385 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2386 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2387 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2388 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2389 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2390 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2391 struct rtw89_vif *rtwvif, 2392 struct rtw89_sta *rtwsta); 2393 2394 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2395 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2396 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2397 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2398 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2399 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2400 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2401 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2402 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2403 }; 2404 2405 enum rtw89_dma_ch { 2406 RTW89_DMA_ACH0 = 0, 2407 RTW89_DMA_ACH1 = 1, 2408 RTW89_DMA_ACH2 = 2, 2409 RTW89_DMA_ACH3 = 3, 2410 RTW89_DMA_ACH4 = 4, 2411 RTW89_DMA_ACH5 = 5, 2412 RTW89_DMA_ACH6 = 6, 2413 RTW89_DMA_ACH7 = 7, 2414 RTW89_DMA_B0MG = 8, 2415 RTW89_DMA_B0HI = 9, 2416 RTW89_DMA_B1MG = 10, 2417 RTW89_DMA_B1HI = 11, 2418 RTW89_DMA_H2C = 12, 2419 RTW89_DMA_CH_NUM = 13 2420 }; 2421 2422 enum rtw89_qta_mode { 2423 RTW89_QTA_SCC, 2424 RTW89_QTA_DLFW, 2425 RTW89_QTA_WOW, 2426 2427 /* keep last */ 2428 RTW89_QTA_INVALID, 2429 }; 2430 2431 struct rtw89_hfc_ch_cfg { 2432 u16 min; 2433 u16 max; 2434 #define grp_0 0 2435 #define grp_1 1 2436 #define grp_num 2 2437 u8 grp; 2438 }; 2439 2440 struct rtw89_hfc_ch_info { 2441 u16 aval; 2442 u16 used; 2443 }; 2444 2445 struct rtw89_hfc_pub_cfg { 2446 u16 grp0; 2447 u16 grp1; 2448 u16 pub_max; 2449 u16 wp_thrd; 2450 }; 2451 2452 struct rtw89_hfc_pub_info { 2453 u16 g0_used; 2454 u16 g1_used; 2455 u16 g0_aval; 2456 u16 g1_aval; 2457 u16 pub_aval; 2458 u16 wp_aval; 2459 }; 2460 2461 struct rtw89_hfc_prec_cfg { 2462 u16 ch011_prec; 2463 u16 h2c_prec; 2464 u16 wp_ch07_prec; 2465 u16 wp_ch811_prec; 2466 u8 ch011_full_cond; 2467 u8 h2c_full_cond; 2468 u8 wp_ch07_full_cond; 2469 u8 wp_ch811_full_cond; 2470 }; 2471 2472 struct rtw89_hfc_param { 2473 bool en; 2474 bool h2c_en; 2475 u8 mode; 2476 const struct rtw89_hfc_ch_cfg *ch_cfg; 2477 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2478 struct rtw89_hfc_pub_cfg pub_cfg; 2479 struct rtw89_hfc_pub_info pub_info; 2480 struct rtw89_hfc_prec_cfg prec_cfg; 2481 }; 2482 2483 struct rtw89_hfc_param_ini { 2484 const struct rtw89_hfc_ch_cfg *ch_cfg; 2485 const struct rtw89_hfc_pub_cfg *pub_cfg; 2486 const struct rtw89_hfc_prec_cfg *prec_cfg; 2487 u8 mode; 2488 }; 2489 2490 struct rtw89_dle_size { 2491 u16 pge_size; 2492 u16 lnk_pge_num; 2493 u16 unlnk_pge_num; 2494 }; 2495 2496 struct rtw89_wde_quota { 2497 u16 hif; 2498 u16 wcpu; 2499 u16 pkt_in; 2500 u16 cpu_io; 2501 }; 2502 2503 struct rtw89_ple_quota { 2504 u16 cma0_tx; 2505 u16 cma1_tx; 2506 u16 c2h; 2507 u16 h2c; 2508 u16 wcpu; 2509 u16 mpdu_proc; 2510 u16 cma0_dma; 2511 u16 cma1_dma; 2512 u16 bb_rpt; 2513 u16 wd_rel; 2514 u16 cpu_io; 2515 u16 tx_rpt; 2516 }; 2517 2518 struct rtw89_dle_mem { 2519 enum rtw89_qta_mode mode; 2520 const struct rtw89_dle_size *wde_size; 2521 const struct rtw89_dle_size *ple_size; 2522 const struct rtw89_wde_quota *wde_min_qt; 2523 const struct rtw89_wde_quota *wde_max_qt; 2524 const struct rtw89_ple_quota *ple_min_qt; 2525 const struct rtw89_ple_quota *ple_max_qt; 2526 }; 2527 2528 struct rtw89_reg_def { 2529 u32 addr; 2530 u32 mask; 2531 }; 2532 2533 struct rtw89_reg2_def { 2534 u32 addr; 2535 u32 data; 2536 }; 2537 2538 struct rtw89_reg3_def { 2539 u32 addr; 2540 u32 mask; 2541 u32 data; 2542 }; 2543 2544 struct rtw89_reg5_def { 2545 u8 flag; /* recognized by parsers */ 2546 u8 path; 2547 u32 addr; 2548 u32 mask; 2549 u32 data; 2550 }; 2551 2552 struct rtw89_phy_table { 2553 const struct rtw89_reg2_def *regs; 2554 u32 n_regs; 2555 enum rtw89_rf_path rf_path; 2556 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2557 enum rtw89_rf_path rf_path, void *data); 2558 }; 2559 2560 struct rtw89_txpwr_table { 2561 const void *data; 2562 u32 size; 2563 void (*load)(struct rtw89_dev *rtwdev, 2564 const struct rtw89_txpwr_table *tbl); 2565 }; 2566 2567 struct rtw89_page_regs { 2568 u32 hci_fc_ctrl; 2569 u32 ch_page_ctrl; 2570 u32 ach_page_ctrl; 2571 u32 ach_page_info; 2572 u32 pub_page_info3; 2573 u32 pub_page_ctrl1; 2574 u32 pub_page_ctrl2; 2575 u32 pub_page_info1; 2576 u32 pub_page_info2; 2577 u32 wp_page_ctrl1; 2578 u32 wp_page_ctrl2; 2579 u32 wp_page_info1; 2580 }; 2581 2582 struct rtw89_imr_info { 2583 u32 wdrls_imr_set; 2584 u32 wsec_imr_reg; 2585 u32 wsec_imr_set; 2586 u32 mpdu_tx_imr_set; 2587 u32 mpdu_rx_imr_set; 2588 u32 sta_sch_imr_set; 2589 u32 txpktctl_imr_b0_reg; 2590 u32 txpktctl_imr_b0_clr; 2591 u32 txpktctl_imr_b0_set; 2592 u32 txpktctl_imr_b1_reg; 2593 u32 txpktctl_imr_b1_clr; 2594 u32 txpktctl_imr_b1_set; 2595 u32 wde_imr_clr; 2596 u32 wde_imr_set; 2597 u32 ple_imr_clr; 2598 u32 ple_imr_set; 2599 u32 host_disp_imr_clr; 2600 u32 host_disp_imr_set; 2601 u32 cpu_disp_imr_clr; 2602 u32 cpu_disp_imr_set; 2603 u32 other_disp_imr_clr; 2604 u32 other_disp_imr_set; 2605 u32 bbrpt_com_err_imr_reg; 2606 u32 bbrpt_chinfo_err_imr_reg; 2607 u32 bbrpt_err_imr_set; 2608 u32 bbrpt_dfs_err_imr_reg; 2609 u32 ptcl_imr_clr; 2610 u32 ptcl_imr_set; 2611 u32 cdma_imr_0_reg; 2612 u32 cdma_imr_0_clr; 2613 u32 cdma_imr_0_set; 2614 u32 cdma_imr_1_reg; 2615 u32 cdma_imr_1_clr; 2616 u32 cdma_imr_1_set; 2617 u32 phy_intf_imr_reg; 2618 u32 phy_intf_imr_clr; 2619 u32 phy_intf_imr_set; 2620 u32 rmac_imr_reg; 2621 u32 rmac_imr_clr; 2622 u32 rmac_imr_set; 2623 u32 tmac_imr_reg; 2624 u32 tmac_imr_clr; 2625 u32 tmac_imr_set; 2626 }; 2627 2628 struct rtw89_rrsr_cfgs { 2629 struct rtw89_reg3_def ref_rate; 2630 struct rtw89_reg3_def rsc; 2631 }; 2632 2633 struct rtw89_dig_regs { 2634 u32 seg0_pd_reg; 2635 u32 pd_lower_bound_mask; 2636 u32 pd_spatial_reuse_en; 2637 struct rtw89_reg_def p0_lna_init; 2638 struct rtw89_reg_def p1_lna_init; 2639 struct rtw89_reg_def p0_tia_init; 2640 struct rtw89_reg_def p1_tia_init; 2641 struct rtw89_reg_def p0_rxb_init; 2642 struct rtw89_reg_def p1_rxb_init; 2643 struct rtw89_reg_def p0_p20_pagcugc_en; 2644 struct rtw89_reg_def p0_s20_pagcugc_en; 2645 struct rtw89_reg_def p1_p20_pagcugc_en; 2646 struct rtw89_reg_def p1_s20_pagcugc_en; 2647 }; 2648 2649 struct rtw89_chip_info { 2650 enum rtw89_core_chip_id chip_id; 2651 const struct rtw89_chip_ops *ops; 2652 const char *fw_name; 2653 u32 fifo_size; 2654 u32 dle_scc_rsvd_size; 2655 u16 max_amsdu_limit; 2656 bool dis_2g_40m_ul_ofdma; 2657 u32 rsvd_ple_ofst; 2658 const struct rtw89_hfc_param_ini *hfc_param_ini; 2659 const struct rtw89_dle_mem *dle_mem; 2660 u8 wde_qempty_acq_num; 2661 u8 wde_qempty_mgq_sel; 2662 u32 rf_base_addr[2]; 2663 u8 support_chanctx_num; 2664 u8 support_bands; 2665 bool support_bw160; 2666 bool hw_sec_hdr; 2667 u8 rf_path_num; 2668 u8 tx_nss; 2669 u8 rx_nss; 2670 u8 acam_num; 2671 u8 bcam_num; 2672 u8 scam_num; 2673 u8 bacam_num; 2674 u8 bacam_dynamic_num; 2675 bool bacam_v1; 2676 2677 u8 sec_ctrl_efuse_size; 2678 u32 physical_efuse_size; 2679 u32 logical_efuse_size; 2680 u32 limit_efuse_size; 2681 u32 dav_phy_efuse_size; 2682 u32 dav_log_efuse_size; 2683 u32 phycap_addr; 2684 u32 phycap_size; 2685 2686 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2687 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2688 const struct rtw89_phy_table *bb_table; 2689 const struct rtw89_phy_table *bb_gain_table; 2690 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2691 const struct rtw89_phy_table *nctl_table; 2692 const struct rtw89_txpwr_table *byr_table; 2693 const struct rtw89_phy_dig_gain_table *dig_table; 2694 const struct rtw89_dig_regs *dig_regs; 2695 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2696 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2697 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2698 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2699 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2700 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2701 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2702 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2703 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2704 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2705 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2706 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2707 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2708 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2709 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2710 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2711 2712 u8 txpwr_factor_rf; 2713 u8 txpwr_factor_mac; 2714 2715 u32 para_ver; 2716 u32 wlcx_desired; 2717 u8 btcx_desired; 2718 u8 scbd; 2719 u8 mailbox; 2720 u16 btc_fwinfo_buf; 2721 2722 u8 fcxbtcrpt_ver; 2723 u8 fcxtdma_ver; 2724 u8 fcxslots_ver; 2725 u8 fcxcysta_ver; 2726 u8 fcxstep_ver; 2727 u8 fcxnullsta_ver; 2728 u8 fcxmreg_ver; 2729 u8 fcxgpiodbg_ver; 2730 u8 fcxbtver_ver; 2731 u8 fcxbtscan_ver; 2732 u8 fcxbtafh_ver; 2733 u8 fcxbtdevinfo_ver; 2734 2735 u8 afh_guard_ch; 2736 const u8 *wl_rssi_thres; 2737 const u8 *bt_rssi_thres; 2738 u8 rssi_tol; 2739 2740 u8 mon_reg_num; 2741 const struct rtw89_btc_fbtc_mreg *mon_reg; 2742 u8 rf_para_ulink_num; 2743 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2744 u8 rf_para_dlink_num; 2745 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2746 u8 ps_mode_supported; 2747 u8 low_power_hci_modes; 2748 2749 u32 h2c_cctl_func_id; 2750 u32 hci_func_en_addr; 2751 u32 h2c_desc_size; 2752 u32 txwd_body_size; 2753 u32 h2c_ctrl_reg; 2754 const u32 *h2c_regs; 2755 u32 c2h_ctrl_reg; 2756 const u32 *c2h_regs; 2757 const struct rtw89_page_regs *page_regs; 2758 const struct rtw89_reg_def *dcfo_comp; 2759 u8 dcfo_comp_sft; 2760 const struct rtw89_imr_info *imr_info; 2761 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 2762 u32 dma_ch_mask; 2763 const struct wiphy_wowlan_support *wowlan_stub; 2764 }; 2765 2766 union rtw89_bus_info { 2767 const struct rtw89_pci_info *pci; 2768 }; 2769 2770 struct rtw89_driver_info { 2771 const struct rtw89_chip_info *chip; 2772 union rtw89_bus_info bus; 2773 }; 2774 2775 enum rtw89_hcifc_mode { 2776 RTW89_HCIFC_POH = 0, 2777 RTW89_HCIFC_STF = 1, 2778 RTW89_HCIFC_SDIO = 2, 2779 2780 /* keep last */ 2781 RTW89_HCIFC_MODE_INVALID, 2782 }; 2783 2784 struct rtw89_dle_info { 2785 enum rtw89_qta_mode qta_mode; 2786 u16 wde_pg_size; 2787 u16 ple_pg_size; 2788 u16 c0_rx_qta; 2789 u16 c1_rx_qta; 2790 }; 2791 2792 enum rtw89_host_rpr_mode { 2793 RTW89_RPR_MODE_POH = 0, 2794 RTW89_RPR_MODE_STF 2795 }; 2796 2797 struct rtw89_mac_info { 2798 struct rtw89_dle_info dle_info; 2799 struct rtw89_hfc_param hfc_param; 2800 enum rtw89_qta_mode qta_mode; 2801 u8 rpwm_seq_num; 2802 u8 cpwm_seq_num; 2803 }; 2804 2805 enum rtw89_fw_type { 2806 RTW89_FW_NORMAL = 1, 2807 RTW89_FW_WOWLAN = 3, 2808 }; 2809 2810 enum rtw89_fw_feature { 2811 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 2812 RTW89_FW_FEATURE_SCAN_OFFLOAD, 2813 RTW89_FW_FEATURE_TX_WAKE, 2814 RTW89_FW_FEATURE_CRASH_TRIGGER, 2815 RTW89_FW_FEATURE_PACKET_DROP, 2816 RTW89_FW_FEATURE_NO_DEEP_PS, 2817 }; 2818 2819 struct rtw89_fw_suit { 2820 const u8 *data; 2821 u32 size; 2822 u8 major_ver; 2823 u8 minor_ver; 2824 u8 sub_ver; 2825 u8 sub_idex; 2826 u16 build_year; 2827 u16 build_mon; 2828 u16 build_date; 2829 u16 build_hour; 2830 u16 build_min; 2831 u8 cmd_ver; 2832 }; 2833 2834 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2835 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2836 #define RTW89_FW_SUIT_VER_CODE(s) \ 2837 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2838 2839 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 2840 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 2841 (mfw_hdr)->ver.minor, \ 2842 (mfw_hdr)->ver.sub, \ 2843 (mfw_hdr)->ver.idx) 2844 2845 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 2846 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 2847 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 2848 GET_FW_HDR_SUBVERSION(fw_hdr), \ 2849 GET_FW_HDR_SUBINDEX(fw_hdr)) 2850 2851 struct rtw89_fw_info { 2852 const struct firmware *firmware; 2853 struct rtw89_dev *rtwdev; 2854 struct completion completion; 2855 u8 h2c_seq; 2856 u8 rec_seq; 2857 struct rtw89_fw_suit normal; 2858 struct rtw89_fw_suit wowlan; 2859 bool fw_log_enable; 2860 u32 feature_map; 2861 }; 2862 2863 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 2864 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 2865 2866 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 2867 ((_fw)->feature_map |= BIT(_fw_feature)) 2868 2869 struct rtw89_cam_info { 2870 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2871 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2872 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2873 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 2874 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 2875 }; 2876 2877 enum rtw89_sar_sources { 2878 RTW89_SAR_SOURCE_NONE, 2879 RTW89_SAR_SOURCE_COMMON, 2880 2881 RTW89_SAR_SOURCE_NR, 2882 }; 2883 2884 enum rtw89_sar_subband { 2885 RTW89_SAR_2GHZ_SUBBAND, 2886 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 2887 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 2888 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 2889 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 2890 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 2891 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 2892 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 2893 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 2894 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 2895 2896 RTW89_SAR_SUBBAND_NR, 2897 }; 2898 2899 struct rtw89_sar_cfg_common { 2900 bool set[RTW89_SAR_SUBBAND_NR]; 2901 s32 cfg[RTW89_SAR_SUBBAND_NR]; 2902 }; 2903 2904 struct rtw89_sar_info { 2905 /* used to decide how to acces SAR cfg union */ 2906 enum rtw89_sar_sources src; 2907 2908 /* reserved for different knids of SAR cfg struct. 2909 * supposed that a single cfg struct cannot handle various SAR sources. 2910 */ 2911 union { 2912 struct rtw89_sar_cfg_common cfg_common; 2913 }; 2914 }; 2915 2916 struct rtw89_chanctx_cfg { 2917 enum rtw89_sub_entity_idx idx; 2918 }; 2919 2920 enum rtw89_entity_mode { 2921 RTW89_ENTITY_MODE_SCC, 2922 }; 2923 2924 struct rtw89_hal { 2925 u32 rx_fltr; 2926 u8 cv; 2927 u32 sw_amsdu_max_size; 2928 u32 antenna_tx; 2929 u32 antenna_rx; 2930 u8 tx_nss; 2931 u8 rx_nss; 2932 bool tx_path_diversity; 2933 bool support_cckpd; 2934 bool support_igi; 2935 2936 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 2937 struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY]; 2938 2939 bool entity_active; 2940 enum rtw89_entity_mode entity_mode; 2941 2942 struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY]; 2943 struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY]; 2944 }; 2945 2946 #define RTW89_MAX_MAC_ID_NUM 128 2947 #define RTW89_MAX_PKT_OFLD_NUM 255 2948 2949 enum rtw89_flags { 2950 RTW89_FLAG_POWERON, 2951 RTW89_FLAG_FW_RDY, 2952 RTW89_FLAG_RUNNING, 2953 RTW89_FLAG_BFEE_MON, 2954 RTW89_FLAG_BFEE_EN, 2955 RTW89_FLAG_NAPI_RUNNING, 2956 RTW89_FLAG_LEISURE_PS, 2957 RTW89_FLAG_LOW_POWER_MODE, 2958 RTW89_FLAG_INACTIVE_PS, 2959 RTW89_FLAG_CRASH_SIMULATING, 2960 RTW89_FLAG_WOWLAN, 2961 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 2962 2963 NUM_OF_RTW89_FLAGS, 2964 }; 2965 2966 enum rtw89_pkt_drop_sel { 2967 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 2968 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 2969 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 2970 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 2971 RTW89_PKT_DROP_SEL_MACID_ALL, 2972 RTW89_PKT_DROP_SEL_MG0_ONCE, 2973 RTW89_PKT_DROP_SEL_HIQ_ONCE, 2974 RTW89_PKT_DROP_SEL_HIQ_PORT, 2975 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 2976 RTW89_PKT_DROP_SEL_BAND, 2977 RTW89_PKT_DROP_SEL_BAND_ONCE, 2978 RTW89_PKT_DROP_SEL_REL_MACID, 2979 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 2980 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 2981 }; 2982 2983 struct rtw89_pkt_drop_params { 2984 enum rtw89_pkt_drop_sel sel; 2985 enum rtw89_mac_idx mac_band; 2986 u8 macid; 2987 u8 port; 2988 u8 mbssid; 2989 bool tf_trs; 2990 u32 macid_band_sel[4]; 2991 }; 2992 2993 struct rtw89_pkt_stat { 2994 u16 beacon_nr; 2995 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2996 }; 2997 2998 DECLARE_EWMA(thermal, 4, 4); 2999 3000 struct rtw89_phy_stat { 3001 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 3002 struct rtw89_pkt_stat cur_pkt_stat; 3003 struct rtw89_pkt_stat last_pkt_stat; 3004 }; 3005 3006 #define RTW89_DACK_PATH_NR 2 3007 #define RTW89_DACK_IDX_NR 2 3008 #define RTW89_DACK_MSBK_NR 16 3009 struct rtw89_dack_info { 3010 bool dack_done; 3011 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 3012 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3013 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3014 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3015 u32 dack_cnt; 3016 bool addck_timeout[RTW89_DACK_PATH_NR]; 3017 bool dadck_timeout[RTW89_DACK_PATH_NR]; 3018 bool msbk_timeout[RTW89_DACK_PATH_NR]; 3019 }; 3020 3021 #define RTW89_IQK_CHS_NR 2 3022 #define RTW89_IQK_PATH_NR 4 3023 3024 struct rtw89_mcc_info { 3025 u8 ch[RTW89_IQK_CHS_NR]; 3026 u8 band[RTW89_IQK_CHS_NR]; 3027 u8 table_idx; 3028 }; 3029 3030 struct rtw89_lck_info { 3031 u8 thermal[RF_PATH_MAX]; 3032 }; 3033 3034 struct rtw89_rx_dck_info { 3035 u8 thermal[RF_PATH_MAX]; 3036 }; 3037 3038 struct rtw89_iqk_info { 3039 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3040 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3041 bool lok_fail[RTW89_IQK_PATH_NR]; 3042 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3043 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3044 u32 iqk_fail_cnt; 3045 bool is_iqk_init; 3046 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3047 u8 iqk_band[RTW89_IQK_PATH_NR]; 3048 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3049 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3050 u8 kcount; 3051 u8 iqk_times; 3052 u8 version; 3053 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3054 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3055 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3056 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3057 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3058 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3059 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3060 bool is_nbiqk; 3061 bool iqk_fft_en; 3062 bool iqk_xym_en; 3063 bool iqk_sram_en; 3064 bool iqk_cfir_en; 3065 u8 thermal[RTW89_IQK_PATH_NR]; 3066 bool thermal_rek_en; 3067 u32 syn1to2; 3068 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3069 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3070 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3071 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3072 }; 3073 3074 #define RTW89_DPK_RF_PATH 2 3075 #define RTW89_DPK_AVG_THERMAL_NUM 8 3076 #define RTW89_DPK_BKUP_NUM 2 3077 struct rtw89_dpk_bkup_para { 3078 enum rtw89_band band; 3079 enum rtw89_bandwidth bw; 3080 u8 ch; 3081 bool path_ok; 3082 u8 mdpd_en; 3083 u8 txagc_dpk; 3084 u8 ther_dpk; 3085 u8 gs; 3086 u16 pwsf; 3087 }; 3088 3089 struct rtw89_dpk_info { 3090 bool is_dpk_enable; 3091 bool is_dpk_reload_en; 3092 u8 dpk_gs[RTW89_PHY_MAX]; 3093 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3094 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3095 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3096 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3097 u8 cur_idx[RTW89_DPK_RF_PATH]; 3098 u8 cur_k_set; 3099 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3100 }; 3101 3102 struct rtw89_fem_info { 3103 bool elna_2g; 3104 bool elna_5g; 3105 bool epa_2g; 3106 bool epa_5g; 3107 bool epa_6g; 3108 }; 3109 3110 struct rtw89_phy_ch_info { 3111 u8 rssi_min; 3112 u16 rssi_min_macid; 3113 u8 pre_rssi_min; 3114 u8 rssi_max; 3115 u16 rssi_max_macid; 3116 u8 rxsc_160; 3117 u8 rxsc_80; 3118 u8 rxsc_40; 3119 u8 rxsc_20; 3120 u8 rxsc_l; 3121 u8 is_noisy; 3122 }; 3123 3124 struct rtw89_agc_gaincode_set { 3125 u8 lna_idx; 3126 u8 tia_idx; 3127 u8 rxb_idx; 3128 }; 3129 3130 #define IGI_RSSI_TH_NUM 5 3131 #define FA_TH_NUM 4 3132 #define LNA_GAIN_NUM 7 3133 #define TIA_GAIN_NUM 2 3134 struct rtw89_dig_info { 3135 struct rtw89_agc_gaincode_set cur_gaincode; 3136 bool force_gaincode_idx_en; 3137 struct rtw89_agc_gaincode_set force_gaincode; 3138 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3139 u16 fa_th[FA_TH_NUM]; 3140 u8 igi_rssi; 3141 u8 igi_fa_rssi; 3142 u8 fa_rssi_ofst; 3143 u8 dyn_igi_max; 3144 u8 dyn_igi_min; 3145 bool dyn_pd_th_en; 3146 u8 dyn_pd_th_max; 3147 u8 pd_low_th_ofst; 3148 u8 ib_pbk; 3149 s8 ib_pkpwr; 3150 s8 lna_gain_a[LNA_GAIN_NUM]; 3151 s8 lna_gain_g[LNA_GAIN_NUM]; 3152 s8 *lna_gain; 3153 s8 tia_gain_a[TIA_GAIN_NUM]; 3154 s8 tia_gain_g[TIA_GAIN_NUM]; 3155 s8 *tia_gain; 3156 bool is_linked_pre; 3157 bool bypass_dig; 3158 }; 3159 3160 enum rtw89_multi_cfo_mode { 3161 RTW89_PKT_BASED_AVG_MODE = 0, 3162 RTW89_ENTRY_BASED_AVG_MODE = 1, 3163 RTW89_TP_BASED_AVG_MODE = 2, 3164 }; 3165 3166 enum rtw89_phy_cfo_status { 3167 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3168 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3169 RTW89_PHY_DCFO_STATE_HOLD = 2, 3170 RTW89_PHY_DCFO_STATE_MAX 3171 }; 3172 3173 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3174 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3175 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3176 }; 3177 3178 struct rtw89_cfo_tracking_info { 3179 u16 cfo_timer_ms; 3180 bool cfo_trig_by_timer_en; 3181 enum rtw89_phy_cfo_status phy_cfo_status; 3182 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3183 u8 phy_cfo_trk_cnt; 3184 bool is_adjust; 3185 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3186 bool apply_compensation; 3187 u8 crystal_cap; 3188 u8 crystal_cap_default; 3189 u8 def_x_cap; 3190 s8 x_cap_ofst; 3191 u32 sta_cfo_tolerance; 3192 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3193 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3194 s32 cfo_avg_pre; 3195 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3196 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3197 u32 packet_count; 3198 u32 packet_count_pre; 3199 s32 residual_cfo_acc; 3200 u8 phy_cfotrk_state; 3201 u8 phy_cfotrk_cnt; 3202 bool divergence_lock_en; 3203 u8 x_cap_lb; 3204 u8 x_cap_ub; 3205 u8 lock_cnt; 3206 }; 3207 3208 enum rtw89_tssi_alimk_band { 3209 TSSI_ALIMK_2G = 0, 3210 TSSI_ALIMK_5GL, 3211 TSSI_ALIMK_5GM, 3212 TSSI_ALIMK_5GH, 3213 TSSI_ALIMK_MAX 3214 }; 3215 3216 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3217 #define TSSI_TRIM_CH_GROUP_NUM 8 3218 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3219 3220 #define TSSI_CCK_CH_GROUP_NUM 6 3221 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3222 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3223 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3224 #define TSSI_MCS_CH_GROUP_NUM \ 3225 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3226 #define TSSI_MAX_CH_NUM 67 3227 #define TSSI_ALIMK_VALUE_NUM 8 3228 3229 struct rtw89_tssi_info { 3230 u8 thermal[RF_PATH_MAX]; 3231 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3232 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3233 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3234 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3235 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3236 s8 extra_ofst[RF_PATH_MAX]; 3237 bool tssi_tracking_check[RF_PATH_MAX]; 3238 u8 default_txagc_offset[RF_PATH_MAX]; 3239 u32 base_thermal[RF_PATH_MAX]; 3240 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 3241 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 3242 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 3243 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 3244 u32 tssi_alimk_time; 3245 }; 3246 3247 struct rtw89_power_trim_info { 3248 bool pg_thermal_trim; 3249 bool pg_pa_bias_trim; 3250 u8 thermal_trim[RF_PATH_MAX]; 3251 u8 pa_bias_trim[RF_PATH_MAX]; 3252 }; 3253 3254 struct rtw89_regulatory { 3255 char alpha2[3]; 3256 u8 txpwr_regd[RTW89_BAND_MAX]; 3257 }; 3258 3259 enum rtw89_ifs_clm_application { 3260 RTW89_IFS_CLM_INIT = 0, 3261 RTW89_IFS_CLM_BACKGROUND = 1, 3262 RTW89_IFS_CLM_ACS = 2, 3263 RTW89_IFS_CLM_DIG = 3, 3264 RTW89_IFS_CLM_TDMA_DIG = 4, 3265 RTW89_IFS_CLM_DBG = 5, 3266 RTW89_IFS_CLM_DBG_MANUAL = 6 3267 }; 3268 3269 enum rtw89_env_racing_lv { 3270 RTW89_RAC_RELEASE = 0, 3271 RTW89_RAC_LV_1 = 1, 3272 RTW89_RAC_LV_2 = 2, 3273 RTW89_RAC_LV_3 = 3, 3274 RTW89_RAC_LV_4 = 4, 3275 RTW89_RAC_MAX_NUM = 5 3276 }; 3277 3278 struct rtw89_ccx_para_info { 3279 enum rtw89_env_racing_lv rac_lv; 3280 u16 mntr_time; 3281 u8 nhm_manual_th_ofst; 3282 u8 nhm_manual_th0; 3283 enum rtw89_ifs_clm_application ifs_clm_app; 3284 u32 ifs_clm_manual_th_times; 3285 u32 ifs_clm_manual_th0; 3286 u8 fahm_manual_th_ofst; 3287 u8 fahm_manual_th0; 3288 u8 fahm_numer_opt; 3289 u8 fahm_denom_opt; 3290 }; 3291 3292 enum rtw89_ccx_edcca_opt_sc_idx { 3293 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3294 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3295 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3296 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3297 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3298 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3299 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3300 RTW89_CCX_EDCCA_SEG1_S3 = 7 3301 }; 3302 3303 enum rtw89_ccx_edcca_opt_bw_idx { 3304 RTW89_CCX_EDCCA_BW20_0 = 0, 3305 RTW89_CCX_EDCCA_BW20_1 = 1, 3306 RTW89_CCX_EDCCA_BW20_2 = 2, 3307 RTW89_CCX_EDCCA_BW20_3 = 3, 3308 RTW89_CCX_EDCCA_BW20_4 = 4, 3309 RTW89_CCX_EDCCA_BW20_5 = 5, 3310 RTW89_CCX_EDCCA_BW20_6 = 6, 3311 RTW89_CCX_EDCCA_BW20_7 = 7 3312 }; 3313 3314 #define RTW89_NHM_TH_NUM 11 3315 #define RTW89_FAHM_TH_NUM 11 3316 #define RTW89_NHM_RPT_NUM 12 3317 #define RTW89_FAHM_RPT_NUM 12 3318 #define RTW89_IFS_CLM_NUM 4 3319 struct rtw89_env_monitor_info { 3320 u32 ccx_trigger_time; 3321 u64 start_time; 3322 u8 ccx_rpt_stamp; 3323 u8 ccx_watchdog_result; 3324 bool ccx_ongoing; 3325 u8 ccx_rac_lv; 3326 bool ccx_manual_ctrl; 3327 u8 ccx_pre_rssi; 3328 u16 clm_mntr_time; 3329 u16 nhm_mntr_time; 3330 u16 ifs_clm_mntr_time; 3331 enum rtw89_ifs_clm_application ifs_clm_app; 3332 u16 fahm_mntr_time; 3333 u16 edcca_clm_mntr_time; 3334 u16 ccx_period; 3335 u8 ccx_unit_idx; 3336 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3337 u8 nhm_th[RTW89_NHM_TH_NUM]; 3338 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3339 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3340 u8 fahm_numer_opt; 3341 u8 fahm_denom_opt; 3342 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3343 u16 clm_result; 3344 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3345 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3346 u16 nhm_tx_cnt; 3347 u16 nhm_cca_cnt; 3348 u16 nhm_idle_cnt; 3349 u16 ifs_clm_tx; 3350 u16 ifs_clm_edcca_excl_cca; 3351 u16 ifs_clm_ofdmfa; 3352 u16 ifs_clm_ofdmcca_excl_fa; 3353 u16 ifs_clm_cckfa; 3354 u16 ifs_clm_cckcca_excl_fa; 3355 u16 ifs_clm_total_ifs; 3356 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3357 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3358 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3359 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3360 u16 fahm_denom_result; 3361 u16 edcca_clm_result; 3362 u8 clm_ratio; 3363 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3364 u8 nhm_tx_ratio; 3365 u8 nhm_cca_ratio; 3366 u8 nhm_idle_ratio; 3367 u8 nhm_ratio; 3368 u16 nhm_result_sum; 3369 u8 nhm_pwr; 3370 u8 ifs_clm_tx_ratio; 3371 u8 ifs_clm_edcca_excl_cca_ratio; 3372 u8 ifs_clm_cck_fa_ratio; 3373 u8 ifs_clm_ofdm_fa_ratio; 3374 u8 ifs_clm_cck_cca_excl_fa_ratio; 3375 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3376 u16 ifs_clm_cck_fa_permil; 3377 u16 ifs_clm_ofdm_fa_permil; 3378 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3379 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3380 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3381 u16 fahm_result_sum; 3382 u8 fahm_ratio; 3383 u8 fahm_denom_ratio; 3384 u8 fahm_pwr; 3385 u8 edcca_clm_ratio; 3386 }; 3387 3388 enum rtw89_ser_rcvy_step { 3389 RTW89_SER_DRV_STOP_TX, 3390 RTW89_SER_DRV_STOP_RX, 3391 RTW89_SER_DRV_STOP_RUN, 3392 RTW89_SER_HAL_STOP_DMA, 3393 RTW89_NUM_OF_SER_FLAGS 3394 }; 3395 3396 struct rtw89_ser { 3397 u8 state; 3398 u8 alarm_event; 3399 3400 struct work_struct ser_hdl_work; 3401 struct delayed_work ser_alarm_work; 3402 const struct state_ent *st_tbl; 3403 const struct event_ent *ev_tbl; 3404 struct list_head msg_q; 3405 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3406 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3407 }; 3408 3409 enum rtw89_mac_ax_ps_mode { 3410 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3411 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3412 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3413 RTW89_MAC_AX_PS_MODE_MAX = 3, 3414 }; 3415 3416 enum rtw89_last_rpwm_mode { 3417 RTW89_LAST_RPWM_PS = 0x0, 3418 RTW89_LAST_RPWM_ACTIVE = 0x6, 3419 }; 3420 3421 struct rtw89_lps_parm { 3422 u8 macid; 3423 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3424 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3425 }; 3426 3427 struct rtw89_ppdu_sts_info { 3428 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3429 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3430 }; 3431 3432 struct rtw89_early_h2c { 3433 struct list_head list; 3434 u8 *h2c; 3435 u16 h2c_len; 3436 }; 3437 3438 struct rtw89_hw_scan_info { 3439 struct ieee80211_vif *scanning_vif; 3440 struct list_head pkt_list[NUM_NL80211_BANDS]; 3441 u8 op_pri_ch; 3442 u8 op_chan; 3443 u8 op_bw; 3444 u8 op_band; 3445 u32 last_chan_idx; 3446 }; 3447 3448 enum rtw89_phy_bb_gain_band { 3449 RTW89_BB_GAIN_BAND_2G = 0, 3450 RTW89_BB_GAIN_BAND_5G_L = 1, 3451 RTW89_BB_GAIN_BAND_5G_M = 2, 3452 RTW89_BB_GAIN_BAND_5G_H = 3, 3453 RTW89_BB_GAIN_BAND_6G_L = 4, 3454 RTW89_BB_GAIN_BAND_6G_M = 5, 3455 RTW89_BB_GAIN_BAND_6G_H = 6, 3456 RTW89_BB_GAIN_BAND_6G_UH = 7, 3457 3458 RTW89_BB_GAIN_BAND_NR, 3459 }; 3460 3461 enum rtw89_phy_bb_rxsc_num { 3462 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3463 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3464 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3465 }; 3466 3467 struct rtw89_phy_bb_gain_info { 3468 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3469 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3470 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3471 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3472 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3473 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3474 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3475 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3476 [RTW89_BB_RXSC_NUM_40]; 3477 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3478 [RTW89_BB_RXSC_NUM_80]; 3479 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3480 [RTW89_BB_RXSC_NUM_160]; 3481 }; 3482 3483 struct rtw89_phy_efuse_gain { 3484 bool offset_valid; 3485 bool comp_valid; 3486 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3487 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3488 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3489 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 3490 }; 3491 3492 #define RTW89_MAX_PATTERN_NUM 18 3493 #define RTW89_MAX_PATTERN_MASK_SIZE 4 3494 #define RTW89_MAX_PATTERN_SIZE 128 3495 3496 struct rtw89_wow_cam_info { 3497 bool r_w; 3498 u8 idx; 3499 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 3500 u16 crc; 3501 bool negative_pattern_match; 3502 bool skip_mac_hdr; 3503 bool uc; 3504 bool mc; 3505 bool bc; 3506 bool valid; 3507 }; 3508 3509 struct rtw89_wow_param { 3510 struct ieee80211_vif *wow_vif; 3511 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 3512 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 3513 u8 pattern_cnt; 3514 struct list_head pkt_list; 3515 }; 3516 3517 struct rtw89_dev { 3518 struct ieee80211_hw *hw; 3519 struct device *dev; 3520 const struct ieee80211_ops *ops; 3521 3522 bool dbcc_en; 3523 struct rtw89_hw_scan_info scan_info; 3524 const struct rtw89_chip_info *chip; 3525 const struct rtw89_pci_info *pci_info; 3526 struct rtw89_hal hal; 3527 struct rtw89_mac_info mac; 3528 struct rtw89_fw_info fw; 3529 struct rtw89_hci_info hci; 3530 struct rtw89_efuse efuse; 3531 struct rtw89_traffic_stats stats; 3532 3533 /* ensures exclusive access from mac80211 callbacks */ 3534 struct mutex mutex; 3535 struct list_head rtwvifs_list; 3536 /* used to protect rf read write */ 3537 struct mutex rf_mutex; 3538 struct workqueue_struct *txq_wq; 3539 struct work_struct txq_work; 3540 struct delayed_work txq_reinvoke_work; 3541 /* used to protect ba_list and forbid_ba_list */ 3542 spinlock_t ba_lock; 3543 /* txqs to setup ba session */ 3544 struct list_head ba_list; 3545 /* txqs to forbid ba session */ 3546 struct list_head forbid_ba_list; 3547 struct work_struct ba_work; 3548 /* used to protect rpwm */ 3549 spinlock_t rpwm_lock; 3550 3551 struct rtw89_cam_info cam_info; 3552 3553 struct sk_buff_head c2h_queue; 3554 struct work_struct c2h_work; 3555 struct work_struct ips_work; 3556 3557 struct list_head early_h2c_list; 3558 3559 struct rtw89_ser ser; 3560 3561 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3562 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3563 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3564 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3565 3566 struct rtw89_phy_stat phystat; 3567 struct rtw89_dack_info dack; 3568 struct rtw89_iqk_info iqk; 3569 struct rtw89_dpk_info dpk; 3570 struct rtw89_mcc_info mcc; 3571 struct rtw89_lck_info lck; 3572 struct rtw89_rx_dck_info rx_dck; 3573 bool is_tssi_mode[RF_PATH_MAX]; 3574 bool is_bt_iqk_timeout; 3575 3576 struct rtw89_fem_info fem; 3577 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3578 struct rtw89_tssi_info tssi; 3579 struct rtw89_power_trim_info pwr_trim; 3580 3581 struct rtw89_cfo_tracking_info cfo_tracking; 3582 struct rtw89_env_monitor_info env_monitor; 3583 struct rtw89_dig_info dig; 3584 struct rtw89_phy_ch_info ch_info; 3585 struct rtw89_phy_bb_gain_info bb_gain; 3586 struct rtw89_phy_efuse_gain efuse_gain; 3587 3588 struct delayed_work track_work; 3589 struct delayed_work coex_act1_work; 3590 struct delayed_work coex_bt_devinfo_work; 3591 struct delayed_work coex_rfk_chk_work; 3592 struct delayed_work cfo_track_work; 3593 struct delayed_work forbid_ba_work; 3594 struct rtw89_ppdu_sts_info ppdu_sts; 3595 u8 total_sta_assoc; 3596 bool scanning; 3597 3598 const struct rtw89_regulatory *regd; 3599 struct rtw89_sar_info sar; 3600 3601 struct rtw89_btc btc; 3602 enum rtw89_ps_mode ps_mode; 3603 bool lps_enabled; 3604 3605 struct rtw89_wow_param wow; 3606 3607 /* napi structure */ 3608 struct net_device netdev; 3609 struct napi_struct napi; 3610 int napi_budget_countdown; 3611 3612 /* HCI related data, keep last */ 3613 u8 priv[] __aligned(sizeof(void *)); 3614 }; 3615 3616 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3617 struct rtw89_core_tx_request *tx_req) 3618 { 3619 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3620 } 3621 3622 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3623 { 3624 rtwdev->hci.ops->reset(rtwdev); 3625 } 3626 3627 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3628 { 3629 return rtwdev->hci.ops->start(rtwdev); 3630 } 3631 3632 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3633 { 3634 rtwdev->hci.ops->stop(rtwdev); 3635 } 3636 3637 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3638 { 3639 return rtwdev->hci.ops->deinit(rtwdev); 3640 } 3641 3642 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3643 { 3644 rtwdev->hci.ops->pause(rtwdev, pause); 3645 } 3646 3647 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3648 { 3649 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3650 } 3651 3652 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3653 { 3654 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3655 } 3656 3657 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3658 { 3659 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3660 } 3661 3662 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3663 { 3664 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3665 } 3666 3667 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3668 bool drop) 3669 { 3670 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3671 return; 3672 3673 if (rtwdev->hci.ops->flush_queues) 3674 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3675 } 3676 3677 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3678 { 3679 if (rtwdev->hci.ops->recovery_start) 3680 rtwdev->hci.ops->recovery_start(rtwdev); 3681 } 3682 3683 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3684 { 3685 if (rtwdev->hci.ops->recovery_complete) 3686 rtwdev->hci.ops->recovery_complete(rtwdev); 3687 } 3688 3689 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 3690 { 3691 if (rtwdev->hci.ops->enable_intr) 3692 rtwdev->hci.ops->enable_intr(rtwdev); 3693 } 3694 3695 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 3696 { 3697 if (rtwdev->hci.ops->disable_intr) 3698 rtwdev->hci.ops->disable_intr(rtwdev); 3699 } 3700 3701 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 3702 { 3703 if (rtwdev->hci.ops->ctrl_txdma_ch) 3704 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 3705 } 3706 3707 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 3708 { 3709 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 3710 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 3711 } 3712 3713 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 3714 { 3715 if (rtwdev->hci.ops->ctrl_trxhci) 3716 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 3717 } 3718 3719 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 3720 { 3721 int ret = 0; 3722 3723 if (rtwdev->hci.ops->poll_txdma_ch) 3724 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 3725 return ret; 3726 } 3727 3728 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 3729 { 3730 if (rtwdev->hci.ops->clr_idx_all) 3731 rtwdev->hci.ops->clr_idx_all(rtwdev); 3732 } 3733 3734 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 3735 { 3736 int ret = 0; 3737 3738 if (rtwdev->hci.ops->rst_bdram) 3739 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 3740 return ret; 3741 } 3742 3743 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 3744 { 3745 if (rtwdev->hci.ops->clear) 3746 rtwdev->hci.ops->clear(rtwdev, pdev); 3747 } 3748 3749 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3750 { 3751 return rtwdev->hci.ops->read8(rtwdev, addr); 3752 } 3753 3754 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3755 { 3756 return rtwdev->hci.ops->read16(rtwdev, addr); 3757 } 3758 3759 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3760 { 3761 return rtwdev->hci.ops->read32(rtwdev, addr); 3762 } 3763 3764 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3765 { 3766 rtwdev->hci.ops->write8(rtwdev, addr, data); 3767 } 3768 3769 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3770 { 3771 rtwdev->hci.ops->write16(rtwdev, addr, data); 3772 } 3773 3774 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3775 { 3776 rtwdev->hci.ops->write32(rtwdev, addr, data); 3777 } 3778 3779 static inline void 3780 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3781 { 3782 u8 val; 3783 3784 val = rtw89_read8(rtwdev, addr); 3785 rtw89_write8(rtwdev, addr, val | bit); 3786 } 3787 3788 static inline void 3789 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3790 { 3791 u16 val; 3792 3793 val = rtw89_read16(rtwdev, addr); 3794 rtw89_write16(rtwdev, addr, val | bit); 3795 } 3796 3797 static inline void 3798 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3799 { 3800 u32 val; 3801 3802 val = rtw89_read32(rtwdev, addr); 3803 rtw89_write32(rtwdev, addr, val | bit); 3804 } 3805 3806 static inline void 3807 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3808 { 3809 u8 val; 3810 3811 val = rtw89_read8(rtwdev, addr); 3812 rtw89_write8(rtwdev, addr, val & ~bit); 3813 } 3814 3815 static inline void 3816 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3817 { 3818 u16 val; 3819 3820 val = rtw89_read16(rtwdev, addr); 3821 rtw89_write16(rtwdev, addr, val & ~bit); 3822 } 3823 3824 static inline void 3825 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3826 { 3827 u32 val; 3828 3829 val = rtw89_read32(rtwdev, addr); 3830 rtw89_write32(rtwdev, addr, val & ~bit); 3831 } 3832 3833 static inline u32 3834 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3835 { 3836 u32 shift = __ffs(mask); 3837 u32 orig; 3838 u32 ret; 3839 3840 orig = rtw89_read32(rtwdev, addr); 3841 ret = (orig & mask) >> shift; 3842 3843 return ret; 3844 } 3845 3846 static inline u16 3847 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3848 { 3849 u32 shift = __ffs(mask); 3850 u32 orig; 3851 u32 ret; 3852 3853 orig = rtw89_read16(rtwdev, addr); 3854 ret = (orig & mask) >> shift; 3855 3856 return ret; 3857 } 3858 3859 static inline u8 3860 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3861 { 3862 u32 shift = __ffs(mask); 3863 u32 orig; 3864 u32 ret; 3865 3866 orig = rtw89_read8(rtwdev, addr); 3867 ret = (orig & mask) >> shift; 3868 3869 return ret; 3870 } 3871 3872 static inline void 3873 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3874 { 3875 u32 shift = __ffs(mask); 3876 u32 orig; 3877 u32 set; 3878 3879 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3880 3881 orig = rtw89_read32(rtwdev, addr); 3882 set = (orig & ~mask) | ((data << shift) & mask); 3883 rtw89_write32(rtwdev, addr, set); 3884 } 3885 3886 static inline void 3887 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3888 { 3889 u32 shift; 3890 u16 orig, set; 3891 3892 mask &= 0xffff; 3893 shift = __ffs(mask); 3894 3895 orig = rtw89_read16(rtwdev, addr); 3896 set = (orig & ~mask) | ((data << shift) & mask); 3897 rtw89_write16(rtwdev, addr, set); 3898 } 3899 3900 static inline void 3901 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3902 { 3903 u32 shift; 3904 u8 orig, set; 3905 3906 mask &= 0xff; 3907 shift = __ffs(mask); 3908 3909 orig = rtw89_read8(rtwdev, addr); 3910 set = (orig & ~mask) | ((data << shift) & mask); 3911 rtw89_write8(rtwdev, addr, set); 3912 } 3913 3914 static inline u32 3915 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3916 u32 addr, u32 mask) 3917 { 3918 u32 val; 3919 3920 mutex_lock(&rtwdev->rf_mutex); 3921 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3922 mutex_unlock(&rtwdev->rf_mutex); 3923 3924 return val; 3925 } 3926 3927 static inline void 3928 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3929 u32 addr, u32 mask, u32 data) 3930 { 3931 mutex_lock(&rtwdev->rf_mutex); 3932 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3933 mutex_unlock(&rtwdev->rf_mutex); 3934 } 3935 3936 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3937 { 3938 void *p = rtwtxq; 3939 3940 return container_of(p, struct ieee80211_txq, drv_priv); 3941 } 3942 3943 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3944 struct ieee80211_txq *txq) 3945 { 3946 struct rtw89_txq *rtwtxq; 3947 3948 if (!txq) 3949 return; 3950 3951 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3952 INIT_LIST_HEAD(&rtwtxq->list); 3953 } 3954 3955 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3956 { 3957 void *p = rtwvif; 3958 3959 return container_of(p, struct ieee80211_vif, drv_priv); 3960 } 3961 3962 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 3963 { 3964 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 3965 } 3966 3967 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 3968 { 3969 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3970 } 3971 3972 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3973 { 3974 void *p = rtwsta; 3975 3976 return container_of(p, struct ieee80211_sta, drv_priv); 3977 } 3978 3979 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3980 { 3981 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3982 } 3983 3984 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3985 { 3986 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3987 } 3988 3989 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3990 { 3991 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3992 return RATE_INFO_BW_160; 3993 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3994 return RATE_INFO_BW_80; 3995 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3996 return RATE_INFO_BW_40; 3997 else 3998 return RATE_INFO_BW_20; 3999 } 4000 4001 static inline 4002 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 4003 { 4004 switch (hw_band) { 4005 default: 4006 case RTW89_BAND_2G: 4007 return NL80211_BAND_2GHZ; 4008 case RTW89_BAND_5G: 4009 return NL80211_BAND_5GHZ; 4010 case RTW89_BAND_6G: 4011 return NL80211_BAND_6GHZ; 4012 } 4013 } 4014 4015 static inline 4016 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 4017 { 4018 switch (nl_band) { 4019 default: 4020 case NL80211_BAND_2GHZ: 4021 return RTW89_BAND_2G; 4022 case NL80211_BAND_5GHZ: 4023 return RTW89_BAND_5G; 4024 case NL80211_BAND_6GHZ: 4025 return RTW89_BAND_6G; 4026 } 4027 } 4028 4029 static inline 4030 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 4031 { 4032 switch (width) { 4033 default: 4034 WARN(1, "Not support bandwidth %d\n", width); 4035 fallthrough; 4036 case NL80211_CHAN_WIDTH_20_NOHT: 4037 case NL80211_CHAN_WIDTH_20: 4038 return RTW89_CHANNEL_WIDTH_20; 4039 case NL80211_CHAN_WIDTH_40: 4040 return RTW89_CHANNEL_WIDTH_40; 4041 case NL80211_CHAN_WIDTH_80: 4042 return RTW89_CHANNEL_WIDTH_80; 4043 case NL80211_CHAN_WIDTH_160: 4044 return RTW89_CHANNEL_WIDTH_160; 4045 } 4046 } 4047 4048 static inline 4049 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 4050 struct rtw89_sta *rtwsta) 4051 { 4052 if (rtwsta) { 4053 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4054 4055 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 4056 return &rtwsta->addr_cam; 4057 } 4058 return &rtwvif->addr_cam; 4059 } 4060 4061 static inline 4062 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 4063 struct rtw89_sta *rtwsta) 4064 { 4065 if (rtwsta) { 4066 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4067 4068 if (sta->tdls) 4069 return &rtwsta->bssid_cam; 4070 } 4071 return &rtwvif->bssid_cam; 4072 } 4073 4074 static inline 4075 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 4076 struct rtw89_channel_help_params *p, 4077 const struct rtw89_chan *chan, 4078 enum rtw89_mac_idx mac_idx, 4079 enum rtw89_phy_idx phy_idx) 4080 { 4081 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 4082 mac_idx, phy_idx); 4083 } 4084 4085 static inline 4086 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 4087 struct rtw89_channel_help_params *p, 4088 const struct rtw89_chan *chan, 4089 enum rtw89_mac_idx mac_idx, 4090 enum rtw89_phy_idx phy_idx) 4091 { 4092 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 4093 mac_idx, phy_idx); 4094 } 4095 4096 static inline 4097 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 4098 enum rtw89_sub_entity_idx idx) 4099 { 4100 struct rtw89_hal *hal = &rtwdev->hal; 4101 4102 return &hal->chandef[idx]; 4103 } 4104 4105 static inline 4106 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 4107 enum rtw89_sub_entity_idx idx) 4108 { 4109 struct rtw89_hal *hal = &rtwdev->hal; 4110 4111 return &hal->chan[idx]; 4112 } 4113 4114 static inline 4115 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 4116 enum rtw89_sub_entity_idx idx) 4117 { 4118 struct rtw89_hal *hal = &rtwdev->hal; 4119 4120 return &hal->chan_rcd[idx]; 4121 } 4122 4123 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 4124 { 4125 const struct rtw89_chip_info *chip = rtwdev->chip; 4126 4127 if (chip->ops->fem_setup) 4128 chip->ops->fem_setup(rtwdev); 4129 } 4130 4131 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 4132 { 4133 const struct rtw89_chip_info *chip = rtwdev->chip; 4134 4135 if (chip->ops->bb_sethw) 4136 chip->ops->bb_sethw(rtwdev); 4137 } 4138 4139 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 4140 { 4141 const struct rtw89_chip_info *chip = rtwdev->chip; 4142 4143 if (chip->ops->rfk_init) 4144 chip->ops->rfk_init(rtwdev); 4145 } 4146 4147 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4148 { 4149 const struct rtw89_chip_info *chip = rtwdev->chip; 4150 4151 if (chip->ops->rfk_channel) 4152 chip->ops->rfk_channel(rtwdev); 4153 } 4154 4155 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4156 enum rtw89_phy_idx phy_idx) 4157 { 4158 const struct rtw89_chip_info *chip = rtwdev->chip; 4159 4160 if (chip->ops->rfk_band_changed) 4161 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4162 } 4163 4164 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4165 { 4166 const struct rtw89_chip_info *chip = rtwdev->chip; 4167 4168 if (chip->ops->rfk_scan) 4169 chip->ops->rfk_scan(rtwdev, start); 4170 } 4171 4172 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4173 { 4174 const struct rtw89_chip_info *chip = rtwdev->chip; 4175 4176 if (chip->ops->rfk_track) 4177 chip->ops->rfk_track(rtwdev); 4178 } 4179 4180 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4181 { 4182 const struct rtw89_chip_info *chip = rtwdev->chip; 4183 4184 if (chip->ops->set_txpwr_ctrl) 4185 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4186 } 4187 4188 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4189 { 4190 const struct rtw89_chip_info *chip = rtwdev->chip; 4191 4192 if (chip->ops->power_trim) 4193 chip->ops->power_trim(rtwdev); 4194 } 4195 4196 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4197 enum rtw89_phy_idx phy_idx) 4198 { 4199 const struct rtw89_chip_info *chip = rtwdev->chip; 4200 4201 if (chip->ops->init_txpwr_unit) 4202 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4203 } 4204 4205 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4206 enum rtw89_rf_path rf_path) 4207 { 4208 const struct rtw89_chip_info *chip = rtwdev->chip; 4209 4210 if (!chip->ops->get_thermal) 4211 return 0x10; 4212 4213 return chip->ops->get_thermal(rtwdev, rf_path); 4214 } 4215 4216 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4217 struct rtw89_rx_phy_ppdu *phy_ppdu, 4218 struct ieee80211_rx_status *status) 4219 { 4220 const struct rtw89_chip_info *chip = rtwdev->chip; 4221 4222 if (chip->ops->query_ppdu) 4223 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4224 } 4225 4226 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4227 bool bt_en) 4228 { 4229 const struct rtw89_chip_info *chip = rtwdev->chip; 4230 4231 if (chip->ops->bb_ctrl_btc_preagc) 4232 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4233 } 4234 4235 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4236 { 4237 const struct rtw89_chip_info *chip = rtwdev->chip; 4238 4239 if (chip->ops->cfg_txrx_path) 4240 chip->ops->cfg_txrx_path(rtwdev); 4241 } 4242 4243 static inline 4244 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4245 struct ieee80211_vif *vif) 4246 { 4247 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4248 const struct rtw89_chip_info *chip = rtwdev->chip; 4249 4250 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4251 return; 4252 4253 if (chip->ops->set_txpwr_ul_tb_offset) 4254 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4255 } 4256 4257 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4258 const struct rtw89_txpwr_table *tbl) 4259 { 4260 tbl->load(rtwdev, tbl); 4261 } 4262 4263 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4264 { 4265 return rtwdev->regd->txpwr_regd[band]; 4266 } 4267 4268 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4269 { 4270 const struct rtw89_chip_info *chip = rtwdev->chip; 4271 4272 if (chip->ops->ctrl_btg) 4273 chip->ops->ctrl_btg(rtwdev, btg); 4274 } 4275 4276 static inline 4277 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4278 struct rtw89_tx_desc_info *desc_info, 4279 void *txdesc) 4280 { 4281 const struct rtw89_chip_info *chip = rtwdev->chip; 4282 4283 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4284 } 4285 4286 static inline 4287 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4288 struct rtw89_tx_desc_info *desc_info, 4289 void *txdesc) 4290 { 4291 const struct rtw89_chip_info *chip = rtwdev->chip; 4292 4293 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4294 } 4295 4296 static inline 4297 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4298 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4299 { 4300 const struct rtw89_chip_info *chip = rtwdev->chip; 4301 4302 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4303 } 4304 4305 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4306 { 4307 const struct rtw89_chip_info *chip = rtwdev->chip; 4308 4309 chip->ops->cfg_ctrl_path(rtwdev, wl); 4310 } 4311 4312 static inline 4313 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4314 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4315 { 4316 const struct rtw89_chip_info *chip = rtwdev->chip; 4317 4318 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4319 } 4320 4321 static inline 4322 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4323 { 4324 const struct rtw89_chip_info *chip = rtwdev->chip; 4325 4326 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4327 } 4328 4329 static inline 4330 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4331 struct rtw89_vif *rtwvif, 4332 struct rtw89_sta *rtwsta) 4333 { 4334 const struct rtw89_chip_info *chip = rtwdev->chip; 4335 4336 if (!chip->ops->h2c_dctl_sec_cam) 4337 return 0; 4338 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4339 } 4340 4341 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4342 { 4343 __le16 fc = hdr->frame_control; 4344 4345 if (ieee80211_has_tods(fc)) 4346 return hdr->addr1; 4347 else if (ieee80211_has_fromds(fc)) 4348 return hdr->addr2; 4349 else 4350 return hdr->addr3; 4351 } 4352 4353 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4354 { 4355 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4356 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4357 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4358 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4359 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4360 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4361 return true; 4362 return false; 4363 } 4364 4365 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4366 enum rtw89_fw_type type) 4367 { 4368 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4369 4370 if (type == RTW89_FW_WOWLAN) 4371 return &fw_info->wowlan; 4372 return &fw_info->normal; 4373 } 4374 4375 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4376 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4377 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4378 struct sk_buff *skb, bool fwdl); 4379 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4380 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4381 struct rtw89_tx_desc_info *desc_info, 4382 void *txdesc); 4383 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4384 struct rtw89_tx_desc_info *desc_info, 4385 void *txdesc); 4386 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4387 struct rtw89_tx_desc_info *desc_info, 4388 void *txdesc); 4389 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4390 struct rtw89_rx_desc_info *desc_info, 4391 struct sk_buff *skb); 4392 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4393 struct rtw89_rx_desc_info *desc_info, 4394 u8 *data, u32 data_offset); 4395 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4396 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4397 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4398 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4399 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4400 struct ieee80211_vif *vif, 4401 struct ieee80211_sta *sta); 4402 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4403 struct ieee80211_vif *vif, 4404 struct ieee80211_sta *sta); 4405 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4406 struct ieee80211_vif *vif, 4407 struct ieee80211_sta *sta); 4408 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4409 struct ieee80211_vif *vif, 4410 struct ieee80211_sta *sta); 4411 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4412 struct ieee80211_vif *vif, 4413 struct ieee80211_sta *sta); 4414 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4415 struct ieee80211_sta *sta, 4416 struct cfg80211_tid_config *tid_config); 4417 int rtw89_core_init(struct rtw89_dev *rtwdev); 4418 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4419 int rtw89_core_register(struct rtw89_dev *rtwdev); 4420 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4421 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4422 u32 bus_data_size, 4423 const struct rtw89_chip_info *chip); 4424 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4425 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4426 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4427 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4428 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4429 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4430 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4431 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4432 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4433 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4434 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4435 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4436 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4437 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4438 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4439 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4440 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4441 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4442 struct rtw89_traffic_stats *stats); 4443 int rtw89_core_start(struct rtw89_dev *rtwdev); 4444 void rtw89_core_stop(struct rtw89_dev *rtwdev); 4445 void rtw89_core_update_beacon_work(struct work_struct *work); 4446 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4447 const u8 *mac_addr, bool hw_scan); 4448 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4449 struct ieee80211_vif *vif, bool hw_scan); 4450 4451 #endif 4452