1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64) 39 40 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 41 #define RTW89_HTC_VARIANT_HE 3 42 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 43 #define RTW89_HTC_VARIANT_HE_CID_OM 1 44 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 45 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 46 47 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 48 enum htc_om_channel_width { 49 HTC_OM_CHANNEL_WIDTH_20 = 0, 50 HTC_OM_CHANNEL_WIDTH_40 = 1, 51 HTC_OM_CHANNEL_WIDTH_80 = 2, 52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 53 }; 54 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 56 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 57 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 58 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 60 61 #define RTW89_TF_PAD GENMASK(11, 0) 62 #define RTW89_TF_BASIC_USER_INFO_SZ 6 63 64 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 66 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 68 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 70 71 enum rtw89_subband { 72 RTW89_CH_2G = 0, 73 RTW89_CH_5G_BAND_1 = 1, 74 /* RTW89_CH_5G_BAND_2 = 2, unused */ 75 RTW89_CH_5G_BAND_3 = 3, 76 RTW89_CH_5G_BAND_4 = 4, 77 78 RTW89_CH_6G_BAND_IDX0, /* Low */ 79 RTW89_CH_6G_BAND_IDX1, /* Low */ 80 RTW89_CH_6G_BAND_IDX2, /* Mid */ 81 RTW89_CH_6G_BAND_IDX3, /* Mid */ 82 RTW89_CH_6G_BAND_IDX4, /* High */ 83 RTW89_CH_6G_BAND_IDX5, /* High */ 84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 86 87 RTW89_SUBBAND_NR, 88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 89 }; 90 91 enum rtw89_gain_offset { 92 RTW89_GAIN_OFFSET_2G_CCK, 93 RTW89_GAIN_OFFSET_2G_OFDM, 94 RTW89_GAIN_OFFSET_5G_LOW, 95 RTW89_GAIN_OFFSET_5G_MID, 96 RTW89_GAIN_OFFSET_5G_HIGH, 97 98 RTW89_GAIN_OFFSET_NR, 99 }; 100 101 enum rtw89_hci_type { 102 RTW89_HCI_TYPE_PCIE, 103 RTW89_HCI_TYPE_USB, 104 RTW89_HCI_TYPE_SDIO, 105 }; 106 107 enum rtw89_core_chip_id { 108 RTL8852A, 109 RTL8852B, 110 RTL8852C, 111 }; 112 113 enum rtw89_cv { 114 CHIP_CAV, 115 CHIP_CBV, 116 CHIP_CCV, 117 CHIP_CDV, 118 CHIP_CEV, 119 CHIP_CFV, 120 CHIP_CV_MAX, 121 CHIP_CV_INVALID = CHIP_CV_MAX, 122 }; 123 124 enum rtw89_core_tx_type { 125 RTW89_CORE_TX_TYPE_DATA, 126 RTW89_CORE_TX_TYPE_MGMT, 127 RTW89_CORE_TX_TYPE_FWCMD, 128 }; 129 130 enum rtw89_core_rx_type { 131 RTW89_CORE_RX_TYPE_WIFI = 0, 132 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 133 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 134 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 135 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 136 RTW89_CORE_RX_TYPE_SS2FW = 5, 137 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 138 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 139 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 140 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 141 RTW89_CORE_RX_TYPE_C2H = 10, 142 RTW89_CORE_RX_TYPE_CSI = 11, 143 RTW89_CORE_RX_TYPE_CQI = 12, 144 RTW89_CORE_RX_TYPE_H2C = 13, 145 RTW89_CORE_RX_TYPE_FWDL = 14, 146 }; 147 148 enum rtw89_txq_flags { 149 RTW89_TXQ_F_AMPDU = 0, 150 RTW89_TXQ_F_BLOCK_BA = 1, 151 RTW89_TXQ_F_FORBID_BA = 2, 152 }; 153 154 enum rtw89_net_type { 155 RTW89_NET_TYPE_NO_LINK = 0, 156 RTW89_NET_TYPE_AD_HOC = 1, 157 RTW89_NET_TYPE_INFRA = 2, 158 RTW89_NET_TYPE_AP_MODE = 3, 159 }; 160 161 enum rtw89_wifi_role { 162 RTW89_WIFI_ROLE_NONE, 163 RTW89_WIFI_ROLE_STATION, 164 RTW89_WIFI_ROLE_AP, 165 RTW89_WIFI_ROLE_AP_VLAN, 166 RTW89_WIFI_ROLE_ADHOC, 167 RTW89_WIFI_ROLE_ADHOC_MASTER, 168 RTW89_WIFI_ROLE_MESH_POINT, 169 RTW89_WIFI_ROLE_MONITOR, 170 RTW89_WIFI_ROLE_P2P_DEVICE, 171 RTW89_WIFI_ROLE_P2P_CLIENT, 172 RTW89_WIFI_ROLE_P2P_GO, 173 RTW89_WIFI_ROLE_NAN, 174 RTW89_WIFI_ROLE_MLME_MAX 175 }; 176 177 enum rtw89_upd_mode { 178 RTW89_ROLE_CREATE, 179 RTW89_ROLE_REMOVE, 180 RTW89_ROLE_TYPE_CHANGE, 181 RTW89_ROLE_INFO_CHANGE, 182 RTW89_ROLE_CON_DISCONN, 183 RTW89_ROLE_BAND_SW, 184 RTW89_ROLE_FW_RESTORE, 185 }; 186 187 enum rtw89_self_role { 188 RTW89_SELF_ROLE_CLIENT, 189 RTW89_SELF_ROLE_AP, 190 RTW89_SELF_ROLE_AP_CLIENT 191 }; 192 193 enum rtw89_msk_sO_el { 194 RTW89_NO_MSK, 195 RTW89_SMA, 196 RTW89_TMA, 197 RTW89_BSSID 198 }; 199 200 enum rtw89_sch_tx_sel { 201 RTW89_SCH_TX_SEL_ALL, 202 RTW89_SCH_TX_SEL_HIQ, 203 RTW89_SCH_TX_SEL_MG0, 204 RTW89_SCH_TX_SEL_MACID, 205 }; 206 207 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 208 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 209 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 210 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 211 */ 212 enum rtw89_add_cam_sec_mode { 213 RTW89_ADDR_CAM_SEC_NONE = 0, 214 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 215 RTW89_ADDR_CAM_SEC_NORMAL = 2, 216 RTW89_ADDR_CAM_SEC_4GROUP = 3, 217 }; 218 219 enum rtw89_sec_key_type { 220 RTW89_SEC_KEY_TYPE_NONE = 0, 221 RTW89_SEC_KEY_TYPE_WEP40 = 1, 222 RTW89_SEC_KEY_TYPE_WEP104 = 2, 223 RTW89_SEC_KEY_TYPE_TKIP = 3, 224 RTW89_SEC_KEY_TYPE_WAPI = 4, 225 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 226 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 227 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 228 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 229 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 230 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 231 }; 232 233 enum rtw89_port { 234 RTW89_PORT_0 = 0, 235 RTW89_PORT_1 = 1, 236 RTW89_PORT_2 = 2, 237 RTW89_PORT_3 = 3, 238 RTW89_PORT_4 = 4, 239 RTW89_PORT_NUM 240 }; 241 242 enum rtw89_band { 243 RTW89_BAND_2G = 0, 244 RTW89_BAND_5G = 1, 245 RTW89_BAND_6G = 2, 246 RTW89_BAND_MAX, 247 }; 248 249 enum rtw89_hw_rate { 250 RTW89_HW_RATE_CCK1 = 0x0, 251 RTW89_HW_RATE_CCK2 = 0x1, 252 RTW89_HW_RATE_CCK5_5 = 0x2, 253 RTW89_HW_RATE_CCK11 = 0x3, 254 RTW89_HW_RATE_OFDM6 = 0x4, 255 RTW89_HW_RATE_OFDM9 = 0x5, 256 RTW89_HW_RATE_OFDM12 = 0x6, 257 RTW89_HW_RATE_OFDM18 = 0x7, 258 RTW89_HW_RATE_OFDM24 = 0x8, 259 RTW89_HW_RATE_OFDM36 = 0x9, 260 RTW89_HW_RATE_OFDM48 = 0xA, 261 RTW89_HW_RATE_OFDM54 = 0xB, 262 RTW89_HW_RATE_MCS0 = 0x80, 263 RTW89_HW_RATE_MCS1 = 0x81, 264 RTW89_HW_RATE_MCS2 = 0x82, 265 RTW89_HW_RATE_MCS3 = 0x83, 266 RTW89_HW_RATE_MCS4 = 0x84, 267 RTW89_HW_RATE_MCS5 = 0x85, 268 RTW89_HW_RATE_MCS6 = 0x86, 269 RTW89_HW_RATE_MCS7 = 0x87, 270 RTW89_HW_RATE_MCS8 = 0x88, 271 RTW89_HW_RATE_MCS9 = 0x89, 272 RTW89_HW_RATE_MCS10 = 0x8A, 273 RTW89_HW_RATE_MCS11 = 0x8B, 274 RTW89_HW_RATE_MCS12 = 0x8C, 275 RTW89_HW_RATE_MCS13 = 0x8D, 276 RTW89_HW_RATE_MCS14 = 0x8E, 277 RTW89_HW_RATE_MCS15 = 0x8F, 278 RTW89_HW_RATE_MCS16 = 0x90, 279 RTW89_HW_RATE_MCS17 = 0x91, 280 RTW89_HW_RATE_MCS18 = 0x92, 281 RTW89_HW_RATE_MCS19 = 0x93, 282 RTW89_HW_RATE_MCS20 = 0x94, 283 RTW89_HW_RATE_MCS21 = 0x95, 284 RTW89_HW_RATE_MCS22 = 0x96, 285 RTW89_HW_RATE_MCS23 = 0x97, 286 RTW89_HW_RATE_MCS24 = 0x98, 287 RTW89_HW_RATE_MCS25 = 0x99, 288 RTW89_HW_RATE_MCS26 = 0x9A, 289 RTW89_HW_RATE_MCS27 = 0x9B, 290 RTW89_HW_RATE_MCS28 = 0x9C, 291 RTW89_HW_RATE_MCS29 = 0x9D, 292 RTW89_HW_RATE_MCS30 = 0x9E, 293 RTW89_HW_RATE_MCS31 = 0x9F, 294 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 295 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 296 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 297 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 298 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 299 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 300 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 301 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 302 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 303 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 304 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 305 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 306 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 307 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 308 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 309 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 310 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 311 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 312 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 313 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 314 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 315 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 316 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 317 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 318 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 319 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 320 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 321 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 322 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 323 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 324 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 325 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 326 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 327 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 328 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 329 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 330 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 331 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 332 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 333 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 334 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 335 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 336 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 337 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 338 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 339 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 340 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 341 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 342 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 343 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 344 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 345 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 346 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 347 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 348 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 349 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 350 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 351 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 352 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 353 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 354 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 355 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 356 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 357 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 358 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 359 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 360 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 361 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 362 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 363 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 364 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 365 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 366 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 367 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 368 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 369 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 370 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 371 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 372 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 373 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 374 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 375 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 376 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 377 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 378 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 379 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 380 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 381 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 382 RTW89_HW_RATE_NR, 383 384 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 385 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 386 }; 387 388 /* 2G channels, 389 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 390 */ 391 #define RTW89_2G_CH_NUM 14 392 393 /* 5G channels, 394 * 36, 38, 40, 42, 44, 46, 48, 50, 395 * 52, 54, 56, 58, 60, 62, 64, 396 * 100, 102, 104, 106, 108, 110, 112, 114, 397 * 116, 118, 120, 122, 124, 126, 128, 130, 398 * 132, 134, 136, 138, 140, 142, 144, 399 * 149, 151, 153, 155, 157, 159, 161, 163, 400 * 165, 167, 169, 171, 173, 175, 177 401 */ 402 #define RTW89_5G_CH_NUM 53 403 404 /* 6G channels, 405 * 1, 3, 5, 7, 9, 11, 13, 15, 406 * 17, 19, 21, 23, 25, 27, 29, 33, 407 * 35, 37, 39, 41, 43, 45, 47, 49, 408 * 51, 53, 55, 57, 59, 61, 65, 67, 409 * 69, 71, 73, 75, 77, 79, 81, 83, 410 * 85, 87, 89, 91, 93, 97, 99, 101, 411 * 103, 105, 107, 109, 111, 113, 115, 117, 412 * 119, 121, 123, 125, 129, 131, 133, 135, 413 * 137, 139, 141, 143, 145, 147, 149, 151, 414 * 153, 155, 157, 161, 163, 165, 167, 169, 415 * 171, 173, 175, 177, 179, 181, 183, 185, 416 * 187, 189, 193, 195, 197, 199, 201, 203, 417 * 205, 207, 209, 211, 213, 215, 217, 219, 418 * 221, 225, 227, 229, 231, 233, 235, 237, 419 * 239, 241, 243, 245, 247, 249, 251, 253, 420 */ 421 #define RTW89_6G_CH_NUM 120 422 423 enum rtw89_rate_section { 424 RTW89_RS_CCK, 425 RTW89_RS_OFDM, 426 RTW89_RS_MCS, /* for HT/VHT/HE */ 427 RTW89_RS_HEDCM, 428 RTW89_RS_OFFSET, 429 RTW89_RS_MAX, 430 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 431 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 432 }; 433 434 enum rtw89_rate_max { 435 RTW89_RATE_CCK_MAX = 4, 436 RTW89_RATE_OFDM_MAX = 8, 437 RTW89_RATE_MCS_MAX = 12, 438 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 439 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 440 }; 441 442 enum rtw89_nss { 443 RTW89_NSS_1 = 0, 444 RTW89_NSS_2 = 1, 445 /* HE DCM only support 1ss and 2ss */ 446 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 447 RTW89_NSS_3 = 2, 448 RTW89_NSS_4 = 3, 449 RTW89_NSS_MAX, 450 }; 451 452 enum rtw89_ntx { 453 RTW89_1TX = 0, 454 RTW89_2TX = 1, 455 RTW89_NTX_NUM, 456 }; 457 458 enum rtw89_beamforming_type { 459 RTW89_NONBF = 0, 460 RTW89_BF = 1, 461 RTW89_BF_NUM, 462 }; 463 464 enum rtw89_regulation_type { 465 RTW89_WW = 0, 466 RTW89_ETSI = 1, 467 RTW89_FCC = 2, 468 RTW89_MKK = 3, 469 RTW89_NA = 4, 470 RTW89_IC = 5, 471 RTW89_KCC = 6, 472 RTW89_ACMA = 7, 473 RTW89_NCC = 8, 474 RTW89_MEXICO = 9, 475 RTW89_CHILE = 10, 476 RTW89_UKRAINE = 11, 477 RTW89_CN = 12, 478 RTW89_QATAR = 13, 479 RTW89_UK = 14, 480 RTW89_REGD_NUM, 481 }; 482 483 enum rtw89_fw_pkt_ofld_type { 484 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 485 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 486 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 487 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 488 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 489 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 490 RTW89_PKT_OFLD_TYPE_NDP = 6, 491 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 492 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 493 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 494 RTW89_PKT_OFLD_TYPE_NUM, 495 }; 496 497 struct rtw89_txpwr_byrate { 498 s8 cck[RTW89_RATE_CCK_MAX]; 499 s8 ofdm[RTW89_RATE_OFDM_MAX]; 500 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 501 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 502 s8 offset[RTW89_RATE_OFFSET_MAX]; 503 }; 504 505 enum rtw89_bandwidth_section_num { 506 RTW89_BW20_SEC_NUM = 8, 507 RTW89_BW40_SEC_NUM = 4, 508 RTW89_BW80_SEC_NUM = 2, 509 }; 510 511 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 512 513 struct rtw89_txpwr_limit { 514 s8 cck_20m[RTW89_BF_NUM]; 515 s8 cck_40m[RTW89_BF_NUM]; 516 s8 ofdm[RTW89_BF_NUM]; 517 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 518 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 519 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 520 s8 mcs_160m[RTW89_BF_NUM]; 521 s8 mcs_40m_0p5[RTW89_BF_NUM]; 522 s8 mcs_40m_2p5[RTW89_BF_NUM]; 523 }; 524 525 #define RTW89_RU_SEC_NUM 8 526 527 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 528 529 struct rtw89_txpwr_limit_ru { 530 s8 ru26[RTW89_RU_SEC_NUM]; 531 s8 ru52[RTW89_RU_SEC_NUM]; 532 s8 ru106[RTW89_RU_SEC_NUM]; 533 }; 534 535 struct rtw89_rate_desc { 536 enum rtw89_nss nss; 537 enum rtw89_rate_section rs; 538 u8 idx; 539 }; 540 541 #define PHY_STS_HDR_LEN 8 542 #define RF_PATH_MAX 4 543 #define RTW89_MAX_PPDU_CNT 8 544 struct rtw89_rx_phy_ppdu { 545 u8 *buf; 546 u32 len; 547 u8 rssi_avg; 548 u8 rssi[RF_PATH_MAX]; 549 u8 mac_id; 550 u8 chan_idx; 551 u8 ie; 552 u16 rate; 553 bool to_self; 554 bool valid; 555 }; 556 557 enum rtw89_mac_idx { 558 RTW89_MAC_0 = 0, 559 RTW89_MAC_1 = 1, 560 }; 561 562 enum rtw89_phy_idx { 563 RTW89_PHY_0 = 0, 564 RTW89_PHY_1 = 1, 565 RTW89_PHY_MAX 566 }; 567 568 enum rtw89_sub_entity_idx { 569 RTW89_SUB_ENTITY_0 = 0, 570 571 NUM_OF_RTW89_SUB_ENTITY, 572 }; 573 574 enum rtw89_rf_path { 575 RF_PATH_A = 0, 576 RF_PATH_B = 1, 577 RF_PATH_C = 2, 578 RF_PATH_D = 3, 579 RF_PATH_AB, 580 RF_PATH_AC, 581 RF_PATH_AD, 582 RF_PATH_BC, 583 RF_PATH_BD, 584 RF_PATH_CD, 585 RF_PATH_ABC, 586 RF_PATH_ABD, 587 RF_PATH_ACD, 588 RF_PATH_BCD, 589 RF_PATH_ABCD, 590 }; 591 592 enum rtw89_rf_path_bit { 593 RF_A = BIT(0), 594 RF_B = BIT(1), 595 RF_C = BIT(2), 596 RF_D = BIT(3), 597 598 RF_AB = (RF_A | RF_B), 599 RF_AC = (RF_A | RF_C), 600 RF_AD = (RF_A | RF_D), 601 RF_BC = (RF_B | RF_C), 602 RF_BD = (RF_B | RF_D), 603 RF_CD = (RF_C | RF_D), 604 605 RF_ABC = (RF_A | RF_B | RF_C), 606 RF_ABD = (RF_A | RF_B | RF_D), 607 RF_ACD = (RF_A | RF_C | RF_D), 608 RF_BCD = (RF_B | RF_C | RF_D), 609 610 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 611 }; 612 613 enum rtw89_bandwidth { 614 RTW89_CHANNEL_WIDTH_20 = 0, 615 RTW89_CHANNEL_WIDTH_40 = 1, 616 RTW89_CHANNEL_WIDTH_80 = 2, 617 RTW89_CHANNEL_WIDTH_160 = 3, 618 RTW89_CHANNEL_WIDTH_80_80 = 4, 619 RTW89_CHANNEL_WIDTH_5 = 5, 620 RTW89_CHANNEL_WIDTH_10 = 6, 621 }; 622 623 enum rtw89_ps_mode { 624 RTW89_PS_MODE_NONE = 0, 625 RTW89_PS_MODE_RFOFF = 1, 626 RTW89_PS_MODE_CLK_GATED = 2, 627 RTW89_PS_MODE_PWR_GATED = 3, 628 }; 629 630 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 631 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 632 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 633 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 634 635 enum rtw89_ru_bandwidth { 636 RTW89_RU26 = 0, 637 RTW89_RU52 = 1, 638 RTW89_RU106 = 2, 639 RTW89_RU_NUM, 640 }; 641 642 enum rtw89_sc_offset { 643 RTW89_SC_DONT_CARE = 0, 644 RTW89_SC_20_UPPER = 1, 645 RTW89_SC_20_LOWER = 2, 646 RTW89_SC_20_UPMOST = 3, 647 RTW89_SC_20_LOWEST = 4, 648 RTW89_SC_20_UP2X = 5, 649 RTW89_SC_20_LOW2X = 6, 650 RTW89_SC_20_UP3X = 7, 651 RTW89_SC_20_LOW3X = 8, 652 RTW89_SC_40_UPPER = 9, 653 RTW89_SC_40_LOWER = 10, 654 }; 655 656 enum rtw89_wow_flags { 657 RTW89_WOW_FLAG_EN_MAGIC_PKT, 658 RTW89_WOW_FLAG_EN_REKEY_PKT, 659 RTW89_WOW_FLAG_EN_DISCONNECT, 660 RTW89_WOW_FLAG_NUM, 661 }; 662 663 struct rtw89_chan { 664 u8 channel; 665 u8 primary_channel; 666 enum rtw89_band band_type; 667 enum rtw89_bandwidth band_width; 668 669 /* The follow-up are derived from the above. We must ensure that it 670 * is assigned correctly in rtw89_chan_create() if new one is added. 671 */ 672 u32 freq; 673 enum rtw89_subband subband_type; 674 enum rtw89_sc_offset pri_ch_idx; 675 }; 676 677 struct rtw89_chan_rcd { 678 u8 prev_primary_channel; 679 enum rtw89_band prev_band_type; 680 }; 681 682 struct rtw89_channel_help_params { 683 u32 tx_en; 684 }; 685 686 struct rtw89_port_reg { 687 u32 port_cfg; 688 u32 tbtt_prohib; 689 u32 bcn_area; 690 u32 bcn_early; 691 u32 tbtt_early; 692 u32 tbtt_agg; 693 u32 bcn_space; 694 u32 bcn_forcetx; 695 u32 bcn_err_cnt; 696 u32 bcn_err_flag; 697 u32 dtim_ctrl; 698 u32 tbtt_shift; 699 u32 bcn_cnt_tmr; 700 u32 tsftr_l; 701 u32 tsftr_h; 702 }; 703 704 struct rtw89_txwd_body { 705 __le32 dword0; 706 __le32 dword1; 707 __le32 dword2; 708 __le32 dword3; 709 __le32 dword4; 710 __le32 dword5; 711 } __packed; 712 713 struct rtw89_txwd_body_v1 { 714 __le32 dword0; 715 __le32 dword1; 716 __le32 dword2; 717 __le32 dword3; 718 __le32 dword4; 719 __le32 dword5; 720 __le32 dword6; 721 __le32 dword7; 722 } __packed; 723 724 struct rtw89_txwd_info { 725 __le32 dword0; 726 __le32 dword1; 727 __le32 dword2; 728 __le32 dword3; 729 __le32 dword4; 730 __le32 dword5; 731 } __packed; 732 733 struct rtw89_rx_desc_info { 734 u16 pkt_size; 735 u8 pkt_type; 736 u8 drv_info_size; 737 u8 shift; 738 u8 wl_hd_iv_len; 739 bool long_rxdesc; 740 bool bb_sel; 741 bool mac_info_valid; 742 u16 data_rate; 743 u8 gi_ltf; 744 u8 bw; 745 u32 free_run_cnt; 746 u8 user_id; 747 bool sr_en; 748 u8 ppdu_cnt; 749 u8 ppdu_type; 750 bool icv_err; 751 bool crc32_err; 752 bool hw_dec; 753 bool sw_dec; 754 bool addr1_match; 755 u8 frag; 756 u16 seq; 757 u8 frame_type; 758 u8 rx_pl_id; 759 bool addr_cam_valid; 760 u8 addr_cam_id; 761 u8 sec_cam_id; 762 u8 mac_id; 763 u16 offset; 764 bool ready; 765 }; 766 767 struct rtw89_rxdesc_short { 768 __le32 dword0; 769 __le32 dword1; 770 __le32 dword2; 771 __le32 dword3; 772 } __packed; 773 774 struct rtw89_rxdesc_long { 775 __le32 dword0; 776 __le32 dword1; 777 __le32 dword2; 778 __le32 dword3; 779 __le32 dword4; 780 __le32 dword5; 781 __le32 dword6; 782 __le32 dword7; 783 } __packed; 784 785 struct rtw89_tx_desc_info { 786 u16 pkt_size; 787 u8 wp_offset; 788 u8 mac_id; 789 u8 qsel; 790 u8 ch_dma; 791 u8 hdr_llc_len; 792 bool is_bmc; 793 bool en_wd_info; 794 bool wd_page; 795 bool use_rate; 796 bool dis_data_fb; 797 bool tid_indicate; 798 bool agg_en; 799 bool bk; 800 u8 ampdu_density; 801 u8 ampdu_num; 802 bool sec_en; 803 u8 addr_info_nr; 804 u8 sec_keyid; 805 u8 sec_type; 806 u8 sec_cam_idx; 807 u8 sec_seq[6]; 808 u16 data_rate; 809 u16 data_retry_lowest_rate; 810 bool fw_dl; 811 u16 seq; 812 bool a_ctrl_bsr; 813 u8 hw_ssn_sel; 814 #define RTW89_MGMT_HW_SSN_SEL 1 815 u8 hw_seq_mode; 816 #define RTW89_MGMT_HW_SEQ_MODE 1 817 bool hiq; 818 u8 port; 819 bool er_cap; 820 }; 821 822 struct rtw89_core_tx_request { 823 enum rtw89_core_tx_type tx_type; 824 825 struct sk_buff *skb; 826 struct ieee80211_vif *vif; 827 struct ieee80211_sta *sta; 828 struct rtw89_tx_desc_info desc_info; 829 }; 830 831 struct rtw89_txq { 832 struct list_head list; 833 unsigned long flags; 834 int wait_cnt; 835 }; 836 837 struct rtw89_mac_ax_gnt { 838 u8 gnt_bt_sw_en; 839 u8 gnt_bt; 840 u8 gnt_wl_sw_en; 841 u8 gnt_wl; 842 } __packed; 843 844 #define RTW89_MAC_AX_COEX_GNT_NR 2 845 struct rtw89_mac_ax_coex_gnt { 846 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 847 }; 848 849 enum rtw89_btc_ncnt { 850 BTC_NCNT_POWER_ON = 0x0, 851 BTC_NCNT_POWER_OFF, 852 BTC_NCNT_INIT_COEX, 853 BTC_NCNT_SCAN_START, 854 BTC_NCNT_SCAN_FINISH, 855 BTC_NCNT_SPECIAL_PACKET, 856 BTC_NCNT_SWITCH_BAND, 857 BTC_NCNT_RFK_TIMEOUT, 858 BTC_NCNT_SHOW_COEX_INFO, 859 BTC_NCNT_ROLE_INFO, 860 BTC_NCNT_CONTROL, 861 BTC_NCNT_RADIO_STATE, 862 BTC_NCNT_CUSTOMERIZE, 863 BTC_NCNT_WL_RFK, 864 BTC_NCNT_WL_STA, 865 BTC_NCNT_FWINFO, 866 BTC_NCNT_TIMER, 867 BTC_NCNT_NUM 868 }; 869 870 enum rtw89_btc_btinfo { 871 BTC_BTINFO_L0 = 0, 872 BTC_BTINFO_L1, 873 BTC_BTINFO_L2, 874 BTC_BTINFO_L3, 875 BTC_BTINFO_H0, 876 BTC_BTINFO_H1, 877 BTC_BTINFO_H2, 878 BTC_BTINFO_H3, 879 BTC_BTINFO_MAX 880 }; 881 882 enum rtw89_btc_dcnt { 883 BTC_DCNT_RUN = 0x0, 884 BTC_DCNT_CX_RUNINFO, 885 BTC_DCNT_RPT, 886 BTC_DCNT_RPT_HANG, 887 BTC_DCNT_CYCLE, 888 BTC_DCNT_CYCLE_HANG, 889 BTC_DCNT_W1, 890 BTC_DCNT_W1_HANG, 891 BTC_DCNT_B1, 892 BTC_DCNT_B1_HANG, 893 BTC_DCNT_TDMA_NONSYNC, 894 BTC_DCNT_SLOT_NONSYNC, 895 BTC_DCNT_BTCNT_HANG, 896 BTC_DCNT_WL_SLOT_DRIFT, 897 BTC_DCNT_WL_STA_LAST, 898 BTC_DCNT_BT_SLOT_DRIFT, 899 BTC_DCNT_BT_SLOT_FLOOD, 900 BTC_DCNT_FDDT_TRIG, 901 BTC_DCNT_E2G, 902 BTC_DCNT_E2G_HANG, 903 BTC_DCNT_NUM 904 }; 905 906 enum rtw89_btc_wl_state_cnt { 907 BTC_WCNT_SCANAP = 0x0, 908 BTC_WCNT_DHCP, 909 BTC_WCNT_EAPOL, 910 BTC_WCNT_ARP, 911 BTC_WCNT_SCBDUPDATE, 912 BTC_WCNT_RFK_REQ, 913 BTC_WCNT_RFK_GO, 914 BTC_WCNT_RFK_REJECT, 915 BTC_WCNT_RFK_TIMEOUT, 916 BTC_WCNT_CH_UPDATE, 917 BTC_WCNT_NUM 918 }; 919 920 enum rtw89_btc_bt_state_cnt { 921 BTC_BCNT_RETRY = 0x0, 922 BTC_BCNT_REINIT, 923 BTC_BCNT_REENABLE, 924 BTC_BCNT_SCBDREAD, 925 BTC_BCNT_RELINK, 926 BTC_BCNT_IGNOWL, 927 BTC_BCNT_INQPAG, 928 BTC_BCNT_INQ, 929 BTC_BCNT_PAGE, 930 BTC_BCNT_ROLESW, 931 BTC_BCNT_AFH, 932 BTC_BCNT_INFOUPDATE, 933 BTC_BCNT_INFOSAME, 934 BTC_BCNT_SCBDUPDATE, 935 BTC_BCNT_HIPRI_TX, 936 BTC_BCNT_HIPRI_RX, 937 BTC_BCNT_LOPRI_TX, 938 BTC_BCNT_LOPRI_RX, 939 BTC_BCNT_POLUT, 940 BTC_BCNT_RATECHG, 941 BTC_BCNT_NUM 942 }; 943 944 enum rtw89_btc_bt_profile { 945 BTC_BT_NOPROFILE = 0, 946 BTC_BT_HFP = BIT(0), 947 BTC_BT_HID = BIT(1), 948 BTC_BT_A2DP = BIT(2), 949 BTC_BT_PAN = BIT(3), 950 BTC_PROFILE_MAX = 4, 951 }; 952 953 struct rtw89_btc_ant_info { 954 u8 type; /* shared, dedicated */ 955 u8 num; 956 u8 isolation; 957 958 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 959 u8 diversity: 1; 960 }; 961 962 enum rtw89_tfc_dir { 963 RTW89_TFC_UL, 964 RTW89_TFC_DL, 965 }; 966 967 struct rtw89_btc_wl_smap { 968 u32 busy: 1; 969 u32 scan: 1; 970 u32 connecting: 1; 971 u32 roaming: 1; 972 u32 _4way: 1; 973 u32 rf_off: 1; 974 u32 lps: 2; 975 u32 ips: 1; 976 u32 init_ok: 1; 977 u32 traffic_dir : 2; 978 u32 rf_off_pre: 1; 979 u32 lps_pre: 2; 980 }; 981 982 enum rtw89_tfc_lv { 983 RTW89_TFC_IDLE, 984 RTW89_TFC_ULTRA_LOW, 985 RTW89_TFC_LOW, 986 RTW89_TFC_MID, 987 RTW89_TFC_HIGH, 988 }; 989 990 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 991 DECLARE_EWMA(tp, 10, 2); 992 993 struct rtw89_traffic_stats { 994 /* units in bytes */ 995 u64 tx_unicast; 996 u64 rx_unicast; 997 u32 tx_avg_len; 998 u32 rx_avg_len; 999 1000 /* count for packets */ 1001 u64 tx_cnt; 1002 u64 rx_cnt; 1003 1004 /* units in Mbps */ 1005 u32 tx_throughput; 1006 u32 rx_throughput; 1007 u32 tx_throughput_raw; 1008 u32 rx_throughput_raw; 1009 1010 u32 rx_tf_acc; 1011 u32 rx_tf_periodic; 1012 1013 enum rtw89_tfc_lv tx_tfc_lv; 1014 enum rtw89_tfc_lv rx_tfc_lv; 1015 struct ewma_tp tx_ewma_tp; 1016 struct ewma_tp rx_ewma_tp; 1017 1018 u16 tx_rate; 1019 u16 rx_rate; 1020 }; 1021 1022 struct rtw89_btc_statistic { 1023 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1024 struct rtw89_traffic_stats traffic; 1025 }; 1026 1027 #define BTC_WL_RSSI_THMAX 4 1028 1029 struct rtw89_btc_wl_link_info { 1030 struct rtw89_btc_statistic stat; 1031 enum rtw89_tfc_dir dir; 1032 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1033 u8 mac_addr[ETH_ALEN]; 1034 u8 busy; 1035 u8 ch; 1036 u8 bw; 1037 u8 band; 1038 u8 role; 1039 u8 pid; 1040 u8 phy; 1041 u8 dtim_period; 1042 u8 mode; 1043 1044 u8 mac_id; 1045 u8 tx_retry; 1046 1047 u32 bcn_period; 1048 u32 busy_t; 1049 u32 tx_time; 1050 u32 client_cnt; 1051 u32 rx_rate_drop_cnt; 1052 1053 u32 active: 1; 1054 u32 noa: 1; 1055 u32 client_ps: 1; 1056 u32 connected: 2; 1057 }; 1058 1059 union rtw89_btc_wl_state_map { 1060 u32 val; 1061 struct rtw89_btc_wl_smap map; 1062 }; 1063 1064 struct rtw89_btc_bt_hfp_desc { 1065 u32 exist: 1; 1066 u32 type: 2; 1067 u32 rsvd: 29; 1068 }; 1069 1070 struct rtw89_btc_bt_hid_desc { 1071 u32 exist: 1; 1072 u32 slot_info: 2; 1073 u32 pair_cnt: 2; 1074 u32 type: 8; 1075 u32 rsvd: 19; 1076 }; 1077 1078 struct rtw89_btc_bt_a2dp_desc { 1079 u8 exist: 1; 1080 u8 exist_last: 1; 1081 u8 play_latency: 1; 1082 u8 type: 3; 1083 u8 active: 1; 1084 u8 sink: 1; 1085 1086 u8 bitpool; 1087 u16 vendor_id; 1088 u32 device_name; 1089 u32 flush_time; 1090 }; 1091 1092 struct rtw89_btc_bt_pan_desc { 1093 u32 exist: 1; 1094 u32 type: 1; 1095 u32 active: 1; 1096 u32 rsvd: 29; 1097 }; 1098 1099 struct rtw89_btc_bt_rfk_info { 1100 u32 run: 1; 1101 u32 req: 1; 1102 u32 timeout: 1; 1103 u32 rsvd: 29; 1104 }; 1105 1106 union rtw89_btc_bt_rfk_info_map { 1107 u32 val; 1108 struct rtw89_btc_bt_rfk_info map; 1109 }; 1110 1111 struct rtw89_btc_bt_ver_info { 1112 u32 fw_coex; /* match with which coex_ver */ 1113 u32 fw; 1114 }; 1115 1116 struct rtw89_btc_bool_sta_chg { 1117 u32 now: 1; 1118 u32 last: 1; 1119 u32 remain: 1; 1120 u32 srvd: 29; 1121 }; 1122 1123 struct rtw89_btc_u8_sta_chg { 1124 u8 now; 1125 u8 last; 1126 u8 remain; 1127 u8 rsvd; 1128 }; 1129 1130 struct rtw89_btc_wl_scan_info { 1131 u8 band[RTW89_PHY_MAX]; 1132 u8 phy_map; 1133 u8 rsvd; 1134 }; 1135 1136 struct rtw89_btc_wl_dbcc_info { 1137 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1138 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1139 u8 real_band[RTW89_PHY_MAX]; 1140 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1141 }; 1142 1143 struct rtw89_btc_wl_active_role { 1144 u8 connected: 1; 1145 u8 pid: 3; 1146 u8 phy: 1; 1147 u8 noa: 1; 1148 u8 band: 2; 1149 1150 u8 client_ps: 1; 1151 u8 bw: 7; 1152 1153 u8 role; 1154 u8 ch; 1155 1156 u16 tx_lvl; 1157 u16 rx_lvl; 1158 u16 tx_rate; 1159 u16 rx_rate; 1160 }; 1161 1162 struct rtw89_btc_wl_active_role_v1 { 1163 u8 connected: 1; 1164 u8 pid: 3; 1165 u8 phy: 1; 1166 u8 noa: 1; 1167 u8 band: 2; 1168 1169 u8 client_ps: 1; 1170 u8 bw: 7; 1171 1172 u8 role; 1173 u8 ch; 1174 1175 u16 tx_lvl; 1176 u16 rx_lvl; 1177 u16 tx_rate; 1178 u16 rx_rate; 1179 1180 u32 noa_duration; /* ms */ 1181 }; 1182 1183 struct rtw89_btc_wl_active_role_v2 { 1184 u8 connected: 1; 1185 u8 pid: 3; 1186 u8 phy: 1; 1187 u8 noa: 1; 1188 u8 band: 2; 1189 1190 u8 client_ps: 1; 1191 u8 bw: 7; 1192 1193 u8 role; 1194 u8 ch; 1195 1196 u32 noa_duration; /* ms */ 1197 }; 1198 1199 struct rtw89_btc_wl_role_info_bpos { 1200 u16 none: 1; 1201 u16 station: 1; 1202 u16 ap: 1; 1203 u16 vap: 1; 1204 u16 adhoc: 1; 1205 u16 adhoc_master: 1; 1206 u16 mesh: 1; 1207 u16 moniter: 1; 1208 u16 p2p_device: 1; 1209 u16 p2p_gc: 1; 1210 u16 p2p_go: 1; 1211 u16 nan: 1; 1212 }; 1213 1214 struct rtw89_btc_wl_scc_ctrl { 1215 u8 null_role1; 1216 u8 null_role2; 1217 u8 ebt_null; /* if tx null at EBT slot */ 1218 }; 1219 1220 union rtw89_btc_wl_role_info_map { 1221 u16 val; 1222 struct rtw89_btc_wl_role_info_bpos role; 1223 }; 1224 1225 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1226 u8 connect_cnt; 1227 u8 link_mode; 1228 union rtw89_btc_wl_role_info_map role_map; 1229 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1230 }; 1231 1232 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1233 u8 connect_cnt; 1234 u8 link_mode; 1235 union rtw89_btc_wl_role_info_map role_map; 1236 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1237 u32 mrole_type; /* btc_wl_mrole_type */ 1238 u32 mrole_noa_duration; /* ms */ 1239 1240 u32 dbcc_en: 1; 1241 u32 dbcc_chg: 1; 1242 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1243 u32 link_mode_chg: 1; 1244 u32 rsvd: 27; 1245 }; 1246 1247 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1248 u8 connect_cnt; 1249 u8 link_mode; 1250 union rtw89_btc_wl_role_info_map role_map; 1251 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1252 u32 mrole_type; /* btc_wl_mrole_type */ 1253 u32 mrole_noa_duration; /* ms */ 1254 1255 u32 dbcc_en: 1; 1256 u32 dbcc_chg: 1; 1257 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1258 u32 link_mode_chg: 1; 1259 u32 rsvd: 27; 1260 }; 1261 1262 struct rtw89_btc_wl_ver_info { 1263 u32 fw_coex; /* match with which coex_ver */ 1264 u32 fw; 1265 u32 mac; 1266 u32 bb; 1267 u32 rf; 1268 }; 1269 1270 struct rtw89_btc_wl_afh_info { 1271 u8 en; 1272 u8 ch; 1273 u8 bw; 1274 u8 rsvd; 1275 } __packed; 1276 1277 struct rtw89_btc_wl_rfk_info { 1278 u32 state: 2; 1279 u32 path_map: 4; 1280 u32 phy_map: 2; 1281 u32 band: 2; 1282 u32 type: 8; 1283 u32 rsvd: 14; 1284 }; 1285 1286 struct rtw89_btc_bt_smap { 1287 u32 connect: 1; 1288 u32 ble_connect: 1; 1289 u32 acl_busy: 1; 1290 u32 sco_busy: 1; 1291 u32 mesh_busy: 1; 1292 u32 inq_pag: 1; 1293 }; 1294 1295 union rtw89_btc_bt_state_map { 1296 u32 val; 1297 struct rtw89_btc_bt_smap map; 1298 }; 1299 1300 #define BTC_BT_RSSI_THMAX 4 1301 #define BTC_BT_AFH_GROUP 12 1302 #define BTC_BT_AFH_LE_GROUP 5 1303 1304 struct rtw89_btc_bt_link_info { 1305 struct rtw89_btc_u8_sta_chg profile_cnt; 1306 struct rtw89_btc_bool_sta_chg multi_link; 1307 struct rtw89_btc_bool_sta_chg relink; 1308 struct rtw89_btc_bt_hfp_desc hfp_desc; 1309 struct rtw89_btc_bt_hid_desc hid_desc; 1310 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1311 struct rtw89_btc_bt_pan_desc pan_desc; 1312 union rtw89_btc_bt_state_map status; 1313 1314 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1315 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1316 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1317 u8 afh_map[BTC_BT_AFH_GROUP]; 1318 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1319 1320 u32 role_sw: 1; 1321 u32 slave_role: 1; 1322 u32 afh_update: 1; 1323 u32 cqddr: 1; 1324 u32 rssi: 8; 1325 u32 tx_3m: 1; 1326 u32 rsvd: 19; 1327 }; 1328 1329 struct rtw89_btc_3rdcx_info { 1330 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1331 u8 hw_coex; 1332 u16 rsvd; 1333 }; 1334 1335 struct rtw89_btc_dm_emap { 1336 u32 init: 1; 1337 u32 pta_owner: 1; 1338 u32 wl_rfk_timeout: 1; 1339 u32 bt_rfk_timeout: 1; 1340 u32 wl_fw_hang: 1; 1341 u32 cycle_hang: 1; 1342 u32 w1_hang: 1; 1343 u32 b1_hang: 1; 1344 u32 tdma_no_sync: 1; 1345 u32 slot_no_sync: 1; 1346 u32 wl_slot_drift: 1; 1347 u32 bt_slot_drift: 1; 1348 u32 role_num_mismatch: 1; 1349 u32 null1_tx_late: 1; 1350 u32 bt_afh_conflict: 1; 1351 u32 bt_leafh_conflict: 1; 1352 u32 bt_slot_flood: 1; 1353 u32 wl_e2g_hang: 1; 1354 u32 wl_ver_mismatch: 1; 1355 u32 bt_ver_mismatch: 1; 1356 }; 1357 1358 union rtw89_btc_dm_error_map { 1359 u32 val; 1360 struct rtw89_btc_dm_emap map; 1361 }; 1362 1363 struct rtw89_btc_rf_para { 1364 u32 tx_pwr_freerun; 1365 u32 rx_gain_freerun; 1366 u32 tx_pwr_perpkt; 1367 u32 rx_gain_perpkt; 1368 }; 1369 1370 struct rtw89_btc_wl_nhm { 1371 u8 instant_wl_nhm_dbm; 1372 u8 instant_wl_nhm_per_mhz; 1373 u16 valid_record_times; 1374 s8 record_pwr[16]; 1375 u8 record_ratio[16]; 1376 s8 pwr; /* dbm_per_MHz */ 1377 u8 ratio; 1378 u8 current_status; 1379 u8 refresh; 1380 bool start_flag; 1381 u8 last_ccx_rpt_stamp; 1382 s8 pwr_max; 1383 s8 pwr_min; 1384 }; 1385 1386 struct rtw89_btc_wl_info { 1387 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1388 struct rtw89_btc_wl_rfk_info rfk_info; 1389 struct rtw89_btc_wl_ver_info ver_info; 1390 struct rtw89_btc_wl_afh_info afh_info; 1391 struct rtw89_btc_wl_role_info role_info; 1392 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1393 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1394 struct rtw89_btc_wl_scan_info scan_info; 1395 struct rtw89_btc_wl_dbcc_info dbcc_info; 1396 struct rtw89_btc_rf_para rf_para; 1397 struct rtw89_btc_wl_nhm nhm; 1398 union rtw89_btc_wl_state_map status; 1399 1400 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1401 u8 rssi_level; 1402 u8 cn_report; 1403 1404 bool scbd_change; 1405 u32 scbd; 1406 }; 1407 1408 struct rtw89_btc_module { 1409 struct rtw89_btc_ant_info ant; 1410 u8 rfe_type; 1411 u8 cv; 1412 1413 u8 bt_solo: 1; 1414 u8 bt_pos: 1; 1415 u8 switch_type: 1; 1416 1417 u8 rsvd; 1418 }; 1419 1420 #define RTW89_BTC_DM_MAXSTEP 30 1421 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1422 1423 struct rtw89_btc_dm_step { 1424 u16 step[RTW89_BTC_DM_MAXSTEP]; 1425 u8 step_pos; 1426 bool step_ov; 1427 }; 1428 1429 struct rtw89_btc_init_info { 1430 struct rtw89_btc_module module; 1431 u8 wl_guard_ch; 1432 1433 u8 wl_only: 1; 1434 u8 wl_init_ok: 1; 1435 u8 dbcc_en: 1; 1436 u8 cx_other: 1; 1437 u8 bt_only: 1; 1438 1439 u16 rsvd; 1440 }; 1441 1442 struct rtw89_btc_wl_tx_limit_para { 1443 u16 enable; 1444 u32 tx_time; /* unit: us */ 1445 u16 tx_retry; 1446 }; 1447 1448 enum rtw89_btc_bt_scan_type { 1449 BTC_SCAN_INQ = 0, 1450 BTC_SCAN_PAGE, 1451 BTC_SCAN_BLE, 1452 BTC_SCAN_INIT, 1453 BTC_SCAN_TV, 1454 BTC_SCAN_ADV, 1455 BTC_SCAN_MAX1, 1456 }; 1457 1458 enum rtw89_btc_ble_scan_type { 1459 CXSCAN_BG = 0, 1460 CXSCAN_INIT, 1461 CXSCAN_LE, 1462 CXSCAN_MAX 1463 }; 1464 1465 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1466 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1467 1468 struct rtw89_btc_bt_scan_info_v1 { 1469 __le16 win; 1470 __le16 intvl; 1471 __le32 flags; 1472 } __packed; 1473 1474 struct rtw89_btc_bt_scan_info_v2 { 1475 __le16 win; 1476 __le16 intvl; 1477 } __packed; 1478 1479 struct rtw89_btc_fbtc_btscan_v1 { 1480 u8 fver; /* btc_ver::fcxbtscan */ 1481 u8 rsvd; 1482 __le16 rsvd2; 1483 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1484 } __packed; 1485 1486 struct rtw89_btc_fbtc_btscan_v2 { 1487 u8 fver; /* btc_ver::fcxbtscan */ 1488 u8 type; 1489 __le16 rsvd2; 1490 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1491 } __packed; 1492 1493 union rtw89_btc_fbtc_btscan { 1494 struct rtw89_btc_fbtc_btscan_v1 v1; 1495 struct rtw89_btc_fbtc_btscan_v2 v2; 1496 }; 1497 1498 struct rtw89_btc_bt_info { 1499 struct rtw89_btc_bt_link_info link_info; 1500 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1501 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1502 struct rtw89_btc_bt_ver_info ver_info; 1503 struct rtw89_btc_bool_sta_chg enable; 1504 struct rtw89_btc_bool_sta_chg inq_pag; 1505 struct rtw89_btc_rf_para rf_para; 1506 union rtw89_btc_bt_rfk_info_map rfk_info; 1507 1508 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1509 1510 u32 scbd; 1511 u32 feature; 1512 1513 u32 mbx_avl: 1; 1514 u32 whql_test: 1; 1515 u32 igno_wl: 1; 1516 u32 reinit: 1; 1517 u32 ble_scan_en: 1; 1518 u32 btg_type: 1; 1519 u32 inq: 1; 1520 u32 pag: 1; 1521 u32 run_patch_code: 1; 1522 u32 hi_lna_rx: 1; 1523 u32 scan_rx_low_pri: 1; 1524 u32 scan_info_update: 1; 1525 u32 rsvd: 20; 1526 }; 1527 1528 struct rtw89_btc_cx { 1529 struct rtw89_btc_wl_info wl; 1530 struct rtw89_btc_bt_info bt; 1531 struct rtw89_btc_3rdcx_info other; 1532 u32 state_map; 1533 u32 cnt_bt[BTC_BCNT_NUM]; 1534 u32 cnt_wl[BTC_WCNT_NUM]; 1535 }; 1536 1537 struct rtw89_btc_fbtc_tdma { 1538 u8 type; /* btc_ver::fcxtdma */ 1539 u8 rxflctrl; 1540 u8 txpause; 1541 u8 wtgle_n; 1542 u8 leak_n; 1543 u8 ext_ctrl; 1544 u8 rxflctrl_role; 1545 u8 option_ctrl; 1546 } __packed; 1547 1548 struct rtw89_btc_fbtc_tdma_v3 { 1549 u8 fver; /* btc_ver::fcxtdma */ 1550 u8 rsvd; 1551 __le16 rsvd1; 1552 struct rtw89_btc_fbtc_tdma tdma; 1553 } __packed; 1554 1555 union rtw89_btc_fbtc_tdma_le32 { 1556 struct rtw89_btc_fbtc_tdma v1; 1557 struct rtw89_btc_fbtc_tdma_v3 v3; 1558 }; 1559 1560 #define CXMREG_MAX 30 1561 #define CXMREG_MAX_V2 20 1562 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1563 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1564 1565 enum rtw89_btc_bt_sta_counter { 1566 BTC_BCNT_RFK_REQ = 0, 1567 BTC_BCNT_RFK_GO = 1, 1568 BTC_BCNT_RFK_REJECT = 2, 1569 BTC_BCNT_RFK_FAIL = 3, 1570 BTC_BCNT_RFK_TIMEOUT = 4, 1571 BTC_BCNT_HI_TX = 5, 1572 BTC_BCNT_HI_RX = 6, 1573 BTC_BCNT_LO_TX = 7, 1574 BTC_BCNT_LO_RX = 8, 1575 BTC_BCNT_POLLUTED = 9, 1576 BTC_BCNT_STA_MAX 1577 }; 1578 1579 enum rtw89_btc_bt_sta_counter_v105 { 1580 BTC_BCNT_RFK_REQ_V105 = 0, 1581 BTC_BCNT_HI_TX_V105 = 1, 1582 BTC_BCNT_HI_RX_V105 = 2, 1583 BTC_BCNT_LO_TX_V105 = 3, 1584 BTC_BCNT_LO_RX_V105 = 4, 1585 BTC_BCNT_POLLUTED_V105 = 5, 1586 BTC_BCNT_STA_MAX_V105 1587 }; 1588 1589 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1590 u16 fver; /* btc_ver::fcxbtcrpt */ 1591 u16 rpt_cnt; /* tmr counters */ 1592 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1593 u32 wl_fw_cx_offload; 1594 u32 wl_fw_ver; 1595 u32 rpt_enable; 1596 u32 rpt_para; /* ms */ 1597 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1598 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1599 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1600 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1601 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1602 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1603 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1604 u32 c2h_cnt; /* fw send c2h counter */ 1605 u32 h2c_cnt; /* fw recv h2c counter */ 1606 } __packed; 1607 1608 struct rtw89_btc_fbtc_rpt_ctrl_info { 1609 __le32 cnt; /* fw report counter */ 1610 __le32 en; /* report map */ 1611 __le32 para; /* not used */ 1612 1613 __le32 cnt_c2h; /* fw send c2h counter */ 1614 __le32 cnt_h2c; /* fw recv h2c counter */ 1615 __le32 len_c2h; /* The total length of the last C2H */ 1616 1617 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1618 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1619 } __packed; 1620 1621 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1622 __le32 cx_ver; /* match which driver's coex version */ 1623 __le32 fw_ver; 1624 __le32 en; /* report map */ 1625 1626 __le16 cnt; /* fw report counter */ 1627 __le16 cnt_c2h; /* fw send c2h counter */ 1628 __le16 cnt_h2c; /* fw recv h2c counter */ 1629 __le16 len_c2h; /* The total length of the last C2H */ 1630 1631 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1632 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1633 } __packed; 1634 1635 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1636 __le32 cx_ver; /* match which driver's coex version */ 1637 __le32 cx_offload; 1638 __le32 fw_ver; 1639 } __packed; 1640 1641 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1642 __le32 cnt_empty; /* a2dp empty count */ 1643 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1644 __le32 cnt_tx; 1645 __le32 cnt_ack; 1646 __le32 cnt_nack; 1647 } __packed; 1648 1649 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1650 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1651 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1652 __le32 cnt_recv; /* fw recv mailbox counter */ 1653 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1654 } __packed; 1655 1656 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1657 u8 fver; 1658 u8 rsvd; 1659 __le16 rsvd1; 1660 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1661 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1662 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1663 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1664 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1665 } __packed; 1666 1667 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1668 u8 fver; 1669 u8 rsvd; 1670 __le16 rsvd1; 1671 1672 u8 gnt_val[RTW89_PHY_MAX][4]; 1673 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1674 1675 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1676 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1677 } __packed; 1678 1679 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1680 u8 fver; 1681 u8 rsvd; 1682 __le16 rsvd1; 1683 1684 u8 gnt_val[RTW89_PHY_MAX][4]; 1685 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1686 1687 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1688 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1689 } __packed; 1690 1691 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1692 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1693 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1694 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1695 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1696 }; 1697 1698 enum rtw89_fbtc_ext_ctrl_type { 1699 CXECTL_OFF = 0x0, /* tdma off */ 1700 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1701 CXECTL_EXT = 0x2, 1702 CXECTL_MAX 1703 }; 1704 1705 union rtw89_btc_fbtc_rxflct { 1706 u8 val; 1707 u8 type: 3; 1708 u8 tgln_n: 5; 1709 }; 1710 1711 enum rtw89_btc_cxst_state { 1712 CXST_OFF = 0x0, 1713 CXST_B2W = 0x1, 1714 CXST_W1 = 0x2, 1715 CXST_W2 = 0x3, 1716 CXST_W2B = 0x4, 1717 CXST_B1 = 0x5, 1718 CXST_B2 = 0x6, 1719 CXST_B3 = 0x7, 1720 CXST_B4 = 0x8, 1721 CXST_LK = 0x9, 1722 CXST_BLK = 0xa, 1723 CXST_E2G = 0xb, 1724 CXST_E5G = 0xc, 1725 CXST_EBT = 0xd, 1726 CXST_ENULL = 0xe, 1727 CXST_WLK = 0xf, 1728 CXST_W1FDD = 0x10, 1729 CXST_B1FDD = 0x11, 1730 CXST_MAX = 0x12, 1731 }; 1732 1733 enum rtw89_btc_cxevnt { 1734 CXEVNT_TDMA_ENTRY = 0x0, 1735 CXEVNT_WL_TMR, 1736 CXEVNT_B1_TMR, 1737 CXEVNT_B2_TMR, 1738 CXEVNT_B3_TMR, 1739 CXEVNT_B4_TMR, 1740 CXEVNT_W2B_TMR, 1741 CXEVNT_B2W_TMR, 1742 CXEVNT_BCN_EARLY, 1743 CXEVNT_A2DP_EMPTY, 1744 CXEVNT_LK_END, 1745 CXEVNT_RX_ISR, 1746 CXEVNT_RX_FC0, 1747 CXEVNT_RX_FC1, 1748 CXEVNT_BT_RELINK, 1749 CXEVNT_BT_RETRY, 1750 CXEVNT_E2G, 1751 CXEVNT_E5G, 1752 CXEVNT_EBT, 1753 CXEVNT_ENULL, 1754 CXEVNT_DRV_WLK, 1755 CXEVNT_BCN_OK, 1756 CXEVNT_BT_CHANGE, 1757 CXEVNT_EBT_EXTEND, 1758 CXEVNT_E2G_NULL1, 1759 CXEVNT_B1FDD_TMR, 1760 CXEVNT_MAX 1761 }; 1762 1763 enum { 1764 CXBCN_ALL = 0x0, 1765 CXBCN_ALL_OK, 1766 CXBCN_BT_SLOT, 1767 CXBCN_BT_OK, 1768 CXBCN_MAX 1769 }; 1770 1771 enum btc_slot_type { 1772 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1773 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1774 CXSTYPE_NUM, 1775 }; 1776 1777 enum { /* TIME */ 1778 CXT_BT = 0x0, 1779 CXT_WL = 0x1, 1780 CXT_MAX 1781 }; 1782 1783 enum { /* TIME-A2DP */ 1784 CXT_FLCTRL_OFF = 0x0, 1785 CXT_FLCTRL_ON = 0x1, 1786 CXT_FLCTRL_MAX 1787 }; 1788 1789 enum { /* STEP TYPE */ 1790 CXSTEP_NONE = 0x0, 1791 CXSTEP_EVNT = 0x1, 1792 CXSTEP_SLOT = 0x2, 1793 CXSTEP_MAX, 1794 }; 1795 1796 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 1797 RPT_BT_AFH_SEQ_LEGACY = 0x10, 1798 RPT_BT_AFH_SEQ_LE = 0x20 1799 }; 1800 1801 #define BTC_DBG_MAX1 32 1802 struct rtw89_btc_fbtc_gpio_dbg { 1803 u8 fver; /* btc_ver::fcxgpiodbg */ 1804 u8 rsvd; 1805 u16 rsvd2; 1806 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1807 u32 pre_state; /* the debug signal is 1 or 0 */ 1808 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1809 } __packed; 1810 1811 struct rtw89_btc_fbtc_mreg_val_v1 { 1812 u8 fver; /* btc_ver::fcxmreg */ 1813 u8 reg_num; 1814 __le16 rsvd; 1815 __le32 mreg_val[CXMREG_MAX]; 1816 } __packed; 1817 1818 struct rtw89_btc_fbtc_mreg_val_v2 { 1819 u8 fver; /* btc_ver::fcxmreg */ 1820 u8 reg_num; 1821 __le16 rsvd; 1822 __le32 mreg_val[CXMREG_MAX_V2]; 1823 } __packed; 1824 1825 union rtw89_btc_fbtc_mreg_val { 1826 struct rtw89_btc_fbtc_mreg_val_v1 v1; 1827 struct rtw89_btc_fbtc_mreg_val_v2 v2; 1828 }; 1829 1830 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1831 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1832 .offset = cpu_to_le32(__offset), } 1833 1834 struct rtw89_btc_fbtc_mreg { 1835 __le16 type; 1836 __le16 bytes; 1837 __le32 offset; 1838 } __packed; 1839 1840 struct rtw89_btc_fbtc_slot { 1841 __le16 dur; 1842 __le32 cxtbl; 1843 __le16 cxtype; 1844 } __packed; 1845 1846 struct rtw89_btc_fbtc_slots { 1847 u8 fver; /* btc_ver::fcxslots */ 1848 u8 tbl_num; 1849 __le16 rsvd; 1850 __le32 update_map; 1851 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1852 } __packed; 1853 1854 struct rtw89_btc_fbtc_step { 1855 u8 type; 1856 u8 val; 1857 __le16 difft; 1858 } __packed; 1859 1860 struct rtw89_btc_fbtc_steps_v2 { 1861 u8 fver; /* btc_ver::fcxstep */ 1862 u8 rsvd; 1863 __le16 cnt; 1864 __le16 pos_old; 1865 __le16 pos_new; 1866 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1867 } __packed; 1868 1869 struct rtw89_btc_fbtc_steps_v3 { 1870 u8 fver; 1871 u8 en; 1872 __le16 rsvd; 1873 __le32 cnt; 1874 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1875 } __packed; 1876 1877 union rtw89_btc_fbtc_steps_info { 1878 struct rtw89_btc_fbtc_steps_v2 v2; 1879 struct rtw89_btc_fbtc_steps_v3 v3; 1880 }; 1881 1882 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 1883 u8 fver; /* btc_ver::fcxcysta */ 1884 u8 rsvd; 1885 __le16 cycles; /* total cycle number */ 1886 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1887 __le16 a2dpept; /* a2dp empty cnt */ 1888 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1889 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1890 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1891 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1892 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1893 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1894 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1895 __le16 tmax_a2dpept; /* max a2dp empty time */ 1896 __le16 tavg_lk; /* avg leak-slot time */ 1897 __le16 tmax_lk; /* max leak-slot time */ 1898 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1899 __le32 bcn_cnt[CXBCN_MAX]; 1900 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1901 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1902 __le32 skip_cnt; 1903 __le32 exception; 1904 __le32 except_cnt; 1905 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1906 } __packed; 1907 1908 struct rtw89_btc_fbtc_fdd_try_info { 1909 __le16 cycles[CXT_FLCTRL_MAX]; 1910 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1911 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1912 } __packed; 1913 1914 struct rtw89_btc_fbtc_cycle_time_info { 1915 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1916 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1917 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1918 } __packed; 1919 1920 struct rtw89_btc_fbtc_cycle_time_info_v5 { 1921 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1922 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1923 } __packed; 1924 1925 struct rtw89_btc_fbtc_a2dp_trx_stat { 1926 u8 empty_cnt; 1927 u8 retry_cnt; 1928 u8 tx_rate; 1929 u8 tx_cnt; 1930 u8 ack_cnt; 1931 u8 nack_cnt; 1932 u8 rsvd1; 1933 u8 rsvd2; 1934 } __packed; 1935 1936 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 1937 u8 empty_cnt; 1938 u8 retry_cnt; 1939 u8 tx_rate; 1940 u8 tx_cnt; 1941 u8 ack_cnt; 1942 u8 nack_cnt; 1943 u8 no_empty_cnt; 1944 u8 rsvd; 1945 } __packed; 1946 1947 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1948 __le16 cnt; /* a2dp empty cnt */ 1949 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1950 __le16 tavg; /* avg a2dp empty time */ 1951 __le16 tmax; /* max a2dp empty time */ 1952 } __packed; 1953 1954 struct rtw89_btc_fbtc_cycle_leak_info { 1955 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1956 __le16 tavg; /* avg leak-slot time */ 1957 __le16 tmax; /* max leak-slot time */ 1958 } __packed; 1959 1960 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 1961 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 1962 1963 struct rtw89_btc_fbtc_cycle_fddt_info { 1964 __le16 train_cycle; 1965 __le16 tp; 1966 1967 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1968 s8 bt_tx_power; /* decrease Tx power (dB) */ 1969 s8 bt_rx_gain; /* LNA constrain level */ 1970 u8 no_empty_cnt; 1971 1972 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 1973 u8 cn; /* condition_num */ 1974 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 1975 u8 train_result; /* refer to enum btc_fddt_check_map */ 1976 } __packed; 1977 1978 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 1979 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 1980 1981 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 1982 __le16 train_cycle; 1983 __le16 tp; 1984 1985 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1986 s8 bt_tx_power; /* decrease Tx power (dB) */ 1987 s8 bt_rx_gain; /* LNA constrain level */ 1988 u8 no_empty_cnt; 1989 1990 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 1991 u8 cn; /* condition_num */ 1992 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 1993 u8 train_result; /* refer to enum btc_fddt_check_map */ 1994 } __packed; 1995 1996 struct rtw89_btc_fbtc_fddt_cell_status { 1997 s8 wl_tx_pwr; 1998 s8 bt_tx_pwr; 1999 s8 bt_rx_gain; 2000 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2001 } __packed; 2002 2003 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2004 s8 wl_tx_pwr; 2005 s8 bt_tx_pwr; 2006 s8 bt_rx_gain; 2007 } __packed; 2008 2009 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2010 u8 fver; 2011 u8 rsvd; 2012 __le16 cycles; /* total cycle number */ 2013 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2014 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2015 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2016 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2017 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2018 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2019 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2020 __le32 bcn_cnt[CXBCN_MAX]; 2021 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2022 __le32 skip_cnt; 2023 __le32 except_cnt; 2024 __le32 except_map; 2025 } __packed; 2026 2027 #define FDD_TRAIN_WL_DIRECTION 2 2028 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2029 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2030 2031 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2032 u8 fver; 2033 u8 rsvd; 2034 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2035 u8 except_cnt; 2036 2037 __le16 skip_cnt; 2038 __le16 cycles; /* total cycle number */ 2039 2040 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2041 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2042 __le16 bcn_cnt[CXBCN_MAX]; 2043 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2044 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2045 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2046 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2047 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2048 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2049 [FDD_TRAIN_WL_RSSI_LEVEL] 2050 [FDD_TRAIN_BT_RSSI_LEVEL]; 2051 __le32 except_map; 2052 } __packed; 2053 2054 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2055 u8 fver; 2056 u8 rsvd; 2057 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2058 u8 except_cnt; 2059 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2060 2061 __le16 skip_cnt; 2062 __le16 cycles; /* total cycle number */ 2063 2064 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2065 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2066 __le16 bcn_cnt[CXBCN_MAX]; 2067 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2068 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2069 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2070 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2071 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2072 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2073 [FDD_TRAIN_WL_RSSI_LEVEL] 2074 [FDD_TRAIN_BT_RSSI_LEVEL]; 2075 __le32 except_map; 2076 } __packed; 2077 2078 union rtw89_btc_fbtc_cysta_info { 2079 struct rtw89_btc_fbtc_cysta_v2 v2; 2080 struct rtw89_btc_fbtc_cysta_v3 v3; 2081 struct rtw89_btc_fbtc_cysta_v4 v4; 2082 struct rtw89_btc_fbtc_cysta_v5 v5; 2083 }; 2084 2085 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2086 u8 fver; /* btc_ver::fcxnullsta */ 2087 u8 rsvd; 2088 __le16 rsvd2; 2089 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2090 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2091 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2092 } __packed; 2093 2094 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2095 u8 fver; /* btc_ver::fcxnullsta */ 2096 u8 rsvd; 2097 __le16 rsvd2; 2098 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2099 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2100 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2101 } __packed; 2102 2103 union rtw89_btc_fbtc_cynullsta_info { 2104 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2105 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2106 }; 2107 2108 struct rtw89_btc_fbtc_btver { 2109 u8 fver; /* btc_ver::fcxbtver */ 2110 u8 rsvd; 2111 __le16 rsvd2; 2112 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2113 __le32 fw_ver; 2114 __le32 feature; 2115 } __packed; 2116 2117 struct rtw89_btc_fbtc_btafh { 2118 u8 fver; /* btc_ver::fcxbtafh */ 2119 u8 rsvd; 2120 __le16 rsvd2; 2121 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2122 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2123 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2124 } __packed; 2125 2126 struct rtw89_btc_fbtc_btafh_v2 { 2127 u8 fver; /* btc_ver::fcxbtafh */ 2128 u8 rsvd; 2129 u8 rsvd2; 2130 u8 map_type; 2131 u8 afh_l[4]; 2132 u8 afh_m[4]; 2133 u8 afh_h[4]; 2134 u8 afh_le_a[4]; 2135 u8 afh_le_b[4]; 2136 } __packed; 2137 2138 struct rtw89_btc_fbtc_btdevinfo { 2139 u8 fver; /* btc_ver::fcxbtdevinfo */ 2140 u8 rsvd; 2141 __le16 vendor_id; 2142 __le32 dev_name; /* only 24 bits valid */ 2143 __le32 flush_time; 2144 } __packed; 2145 2146 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2147 struct rtw89_btc_rf_trx_para { 2148 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2149 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2150 u8 bt_tx_power; /* decrease Tx power (dB) */ 2151 u8 bt_rx_gain; /* LNA constrain level */ 2152 }; 2153 2154 struct rtw89_btc_trx_info { 2155 u8 tx_lvl; 2156 u8 rx_lvl; 2157 u8 wl_rssi; 2158 u8 bt_rssi; 2159 2160 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2161 s8 rx_gain; /* rx gain table index (TBD.) */ 2162 s8 bt_tx_power; /* decrease Tx power (dB) */ 2163 s8 bt_rx_gain; /* LNA constrain level */ 2164 2165 u8 cn; /* condition_num */ 2166 s8 nhm; 2167 u8 bt_profile; 2168 u8 rsvd2; 2169 2170 u16 tx_rate; 2171 u16 rx_rate; 2172 2173 u32 tx_tp; 2174 u32 rx_tp; 2175 u32 rx_err_ratio; 2176 }; 2177 2178 struct rtw89_btc_dm { 2179 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2180 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2181 struct rtw89_btc_fbtc_tdma tdma; 2182 struct rtw89_btc_fbtc_tdma tdma_now; 2183 struct rtw89_mac_ax_coex_gnt gnt; 2184 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2185 struct rtw89_btc_rf_trx_para rf_trx_para; 2186 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2187 struct rtw89_btc_dm_step dm_step; 2188 struct rtw89_btc_wl_scc_ctrl wl_scc; 2189 struct rtw89_btc_trx_info trx_info; 2190 union rtw89_btc_dm_error_map error; 2191 u32 cnt_dm[BTC_DCNT_NUM]; 2192 u32 cnt_notify[BTC_NCNT_NUM]; 2193 2194 u32 update_slot_map; 2195 u32 set_ant_path; 2196 2197 u32 wl_only: 1; 2198 u32 wl_fw_cx_offload: 1; 2199 u32 freerun: 1; 2200 u32 fddt_train: 1; 2201 u32 wl_ps_ctrl: 2; 2202 u32 wl_mimo_ps: 1; 2203 u32 leak_ap: 1; 2204 u32 noisy_level: 3; 2205 u32 coex_info_map: 8; 2206 u32 bt_only: 1; 2207 u32 wl_btg_rx: 1; 2208 u32 trx_para_level: 8; 2209 u32 wl_stb_chg: 1; 2210 u32 pta_owner: 1; 2211 u32 tdma_instant_excute: 1; 2212 2213 u16 slot_dur[CXST_MAX]; 2214 2215 u8 run_reason; 2216 u8 run_action; 2217 2218 u8 wl_lna2: 1; 2219 }; 2220 2221 struct rtw89_btc_ctrl { 2222 u32 manual: 1; 2223 u32 igno_bt: 1; 2224 u32 always_freerun: 1; 2225 u32 trace_step: 16; 2226 u32 rsvd: 12; 2227 }; 2228 2229 struct rtw89_btc_dbg { 2230 /* cmd "rb" */ 2231 bool rb_done; 2232 u32 rb_val; 2233 }; 2234 2235 enum rtw89_btc_btf_fw_event { 2236 BTF_EVNT_RPT = 0, 2237 BTF_EVNT_BT_INFO = 1, 2238 BTF_EVNT_BT_SCBD = 2, 2239 BTF_EVNT_BT_REG = 3, 2240 BTF_EVNT_CX_RUNINFO = 4, 2241 BTF_EVNT_BT_PSD = 5, 2242 BTF_EVNT_BUF_OVERFLOW, 2243 BTF_EVNT_C2H_LOOPBACK, 2244 BTF_EVNT_MAX, 2245 }; 2246 2247 enum btf_fw_event_report { 2248 BTC_RPT_TYPE_CTRL = 0x0, 2249 BTC_RPT_TYPE_TDMA, 2250 BTC_RPT_TYPE_SLOT, 2251 BTC_RPT_TYPE_CYSTA, 2252 BTC_RPT_TYPE_STEP, 2253 BTC_RPT_TYPE_NULLSTA, 2254 BTC_RPT_TYPE_MREG, 2255 BTC_RPT_TYPE_GPIO_DBG, 2256 BTC_RPT_TYPE_BT_VER, 2257 BTC_RPT_TYPE_BT_SCAN, 2258 BTC_RPT_TYPE_BT_AFH, 2259 BTC_RPT_TYPE_BT_DEVICE, 2260 BTC_RPT_TYPE_TEST, 2261 BTC_RPT_TYPE_MAX = 31 2262 }; 2263 2264 enum rtw_btc_btf_reg_type { 2265 REG_MAC = 0x0, 2266 REG_BB = 0x1, 2267 REG_RF = 0x2, 2268 REG_BT_RF = 0x3, 2269 REG_BT_MODEM = 0x4, 2270 REG_BT_BLUEWIZE = 0x5, 2271 REG_BT_VENDOR = 0x6, 2272 REG_BT_LE = 0x7, 2273 REG_MAX_TYPE, 2274 }; 2275 2276 struct rtw89_btc_rpt_cmn_info { 2277 u32 rx_cnt; 2278 u32 rx_len; 2279 u32 req_len; /* expected rsp len */ 2280 u8 req_fver; /* expected rsp fver */ 2281 u8 rsp_fver; /* fver from fw */ 2282 u8 valid; 2283 } __packed; 2284 2285 union rtw89_btc_fbtc_btafh_info { 2286 struct rtw89_btc_fbtc_btafh v1; 2287 struct rtw89_btc_fbtc_btafh_v2 v2; 2288 }; 2289 2290 struct rtw89_btc_report_ctrl_state { 2291 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2292 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2293 }; 2294 2295 struct rtw89_btc_rpt_fbtc_tdma { 2296 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2297 union rtw89_btc_fbtc_tdma_le32 finfo; 2298 }; 2299 2300 struct rtw89_btc_rpt_fbtc_slots { 2301 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2302 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2303 }; 2304 2305 struct rtw89_btc_rpt_fbtc_cysta { 2306 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2307 union rtw89_btc_fbtc_cysta_info finfo; 2308 }; 2309 2310 struct rtw89_btc_rpt_fbtc_step { 2311 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2312 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2313 }; 2314 2315 struct rtw89_btc_rpt_fbtc_nullsta { 2316 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2317 union rtw89_btc_fbtc_cynullsta_info finfo; 2318 }; 2319 2320 struct rtw89_btc_rpt_fbtc_mreg { 2321 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2322 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2323 }; 2324 2325 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2326 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2327 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2328 }; 2329 2330 struct rtw89_btc_rpt_fbtc_btver { 2331 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2332 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2333 }; 2334 2335 struct rtw89_btc_rpt_fbtc_btscan { 2336 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2337 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2338 }; 2339 2340 struct rtw89_btc_rpt_fbtc_btafh { 2341 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2342 union rtw89_btc_fbtc_btafh_info finfo; 2343 }; 2344 2345 struct rtw89_btc_rpt_fbtc_btdev { 2346 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2347 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2348 }; 2349 2350 enum rtw89_btc_btfre_type { 2351 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2352 BTFRE_UNDEF_TYPE, 2353 BTFRE_EXCEPTION, 2354 BTFRE_MAX, 2355 }; 2356 2357 struct rtw89_btc_btf_fwinfo { 2358 u32 cnt_c2h; 2359 u32 cnt_h2c; 2360 u32 cnt_h2c_fail; 2361 u32 event[BTF_EVNT_MAX]; 2362 2363 u32 err[BTFRE_MAX]; 2364 u32 len_mismch; 2365 u32 fver_mismch; 2366 u32 rpt_en_map; 2367 2368 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2369 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2370 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2371 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2372 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2373 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2374 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2375 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2376 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2377 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2378 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2379 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2380 }; 2381 2382 struct rtw89_btc_ver { 2383 enum rtw89_core_chip_id chip_id; 2384 u32 fw_ver_code; 2385 2386 u8 fcxbtcrpt; 2387 u8 fcxtdma; 2388 u8 fcxslots; 2389 u8 fcxcysta; 2390 u8 fcxstep; 2391 u8 fcxnullsta; 2392 u8 fcxmreg; 2393 u8 fcxgpiodbg; 2394 u8 fcxbtver; 2395 u8 fcxbtscan; 2396 u8 fcxbtafh; 2397 u8 fcxbtdevinfo; 2398 u8 fwlrole; 2399 u8 frptmap; 2400 u8 fcxctrl; 2401 2402 u16 info_buf; 2403 u8 max_role_num; 2404 }; 2405 2406 #define RTW89_BTC_POLICY_MAXLEN 512 2407 2408 struct rtw89_btc { 2409 const struct rtw89_btc_ver *ver; 2410 2411 struct rtw89_btc_cx cx; 2412 struct rtw89_btc_dm dm; 2413 struct rtw89_btc_ctrl ctrl; 2414 struct rtw89_btc_module mdinfo; 2415 struct rtw89_btc_btf_fwinfo fwinfo; 2416 struct rtw89_btc_dbg dbg; 2417 2418 struct work_struct eapol_notify_work; 2419 struct work_struct arp_notify_work; 2420 struct work_struct dhcp_notify_work; 2421 struct work_struct icmp_notify_work; 2422 2423 u32 bt_req_len; 2424 2425 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2426 u16 policy_len; 2427 u16 policy_type; 2428 bool bt_req_en; 2429 bool update_policy_force; 2430 bool lps; 2431 }; 2432 2433 enum rtw89_ra_mode { 2434 RTW89_RA_MODE_CCK = BIT(0), 2435 RTW89_RA_MODE_OFDM = BIT(1), 2436 RTW89_RA_MODE_HT = BIT(2), 2437 RTW89_RA_MODE_VHT = BIT(3), 2438 RTW89_RA_MODE_HE = BIT(4), 2439 }; 2440 2441 enum rtw89_ra_report_mode { 2442 RTW89_RA_RPT_MODE_LEGACY, 2443 RTW89_RA_RPT_MODE_HT, 2444 RTW89_RA_RPT_MODE_VHT, 2445 RTW89_RA_RPT_MODE_HE, 2446 }; 2447 2448 enum rtw89_dig_noisy_level { 2449 RTW89_DIG_NOISY_LEVEL0 = -1, 2450 RTW89_DIG_NOISY_LEVEL1 = 0, 2451 RTW89_DIG_NOISY_LEVEL2 = 1, 2452 RTW89_DIG_NOISY_LEVEL3 = 2, 2453 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2454 }; 2455 2456 enum rtw89_gi_ltf { 2457 RTW89_GILTF_LGI_4XHE32 = 0, 2458 RTW89_GILTF_SGI_4XHE08 = 1, 2459 RTW89_GILTF_2XHE16 = 2, 2460 RTW89_GILTF_2XHE08 = 3, 2461 RTW89_GILTF_1XHE16 = 4, 2462 RTW89_GILTF_1XHE08 = 5, 2463 RTW89_GILTF_MAX 2464 }; 2465 2466 enum rtw89_rx_frame_type { 2467 RTW89_RX_TYPE_MGNT = 0, 2468 RTW89_RX_TYPE_CTRL = 1, 2469 RTW89_RX_TYPE_DATA = 2, 2470 RTW89_RX_TYPE_RSVD = 3, 2471 }; 2472 2473 struct rtw89_ra_info { 2474 u8 is_dis_ra:1; 2475 /* Bit0 : CCK 2476 * Bit1 : OFDM 2477 * Bit2 : HT 2478 * Bit3 : VHT 2479 * Bit4 : HE 2480 */ 2481 u8 mode_ctrl:5; 2482 u8 bw_cap:2; 2483 u8 macid; 2484 u8 dcm_cap:1; 2485 u8 er_cap:1; 2486 u8 init_rate_lv:2; 2487 u8 upd_all:1; 2488 u8 en_sgi:1; 2489 u8 ldpc_cap:1; 2490 u8 stbc_cap:1; 2491 u8 ss_num:3; 2492 u8 giltf:3; 2493 u8 upd_bw_nss_mask:1; 2494 u8 upd_mask:1; 2495 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2496 /* BFee CSI */ 2497 u8 band_num; 2498 u8 ra_csi_rate_en:1; 2499 u8 fixed_csi_rate_en:1; 2500 u8 cr_tbl_sel:1; 2501 u8 fix_giltf_en:1; 2502 u8 fix_giltf:3; 2503 u8 rsvd2:1; 2504 u8 csi_mcs_ss_idx; 2505 u8 csi_mode:2; 2506 u8 csi_gi_ltf:3; 2507 u8 csi_bw:3; 2508 }; 2509 2510 #define RTW89_PPDU_MAX_USR 4 2511 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2512 #define RTW89_PPDU_MAC_INFO_SIZE 8 2513 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2514 2515 #define RTW89_MAX_RX_AGG_NUM 64 2516 #define RTW89_MAX_TX_AGG_NUM 128 2517 2518 struct rtw89_ampdu_params { 2519 u16 agg_num; 2520 bool amsdu; 2521 }; 2522 2523 struct rtw89_ra_report { 2524 struct rate_info txrate; 2525 u32 bit_rate; 2526 u16 hw_rate; 2527 bool might_fallback_legacy; 2528 }; 2529 2530 DECLARE_EWMA(rssi, 10, 16); 2531 2532 struct rtw89_ba_cam_entry { 2533 struct list_head list; 2534 u8 tid; 2535 }; 2536 2537 #define RTW89_MAX_ADDR_CAM_NUM 128 2538 #define RTW89_MAX_BSSID_CAM_NUM 20 2539 #define RTW89_MAX_SEC_CAM_NUM 128 2540 #define RTW89_MAX_BA_CAM_NUM 8 2541 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2542 2543 struct rtw89_addr_cam_entry { 2544 u8 addr_cam_idx; 2545 u8 offset; 2546 u8 len; 2547 u8 valid : 1; 2548 u8 addr_mask : 6; 2549 u8 wapi : 1; 2550 u8 mask_sel : 2; 2551 u8 bssid_cam_idx: 6; 2552 2553 u8 sec_ent_mode; 2554 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2555 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2556 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2557 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2558 }; 2559 2560 struct rtw89_bssid_cam_entry { 2561 u8 bssid[ETH_ALEN]; 2562 u8 phy_idx; 2563 u8 bssid_cam_idx; 2564 u8 offset; 2565 u8 len; 2566 u8 valid : 1; 2567 u8 num; 2568 }; 2569 2570 struct rtw89_sec_cam_entry { 2571 u8 sec_cam_idx; 2572 u8 offset; 2573 u8 len; 2574 u8 type : 4; 2575 u8 ext_key : 1; 2576 u8 spp_mode : 1; 2577 /* 256 bits */ 2578 u8 key[32]; 2579 }; 2580 2581 struct rtw89_sta { 2582 u8 mac_id; 2583 bool disassoc; 2584 bool er_cap; 2585 struct rtw89_dev *rtwdev; 2586 struct rtw89_vif *rtwvif; 2587 struct rtw89_ra_info ra; 2588 struct rtw89_ra_report ra_report; 2589 int max_agg_wait; 2590 u8 prev_rssi; 2591 struct ewma_rssi avg_rssi; 2592 struct ewma_rssi rssi[RF_PATH_MAX]; 2593 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2594 struct ieee80211_rx_status rx_status; 2595 u16 rx_hw_rate; 2596 __le32 htc_template; 2597 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2598 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2599 struct list_head ba_cam_list; 2600 2601 bool use_cfg_mask; 2602 struct cfg80211_bitrate_mask mask; 2603 2604 bool cctl_tx_time; 2605 u32 ampdu_max_time:4; 2606 bool cctl_tx_retry_limit; 2607 u32 data_tx_cnt_lmt:6; 2608 }; 2609 2610 struct rtw89_efuse { 2611 bool valid; 2612 bool power_k_valid; 2613 u8 xtal_cap; 2614 u8 addr[ETH_ALEN]; 2615 u8 rfe_type; 2616 char country_code[2]; 2617 }; 2618 2619 struct rtw89_phy_rate_pattern { 2620 u64 ra_mask; 2621 u16 rate; 2622 u8 ra_mode; 2623 bool enable; 2624 }; 2625 2626 #define RTW89_P2P_MAX_NOA_NUM 2 2627 2628 struct rtw89_vif { 2629 struct list_head list; 2630 struct rtw89_dev *rtwdev; 2631 enum rtw89_sub_entity_idx sub_entity_idx; 2632 2633 u8 mac_id; 2634 u8 port; 2635 u8 mac_addr[ETH_ALEN]; 2636 u8 bssid[ETH_ALEN]; 2637 u8 phy_idx; 2638 u8 mac_idx; 2639 u8 net_type; 2640 u8 wifi_role; 2641 u8 self_role; 2642 u8 wmm; 2643 u8 bcn_hit_cond; 2644 u8 hit_rule; 2645 u8 last_noa_nr; 2646 bool trigger; 2647 bool lsig_txop; 2648 u8 tgt_ind; 2649 u8 frm_tgt_ind; 2650 bool wowlan_pattern; 2651 bool wowlan_uc; 2652 bool wowlan_magic; 2653 bool is_hesta; 2654 bool last_a_ctrl; 2655 bool dyn_tb_bedge_en; 2656 u8 def_tri_idx; 2657 u32 tdls_peer; 2658 struct work_struct update_beacon_work; 2659 struct rtw89_addr_cam_entry addr_cam; 2660 struct rtw89_bssid_cam_entry bssid_cam; 2661 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2662 struct rtw89_traffic_stats stats; 2663 struct rtw89_phy_rate_pattern rate_pattern; 2664 struct cfg80211_scan_request *scan_req; 2665 struct ieee80211_scan_ies *scan_ies; 2666 struct list_head general_pkt_list; 2667 }; 2668 2669 enum rtw89_lv1_rcvy_step { 2670 RTW89_LV1_RCVY_STEP_1, 2671 RTW89_LV1_RCVY_STEP_2, 2672 }; 2673 2674 struct rtw89_hci_ops { 2675 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2676 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2677 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2678 void (*reset)(struct rtw89_dev *rtwdev); 2679 int (*start)(struct rtw89_dev *rtwdev); 2680 void (*stop)(struct rtw89_dev *rtwdev); 2681 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2682 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2683 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2684 2685 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2686 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2687 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2688 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2689 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2690 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2691 2692 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2693 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2694 int (*deinit)(struct rtw89_dev *rtwdev); 2695 2696 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2697 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2698 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2699 int (*napi_poll)(struct napi_struct *napi, int budget); 2700 2701 /* Deal with locks inside recovery_start and recovery_complete callbacks 2702 * by hci instance, and handle things which need to consider under SER. 2703 * e.g. turn on/off interrupts except for the one for halt notification. 2704 */ 2705 void (*recovery_start)(struct rtw89_dev *rtwdev); 2706 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2707 2708 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 2709 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 2710 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 2711 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 2712 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 2713 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 2714 void (*disable_intr)(struct rtw89_dev *rtwdev); 2715 void (*enable_intr)(struct rtw89_dev *rtwdev); 2716 int (*rst_bdram)(struct rtw89_dev *rtwdev); 2717 }; 2718 2719 struct rtw89_hci_info { 2720 const struct rtw89_hci_ops *ops; 2721 enum rtw89_hci_type type; 2722 u32 rpwm_addr; 2723 u32 cpwm_addr; 2724 bool paused; 2725 }; 2726 2727 struct rtw89_chip_ops { 2728 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2729 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2730 void (*bb_reset)(struct rtw89_dev *rtwdev, 2731 enum rtw89_phy_idx phy_idx); 2732 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2733 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2734 u32 addr, u32 mask); 2735 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2736 u32 addr, u32 mask, u32 data); 2737 void (*set_channel)(struct rtw89_dev *rtwdev, 2738 const struct rtw89_chan *chan, 2739 enum rtw89_mac_idx mac_idx, 2740 enum rtw89_phy_idx phy_idx); 2741 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2742 struct rtw89_channel_help_params *p, 2743 const struct rtw89_chan *chan, 2744 enum rtw89_mac_idx mac_idx, 2745 enum rtw89_phy_idx phy_idx); 2746 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2747 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2748 void (*fem_setup)(struct rtw89_dev *rtwdev); 2749 void (*rfk_init)(struct rtw89_dev *rtwdev); 2750 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2751 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2752 enum rtw89_phy_idx phy_idx); 2753 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2754 void (*rfk_track)(struct rtw89_dev *rtwdev); 2755 void (*power_trim)(struct rtw89_dev *rtwdev); 2756 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2757 const struct rtw89_chan *chan, 2758 enum rtw89_phy_idx phy_idx); 2759 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2760 enum rtw89_phy_idx phy_idx); 2761 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2762 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2763 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2764 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2765 struct rtw89_rx_phy_ppdu *phy_ppdu, 2766 struct ieee80211_rx_status *status); 2767 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2768 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2769 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2770 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2771 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2772 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2773 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2774 struct rtw89_tx_desc_info *desc_info, 2775 void *txdesc); 2776 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2777 struct rtw89_tx_desc_info *desc_info, 2778 void *txdesc); 2779 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2780 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2781 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2782 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2783 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2784 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2785 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2786 struct rtw89_vif *rtwvif, 2787 struct rtw89_sta *rtwsta); 2788 2789 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2790 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2791 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2792 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2793 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2794 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2795 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2796 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2797 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2798 }; 2799 2800 enum rtw89_dma_ch { 2801 RTW89_DMA_ACH0 = 0, 2802 RTW89_DMA_ACH1 = 1, 2803 RTW89_DMA_ACH2 = 2, 2804 RTW89_DMA_ACH3 = 3, 2805 RTW89_DMA_ACH4 = 4, 2806 RTW89_DMA_ACH5 = 5, 2807 RTW89_DMA_ACH6 = 6, 2808 RTW89_DMA_ACH7 = 7, 2809 RTW89_DMA_B0MG = 8, 2810 RTW89_DMA_B0HI = 9, 2811 RTW89_DMA_B1MG = 10, 2812 RTW89_DMA_B1HI = 11, 2813 RTW89_DMA_H2C = 12, 2814 RTW89_DMA_CH_NUM = 13 2815 }; 2816 2817 enum rtw89_qta_mode { 2818 RTW89_QTA_SCC, 2819 RTW89_QTA_DLFW, 2820 RTW89_QTA_WOW, 2821 2822 /* keep last */ 2823 RTW89_QTA_INVALID, 2824 }; 2825 2826 struct rtw89_hfc_ch_cfg { 2827 u16 min; 2828 u16 max; 2829 #define grp_0 0 2830 #define grp_1 1 2831 #define grp_num 2 2832 u8 grp; 2833 }; 2834 2835 struct rtw89_hfc_ch_info { 2836 u16 aval; 2837 u16 used; 2838 }; 2839 2840 struct rtw89_hfc_pub_cfg { 2841 u16 grp0; 2842 u16 grp1; 2843 u16 pub_max; 2844 u16 wp_thrd; 2845 }; 2846 2847 struct rtw89_hfc_pub_info { 2848 u16 g0_used; 2849 u16 g1_used; 2850 u16 g0_aval; 2851 u16 g1_aval; 2852 u16 pub_aval; 2853 u16 wp_aval; 2854 }; 2855 2856 struct rtw89_hfc_prec_cfg { 2857 u16 ch011_prec; 2858 u16 h2c_prec; 2859 u16 wp_ch07_prec; 2860 u16 wp_ch811_prec; 2861 u8 ch011_full_cond; 2862 u8 h2c_full_cond; 2863 u8 wp_ch07_full_cond; 2864 u8 wp_ch811_full_cond; 2865 }; 2866 2867 struct rtw89_hfc_param { 2868 bool en; 2869 bool h2c_en; 2870 u8 mode; 2871 const struct rtw89_hfc_ch_cfg *ch_cfg; 2872 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2873 struct rtw89_hfc_pub_cfg pub_cfg; 2874 struct rtw89_hfc_pub_info pub_info; 2875 struct rtw89_hfc_prec_cfg prec_cfg; 2876 }; 2877 2878 struct rtw89_hfc_param_ini { 2879 const struct rtw89_hfc_ch_cfg *ch_cfg; 2880 const struct rtw89_hfc_pub_cfg *pub_cfg; 2881 const struct rtw89_hfc_prec_cfg *prec_cfg; 2882 u8 mode; 2883 }; 2884 2885 struct rtw89_dle_size { 2886 u16 pge_size; 2887 u16 lnk_pge_num; 2888 u16 unlnk_pge_num; 2889 }; 2890 2891 struct rtw89_wde_quota { 2892 u16 hif; 2893 u16 wcpu; 2894 u16 pkt_in; 2895 u16 cpu_io; 2896 }; 2897 2898 struct rtw89_ple_quota { 2899 u16 cma0_tx; 2900 u16 cma1_tx; 2901 u16 c2h; 2902 u16 h2c; 2903 u16 wcpu; 2904 u16 mpdu_proc; 2905 u16 cma0_dma; 2906 u16 cma1_dma; 2907 u16 bb_rpt; 2908 u16 wd_rel; 2909 u16 cpu_io; 2910 u16 tx_rpt; 2911 }; 2912 2913 struct rtw89_dle_mem { 2914 enum rtw89_qta_mode mode; 2915 const struct rtw89_dle_size *wde_size; 2916 const struct rtw89_dle_size *ple_size; 2917 const struct rtw89_wde_quota *wde_min_qt; 2918 const struct rtw89_wde_quota *wde_max_qt; 2919 const struct rtw89_ple_quota *ple_min_qt; 2920 const struct rtw89_ple_quota *ple_max_qt; 2921 }; 2922 2923 struct rtw89_reg_def { 2924 u32 addr; 2925 u32 mask; 2926 }; 2927 2928 struct rtw89_reg2_def { 2929 u32 addr; 2930 u32 data; 2931 }; 2932 2933 struct rtw89_reg3_def { 2934 u32 addr; 2935 u32 mask; 2936 u32 data; 2937 }; 2938 2939 struct rtw89_reg5_def { 2940 u8 flag; /* recognized by parsers */ 2941 u8 path; 2942 u32 addr; 2943 u32 mask; 2944 u32 data; 2945 }; 2946 2947 struct rtw89_phy_table { 2948 const struct rtw89_reg2_def *regs; 2949 u32 n_regs; 2950 enum rtw89_rf_path rf_path; 2951 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2952 enum rtw89_rf_path rf_path, void *data); 2953 }; 2954 2955 struct rtw89_txpwr_table { 2956 const void *data; 2957 u32 size; 2958 void (*load)(struct rtw89_dev *rtwdev, 2959 const struct rtw89_txpwr_table *tbl); 2960 }; 2961 2962 struct rtw89_page_regs { 2963 u32 hci_fc_ctrl; 2964 u32 ch_page_ctrl; 2965 u32 ach_page_ctrl; 2966 u32 ach_page_info; 2967 u32 pub_page_info3; 2968 u32 pub_page_ctrl1; 2969 u32 pub_page_ctrl2; 2970 u32 pub_page_info1; 2971 u32 pub_page_info2; 2972 u32 wp_page_ctrl1; 2973 u32 wp_page_ctrl2; 2974 u32 wp_page_info1; 2975 }; 2976 2977 struct rtw89_imr_info { 2978 u32 wdrls_imr_set; 2979 u32 wsec_imr_reg; 2980 u32 wsec_imr_set; 2981 u32 mpdu_tx_imr_set; 2982 u32 mpdu_rx_imr_set; 2983 u32 sta_sch_imr_set; 2984 u32 txpktctl_imr_b0_reg; 2985 u32 txpktctl_imr_b0_clr; 2986 u32 txpktctl_imr_b0_set; 2987 u32 txpktctl_imr_b1_reg; 2988 u32 txpktctl_imr_b1_clr; 2989 u32 txpktctl_imr_b1_set; 2990 u32 wde_imr_clr; 2991 u32 wde_imr_set; 2992 u32 ple_imr_clr; 2993 u32 ple_imr_set; 2994 u32 host_disp_imr_clr; 2995 u32 host_disp_imr_set; 2996 u32 cpu_disp_imr_clr; 2997 u32 cpu_disp_imr_set; 2998 u32 other_disp_imr_clr; 2999 u32 other_disp_imr_set; 3000 u32 bbrpt_com_err_imr_reg; 3001 u32 bbrpt_chinfo_err_imr_reg; 3002 u32 bbrpt_err_imr_set; 3003 u32 bbrpt_dfs_err_imr_reg; 3004 u32 ptcl_imr_clr; 3005 u32 ptcl_imr_set; 3006 u32 cdma_imr_0_reg; 3007 u32 cdma_imr_0_clr; 3008 u32 cdma_imr_0_set; 3009 u32 cdma_imr_1_reg; 3010 u32 cdma_imr_1_clr; 3011 u32 cdma_imr_1_set; 3012 u32 phy_intf_imr_reg; 3013 u32 phy_intf_imr_clr; 3014 u32 phy_intf_imr_set; 3015 u32 rmac_imr_reg; 3016 u32 rmac_imr_clr; 3017 u32 rmac_imr_set; 3018 u32 tmac_imr_reg; 3019 u32 tmac_imr_clr; 3020 u32 tmac_imr_set; 3021 }; 3022 3023 struct rtw89_rrsr_cfgs { 3024 struct rtw89_reg3_def ref_rate; 3025 struct rtw89_reg3_def rsc; 3026 }; 3027 3028 struct rtw89_dig_regs { 3029 u32 seg0_pd_reg; 3030 u32 pd_lower_bound_mask; 3031 u32 pd_spatial_reuse_en; 3032 struct rtw89_reg_def p0_lna_init; 3033 struct rtw89_reg_def p1_lna_init; 3034 struct rtw89_reg_def p0_tia_init; 3035 struct rtw89_reg_def p1_tia_init; 3036 struct rtw89_reg_def p0_rxb_init; 3037 struct rtw89_reg_def p1_rxb_init; 3038 struct rtw89_reg_def p0_p20_pagcugc_en; 3039 struct rtw89_reg_def p0_s20_pagcugc_en; 3040 struct rtw89_reg_def p1_p20_pagcugc_en; 3041 struct rtw89_reg_def p1_s20_pagcugc_en; 3042 }; 3043 3044 struct rtw89_phy_ul_tb_info { 3045 bool dyn_tb_tri_en; 3046 u8 def_if_bandedge; 3047 }; 3048 3049 struct rtw89_chip_info { 3050 enum rtw89_core_chip_id chip_id; 3051 const struct rtw89_chip_ops *ops; 3052 const char *fw_name; 3053 bool try_ce_fw; 3054 u32 fifo_size; 3055 u32 dle_scc_rsvd_size; 3056 u16 max_amsdu_limit; 3057 bool dis_2g_40m_ul_ofdma; 3058 u32 rsvd_ple_ofst; 3059 const struct rtw89_hfc_param_ini *hfc_param_ini; 3060 const struct rtw89_dle_mem *dle_mem; 3061 u8 wde_qempty_acq_num; 3062 u8 wde_qempty_mgq_sel; 3063 u32 rf_base_addr[2]; 3064 u8 support_chanctx_num; 3065 u8 support_bands; 3066 bool support_bw160; 3067 bool support_ul_tb_ctrl; 3068 bool hw_sec_hdr; 3069 u8 rf_path_num; 3070 u8 tx_nss; 3071 u8 rx_nss; 3072 u8 acam_num; 3073 u8 bcam_num; 3074 u8 scam_num; 3075 u8 bacam_num; 3076 u8 bacam_dynamic_num; 3077 bool bacam_v1; 3078 3079 u8 sec_ctrl_efuse_size; 3080 u32 physical_efuse_size; 3081 u32 logical_efuse_size; 3082 u32 limit_efuse_size; 3083 u32 dav_phy_efuse_size; 3084 u32 dav_log_efuse_size; 3085 u32 phycap_addr; 3086 u32 phycap_size; 3087 3088 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3089 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3090 const struct rtw89_phy_table *bb_table; 3091 const struct rtw89_phy_table *bb_gain_table; 3092 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3093 const struct rtw89_phy_table *nctl_table; 3094 const struct rtw89_txpwr_table *byr_table; 3095 const struct rtw89_phy_dig_gain_table *dig_table; 3096 const struct rtw89_dig_regs *dig_regs; 3097 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3098 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3099 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3100 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3101 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3102 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3103 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3104 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3105 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3106 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 3107 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 3108 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3109 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 3110 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3111 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 3112 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 3113 3114 u8 txpwr_factor_rf; 3115 u8 txpwr_factor_mac; 3116 3117 u32 para_ver; 3118 u32 wlcx_desired; 3119 u8 btcx_desired; 3120 u8 scbd; 3121 u8 mailbox; 3122 3123 u8 afh_guard_ch; 3124 const u8 *wl_rssi_thres; 3125 const u8 *bt_rssi_thres; 3126 u8 rssi_tol; 3127 3128 u8 mon_reg_num; 3129 const struct rtw89_btc_fbtc_mreg *mon_reg; 3130 u8 rf_para_ulink_num; 3131 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3132 u8 rf_para_dlink_num; 3133 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3134 u8 ps_mode_supported; 3135 u8 low_power_hci_modes; 3136 3137 u32 h2c_cctl_func_id; 3138 u32 hci_func_en_addr; 3139 u32 h2c_desc_size; 3140 u32 txwd_body_size; 3141 u32 h2c_ctrl_reg; 3142 const u32 *h2c_regs; 3143 struct rtw89_reg_def h2c_counter_reg; 3144 u32 c2h_ctrl_reg; 3145 const u32 *c2h_regs; 3146 struct rtw89_reg_def c2h_counter_reg; 3147 const struct rtw89_page_regs *page_regs; 3148 bool cfo_src_fd; 3149 const struct rtw89_reg_def *dcfo_comp; 3150 u8 dcfo_comp_sft; 3151 const struct rtw89_imr_info *imr_info; 3152 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3153 u32 bss_clr_map_reg; 3154 u32 dma_ch_mask; 3155 u32 edcca_lvl_reg; 3156 const struct wiphy_wowlan_support *wowlan_stub; 3157 }; 3158 3159 union rtw89_bus_info { 3160 const struct rtw89_pci_info *pci; 3161 }; 3162 3163 struct rtw89_driver_info { 3164 const struct rtw89_chip_info *chip; 3165 union rtw89_bus_info bus; 3166 }; 3167 3168 enum rtw89_hcifc_mode { 3169 RTW89_HCIFC_POH = 0, 3170 RTW89_HCIFC_STF = 1, 3171 RTW89_HCIFC_SDIO = 2, 3172 3173 /* keep last */ 3174 RTW89_HCIFC_MODE_INVALID, 3175 }; 3176 3177 struct rtw89_dle_info { 3178 enum rtw89_qta_mode qta_mode; 3179 u16 wde_pg_size; 3180 u16 ple_pg_size; 3181 u16 c0_rx_qta; 3182 u16 c1_rx_qta; 3183 }; 3184 3185 enum rtw89_host_rpr_mode { 3186 RTW89_RPR_MODE_POH = 0, 3187 RTW89_RPR_MODE_STF 3188 }; 3189 3190 struct rtw89_mac_info { 3191 struct rtw89_dle_info dle_info; 3192 struct rtw89_hfc_param hfc_param; 3193 enum rtw89_qta_mode qta_mode; 3194 u8 rpwm_seq_num; 3195 u8 cpwm_seq_num; 3196 }; 3197 3198 #define RTW89_COMPLETION_BUF_SIZE 24 3199 #define RTW89_WAIT_COND_IDLE UINT_MAX 3200 3201 struct rtw89_completion_data { 3202 bool err; 3203 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3204 }; 3205 3206 struct rtw89_wait_info { 3207 atomic_t cond; 3208 struct completion completion; 3209 struct rtw89_completion_data data; 3210 }; 3211 3212 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3213 3214 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3215 { 3216 init_completion(&wait->completion); 3217 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3218 } 3219 3220 enum rtw89_fw_type { 3221 RTW89_FW_NORMAL = 1, 3222 RTW89_FW_WOWLAN = 3, 3223 RTW89_FW_NORMAL_CE = 5, 3224 }; 3225 3226 enum rtw89_fw_feature { 3227 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3228 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3229 RTW89_FW_FEATURE_TX_WAKE, 3230 RTW89_FW_FEATURE_CRASH_TRIGGER, 3231 RTW89_FW_FEATURE_NO_PACKET_DROP, 3232 RTW89_FW_FEATURE_NO_DEEP_PS, 3233 RTW89_FW_FEATURE_NO_LPS_PG, 3234 }; 3235 3236 struct rtw89_fw_suit { 3237 const u8 *data; 3238 u32 size; 3239 u8 major_ver; 3240 u8 minor_ver; 3241 u8 sub_ver; 3242 u8 sub_idex; 3243 u16 build_year; 3244 u16 build_mon; 3245 u16 build_date; 3246 u16 build_hour; 3247 u16 build_min; 3248 u8 cmd_ver; 3249 }; 3250 3251 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3252 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3253 #define RTW89_FW_SUIT_VER_CODE(s) \ 3254 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3255 3256 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3257 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3258 (mfw_hdr)->ver.minor, \ 3259 (mfw_hdr)->ver.sub, \ 3260 (mfw_hdr)->ver.idx) 3261 3262 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3263 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 3264 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 3265 GET_FW_HDR_SUBVERSION(fw_hdr), \ 3266 GET_FW_HDR_SUBINDEX(fw_hdr)) 3267 3268 struct rtw89_fw_info { 3269 const struct firmware *firmware; 3270 struct rtw89_dev *rtwdev; 3271 struct completion completion; 3272 u8 h2c_seq; 3273 u8 rec_seq; 3274 u8 h2c_counter; 3275 u8 c2h_counter; 3276 struct rtw89_fw_suit normal; 3277 struct rtw89_fw_suit wowlan; 3278 bool fw_log_enable; 3279 u32 feature_map; 3280 }; 3281 3282 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3283 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3284 3285 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3286 ((_fw)->feature_map |= BIT(_fw_feature)) 3287 3288 struct rtw89_cam_info { 3289 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3290 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3291 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3292 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3293 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3294 }; 3295 3296 enum rtw89_sar_sources { 3297 RTW89_SAR_SOURCE_NONE, 3298 RTW89_SAR_SOURCE_COMMON, 3299 3300 RTW89_SAR_SOURCE_NR, 3301 }; 3302 3303 enum rtw89_sar_subband { 3304 RTW89_SAR_2GHZ_SUBBAND, 3305 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3306 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3307 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3308 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3309 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3310 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3311 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3312 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3313 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3314 3315 RTW89_SAR_SUBBAND_NR, 3316 }; 3317 3318 struct rtw89_sar_cfg_common { 3319 bool set[RTW89_SAR_SUBBAND_NR]; 3320 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3321 }; 3322 3323 struct rtw89_sar_info { 3324 /* used to decide how to acces SAR cfg union */ 3325 enum rtw89_sar_sources src; 3326 3327 /* reserved for different knids of SAR cfg struct. 3328 * supposed that a single cfg struct cannot handle various SAR sources. 3329 */ 3330 union { 3331 struct rtw89_sar_cfg_common cfg_common; 3332 }; 3333 }; 3334 3335 struct rtw89_chanctx_cfg { 3336 enum rtw89_sub_entity_idx idx; 3337 }; 3338 3339 enum rtw89_entity_mode { 3340 RTW89_ENTITY_MODE_SCC, 3341 }; 3342 3343 struct rtw89_sub_entity { 3344 struct cfg80211_chan_def chandef; 3345 struct rtw89_chan chan; 3346 struct rtw89_chan_rcd rcd; 3347 struct rtw89_chanctx_cfg *cfg; 3348 }; 3349 3350 struct rtw89_hal { 3351 u32 rx_fltr; 3352 u8 cv; 3353 u32 sw_amsdu_max_size; 3354 u32 antenna_tx; 3355 u32 antenna_rx; 3356 u8 tx_nss; 3357 u8 rx_nss; 3358 bool tx_path_diversity; 3359 bool support_cckpd; 3360 bool support_igi; 3361 3362 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 3363 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 3364 3365 bool entity_active; 3366 enum rtw89_entity_mode entity_mode; 3367 3368 u32 edcca_bak; 3369 }; 3370 3371 #define RTW89_MAX_MAC_ID_NUM 128 3372 #define RTW89_MAX_PKT_OFLD_NUM 255 3373 3374 enum rtw89_flags { 3375 RTW89_FLAG_POWERON, 3376 RTW89_FLAG_FW_RDY, 3377 RTW89_FLAG_RUNNING, 3378 RTW89_FLAG_BFEE_MON, 3379 RTW89_FLAG_BFEE_EN, 3380 RTW89_FLAG_BFEE_TIMER_KEEP, 3381 RTW89_FLAG_NAPI_RUNNING, 3382 RTW89_FLAG_LEISURE_PS, 3383 RTW89_FLAG_LOW_POWER_MODE, 3384 RTW89_FLAG_INACTIVE_PS, 3385 RTW89_FLAG_CRASH_SIMULATING, 3386 RTW89_FLAG_WOWLAN, 3387 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 3388 RTW89_FLAG_CHANGING_INTERFACE, 3389 3390 NUM_OF_RTW89_FLAGS, 3391 }; 3392 3393 enum rtw89_pkt_drop_sel { 3394 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 3395 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 3396 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 3397 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 3398 RTW89_PKT_DROP_SEL_MACID_ALL, 3399 RTW89_PKT_DROP_SEL_MG0_ONCE, 3400 RTW89_PKT_DROP_SEL_HIQ_ONCE, 3401 RTW89_PKT_DROP_SEL_HIQ_PORT, 3402 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 3403 RTW89_PKT_DROP_SEL_BAND, 3404 RTW89_PKT_DROP_SEL_BAND_ONCE, 3405 RTW89_PKT_DROP_SEL_REL_MACID, 3406 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 3407 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 3408 }; 3409 3410 struct rtw89_pkt_drop_params { 3411 enum rtw89_pkt_drop_sel sel; 3412 enum rtw89_mac_idx mac_band; 3413 u8 macid; 3414 u8 port; 3415 u8 mbssid; 3416 bool tf_trs; 3417 u32 macid_band_sel[4]; 3418 }; 3419 3420 struct rtw89_pkt_stat { 3421 u16 beacon_nr; 3422 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 3423 }; 3424 3425 DECLARE_EWMA(thermal, 4, 4); 3426 3427 struct rtw89_phy_stat { 3428 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 3429 struct rtw89_pkt_stat cur_pkt_stat; 3430 struct rtw89_pkt_stat last_pkt_stat; 3431 }; 3432 3433 #define RTW89_DACK_PATH_NR 2 3434 #define RTW89_DACK_IDX_NR 2 3435 #define RTW89_DACK_MSBK_NR 16 3436 struct rtw89_dack_info { 3437 bool dack_done; 3438 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 3439 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3440 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3441 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3442 u32 dack_cnt; 3443 bool addck_timeout[RTW89_DACK_PATH_NR]; 3444 bool dadck_timeout[RTW89_DACK_PATH_NR]; 3445 bool msbk_timeout[RTW89_DACK_PATH_NR]; 3446 }; 3447 3448 #define RTW89_IQK_CHS_NR 2 3449 #define RTW89_IQK_PATH_NR 4 3450 3451 struct rtw89_rfk_mcc_info { 3452 u8 ch[RTW89_IQK_CHS_NR]; 3453 u8 band[RTW89_IQK_CHS_NR]; 3454 u8 table_idx; 3455 }; 3456 3457 struct rtw89_lck_info { 3458 u8 thermal[RF_PATH_MAX]; 3459 }; 3460 3461 struct rtw89_rx_dck_info { 3462 u8 thermal[RF_PATH_MAX]; 3463 }; 3464 3465 struct rtw89_iqk_info { 3466 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3467 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3468 bool lok_fail[RTW89_IQK_PATH_NR]; 3469 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3470 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3471 u32 iqk_fail_cnt; 3472 bool is_iqk_init; 3473 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3474 u8 iqk_band[RTW89_IQK_PATH_NR]; 3475 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3476 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3477 u8 kcount; 3478 u8 iqk_times; 3479 u8 version; 3480 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3481 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3482 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3483 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3484 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3485 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3486 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3487 bool is_nbiqk; 3488 bool iqk_fft_en; 3489 bool iqk_xym_en; 3490 bool iqk_sram_en; 3491 bool iqk_cfir_en; 3492 u8 thermal[RTW89_IQK_PATH_NR]; 3493 bool thermal_rek_en; 3494 u32 syn1to2; 3495 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3496 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3497 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3498 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3499 }; 3500 3501 #define RTW89_DPK_RF_PATH 2 3502 #define RTW89_DPK_AVG_THERMAL_NUM 8 3503 #define RTW89_DPK_BKUP_NUM 2 3504 struct rtw89_dpk_bkup_para { 3505 enum rtw89_band band; 3506 enum rtw89_bandwidth bw; 3507 u8 ch; 3508 bool path_ok; 3509 u8 mdpd_en; 3510 u8 txagc_dpk; 3511 u8 ther_dpk; 3512 u8 gs; 3513 u16 pwsf; 3514 }; 3515 3516 struct rtw89_dpk_info { 3517 bool is_dpk_enable; 3518 bool is_dpk_reload_en; 3519 u8 dpk_gs[RTW89_PHY_MAX]; 3520 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3521 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3522 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3523 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3524 u8 cur_idx[RTW89_DPK_RF_PATH]; 3525 u8 cur_k_set; 3526 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3527 }; 3528 3529 struct rtw89_fem_info { 3530 bool elna_2g; 3531 bool elna_5g; 3532 bool epa_2g; 3533 bool epa_5g; 3534 bool epa_6g; 3535 }; 3536 3537 struct rtw89_phy_ch_info { 3538 u8 rssi_min; 3539 u16 rssi_min_macid; 3540 u8 pre_rssi_min; 3541 u8 rssi_max; 3542 u16 rssi_max_macid; 3543 u8 rxsc_160; 3544 u8 rxsc_80; 3545 u8 rxsc_40; 3546 u8 rxsc_20; 3547 u8 rxsc_l; 3548 u8 is_noisy; 3549 }; 3550 3551 struct rtw89_agc_gaincode_set { 3552 u8 lna_idx; 3553 u8 tia_idx; 3554 u8 rxb_idx; 3555 }; 3556 3557 #define IGI_RSSI_TH_NUM 5 3558 #define FA_TH_NUM 4 3559 #define LNA_GAIN_NUM 7 3560 #define TIA_GAIN_NUM 2 3561 struct rtw89_dig_info { 3562 struct rtw89_agc_gaincode_set cur_gaincode; 3563 bool force_gaincode_idx_en; 3564 struct rtw89_agc_gaincode_set force_gaincode; 3565 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3566 u16 fa_th[FA_TH_NUM]; 3567 u8 igi_rssi; 3568 u8 igi_fa_rssi; 3569 u8 fa_rssi_ofst; 3570 u8 dyn_igi_max; 3571 u8 dyn_igi_min; 3572 bool dyn_pd_th_en; 3573 u8 dyn_pd_th_max; 3574 u8 pd_low_th_ofst; 3575 u8 ib_pbk; 3576 s8 ib_pkpwr; 3577 s8 lna_gain_a[LNA_GAIN_NUM]; 3578 s8 lna_gain_g[LNA_GAIN_NUM]; 3579 s8 *lna_gain; 3580 s8 tia_gain_a[TIA_GAIN_NUM]; 3581 s8 tia_gain_g[TIA_GAIN_NUM]; 3582 s8 *tia_gain; 3583 bool is_linked_pre; 3584 bool bypass_dig; 3585 }; 3586 3587 enum rtw89_multi_cfo_mode { 3588 RTW89_PKT_BASED_AVG_MODE = 0, 3589 RTW89_ENTRY_BASED_AVG_MODE = 1, 3590 RTW89_TP_BASED_AVG_MODE = 2, 3591 }; 3592 3593 enum rtw89_phy_cfo_status { 3594 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3595 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3596 RTW89_PHY_DCFO_STATE_HOLD = 2, 3597 RTW89_PHY_DCFO_STATE_MAX 3598 }; 3599 3600 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3601 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3602 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3603 }; 3604 3605 struct rtw89_cfo_tracking_info { 3606 u16 cfo_timer_ms; 3607 bool cfo_trig_by_timer_en; 3608 enum rtw89_phy_cfo_status phy_cfo_status; 3609 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3610 u8 phy_cfo_trk_cnt; 3611 bool is_adjust; 3612 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3613 bool apply_compensation; 3614 u8 crystal_cap; 3615 u8 crystal_cap_default; 3616 u8 def_x_cap; 3617 s8 x_cap_ofst; 3618 u32 sta_cfo_tolerance; 3619 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3620 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3621 s32 cfo_avg_pre; 3622 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3623 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3624 u32 packet_count; 3625 u32 packet_count_pre; 3626 s32 residual_cfo_acc; 3627 u8 phy_cfotrk_state; 3628 u8 phy_cfotrk_cnt; 3629 bool divergence_lock_en; 3630 u8 x_cap_lb; 3631 u8 x_cap_ub; 3632 u8 lock_cnt; 3633 }; 3634 3635 enum rtw89_tssi_alimk_band { 3636 TSSI_ALIMK_2G = 0, 3637 TSSI_ALIMK_5GL, 3638 TSSI_ALIMK_5GM, 3639 TSSI_ALIMK_5GH, 3640 TSSI_ALIMK_MAX 3641 }; 3642 3643 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3644 #define TSSI_TRIM_CH_GROUP_NUM 8 3645 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3646 3647 #define TSSI_CCK_CH_GROUP_NUM 6 3648 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3649 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3650 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3651 #define TSSI_MCS_CH_GROUP_NUM \ 3652 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3653 #define TSSI_MAX_CH_NUM 67 3654 #define TSSI_ALIMK_VALUE_NUM 8 3655 3656 struct rtw89_tssi_info { 3657 u8 thermal[RF_PATH_MAX]; 3658 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3659 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3660 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3661 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3662 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3663 s8 extra_ofst[RF_PATH_MAX]; 3664 bool tssi_tracking_check[RF_PATH_MAX]; 3665 u8 default_txagc_offset[RF_PATH_MAX]; 3666 u32 base_thermal[RF_PATH_MAX]; 3667 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 3668 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 3669 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 3670 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 3671 u32 tssi_alimk_time; 3672 }; 3673 3674 struct rtw89_power_trim_info { 3675 bool pg_thermal_trim; 3676 bool pg_pa_bias_trim; 3677 u8 thermal_trim[RF_PATH_MAX]; 3678 u8 pa_bias_trim[RF_PATH_MAX]; 3679 }; 3680 3681 struct rtw89_regulatory { 3682 char alpha2[3]; 3683 u8 txpwr_regd[RTW89_BAND_MAX]; 3684 }; 3685 3686 enum rtw89_ifs_clm_application { 3687 RTW89_IFS_CLM_INIT = 0, 3688 RTW89_IFS_CLM_BACKGROUND = 1, 3689 RTW89_IFS_CLM_ACS = 2, 3690 RTW89_IFS_CLM_DIG = 3, 3691 RTW89_IFS_CLM_TDMA_DIG = 4, 3692 RTW89_IFS_CLM_DBG = 5, 3693 RTW89_IFS_CLM_DBG_MANUAL = 6 3694 }; 3695 3696 enum rtw89_env_racing_lv { 3697 RTW89_RAC_RELEASE = 0, 3698 RTW89_RAC_LV_1 = 1, 3699 RTW89_RAC_LV_2 = 2, 3700 RTW89_RAC_LV_3 = 3, 3701 RTW89_RAC_LV_4 = 4, 3702 RTW89_RAC_MAX_NUM = 5 3703 }; 3704 3705 struct rtw89_ccx_para_info { 3706 enum rtw89_env_racing_lv rac_lv; 3707 u16 mntr_time; 3708 u8 nhm_manual_th_ofst; 3709 u8 nhm_manual_th0; 3710 enum rtw89_ifs_clm_application ifs_clm_app; 3711 u32 ifs_clm_manual_th_times; 3712 u32 ifs_clm_manual_th0; 3713 u8 fahm_manual_th_ofst; 3714 u8 fahm_manual_th0; 3715 u8 fahm_numer_opt; 3716 u8 fahm_denom_opt; 3717 }; 3718 3719 enum rtw89_ccx_edcca_opt_sc_idx { 3720 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3721 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3722 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3723 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3724 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3725 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3726 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3727 RTW89_CCX_EDCCA_SEG1_S3 = 7 3728 }; 3729 3730 enum rtw89_ccx_edcca_opt_bw_idx { 3731 RTW89_CCX_EDCCA_BW20_0 = 0, 3732 RTW89_CCX_EDCCA_BW20_1 = 1, 3733 RTW89_CCX_EDCCA_BW20_2 = 2, 3734 RTW89_CCX_EDCCA_BW20_3 = 3, 3735 RTW89_CCX_EDCCA_BW20_4 = 4, 3736 RTW89_CCX_EDCCA_BW20_5 = 5, 3737 RTW89_CCX_EDCCA_BW20_6 = 6, 3738 RTW89_CCX_EDCCA_BW20_7 = 7 3739 }; 3740 3741 #define RTW89_NHM_TH_NUM 11 3742 #define RTW89_FAHM_TH_NUM 11 3743 #define RTW89_NHM_RPT_NUM 12 3744 #define RTW89_FAHM_RPT_NUM 12 3745 #define RTW89_IFS_CLM_NUM 4 3746 struct rtw89_env_monitor_info { 3747 u32 ccx_trigger_time; 3748 u64 start_time; 3749 u8 ccx_rpt_stamp; 3750 u8 ccx_watchdog_result; 3751 bool ccx_ongoing; 3752 u8 ccx_rac_lv; 3753 bool ccx_manual_ctrl; 3754 u8 ccx_pre_rssi; 3755 u16 clm_mntr_time; 3756 u16 nhm_mntr_time; 3757 u16 ifs_clm_mntr_time; 3758 enum rtw89_ifs_clm_application ifs_clm_app; 3759 u16 fahm_mntr_time; 3760 u16 edcca_clm_mntr_time; 3761 u16 ccx_period; 3762 u8 ccx_unit_idx; 3763 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3764 u8 nhm_th[RTW89_NHM_TH_NUM]; 3765 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3766 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3767 u8 fahm_numer_opt; 3768 u8 fahm_denom_opt; 3769 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3770 u16 clm_result; 3771 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3772 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3773 u16 nhm_tx_cnt; 3774 u16 nhm_cca_cnt; 3775 u16 nhm_idle_cnt; 3776 u16 ifs_clm_tx; 3777 u16 ifs_clm_edcca_excl_cca; 3778 u16 ifs_clm_ofdmfa; 3779 u16 ifs_clm_ofdmcca_excl_fa; 3780 u16 ifs_clm_cckfa; 3781 u16 ifs_clm_cckcca_excl_fa; 3782 u16 ifs_clm_total_ifs; 3783 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3784 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3785 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3786 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3787 u16 fahm_denom_result; 3788 u16 edcca_clm_result; 3789 u8 clm_ratio; 3790 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3791 u8 nhm_tx_ratio; 3792 u8 nhm_cca_ratio; 3793 u8 nhm_idle_ratio; 3794 u8 nhm_ratio; 3795 u16 nhm_result_sum; 3796 u8 nhm_pwr; 3797 u8 ifs_clm_tx_ratio; 3798 u8 ifs_clm_edcca_excl_cca_ratio; 3799 u8 ifs_clm_cck_fa_ratio; 3800 u8 ifs_clm_ofdm_fa_ratio; 3801 u8 ifs_clm_cck_cca_excl_fa_ratio; 3802 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3803 u16 ifs_clm_cck_fa_permil; 3804 u16 ifs_clm_ofdm_fa_permil; 3805 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3806 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3807 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3808 u16 fahm_result_sum; 3809 u8 fahm_ratio; 3810 u8 fahm_denom_ratio; 3811 u8 fahm_pwr; 3812 u8 edcca_clm_ratio; 3813 }; 3814 3815 enum rtw89_ser_rcvy_step { 3816 RTW89_SER_DRV_STOP_TX, 3817 RTW89_SER_DRV_STOP_RX, 3818 RTW89_SER_DRV_STOP_RUN, 3819 RTW89_SER_HAL_STOP_DMA, 3820 RTW89_NUM_OF_SER_FLAGS 3821 }; 3822 3823 struct rtw89_ser { 3824 u8 state; 3825 u8 alarm_event; 3826 3827 struct work_struct ser_hdl_work; 3828 struct delayed_work ser_alarm_work; 3829 const struct state_ent *st_tbl; 3830 const struct event_ent *ev_tbl; 3831 struct list_head msg_q; 3832 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3833 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3834 }; 3835 3836 enum rtw89_mac_ax_ps_mode { 3837 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3838 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3839 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3840 RTW89_MAC_AX_PS_MODE_MAX = 3, 3841 }; 3842 3843 enum rtw89_last_rpwm_mode { 3844 RTW89_LAST_RPWM_PS = 0x0, 3845 RTW89_LAST_RPWM_ACTIVE = 0x6, 3846 }; 3847 3848 struct rtw89_lps_parm { 3849 u8 macid; 3850 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3851 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3852 }; 3853 3854 struct rtw89_ppdu_sts_info { 3855 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3856 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3857 }; 3858 3859 struct rtw89_early_h2c { 3860 struct list_head list; 3861 u8 *h2c; 3862 u16 h2c_len; 3863 }; 3864 3865 struct rtw89_hw_scan_info { 3866 struct ieee80211_vif *scanning_vif; 3867 struct list_head pkt_list[NUM_NL80211_BANDS]; 3868 u8 op_pri_ch; 3869 u8 op_chan; 3870 u8 op_bw; 3871 u8 op_band; 3872 u32 last_chan_idx; 3873 }; 3874 3875 enum rtw89_phy_bb_gain_band { 3876 RTW89_BB_GAIN_BAND_2G = 0, 3877 RTW89_BB_GAIN_BAND_5G_L = 1, 3878 RTW89_BB_GAIN_BAND_5G_M = 2, 3879 RTW89_BB_GAIN_BAND_5G_H = 3, 3880 RTW89_BB_GAIN_BAND_6G_L = 4, 3881 RTW89_BB_GAIN_BAND_6G_M = 5, 3882 RTW89_BB_GAIN_BAND_6G_H = 6, 3883 RTW89_BB_GAIN_BAND_6G_UH = 7, 3884 3885 RTW89_BB_GAIN_BAND_NR, 3886 }; 3887 3888 enum rtw89_phy_bb_rxsc_num { 3889 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3890 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3891 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3892 }; 3893 3894 struct rtw89_phy_bb_gain_info { 3895 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3896 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3897 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3898 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3899 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3900 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3901 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3902 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3903 [RTW89_BB_RXSC_NUM_40]; 3904 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3905 [RTW89_BB_RXSC_NUM_80]; 3906 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3907 [RTW89_BB_RXSC_NUM_160]; 3908 }; 3909 3910 struct rtw89_phy_efuse_gain { 3911 bool offset_valid; 3912 bool comp_valid; 3913 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3914 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3915 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3916 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 3917 }; 3918 3919 #define RTW89_MAX_PATTERN_NUM 18 3920 #define RTW89_MAX_PATTERN_MASK_SIZE 4 3921 #define RTW89_MAX_PATTERN_SIZE 128 3922 3923 struct rtw89_wow_cam_info { 3924 bool r_w; 3925 u8 idx; 3926 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 3927 u16 crc; 3928 bool negative_pattern_match; 3929 bool skip_mac_hdr; 3930 bool uc; 3931 bool mc; 3932 bool bc; 3933 bool valid; 3934 }; 3935 3936 struct rtw89_wow_param { 3937 struct ieee80211_vif *wow_vif; 3938 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 3939 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 3940 u8 pattern_cnt; 3941 }; 3942 3943 struct rtw89_mcc_info { 3944 struct rtw89_wait_info wait; 3945 }; 3946 3947 struct rtw89_dev { 3948 struct ieee80211_hw *hw; 3949 struct device *dev; 3950 const struct ieee80211_ops *ops; 3951 3952 bool dbcc_en; 3953 struct rtw89_hw_scan_info scan_info; 3954 const struct rtw89_chip_info *chip; 3955 const struct rtw89_pci_info *pci_info; 3956 struct rtw89_hal hal; 3957 struct rtw89_mcc_info mcc; 3958 struct rtw89_mac_info mac; 3959 struct rtw89_fw_info fw; 3960 struct rtw89_hci_info hci; 3961 struct rtw89_efuse efuse; 3962 struct rtw89_traffic_stats stats; 3963 3964 /* ensures exclusive access from mac80211 callbacks */ 3965 struct mutex mutex; 3966 struct list_head rtwvifs_list; 3967 /* used to protect rf read write */ 3968 struct mutex rf_mutex; 3969 struct workqueue_struct *txq_wq; 3970 struct work_struct txq_work; 3971 struct delayed_work txq_reinvoke_work; 3972 /* used to protect ba_list and forbid_ba_list */ 3973 spinlock_t ba_lock; 3974 /* txqs to setup ba session */ 3975 struct list_head ba_list; 3976 /* txqs to forbid ba session */ 3977 struct list_head forbid_ba_list; 3978 struct work_struct ba_work; 3979 /* used to protect rpwm */ 3980 spinlock_t rpwm_lock; 3981 3982 struct rtw89_cam_info cam_info; 3983 3984 struct sk_buff_head c2h_queue; 3985 struct work_struct c2h_work; 3986 struct work_struct ips_work; 3987 3988 struct list_head early_h2c_list; 3989 3990 struct rtw89_ser ser; 3991 3992 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3993 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3994 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3995 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3996 3997 struct rtw89_phy_stat phystat; 3998 struct rtw89_dack_info dack; 3999 struct rtw89_iqk_info iqk; 4000 struct rtw89_dpk_info dpk; 4001 struct rtw89_rfk_mcc_info rfk_mcc; 4002 struct rtw89_lck_info lck; 4003 struct rtw89_rx_dck_info rx_dck; 4004 bool is_tssi_mode[RF_PATH_MAX]; 4005 bool is_bt_iqk_timeout; 4006 4007 struct rtw89_fem_info fem; 4008 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 4009 struct rtw89_tssi_info tssi; 4010 struct rtw89_power_trim_info pwr_trim; 4011 4012 struct rtw89_cfo_tracking_info cfo_tracking; 4013 struct rtw89_env_monitor_info env_monitor; 4014 struct rtw89_dig_info dig; 4015 struct rtw89_phy_ch_info ch_info; 4016 struct rtw89_phy_bb_gain_info bb_gain; 4017 struct rtw89_phy_efuse_gain efuse_gain; 4018 struct rtw89_phy_ul_tb_info ul_tb_info; 4019 4020 struct delayed_work track_work; 4021 struct delayed_work coex_act1_work; 4022 struct delayed_work coex_bt_devinfo_work; 4023 struct delayed_work coex_rfk_chk_work; 4024 struct delayed_work cfo_track_work; 4025 struct delayed_work forbid_ba_work; 4026 struct rtw89_ppdu_sts_info ppdu_sts; 4027 u8 total_sta_assoc; 4028 bool scanning; 4029 4030 const struct rtw89_regulatory *regd; 4031 struct rtw89_sar_info sar; 4032 4033 struct rtw89_btc btc; 4034 enum rtw89_ps_mode ps_mode; 4035 bool lps_enabled; 4036 4037 struct rtw89_wow_param wow; 4038 4039 /* napi structure */ 4040 struct net_device netdev; 4041 struct napi_struct napi; 4042 int napi_budget_countdown; 4043 4044 /* HCI related data, keep last */ 4045 u8 priv[] __aligned(sizeof(void *)); 4046 }; 4047 4048 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4049 struct rtw89_core_tx_request *tx_req) 4050 { 4051 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4052 } 4053 4054 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4055 { 4056 rtwdev->hci.ops->reset(rtwdev); 4057 } 4058 4059 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4060 { 4061 return rtwdev->hci.ops->start(rtwdev); 4062 } 4063 4064 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4065 { 4066 rtwdev->hci.ops->stop(rtwdev); 4067 } 4068 4069 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4070 { 4071 return rtwdev->hci.ops->deinit(rtwdev); 4072 } 4073 4074 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4075 { 4076 rtwdev->hci.ops->pause(rtwdev, pause); 4077 } 4078 4079 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4080 { 4081 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4082 } 4083 4084 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4085 { 4086 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4087 } 4088 4089 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4090 { 4091 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4092 } 4093 4094 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4095 { 4096 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4097 } 4098 4099 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4100 bool drop) 4101 { 4102 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4103 return; 4104 4105 if (rtwdev->hci.ops->flush_queues) 4106 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4107 } 4108 4109 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4110 { 4111 if (rtwdev->hci.ops->recovery_start) 4112 rtwdev->hci.ops->recovery_start(rtwdev); 4113 } 4114 4115 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4116 { 4117 if (rtwdev->hci.ops->recovery_complete) 4118 rtwdev->hci.ops->recovery_complete(rtwdev); 4119 } 4120 4121 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4122 { 4123 if (rtwdev->hci.ops->enable_intr) 4124 rtwdev->hci.ops->enable_intr(rtwdev); 4125 } 4126 4127 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4128 { 4129 if (rtwdev->hci.ops->disable_intr) 4130 rtwdev->hci.ops->disable_intr(rtwdev); 4131 } 4132 4133 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4134 { 4135 if (rtwdev->hci.ops->ctrl_txdma_ch) 4136 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4137 } 4138 4139 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4140 { 4141 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4142 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4143 } 4144 4145 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4146 { 4147 if (rtwdev->hci.ops->ctrl_trxhci) 4148 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4149 } 4150 4151 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4152 { 4153 int ret = 0; 4154 4155 if (rtwdev->hci.ops->poll_txdma_ch) 4156 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4157 return ret; 4158 } 4159 4160 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4161 { 4162 if (rtwdev->hci.ops->clr_idx_all) 4163 rtwdev->hci.ops->clr_idx_all(rtwdev); 4164 } 4165 4166 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4167 { 4168 int ret = 0; 4169 4170 if (rtwdev->hci.ops->rst_bdram) 4171 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4172 return ret; 4173 } 4174 4175 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4176 { 4177 if (rtwdev->hci.ops->clear) 4178 rtwdev->hci.ops->clear(rtwdev, pdev); 4179 } 4180 4181 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4182 { 4183 return rtwdev->hci.ops->read8(rtwdev, addr); 4184 } 4185 4186 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4187 { 4188 return rtwdev->hci.ops->read16(rtwdev, addr); 4189 } 4190 4191 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4192 { 4193 return rtwdev->hci.ops->read32(rtwdev, addr); 4194 } 4195 4196 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4197 { 4198 rtwdev->hci.ops->write8(rtwdev, addr, data); 4199 } 4200 4201 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4202 { 4203 rtwdev->hci.ops->write16(rtwdev, addr, data); 4204 } 4205 4206 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4207 { 4208 rtwdev->hci.ops->write32(rtwdev, addr, data); 4209 } 4210 4211 static inline void 4212 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4213 { 4214 u8 val; 4215 4216 val = rtw89_read8(rtwdev, addr); 4217 rtw89_write8(rtwdev, addr, val | bit); 4218 } 4219 4220 static inline void 4221 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4222 { 4223 u16 val; 4224 4225 val = rtw89_read16(rtwdev, addr); 4226 rtw89_write16(rtwdev, addr, val | bit); 4227 } 4228 4229 static inline void 4230 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4231 { 4232 u32 val; 4233 4234 val = rtw89_read32(rtwdev, addr); 4235 rtw89_write32(rtwdev, addr, val | bit); 4236 } 4237 4238 static inline void 4239 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4240 { 4241 u8 val; 4242 4243 val = rtw89_read8(rtwdev, addr); 4244 rtw89_write8(rtwdev, addr, val & ~bit); 4245 } 4246 4247 static inline void 4248 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4249 { 4250 u16 val; 4251 4252 val = rtw89_read16(rtwdev, addr); 4253 rtw89_write16(rtwdev, addr, val & ~bit); 4254 } 4255 4256 static inline void 4257 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4258 { 4259 u32 val; 4260 4261 val = rtw89_read32(rtwdev, addr); 4262 rtw89_write32(rtwdev, addr, val & ~bit); 4263 } 4264 4265 static inline u32 4266 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4267 { 4268 u32 shift = __ffs(mask); 4269 u32 orig; 4270 u32 ret; 4271 4272 orig = rtw89_read32(rtwdev, addr); 4273 ret = (orig & mask) >> shift; 4274 4275 return ret; 4276 } 4277 4278 static inline u16 4279 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4280 { 4281 u32 shift = __ffs(mask); 4282 u32 orig; 4283 u32 ret; 4284 4285 orig = rtw89_read16(rtwdev, addr); 4286 ret = (orig & mask) >> shift; 4287 4288 return ret; 4289 } 4290 4291 static inline u8 4292 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4293 { 4294 u32 shift = __ffs(mask); 4295 u32 orig; 4296 u32 ret; 4297 4298 orig = rtw89_read8(rtwdev, addr); 4299 ret = (orig & mask) >> shift; 4300 4301 return ret; 4302 } 4303 4304 static inline void 4305 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 4306 { 4307 u32 shift = __ffs(mask); 4308 u32 orig; 4309 u32 set; 4310 4311 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 4312 4313 orig = rtw89_read32(rtwdev, addr); 4314 set = (orig & ~mask) | ((data << shift) & mask); 4315 rtw89_write32(rtwdev, addr, set); 4316 } 4317 4318 static inline void 4319 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 4320 { 4321 u32 shift; 4322 u16 orig, set; 4323 4324 mask &= 0xffff; 4325 shift = __ffs(mask); 4326 4327 orig = rtw89_read16(rtwdev, addr); 4328 set = (orig & ~mask) | ((data << shift) & mask); 4329 rtw89_write16(rtwdev, addr, set); 4330 } 4331 4332 static inline void 4333 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 4334 { 4335 u32 shift; 4336 u8 orig, set; 4337 4338 mask &= 0xff; 4339 shift = __ffs(mask); 4340 4341 orig = rtw89_read8(rtwdev, addr); 4342 set = (orig & ~mask) | ((data << shift) & mask); 4343 rtw89_write8(rtwdev, addr, set); 4344 } 4345 4346 static inline u32 4347 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4348 u32 addr, u32 mask) 4349 { 4350 u32 val; 4351 4352 mutex_lock(&rtwdev->rf_mutex); 4353 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 4354 mutex_unlock(&rtwdev->rf_mutex); 4355 4356 return val; 4357 } 4358 4359 static inline void 4360 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4361 u32 addr, u32 mask, u32 data) 4362 { 4363 mutex_lock(&rtwdev->rf_mutex); 4364 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 4365 mutex_unlock(&rtwdev->rf_mutex); 4366 } 4367 4368 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 4369 { 4370 void *p = rtwtxq; 4371 4372 return container_of(p, struct ieee80211_txq, drv_priv); 4373 } 4374 4375 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 4376 struct ieee80211_txq *txq) 4377 { 4378 struct rtw89_txq *rtwtxq; 4379 4380 if (!txq) 4381 return; 4382 4383 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4384 INIT_LIST_HEAD(&rtwtxq->list); 4385 } 4386 4387 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 4388 { 4389 void *p = rtwvif; 4390 4391 return container_of(p, struct ieee80211_vif, drv_priv); 4392 } 4393 4394 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 4395 { 4396 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 4397 } 4398 4399 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 4400 { 4401 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4402 } 4403 4404 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 4405 { 4406 void *p = rtwsta; 4407 4408 return container_of(p, struct ieee80211_sta, drv_priv); 4409 } 4410 4411 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 4412 { 4413 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 4414 } 4415 4416 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 4417 { 4418 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 4419 } 4420 4421 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 4422 { 4423 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 4424 return RATE_INFO_BW_160; 4425 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 4426 return RATE_INFO_BW_80; 4427 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 4428 return RATE_INFO_BW_40; 4429 else 4430 return RATE_INFO_BW_20; 4431 } 4432 4433 static inline 4434 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 4435 { 4436 switch (hw_band) { 4437 default: 4438 case RTW89_BAND_2G: 4439 return NL80211_BAND_2GHZ; 4440 case RTW89_BAND_5G: 4441 return NL80211_BAND_5GHZ; 4442 case RTW89_BAND_6G: 4443 return NL80211_BAND_6GHZ; 4444 } 4445 } 4446 4447 static inline 4448 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 4449 { 4450 switch (nl_band) { 4451 default: 4452 case NL80211_BAND_2GHZ: 4453 return RTW89_BAND_2G; 4454 case NL80211_BAND_5GHZ: 4455 return RTW89_BAND_5G; 4456 case NL80211_BAND_6GHZ: 4457 return RTW89_BAND_6G; 4458 } 4459 } 4460 4461 static inline 4462 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 4463 { 4464 switch (width) { 4465 default: 4466 WARN(1, "Not support bandwidth %d\n", width); 4467 fallthrough; 4468 case NL80211_CHAN_WIDTH_20_NOHT: 4469 case NL80211_CHAN_WIDTH_20: 4470 return RTW89_CHANNEL_WIDTH_20; 4471 case NL80211_CHAN_WIDTH_40: 4472 return RTW89_CHANNEL_WIDTH_40; 4473 case NL80211_CHAN_WIDTH_80: 4474 return RTW89_CHANNEL_WIDTH_80; 4475 case NL80211_CHAN_WIDTH_160: 4476 return RTW89_CHANNEL_WIDTH_160; 4477 } 4478 } 4479 4480 static inline 4481 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 4482 struct rtw89_sta *rtwsta) 4483 { 4484 if (rtwsta) { 4485 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4486 4487 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 4488 return &rtwsta->addr_cam; 4489 } 4490 return &rtwvif->addr_cam; 4491 } 4492 4493 static inline 4494 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 4495 struct rtw89_sta *rtwsta) 4496 { 4497 if (rtwsta) { 4498 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4499 4500 if (sta->tdls) 4501 return &rtwsta->bssid_cam; 4502 } 4503 return &rtwvif->bssid_cam; 4504 } 4505 4506 static inline 4507 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 4508 struct rtw89_channel_help_params *p, 4509 const struct rtw89_chan *chan, 4510 enum rtw89_mac_idx mac_idx, 4511 enum rtw89_phy_idx phy_idx) 4512 { 4513 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 4514 mac_idx, phy_idx); 4515 } 4516 4517 static inline 4518 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 4519 struct rtw89_channel_help_params *p, 4520 const struct rtw89_chan *chan, 4521 enum rtw89_mac_idx mac_idx, 4522 enum rtw89_phy_idx phy_idx) 4523 { 4524 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 4525 mac_idx, phy_idx); 4526 } 4527 4528 static inline 4529 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 4530 enum rtw89_sub_entity_idx idx) 4531 { 4532 struct rtw89_hal *hal = &rtwdev->hal; 4533 4534 return &hal->sub[idx].chandef; 4535 } 4536 4537 static inline 4538 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 4539 enum rtw89_sub_entity_idx idx) 4540 { 4541 struct rtw89_hal *hal = &rtwdev->hal; 4542 4543 return &hal->sub[idx].chan; 4544 } 4545 4546 static inline 4547 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 4548 enum rtw89_sub_entity_idx idx) 4549 { 4550 struct rtw89_hal *hal = &rtwdev->hal; 4551 4552 return &hal->sub[idx].rcd; 4553 } 4554 4555 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 4556 { 4557 const struct rtw89_chip_info *chip = rtwdev->chip; 4558 4559 if (chip->ops->fem_setup) 4560 chip->ops->fem_setup(rtwdev); 4561 } 4562 4563 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 4564 { 4565 const struct rtw89_chip_info *chip = rtwdev->chip; 4566 4567 if (chip->ops->bb_sethw) 4568 chip->ops->bb_sethw(rtwdev); 4569 } 4570 4571 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 4572 { 4573 const struct rtw89_chip_info *chip = rtwdev->chip; 4574 4575 if (chip->ops->rfk_init) 4576 chip->ops->rfk_init(rtwdev); 4577 } 4578 4579 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4580 { 4581 const struct rtw89_chip_info *chip = rtwdev->chip; 4582 4583 if (chip->ops->rfk_channel) 4584 chip->ops->rfk_channel(rtwdev); 4585 } 4586 4587 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4588 enum rtw89_phy_idx phy_idx) 4589 { 4590 const struct rtw89_chip_info *chip = rtwdev->chip; 4591 4592 if (chip->ops->rfk_band_changed) 4593 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4594 } 4595 4596 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4597 { 4598 const struct rtw89_chip_info *chip = rtwdev->chip; 4599 4600 if (chip->ops->rfk_scan) 4601 chip->ops->rfk_scan(rtwdev, start); 4602 } 4603 4604 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4605 { 4606 const struct rtw89_chip_info *chip = rtwdev->chip; 4607 4608 if (chip->ops->rfk_track) 4609 chip->ops->rfk_track(rtwdev); 4610 } 4611 4612 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4613 { 4614 const struct rtw89_chip_info *chip = rtwdev->chip; 4615 4616 if (chip->ops->set_txpwr_ctrl) 4617 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4618 } 4619 4620 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4621 { 4622 const struct rtw89_chip_info *chip = rtwdev->chip; 4623 4624 if (chip->ops->power_trim) 4625 chip->ops->power_trim(rtwdev); 4626 } 4627 4628 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4629 enum rtw89_phy_idx phy_idx) 4630 { 4631 const struct rtw89_chip_info *chip = rtwdev->chip; 4632 4633 if (chip->ops->init_txpwr_unit) 4634 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4635 } 4636 4637 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4638 enum rtw89_rf_path rf_path) 4639 { 4640 const struct rtw89_chip_info *chip = rtwdev->chip; 4641 4642 if (!chip->ops->get_thermal) 4643 return 0x10; 4644 4645 return chip->ops->get_thermal(rtwdev, rf_path); 4646 } 4647 4648 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4649 struct rtw89_rx_phy_ppdu *phy_ppdu, 4650 struct ieee80211_rx_status *status) 4651 { 4652 const struct rtw89_chip_info *chip = rtwdev->chip; 4653 4654 if (chip->ops->query_ppdu) 4655 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4656 } 4657 4658 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4659 bool bt_en) 4660 { 4661 const struct rtw89_chip_info *chip = rtwdev->chip; 4662 4663 if (chip->ops->bb_ctrl_btc_preagc) 4664 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4665 } 4666 4667 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4668 { 4669 const struct rtw89_chip_info *chip = rtwdev->chip; 4670 4671 if (chip->ops->cfg_txrx_path) 4672 chip->ops->cfg_txrx_path(rtwdev); 4673 } 4674 4675 static inline 4676 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4677 struct ieee80211_vif *vif) 4678 { 4679 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4680 const struct rtw89_chip_info *chip = rtwdev->chip; 4681 4682 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4683 return; 4684 4685 if (chip->ops->set_txpwr_ul_tb_offset) 4686 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4687 } 4688 4689 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4690 const struct rtw89_txpwr_table *tbl) 4691 { 4692 tbl->load(rtwdev, tbl); 4693 } 4694 4695 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4696 { 4697 return rtwdev->regd->txpwr_regd[band]; 4698 } 4699 4700 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4701 { 4702 const struct rtw89_chip_info *chip = rtwdev->chip; 4703 4704 if (chip->ops->ctrl_btg) 4705 chip->ops->ctrl_btg(rtwdev, btg); 4706 } 4707 4708 static inline 4709 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4710 struct rtw89_tx_desc_info *desc_info, 4711 void *txdesc) 4712 { 4713 const struct rtw89_chip_info *chip = rtwdev->chip; 4714 4715 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4716 } 4717 4718 static inline 4719 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4720 struct rtw89_tx_desc_info *desc_info, 4721 void *txdesc) 4722 { 4723 const struct rtw89_chip_info *chip = rtwdev->chip; 4724 4725 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4726 } 4727 4728 static inline 4729 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4730 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4731 { 4732 const struct rtw89_chip_info *chip = rtwdev->chip; 4733 4734 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4735 } 4736 4737 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4738 { 4739 const struct rtw89_chip_info *chip = rtwdev->chip; 4740 4741 chip->ops->cfg_ctrl_path(rtwdev, wl); 4742 } 4743 4744 static inline 4745 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4746 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4747 { 4748 const struct rtw89_chip_info *chip = rtwdev->chip; 4749 4750 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4751 } 4752 4753 static inline 4754 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4755 { 4756 const struct rtw89_chip_info *chip = rtwdev->chip; 4757 4758 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4759 } 4760 4761 static inline 4762 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4763 struct rtw89_vif *rtwvif, 4764 struct rtw89_sta *rtwsta) 4765 { 4766 const struct rtw89_chip_info *chip = rtwdev->chip; 4767 4768 if (!chip->ops->h2c_dctl_sec_cam) 4769 return 0; 4770 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4771 } 4772 4773 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4774 { 4775 __le16 fc = hdr->frame_control; 4776 4777 if (ieee80211_has_tods(fc)) 4778 return hdr->addr1; 4779 else if (ieee80211_has_fromds(fc)) 4780 return hdr->addr2; 4781 else 4782 return hdr->addr3; 4783 } 4784 4785 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4786 { 4787 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4788 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4789 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4790 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4791 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4792 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4793 return true; 4794 return false; 4795 } 4796 4797 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4798 enum rtw89_fw_type type) 4799 { 4800 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4801 4802 if (type == RTW89_FW_WOWLAN) 4803 return &fw_info->wowlan; 4804 return &fw_info->normal; 4805 } 4806 4807 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 4808 unsigned int length) 4809 { 4810 struct sk_buff *skb; 4811 4812 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 4813 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 4814 if (!skb) 4815 return NULL; 4816 4817 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 4818 return skb; 4819 } 4820 4821 return dev_alloc_skb(length); 4822 } 4823 4824 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4825 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4826 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4827 struct sk_buff *skb, bool fwdl); 4828 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4829 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4830 struct rtw89_tx_desc_info *desc_info, 4831 void *txdesc); 4832 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4833 struct rtw89_tx_desc_info *desc_info, 4834 void *txdesc); 4835 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4836 struct rtw89_tx_desc_info *desc_info, 4837 void *txdesc); 4838 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4839 struct rtw89_rx_desc_info *desc_info, 4840 struct sk_buff *skb); 4841 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4842 struct rtw89_rx_desc_info *desc_info, 4843 u8 *data, u32 data_offset); 4844 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4845 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4846 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4847 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4848 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4849 struct ieee80211_vif *vif, 4850 struct ieee80211_sta *sta); 4851 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4852 struct ieee80211_vif *vif, 4853 struct ieee80211_sta *sta); 4854 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4855 struct ieee80211_vif *vif, 4856 struct ieee80211_sta *sta); 4857 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4858 struct ieee80211_vif *vif, 4859 struct ieee80211_sta *sta); 4860 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4861 struct ieee80211_vif *vif, 4862 struct ieee80211_sta *sta); 4863 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4864 struct ieee80211_sta *sta, 4865 struct cfg80211_tid_config *tid_config); 4866 int rtw89_core_init(struct rtw89_dev *rtwdev); 4867 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4868 int rtw89_core_register(struct rtw89_dev *rtwdev); 4869 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4870 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4871 u32 bus_data_size, 4872 const struct rtw89_chip_info *chip); 4873 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4874 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4875 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4876 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4877 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4878 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4879 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4880 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4881 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4882 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4883 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4884 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4885 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4886 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4887 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4888 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4889 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4890 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4891 struct rtw89_traffic_stats *stats); 4892 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 4893 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4894 const struct rtw89_completion_data *data); 4895 int rtw89_core_start(struct rtw89_dev *rtwdev); 4896 void rtw89_core_stop(struct rtw89_dev *rtwdev); 4897 void rtw89_core_update_beacon_work(struct work_struct *work); 4898 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4899 const u8 *mac_addr, bool hw_scan); 4900 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4901 struct ieee80211_vif *vif, bool hw_scan); 4902 4903 #endif 4904