1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64) 39 40 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 41 #define RTW89_HTC_VARIANT_HE 3 42 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 43 #define RTW89_HTC_VARIANT_HE_CID_OM 1 44 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 45 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 46 47 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 48 enum htc_om_channel_width { 49 HTC_OM_CHANNEL_WIDTH_20 = 0, 50 HTC_OM_CHANNEL_WIDTH_40 = 1, 51 HTC_OM_CHANNEL_WIDTH_80 = 2, 52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 53 }; 54 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 56 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 57 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 58 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 60 61 #define RTW89_TF_PAD GENMASK(11, 0) 62 #define RTW89_TF_BASIC_USER_INFO_SZ 6 63 64 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 66 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 68 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 70 71 enum rtw89_subband { 72 RTW89_CH_2G = 0, 73 RTW89_CH_5G_BAND_1 = 1, 74 /* RTW89_CH_5G_BAND_2 = 2, unused */ 75 RTW89_CH_5G_BAND_3 = 3, 76 RTW89_CH_5G_BAND_4 = 4, 77 78 RTW89_CH_6G_BAND_IDX0, /* Low */ 79 RTW89_CH_6G_BAND_IDX1, /* Low */ 80 RTW89_CH_6G_BAND_IDX2, /* Mid */ 81 RTW89_CH_6G_BAND_IDX3, /* Mid */ 82 RTW89_CH_6G_BAND_IDX4, /* High */ 83 RTW89_CH_6G_BAND_IDX5, /* High */ 84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 86 87 RTW89_SUBBAND_NR, 88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 89 }; 90 91 enum rtw89_gain_offset { 92 RTW89_GAIN_OFFSET_2G_CCK, 93 RTW89_GAIN_OFFSET_2G_OFDM, 94 RTW89_GAIN_OFFSET_5G_LOW, 95 RTW89_GAIN_OFFSET_5G_MID, 96 RTW89_GAIN_OFFSET_5G_HIGH, 97 98 RTW89_GAIN_OFFSET_NR, 99 }; 100 101 enum rtw89_hci_type { 102 RTW89_HCI_TYPE_PCIE, 103 RTW89_HCI_TYPE_USB, 104 RTW89_HCI_TYPE_SDIO, 105 }; 106 107 enum rtw89_core_chip_id { 108 RTL8852A, 109 RTL8852B, 110 RTL8852C, 111 RTL8851B, 112 }; 113 114 enum rtw89_cv { 115 CHIP_CAV, 116 CHIP_CBV, 117 CHIP_CCV, 118 CHIP_CDV, 119 CHIP_CEV, 120 CHIP_CFV, 121 CHIP_CV_MAX, 122 CHIP_CV_INVALID = CHIP_CV_MAX, 123 }; 124 125 enum rtw89_core_tx_type { 126 RTW89_CORE_TX_TYPE_DATA, 127 RTW89_CORE_TX_TYPE_MGMT, 128 RTW89_CORE_TX_TYPE_FWCMD, 129 }; 130 131 enum rtw89_core_rx_type { 132 RTW89_CORE_RX_TYPE_WIFI = 0, 133 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 134 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 135 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 136 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 137 RTW89_CORE_RX_TYPE_SS2FW = 5, 138 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 139 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 140 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 141 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 142 RTW89_CORE_RX_TYPE_C2H = 10, 143 RTW89_CORE_RX_TYPE_CSI = 11, 144 RTW89_CORE_RX_TYPE_CQI = 12, 145 RTW89_CORE_RX_TYPE_H2C = 13, 146 RTW89_CORE_RX_TYPE_FWDL = 14, 147 }; 148 149 enum rtw89_txq_flags { 150 RTW89_TXQ_F_AMPDU = 0, 151 RTW89_TXQ_F_BLOCK_BA = 1, 152 RTW89_TXQ_F_FORBID_BA = 2, 153 }; 154 155 enum rtw89_net_type { 156 RTW89_NET_TYPE_NO_LINK = 0, 157 RTW89_NET_TYPE_AD_HOC = 1, 158 RTW89_NET_TYPE_INFRA = 2, 159 RTW89_NET_TYPE_AP_MODE = 3, 160 }; 161 162 enum rtw89_wifi_role { 163 RTW89_WIFI_ROLE_NONE, 164 RTW89_WIFI_ROLE_STATION, 165 RTW89_WIFI_ROLE_AP, 166 RTW89_WIFI_ROLE_AP_VLAN, 167 RTW89_WIFI_ROLE_ADHOC, 168 RTW89_WIFI_ROLE_ADHOC_MASTER, 169 RTW89_WIFI_ROLE_MESH_POINT, 170 RTW89_WIFI_ROLE_MONITOR, 171 RTW89_WIFI_ROLE_P2P_DEVICE, 172 RTW89_WIFI_ROLE_P2P_CLIENT, 173 RTW89_WIFI_ROLE_P2P_GO, 174 RTW89_WIFI_ROLE_NAN, 175 RTW89_WIFI_ROLE_MLME_MAX 176 }; 177 178 enum rtw89_upd_mode { 179 RTW89_ROLE_CREATE, 180 RTW89_ROLE_REMOVE, 181 RTW89_ROLE_TYPE_CHANGE, 182 RTW89_ROLE_INFO_CHANGE, 183 RTW89_ROLE_CON_DISCONN, 184 RTW89_ROLE_BAND_SW, 185 RTW89_ROLE_FW_RESTORE, 186 }; 187 188 enum rtw89_self_role { 189 RTW89_SELF_ROLE_CLIENT, 190 RTW89_SELF_ROLE_AP, 191 RTW89_SELF_ROLE_AP_CLIENT 192 }; 193 194 enum rtw89_msk_sO_el { 195 RTW89_NO_MSK, 196 RTW89_SMA, 197 RTW89_TMA, 198 RTW89_BSSID 199 }; 200 201 enum rtw89_sch_tx_sel { 202 RTW89_SCH_TX_SEL_ALL, 203 RTW89_SCH_TX_SEL_HIQ, 204 RTW89_SCH_TX_SEL_MG0, 205 RTW89_SCH_TX_SEL_MACID, 206 }; 207 208 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 209 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 210 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 211 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 212 */ 213 enum rtw89_add_cam_sec_mode { 214 RTW89_ADDR_CAM_SEC_NONE = 0, 215 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 216 RTW89_ADDR_CAM_SEC_NORMAL = 2, 217 RTW89_ADDR_CAM_SEC_4GROUP = 3, 218 }; 219 220 enum rtw89_sec_key_type { 221 RTW89_SEC_KEY_TYPE_NONE = 0, 222 RTW89_SEC_KEY_TYPE_WEP40 = 1, 223 RTW89_SEC_KEY_TYPE_WEP104 = 2, 224 RTW89_SEC_KEY_TYPE_TKIP = 3, 225 RTW89_SEC_KEY_TYPE_WAPI = 4, 226 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 227 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 228 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 229 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 230 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 231 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 232 }; 233 234 enum rtw89_port { 235 RTW89_PORT_0 = 0, 236 RTW89_PORT_1 = 1, 237 RTW89_PORT_2 = 2, 238 RTW89_PORT_3 = 3, 239 RTW89_PORT_4 = 4, 240 RTW89_PORT_NUM 241 }; 242 243 enum rtw89_band { 244 RTW89_BAND_2G = 0, 245 RTW89_BAND_5G = 1, 246 RTW89_BAND_6G = 2, 247 RTW89_BAND_MAX, 248 }; 249 250 enum rtw89_hw_rate { 251 RTW89_HW_RATE_CCK1 = 0x0, 252 RTW89_HW_RATE_CCK2 = 0x1, 253 RTW89_HW_RATE_CCK5_5 = 0x2, 254 RTW89_HW_RATE_CCK11 = 0x3, 255 RTW89_HW_RATE_OFDM6 = 0x4, 256 RTW89_HW_RATE_OFDM9 = 0x5, 257 RTW89_HW_RATE_OFDM12 = 0x6, 258 RTW89_HW_RATE_OFDM18 = 0x7, 259 RTW89_HW_RATE_OFDM24 = 0x8, 260 RTW89_HW_RATE_OFDM36 = 0x9, 261 RTW89_HW_RATE_OFDM48 = 0xA, 262 RTW89_HW_RATE_OFDM54 = 0xB, 263 RTW89_HW_RATE_MCS0 = 0x80, 264 RTW89_HW_RATE_MCS1 = 0x81, 265 RTW89_HW_RATE_MCS2 = 0x82, 266 RTW89_HW_RATE_MCS3 = 0x83, 267 RTW89_HW_RATE_MCS4 = 0x84, 268 RTW89_HW_RATE_MCS5 = 0x85, 269 RTW89_HW_RATE_MCS6 = 0x86, 270 RTW89_HW_RATE_MCS7 = 0x87, 271 RTW89_HW_RATE_MCS8 = 0x88, 272 RTW89_HW_RATE_MCS9 = 0x89, 273 RTW89_HW_RATE_MCS10 = 0x8A, 274 RTW89_HW_RATE_MCS11 = 0x8B, 275 RTW89_HW_RATE_MCS12 = 0x8C, 276 RTW89_HW_RATE_MCS13 = 0x8D, 277 RTW89_HW_RATE_MCS14 = 0x8E, 278 RTW89_HW_RATE_MCS15 = 0x8F, 279 RTW89_HW_RATE_MCS16 = 0x90, 280 RTW89_HW_RATE_MCS17 = 0x91, 281 RTW89_HW_RATE_MCS18 = 0x92, 282 RTW89_HW_RATE_MCS19 = 0x93, 283 RTW89_HW_RATE_MCS20 = 0x94, 284 RTW89_HW_RATE_MCS21 = 0x95, 285 RTW89_HW_RATE_MCS22 = 0x96, 286 RTW89_HW_RATE_MCS23 = 0x97, 287 RTW89_HW_RATE_MCS24 = 0x98, 288 RTW89_HW_RATE_MCS25 = 0x99, 289 RTW89_HW_RATE_MCS26 = 0x9A, 290 RTW89_HW_RATE_MCS27 = 0x9B, 291 RTW89_HW_RATE_MCS28 = 0x9C, 292 RTW89_HW_RATE_MCS29 = 0x9D, 293 RTW89_HW_RATE_MCS30 = 0x9E, 294 RTW89_HW_RATE_MCS31 = 0x9F, 295 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 296 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 297 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 298 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 299 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 300 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 301 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 302 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 303 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 304 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 305 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 306 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 307 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 308 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 309 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 310 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 311 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 312 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 313 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 314 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 315 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 316 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 317 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 318 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 319 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 320 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 321 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 322 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 323 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 324 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 325 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 326 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 327 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 328 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 329 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 330 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 331 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 332 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 333 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 334 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 335 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 336 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 337 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 338 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 339 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 340 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 341 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 342 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 343 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 344 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 345 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 346 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 347 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 348 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 349 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 350 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 351 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 352 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 353 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 354 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 355 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 356 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 357 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 358 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 359 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 360 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 361 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 362 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 363 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 364 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 365 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 366 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 367 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 368 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 369 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 370 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 371 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 372 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 373 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 374 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 375 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 376 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 377 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 378 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 379 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 380 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 381 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 382 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 383 RTW89_HW_RATE_NR, 384 385 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 386 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 387 }; 388 389 /* 2G channels, 390 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 391 */ 392 #define RTW89_2G_CH_NUM 14 393 394 /* 5G channels, 395 * 36, 38, 40, 42, 44, 46, 48, 50, 396 * 52, 54, 56, 58, 60, 62, 64, 397 * 100, 102, 104, 106, 108, 110, 112, 114, 398 * 116, 118, 120, 122, 124, 126, 128, 130, 399 * 132, 134, 136, 138, 140, 142, 144, 400 * 149, 151, 153, 155, 157, 159, 161, 163, 401 * 165, 167, 169, 171, 173, 175, 177 402 */ 403 #define RTW89_5G_CH_NUM 53 404 405 /* 6G channels, 406 * 1, 3, 5, 7, 9, 11, 13, 15, 407 * 17, 19, 21, 23, 25, 27, 29, 33, 408 * 35, 37, 39, 41, 43, 45, 47, 49, 409 * 51, 53, 55, 57, 59, 61, 65, 67, 410 * 69, 71, 73, 75, 77, 79, 81, 83, 411 * 85, 87, 89, 91, 93, 97, 99, 101, 412 * 103, 105, 107, 109, 111, 113, 115, 117, 413 * 119, 121, 123, 125, 129, 131, 133, 135, 414 * 137, 139, 141, 143, 145, 147, 149, 151, 415 * 153, 155, 157, 161, 163, 165, 167, 169, 416 * 171, 173, 175, 177, 179, 181, 183, 185, 417 * 187, 189, 193, 195, 197, 199, 201, 203, 418 * 205, 207, 209, 211, 213, 215, 217, 219, 419 * 221, 225, 227, 229, 231, 233, 235, 237, 420 * 239, 241, 243, 245, 247, 249, 251, 253, 421 */ 422 #define RTW89_6G_CH_NUM 120 423 424 enum rtw89_rate_section { 425 RTW89_RS_CCK, 426 RTW89_RS_OFDM, 427 RTW89_RS_MCS, /* for HT/VHT/HE */ 428 RTW89_RS_HEDCM, 429 RTW89_RS_OFFSET, 430 RTW89_RS_MAX, 431 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 432 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 433 }; 434 435 enum rtw89_rate_max { 436 RTW89_RATE_CCK_MAX = 4, 437 RTW89_RATE_OFDM_MAX = 8, 438 RTW89_RATE_MCS_MAX = 12, 439 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 440 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 441 }; 442 443 enum rtw89_nss { 444 RTW89_NSS_1 = 0, 445 RTW89_NSS_2 = 1, 446 /* HE DCM only support 1ss and 2ss */ 447 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 448 RTW89_NSS_3 = 2, 449 RTW89_NSS_4 = 3, 450 RTW89_NSS_MAX, 451 }; 452 453 enum rtw89_ntx { 454 RTW89_1TX = 0, 455 RTW89_2TX = 1, 456 RTW89_NTX_NUM, 457 }; 458 459 enum rtw89_beamforming_type { 460 RTW89_NONBF = 0, 461 RTW89_BF = 1, 462 RTW89_BF_NUM, 463 }; 464 465 enum rtw89_regulation_type { 466 RTW89_WW = 0, 467 RTW89_ETSI = 1, 468 RTW89_FCC = 2, 469 RTW89_MKK = 3, 470 RTW89_NA = 4, 471 RTW89_IC = 5, 472 RTW89_KCC = 6, 473 RTW89_ACMA = 7, 474 RTW89_NCC = 8, 475 RTW89_MEXICO = 9, 476 RTW89_CHILE = 10, 477 RTW89_UKRAINE = 11, 478 RTW89_CN = 12, 479 RTW89_QATAR = 13, 480 RTW89_UK = 14, 481 RTW89_REGD_NUM, 482 }; 483 484 enum rtw89_fw_pkt_ofld_type { 485 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 486 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 487 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 488 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 489 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 490 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 491 RTW89_PKT_OFLD_TYPE_NDP = 6, 492 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 493 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 494 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 495 RTW89_PKT_OFLD_TYPE_NUM, 496 }; 497 498 struct rtw89_txpwr_byrate { 499 s8 cck[RTW89_RATE_CCK_MAX]; 500 s8 ofdm[RTW89_RATE_OFDM_MAX]; 501 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 502 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 503 s8 offset[RTW89_RATE_OFFSET_MAX]; 504 }; 505 506 enum rtw89_bandwidth_section_num { 507 RTW89_BW20_SEC_NUM = 8, 508 RTW89_BW40_SEC_NUM = 4, 509 RTW89_BW80_SEC_NUM = 2, 510 }; 511 512 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 513 514 struct rtw89_txpwr_limit { 515 s8 cck_20m[RTW89_BF_NUM]; 516 s8 cck_40m[RTW89_BF_NUM]; 517 s8 ofdm[RTW89_BF_NUM]; 518 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 519 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 520 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 521 s8 mcs_160m[RTW89_BF_NUM]; 522 s8 mcs_40m_0p5[RTW89_BF_NUM]; 523 s8 mcs_40m_2p5[RTW89_BF_NUM]; 524 }; 525 526 #define RTW89_RU_SEC_NUM 8 527 528 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 529 530 struct rtw89_txpwr_limit_ru { 531 s8 ru26[RTW89_RU_SEC_NUM]; 532 s8 ru52[RTW89_RU_SEC_NUM]; 533 s8 ru106[RTW89_RU_SEC_NUM]; 534 }; 535 536 struct rtw89_rate_desc { 537 enum rtw89_nss nss; 538 enum rtw89_rate_section rs; 539 u8 idx; 540 }; 541 542 #define PHY_STS_HDR_LEN 8 543 #define RF_PATH_MAX 4 544 #define RTW89_MAX_PPDU_CNT 8 545 struct rtw89_rx_phy_ppdu { 546 u8 *buf; 547 u32 len; 548 u8 rssi_avg; 549 u8 rssi[RF_PATH_MAX]; 550 u8 mac_id; 551 u8 chan_idx; 552 u8 ie; 553 u16 rate; 554 bool to_self; 555 bool valid; 556 }; 557 558 enum rtw89_mac_idx { 559 RTW89_MAC_0 = 0, 560 RTW89_MAC_1 = 1, 561 }; 562 563 enum rtw89_phy_idx { 564 RTW89_PHY_0 = 0, 565 RTW89_PHY_1 = 1, 566 RTW89_PHY_MAX 567 }; 568 569 enum rtw89_sub_entity_idx { 570 RTW89_SUB_ENTITY_0 = 0, 571 572 NUM_OF_RTW89_SUB_ENTITY, 573 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 574 }; 575 576 enum rtw89_rf_path { 577 RF_PATH_A = 0, 578 RF_PATH_B = 1, 579 RF_PATH_C = 2, 580 RF_PATH_D = 3, 581 RF_PATH_AB, 582 RF_PATH_AC, 583 RF_PATH_AD, 584 RF_PATH_BC, 585 RF_PATH_BD, 586 RF_PATH_CD, 587 RF_PATH_ABC, 588 RF_PATH_ABD, 589 RF_PATH_ACD, 590 RF_PATH_BCD, 591 RF_PATH_ABCD, 592 }; 593 594 enum rtw89_rf_path_bit { 595 RF_A = BIT(0), 596 RF_B = BIT(1), 597 RF_C = BIT(2), 598 RF_D = BIT(3), 599 600 RF_AB = (RF_A | RF_B), 601 RF_AC = (RF_A | RF_C), 602 RF_AD = (RF_A | RF_D), 603 RF_BC = (RF_B | RF_C), 604 RF_BD = (RF_B | RF_D), 605 RF_CD = (RF_C | RF_D), 606 607 RF_ABC = (RF_A | RF_B | RF_C), 608 RF_ABD = (RF_A | RF_B | RF_D), 609 RF_ACD = (RF_A | RF_C | RF_D), 610 RF_BCD = (RF_B | RF_C | RF_D), 611 612 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 613 }; 614 615 enum rtw89_bandwidth { 616 RTW89_CHANNEL_WIDTH_20 = 0, 617 RTW89_CHANNEL_WIDTH_40 = 1, 618 RTW89_CHANNEL_WIDTH_80 = 2, 619 RTW89_CHANNEL_WIDTH_160 = 3, 620 RTW89_CHANNEL_WIDTH_80_80 = 4, 621 RTW89_CHANNEL_WIDTH_5 = 5, 622 RTW89_CHANNEL_WIDTH_10 = 6, 623 }; 624 625 enum rtw89_ps_mode { 626 RTW89_PS_MODE_NONE = 0, 627 RTW89_PS_MODE_RFOFF = 1, 628 RTW89_PS_MODE_CLK_GATED = 2, 629 RTW89_PS_MODE_PWR_GATED = 3, 630 }; 631 632 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 633 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 634 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 635 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 636 637 enum rtw89_ru_bandwidth { 638 RTW89_RU26 = 0, 639 RTW89_RU52 = 1, 640 RTW89_RU106 = 2, 641 RTW89_RU_NUM, 642 }; 643 644 enum rtw89_sc_offset { 645 RTW89_SC_DONT_CARE = 0, 646 RTW89_SC_20_UPPER = 1, 647 RTW89_SC_20_LOWER = 2, 648 RTW89_SC_20_UPMOST = 3, 649 RTW89_SC_20_LOWEST = 4, 650 RTW89_SC_20_UP2X = 5, 651 RTW89_SC_20_LOW2X = 6, 652 RTW89_SC_20_UP3X = 7, 653 RTW89_SC_20_LOW3X = 8, 654 RTW89_SC_40_UPPER = 9, 655 RTW89_SC_40_LOWER = 10, 656 }; 657 658 enum rtw89_wow_flags { 659 RTW89_WOW_FLAG_EN_MAGIC_PKT, 660 RTW89_WOW_FLAG_EN_REKEY_PKT, 661 RTW89_WOW_FLAG_EN_DISCONNECT, 662 RTW89_WOW_FLAG_NUM, 663 }; 664 665 struct rtw89_chan { 666 u8 channel; 667 u8 primary_channel; 668 enum rtw89_band band_type; 669 enum rtw89_bandwidth band_width; 670 671 /* The follow-up are derived from the above. We must ensure that it 672 * is assigned correctly in rtw89_chan_create() if new one is added. 673 */ 674 u32 freq; 675 enum rtw89_subband subband_type; 676 enum rtw89_sc_offset pri_ch_idx; 677 }; 678 679 struct rtw89_chan_rcd { 680 u8 prev_primary_channel; 681 enum rtw89_band prev_band_type; 682 }; 683 684 struct rtw89_channel_help_params { 685 u32 tx_en; 686 }; 687 688 struct rtw89_port_reg { 689 u32 port_cfg; 690 u32 tbtt_prohib; 691 u32 bcn_area; 692 u32 bcn_early; 693 u32 tbtt_early; 694 u32 tbtt_agg; 695 u32 bcn_space; 696 u32 bcn_forcetx; 697 u32 bcn_err_cnt; 698 u32 bcn_err_flag; 699 u32 dtim_ctrl; 700 u32 tbtt_shift; 701 u32 bcn_cnt_tmr; 702 u32 tsftr_l; 703 u32 tsftr_h; 704 }; 705 706 struct rtw89_txwd_body { 707 __le32 dword0; 708 __le32 dword1; 709 __le32 dword2; 710 __le32 dword3; 711 __le32 dword4; 712 __le32 dword5; 713 } __packed; 714 715 struct rtw89_txwd_body_v1 { 716 __le32 dword0; 717 __le32 dword1; 718 __le32 dword2; 719 __le32 dword3; 720 __le32 dword4; 721 __le32 dword5; 722 __le32 dword6; 723 __le32 dword7; 724 } __packed; 725 726 struct rtw89_txwd_info { 727 __le32 dword0; 728 __le32 dword1; 729 __le32 dword2; 730 __le32 dword3; 731 __le32 dword4; 732 __le32 dword5; 733 } __packed; 734 735 struct rtw89_rx_desc_info { 736 u16 pkt_size; 737 u8 pkt_type; 738 u8 drv_info_size; 739 u8 shift; 740 u8 wl_hd_iv_len; 741 bool long_rxdesc; 742 bool bb_sel; 743 bool mac_info_valid; 744 u16 data_rate; 745 u8 gi_ltf; 746 u8 bw; 747 u32 free_run_cnt; 748 u8 user_id; 749 bool sr_en; 750 u8 ppdu_cnt; 751 u8 ppdu_type; 752 bool icv_err; 753 bool crc32_err; 754 bool hw_dec; 755 bool sw_dec; 756 bool addr1_match; 757 u8 frag; 758 u16 seq; 759 u8 frame_type; 760 u8 rx_pl_id; 761 bool addr_cam_valid; 762 u8 addr_cam_id; 763 u8 sec_cam_id; 764 u8 mac_id; 765 u16 offset; 766 bool ready; 767 }; 768 769 struct rtw89_rxdesc_short { 770 __le32 dword0; 771 __le32 dword1; 772 __le32 dword2; 773 __le32 dword3; 774 } __packed; 775 776 struct rtw89_rxdesc_long { 777 __le32 dword0; 778 __le32 dword1; 779 __le32 dword2; 780 __le32 dword3; 781 __le32 dword4; 782 __le32 dword5; 783 __le32 dword6; 784 __le32 dword7; 785 } __packed; 786 787 struct rtw89_tx_desc_info { 788 u16 pkt_size; 789 u8 wp_offset; 790 u8 mac_id; 791 u8 qsel; 792 u8 ch_dma; 793 u8 hdr_llc_len; 794 bool is_bmc; 795 bool en_wd_info; 796 bool wd_page; 797 bool use_rate; 798 bool dis_data_fb; 799 bool tid_indicate; 800 bool agg_en; 801 bool bk; 802 u8 ampdu_density; 803 u8 ampdu_num; 804 bool sec_en; 805 u8 addr_info_nr; 806 u8 sec_keyid; 807 u8 sec_type; 808 u8 sec_cam_idx; 809 u8 sec_seq[6]; 810 u16 data_rate; 811 u16 data_retry_lowest_rate; 812 bool fw_dl; 813 u16 seq; 814 bool a_ctrl_bsr; 815 u8 hw_ssn_sel; 816 #define RTW89_MGMT_HW_SSN_SEL 1 817 u8 hw_seq_mode; 818 #define RTW89_MGMT_HW_SEQ_MODE 1 819 bool hiq; 820 u8 port; 821 bool er_cap; 822 }; 823 824 struct rtw89_core_tx_request { 825 enum rtw89_core_tx_type tx_type; 826 827 struct sk_buff *skb; 828 struct ieee80211_vif *vif; 829 struct ieee80211_sta *sta; 830 struct rtw89_tx_desc_info desc_info; 831 }; 832 833 struct rtw89_txq { 834 struct list_head list; 835 unsigned long flags; 836 int wait_cnt; 837 }; 838 839 struct rtw89_mac_ax_gnt { 840 u8 gnt_bt_sw_en; 841 u8 gnt_bt; 842 u8 gnt_wl_sw_en; 843 u8 gnt_wl; 844 } __packed; 845 846 #define RTW89_MAC_AX_COEX_GNT_NR 2 847 struct rtw89_mac_ax_coex_gnt { 848 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 849 }; 850 851 enum rtw89_btc_ncnt { 852 BTC_NCNT_POWER_ON = 0x0, 853 BTC_NCNT_POWER_OFF, 854 BTC_NCNT_INIT_COEX, 855 BTC_NCNT_SCAN_START, 856 BTC_NCNT_SCAN_FINISH, 857 BTC_NCNT_SPECIAL_PACKET, 858 BTC_NCNT_SWITCH_BAND, 859 BTC_NCNT_RFK_TIMEOUT, 860 BTC_NCNT_SHOW_COEX_INFO, 861 BTC_NCNT_ROLE_INFO, 862 BTC_NCNT_CONTROL, 863 BTC_NCNT_RADIO_STATE, 864 BTC_NCNT_CUSTOMERIZE, 865 BTC_NCNT_WL_RFK, 866 BTC_NCNT_WL_STA, 867 BTC_NCNT_FWINFO, 868 BTC_NCNT_TIMER, 869 BTC_NCNT_NUM 870 }; 871 872 enum rtw89_btc_btinfo { 873 BTC_BTINFO_L0 = 0, 874 BTC_BTINFO_L1, 875 BTC_BTINFO_L2, 876 BTC_BTINFO_L3, 877 BTC_BTINFO_H0, 878 BTC_BTINFO_H1, 879 BTC_BTINFO_H2, 880 BTC_BTINFO_H3, 881 BTC_BTINFO_MAX 882 }; 883 884 enum rtw89_btc_dcnt { 885 BTC_DCNT_RUN = 0x0, 886 BTC_DCNT_CX_RUNINFO, 887 BTC_DCNT_RPT, 888 BTC_DCNT_RPT_HANG, 889 BTC_DCNT_CYCLE, 890 BTC_DCNT_CYCLE_HANG, 891 BTC_DCNT_W1, 892 BTC_DCNT_W1_HANG, 893 BTC_DCNT_B1, 894 BTC_DCNT_B1_HANG, 895 BTC_DCNT_TDMA_NONSYNC, 896 BTC_DCNT_SLOT_NONSYNC, 897 BTC_DCNT_BTCNT_HANG, 898 BTC_DCNT_WL_SLOT_DRIFT, 899 BTC_DCNT_WL_STA_LAST, 900 BTC_DCNT_BT_SLOT_DRIFT, 901 BTC_DCNT_BT_SLOT_FLOOD, 902 BTC_DCNT_FDDT_TRIG, 903 BTC_DCNT_E2G, 904 BTC_DCNT_E2G_HANG, 905 BTC_DCNT_NUM 906 }; 907 908 enum rtw89_btc_wl_state_cnt { 909 BTC_WCNT_SCANAP = 0x0, 910 BTC_WCNT_DHCP, 911 BTC_WCNT_EAPOL, 912 BTC_WCNT_ARP, 913 BTC_WCNT_SCBDUPDATE, 914 BTC_WCNT_RFK_REQ, 915 BTC_WCNT_RFK_GO, 916 BTC_WCNT_RFK_REJECT, 917 BTC_WCNT_RFK_TIMEOUT, 918 BTC_WCNT_CH_UPDATE, 919 BTC_WCNT_NUM 920 }; 921 922 enum rtw89_btc_bt_state_cnt { 923 BTC_BCNT_RETRY = 0x0, 924 BTC_BCNT_REINIT, 925 BTC_BCNT_REENABLE, 926 BTC_BCNT_SCBDREAD, 927 BTC_BCNT_RELINK, 928 BTC_BCNT_IGNOWL, 929 BTC_BCNT_INQPAG, 930 BTC_BCNT_INQ, 931 BTC_BCNT_PAGE, 932 BTC_BCNT_ROLESW, 933 BTC_BCNT_AFH, 934 BTC_BCNT_INFOUPDATE, 935 BTC_BCNT_INFOSAME, 936 BTC_BCNT_SCBDUPDATE, 937 BTC_BCNT_HIPRI_TX, 938 BTC_BCNT_HIPRI_RX, 939 BTC_BCNT_LOPRI_TX, 940 BTC_BCNT_LOPRI_RX, 941 BTC_BCNT_POLUT, 942 BTC_BCNT_RATECHG, 943 BTC_BCNT_NUM 944 }; 945 946 enum rtw89_btc_bt_profile { 947 BTC_BT_NOPROFILE = 0, 948 BTC_BT_HFP = BIT(0), 949 BTC_BT_HID = BIT(1), 950 BTC_BT_A2DP = BIT(2), 951 BTC_BT_PAN = BIT(3), 952 BTC_PROFILE_MAX = 4, 953 }; 954 955 struct rtw89_btc_ant_info { 956 u8 type; /* shared, dedicated */ 957 u8 num; 958 u8 isolation; 959 960 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 961 u8 diversity: 1; 962 u8 btg_pos: 2; 963 u8 stream_cnt: 4; 964 }; 965 966 enum rtw89_tfc_dir { 967 RTW89_TFC_UL, 968 RTW89_TFC_DL, 969 }; 970 971 struct rtw89_btc_wl_smap { 972 u32 busy: 1; 973 u32 scan: 1; 974 u32 connecting: 1; 975 u32 roaming: 1; 976 u32 _4way: 1; 977 u32 rf_off: 1; 978 u32 lps: 2; 979 u32 ips: 1; 980 u32 init_ok: 1; 981 u32 traffic_dir : 2; 982 u32 rf_off_pre: 1; 983 u32 lps_pre: 2; 984 }; 985 986 enum rtw89_tfc_lv { 987 RTW89_TFC_IDLE, 988 RTW89_TFC_ULTRA_LOW, 989 RTW89_TFC_LOW, 990 RTW89_TFC_MID, 991 RTW89_TFC_HIGH, 992 }; 993 994 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 995 DECLARE_EWMA(tp, 10, 2); 996 997 struct rtw89_traffic_stats { 998 /* units in bytes */ 999 u64 tx_unicast; 1000 u64 rx_unicast; 1001 u32 tx_avg_len; 1002 u32 rx_avg_len; 1003 1004 /* count for packets */ 1005 u64 tx_cnt; 1006 u64 rx_cnt; 1007 1008 /* units in Mbps */ 1009 u32 tx_throughput; 1010 u32 rx_throughput; 1011 u32 tx_throughput_raw; 1012 u32 rx_throughput_raw; 1013 1014 u32 rx_tf_acc; 1015 u32 rx_tf_periodic; 1016 1017 enum rtw89_tfc_lv tx_tfc_lv; 1018 enum rtw89_tfc_lv rx_tfc_lv; 1019 struct ewma_tp tx_ewma_tp; 1020 struct ewma_tp rx_ewma_tp; 1021 1022 u16 tx_rate; 1023 u16 rx_rate; 1024 }; 1025 1026 struct rtw89_btc_statistic { 1027 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1028 struct rtw89_traffic_stats traffic; 1029 }; 1030 1031 #define BTC_WL_RSSI_THMAX 4 1032 1033 struct rtw89_btc_wl_link_info { 1034 struct rtw89_btc_statistic stat; 1035 enum rtw89_tfc_dir dir; 1036 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1037 u8 mac_addr[ETH_ALEN]; 1038 u8 busy; 1039 u8 ch; 1040 u8 bw; 1041 u8 band; 1042 u8 role; 1043 u8 pid; 1044 u8 phy; 1045 u8 dtim_period; 1046 u8 mode; 1047 1048 u8 mac_id; 1049 u8 tx_retry; 1050 1051 u32 bcn_period; 1052 u32 busy_t; 1053 u32 tx_time; 1054 u32 client_cnt; 1055 u32 rx_rate_drop_cnt; 1056 1057 u32 active: 1; 1058 u32 noa: 1; 1059 u32 client_ps: 1; 1060 u32 connected: 2; 1061 }; 1062 1063 union rtw89_btc_wl_state_map { 1064 u32 val; 1065 struct rtw89_btc_wl_smap map; 1066 }; 1067 1068 struct rtw89_btc_bt_hfp_desc { 1069 u32 exist: 1; 1070 u32 type: 2; 1071 u32 rsvd: 29; 1072 }; 1073 1074 struct rtw89_btc_bt_hid_desc { 1075 u32 exist: 1; 1076 u32 slot_info: 2; 1077 u32 pair_cnt: 2; 1078 u32 type: 8; 1079 u32 rsvd: 19; 1080 }; 1081 1082 struct rtw89_btc_bt_a2dp_desc { 1083 u8 exist: 1; 1084 u8 exist_last: 1; 1085 u8 play_latency: 1; 1086 u8 type: 3; 1087 u8 active: 1; 1088 u8 sink: 1; 1089 1090 u8 bitpool; 1091 u16 vendor_id; 1092 u32 device_name; 1093 u32 flush_time; 1094 }; 1095 1096 struct rtw89_btc_bt_pan_desc { 1097 u32 exist: 1; 1098 u32 type: 1; 1099 u32 active: 1; 1100 u32 rsvd: 29; 1101 }; 1102 1103 struct rtw89_btc_bt_rfk_info { 1104 u32 run: 1; 1105 u32 req: 1; 1106 u32 timeout: 1; 1107 u32 rsvd: 29; 1108 }; 1109 1110 union rtw89_btc_bt_rfk_info_map { 1111 u32 val; 1112 struct rtw89_btc_bt_rfk_info map; 1113 }; 1114 1115 struct rtw89_btc_bt_ver_info { 1116 u32 fw_coex; /* match with which coex_ver */ 1117 u32 fw; 1118 }; 1119 1120 struct rtw89_btc_bool_sta_chg { 1121 u32 now: 1; 1122 u32 last: 1; 1123 u32 remain: 1; 1124 u32 srvd: 29; 1125 }; 1126 1127 struct rtw89_btc_u8_sta_chg { 1128 u8 now; 1129 u8 last; 1130 u8 remain; 1131 u8 rsvd; 1132 }; 1133 1134 struct rtw89_btc_wl_scan_info { 1135 u8 band[RTW89_PHY_MAX]; 1136 u8 phy_map; 1137 u8 rsvd; 1138 }; 1139 1140 struct rtw89_btc_wl_dbcc_info { 1141 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1142 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1143 u8 real_band[RTW89_PHY_MAX]; 1144 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1145 }; 1146 1147 struct rtw89_btc_wl_active_role { 1148 u8 connected: 1; 1149 u8 pid: 3; 1150 u8 phy: 1; 1151 u8 noa: 1; 1152 u8 band: 2; 1153 1154 u8 client_ps: 1; 1155 u8 bw: 7; 1156 1157 u8 role; 1158 u8 ch; 1159 1160 u16 tx_lvl; 1161 u16 rx_lvl; 1162 u16 tx_rate; 1163 u16 rx_rate; 1164 }; 1165 1166 struct rtw89_btc_wl_active_role_v1 { 1167 u8 connected: 1; 1168 u8 pid: 3; 1169 u8 phy: 1; 1170 u8 noa: 1; 1171 u8 band: 2; 1172 1173 u8 client_ps: 1; 1174 u8 bw: 7; 1175 1176 u8 role; 1177 u8 ch; 1178 1179 u16 tx_lvl; 1180 u16 rx_lvl; 1181 u16 tx_rate; 1182 u16 rx_rate; 1183 1184 u32 noa_duration; /* ms */ 1185 }; 1186 1187 struct rtw89_btc_wl_active_role_v2 { 1188 u8 connected: 1; 1189 u8 pid: 3; 1190 u8 phy: 1; 1191 u8 noa: 1; 1192 u8 band: 2; 1193 1194 u8 client_ps: 1; 1195 u8 bw: 7; 1196 1197 u8 role; 1198 u8 ch; 1199 1200 u32 noa_duration; /* ms */ 1201 }; 1202 1203 struct rtw89_btc_wl_role_info_bpos { 1204 u16 none: 1; 1205 u16 station: 1; 1206 u16 ap: 1; 1207 u16 vap: 1; 1208 u16 adhoc: 1; 1209 u16 adhoc_master: 1; 1210 u16 mesh: 1; 1211 u16 moniter: 1; 1212 u16 p2p_device: 1; 1213 u16 p2p_gc: 1; 1214 u16 p2p_go: 1; 1215 u16 nan: 1; 1216 }; 1217 1218 struct rtw89_btc_wl_scc_ctrl { 1219 u8 null_role1; 1220 u8 null_role2; 1221 u8 ebt_null; /* if tx null at EBT slot */ 1222 }; 1223 1224 union rtw89_btc_wl_role_info_map { 1225 u16 val; 1226 struct rtw89_btc_wl_role_info_bpos role; 1227 }; 1228 1229 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1230 u8 connect_cnt; 1231 u8 link_mode; 1232 union rtw89_btc_wl_role_info_map role_map; 1233 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1234 }; 1235 1236 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1237 u8 connect_cnt; 1238 u8 link_mode; 1239 union rtw89_btc_wl_role_info_map role_map; 1240 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1241 u32 mrole_type; /* btc_wl_mrole_type */ 1242 u32 mrole_noa_duration; /* ms */ 1243 1244 u32 dbcc_en: 1; 1245 u32 dbcc_chg: 1; 1246 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1247 u32 link_mode_chg: 1; 1248 u32 rsvd: 27; 1249 }; 1250 1251 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1252 u8 connect_cnt; 1253 u8 link_mode; 1254 union rtw89_btc_wl_role_info_map role_map; 1255 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1256 u32 mrole_type; /* btc_wl_mrole_type */ 1257 u32 mrole_noa_duration; /* ms */ 1258 1259 u32 dbcc_en: 1; 1260 u32 dbcc_chg: 1; 1261 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1262 u32 link_mode_chg: 1; 1263 u32 rsvd: 27; 1264 }; 1265 1266 struct rtw89_btc_wl_ver_info { 1267 u32 fw_coex; /* match with which coex_ver */ 1268 u32 fw; 1269 u32 mac; 1270 u32 bb; 1271 u32 rf; 1272 }; 1273 1274 struct rtw89_btc_wl_afh_info { 1275 u8 en; 1276 u8 ch; 1277 u8 bw; 1278 u8 rsvd; 1279 } __packed; 1280 1281 struct rtw89_btc_wl_rfk_info { 1282 u32 state: 2; 1283 u32 path_map: 4; 1284 u32 phy_map: 2; 1285 u32 band: 2; 1286 u32 type: 8; 1287 u32 rsvd: 14; 1288 }; 1289 1290 struct rtw89_btc_bt_smap { 1291 u32 connect: 1; 1292 u32 ble_connect: 1; 1293 u32 acl_busy: 1; 1294 u32 sco_busy: 1; 1295 u32 mesh_busy: 1; 1296 u32 inq_pag: 1; 1297 }; 1298 1299 union rtw89_btc_bt_state_map { 1300 u32 val; 1301 struct rtw89_btc_bt_smap map; 1302 }; 1303 1304 #define BTC_BT_RSSI_THMAX 4 1305 #define BTC_BT_AFH_GROUP 12 1306 #define BTC_BT_AFH_LE_GROUP 5 1307 1308 struct rtw89_btc_bt_link_info { 1309 struct rtw89_btc_u8_sta_chg profile_cnt; 1310 struct rtw89_btc_bool_sta_chg multi_link; 1311 struct rtw89_btc_bool_sta_chg relink; 1312 struct rtw89_btc_bt_hfp_desc hfp_desc; 1313 struct rtw89_btc_bt_hid_desc hid_desc; 1314 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1315 struct rtw89_btc_bt_pan_desc pan_desc; 1316 union rtw89_btc_bt_state_map status; 1317 1318 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1319 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1320 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1321 u8 afh_map[BTC_BT_AFH_GROUP]; 1322 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1323 1324 u32 role_sw: 1; 1325 u32 slave_role: 1; 1326 u32 afh_update: 1; 1327 u32 cqddr: 1; 1328 u32 rssi: 8; 1329 u32 tx_3m: 1; 1330 u32 rsvd: 19; 1331 }; 1332 1333 struct rtw89_btc_3rdcx_info { 1334 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1335 u8 hw_coex; 1336 u16 rsvd; 1337 }; 1338 1339 struct rtw89_btc_dm_emap { 1340 u32 init: 1; 1341 u32 pta_owner: 1; 1342 u32 wl_rfk_timeout: 1; 1343 u32 bt_rfk_timeout: 1; 1344 u32 wl_fw_hang: 1; 1345 u32 cycle_hang: 1; 1346 u32 w1_hang: 1; 1347 u32 b1_hang: 1; 1348 u32 tdma_no_sync: 1; 1349 u32 slot_no_sync: 1; 1350 u32 wl_slot_drift: 1; 1351 u32 bt_slot_drift: 1; 1352 u32 role_num_mismatch: 1; 1353 u32 null1_tx_late: 1; 1354 u32 bt_afh_conflict: 1; 1355 u32 bt_leafh_conflict: 1; 1356 u32 bt_slot_flood: 1; 1357 u32 wl_e2g_hang: 1; 1358 u32 wl_ver_mismatch: 1; 1359 u32 bt_ver_mismatch: 1; 1360 }; 1361 1362 union rtw89_btc_dm_error_map { 1363 u32 val; 1364 struct rtw89_btc_dm_emap map; 1365 }; 1366 1367 struct rtw89_btc_rf_para { 1368 u32 tx_pwr_freerun; 1369 u32 rx_gain_freerun; 1370 u32 tx_pwr_perpkt; 1371 u32 rx_gain_perpkt; 1372 }; 1373 1374 struct rtw89_btc_wl_nhm { 1375 u8 instant_wl_nhm_dbm; 1376 u8 instant_wl_nhm_per_mhz; 1377 u16 valid_record_times; 1378 s8 record_pwr[16]; 1379 u8 record_ratio[16]; 1380 s8 pwr; /* dbm_per_MHz */ 1381 u8 ratio; 1382 u8 current_status; 1383 u8 refresh; 1384 bool start_flag; 1385 u8 last_ccx_rpt_stamp; 1386 s8 pwr_max; 1387 s8 pwr_min; 1388 }; 1389 1390 struct rtw89_btc_wl_info { 1391 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1392 struct rtw89_btc_wl_rfk_info rfk_info; 1393 struct rtw89_btc_wl_ver_info ver_info; 1394 struct rtw89_btc_wl_afh_info afh_info; 1395 struct rtw89_btc_wl_role_info role_info; 1396 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1397 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1398 struct rtw89_btc_wl_scan_info scan_info; 1399 struct rtw89_btc_wl_dbcc_info dbcc_info; 1400 struct rtw89_btc_rf_para rf_para; 1401 struct rtw89_btc_wl_nhm nhm; 1402 union rtw89_btc_wl_state_map status; 1403 1404 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1405 u8 rssi_level; 1406 u8 cn_report; 1407 1408 bool scbd_change; 1409 u32 scbd; 1410 }; 1411 1412 struct rtw89_btc_module { 1413 struct rtw89_btc_ant_info ant; 1414 u8 rfe_type; 1415 u8 cv; 1416 1417 u8 bt_solo: 1; 1418 u8 bt_pos: 1; 1419 u8 switch_type: 1; 1420 u8 wa_type: 3; 1421 1422 u8 kt_ver_adie; 1423 }; 1424 1425 #define RTW89_BTC_DM_MAXSTEP 30 1426 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1427 1428 struct rtw89_btc_dm_step { 1429 u16 step[RTW89_BTC_DM_MAXSTEP]; 1430 u8 step_pos; 1431 bool step_ov; 1432 }; 1433 1434 struct rtw89_btc_init_info { 1435 struct rtw89_btc_module module; 1436 u8 wl_guard_ch; 1437 1438 u8 wl_only: 1; 1439 u8 wl_init_ok: 1; 1440 u8 dbcc_en: 1; 1441 u8 cx_other: 1; 1442 u8 bt_only: 1; 1443 1444 u16 rsvd; 1445 }; 1446 1447 struct rtw89_btc_wl_tx_limit_para { 1448 u16 enable; 1449 u32 tx_time; /* unit: us */ 1450 u16 tx_retry; 1451 }; 1452 1453 enum rtw89_btc_bt_scan_type { 1454 BTC_SCAN_INQ = 0, 1455 BTC_SCAN_PAGE, 1456 BTC_SCAN_BLE, 1457 BTC_SCAN_INIT, 1458 BTC_SCAN_TV, 1459 BTC_SCAN_ADV, 1460 BTC_SCAN_MAX1, 1461 }; 1462 1463 enum rtw89_btc_ble_scan_type { 1464 CXSCAN_BG = 0, 1465 CXSCAN_INIT, 1466 CXSCAN_LE, 1467 CXSCAN_MAX 1468 }; 1469 1470 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1471 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1472 1473 struct rtw89_btc_bt_scan_info_v1 { 1474 __le16 win; 1475 __le16 intvl; 1476 __le32 flags; 1477 } __packed; 1478 1479 struct rtw89_btc_bt_scan_info_v2 { 1480 __le16 win; 1481 __le16 intvl; 1482 } __packed; 1483 1484 struct rtw89_btc_fbtc_btscan_v1 { 1485 u8 fver; /* btc_ver::fcxbtscan */ 1486 u8 rsvd; 1487 __le16 rsvd2; 1488 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1489 } __packed; 1490 1491 struct rtw89_btc_fbtc_btscan_v2 { 1492 u8 fver; /* btc_ver::fcxbtscan */ 1493 u8 type; 1494 __le16 rsvd2; 1495 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1496 } __packed; 1497 1498 union rtw89_btc_fbtc_btscan { 1499 struct rtw89_btc_fbtc_btscan_v1 v1; 1500 struct rtw89_btc_fbtc_btscan_v2 v2; 1501 }; 1502 1503 struct rtw89_btc_bt_info { 1504 struct rtw89_btc_bt_link_info link_info; 1505 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1506 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1507 struct rtw89_btc_bt_ver_info ver_info; 1508 struct rtw89_btc_bool_sta_chg enable; 1509 struct rtw89_btc_bool_sta_chg inq_pag; 1510 struct rtw89_btc_rf_para rf_para; 1511 union rtw89_btc_bt_rfk_info_map rfk_info; 1512 1513 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1514 1515 u32 scbd; 1516 u32 feature; 1517 1518 u32 mbx_avl: 1; 1519 u32 whql_test: 1; 1520 u32 igno_wl: 1; 1521 u32 reinit: 1; 1522 u32 ble_scan_en: 1; 1523 u32 btg_type: 1; 1524 u32 inq: 1; 1525 u32 pag: 1; 1526 u32 run_patch_code: 1; 1527 u32 hi_lna_rx: 1; 1528 u32 scan_rx_low_pri: 1; 1529 u32 scan_info_update: 1; 1530 u32 rsvd: 20; 1531 }; 1532 1533 struct rtw89_btc_cx { 1534 struct rtw89_btc_wl_info wl; 1535 struct rtw89_btc_bt_info bt; 1536 struct rtw89_btc_3rdcx_info other; 1537 u32 state_map; 1538 u32 cnt_bt[BTC_BCNT_NUM]; 1539 u32 cnt_wl[BTC_WCNT_NUM]; 1540 }; 1541 1542 struct rtw89_btc_fbtc_tdma { 1543 u8 type; /* btc_ver::fcxtdma */ 1544 u8 rxflctrl; 1545 u8 txpause; 1546 u8 wtgle_n; 1547 u8 leak_n; 1548 u8 ext_ctrl; 1549 u8 rxflctrl_role; 1550 u8 option_ctrl; 1551 } __packed; 1552 1553 struct rtw89_btc_fbtc_tdma_v3 { 1554 u8 fver; /* btc_ver::fcxtdma */ 1555 u8 rsvd; 1556 __le16 rsvd1; 1557 struct rtw89_btc_fbtc_tdma tdma; 1558 } __packed; 1559 1560 union rtw89_btc_fbtc_tdma_le32 { 1561 struct rtw89_btc_fbtc_tdma v1; 1562 struct rtw89_btc_fbtc_tdma_v3 v3; 1563 }; 1564 1565 #define CXMREG_MAX 30 1566 #define CXMREG_MAX_V2 20 1567 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1568 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1569 1570 enum rtw89_btc_bt_sta_counter { 1571 BTC_BCNT_RFK_REQ = 0, 1572 BTC_BCNT_RFK_GO = 1, 1573 BTC_BCNT_RFK_REJECT = 2, 1574 BTC_BCNT_RFK_FAIL = 3, 1575 BTC_BCNT_RFK_TIMEOUT = 4, 1576 BTC_BCNT_HI_TX = 5, 1577 BTC_BCNT_HI_RX = 6, 1578 BTC_BCNT_LO_TX = 7, 1579 BTC_BCNT_LO_RX = 8, 1580 BTC_BCNT_POLLUTED = 9, 1581 BTC_BCNT_STA_MAX 1582 }; 1583 1584 enum rtw89_btc_bt_sta_counter_v105 { 1585 BTC_BCNT_RFK_REQ_V105 = 0, 1586 BTC_BCNT_HI_TX_V105 = 1, 1587 BTC_BCNT_HI_RX_V105 = 2, 1588 BTC_BCNT_LO_TX_V105 = 3, 1589 BTC_BCNT_LO_RX_V105 = 4, 1590 BTC_BCNT_POLLUTED_V105 = 5, 1591 BTC_BCNT_STA_MAX_V105 1592 }; 1593 1594 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1595 u16 fver; /* btc_ver::fcxbtcrpt */ 1596 u16 rpt_cnt; /* tmr counters */ 1597 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1598 u32 wl_fw_cx_offload; 1599 u32 wl_fw_ver; 1600 u32 rpt_enable; 1601 u32 rpt_para; /* ms */ 1602 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1603 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1604 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1605 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1606 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1607 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1608 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1609 u32 c2h_cnt; /* fw send c2h counter */ 1610 u32 h2c_cnt; /* fw recv h2c counter */ 1611 } __packed; 1612 1613 struct rtw89_btc_fbtc_rpt_ctrl_info { 1614 __le32 cnt; /* fw report counter */ 1615 __le32 en; /* report map */ 1616 __le32 para; /* not used */ 1617 1618 __le32 cnt_c2h; /* fw send c2h counter */ 1619 __le32 cnt_h2c; /* fw recv h2c counter */ 1620 __le32 len_c2h; /* The total length of the last C2H */ 1621 1622 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1623 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1624 } __packed; 1625 1626 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1627 __le32 cx_ver; /* match which driver's coex version */ 1628 __le32 fw_ver; 1629 __le32 en; /* report map */ 1630 1631 __le16 cnt; /* fw report counter */ 1632 __le16 cnt_c2h; /* fw send c2h counter */ 1633 __le16 cnt_h2c; /* fw recv h2c counter */ 1634 __le16 len_c2h; /* The total length of the last C2H */ 1635 1636 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1637 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1638 } __packed; 1639 1640 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1641 __le32 cx_ver; /* match which driver's coex version */ 1642 __le32 cx_offload; 1643 __le32 fw_ver; 1644 } __packed; 1645 1646 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1647 __le32 cnt_empty; /* a2dp empty count */ 1648 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1649 __le32 cnt_tx; 1650 __le32 cnt_ack; 1651 __le32 cnt_nack; 1652 } __packed; 1653 1654 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1655 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1656 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1657 __le32 cnt_recv; /* fw recv mailbox counter */ 1658 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1659 } __packed; 1660 1661 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1662 u8 fver; 1663 u8 rsvd; 1664 __le16 rsvd1; 1665 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1666 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1667 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1668 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1669 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1670 } __packed; 1671 1672 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1673 u8 fver; 1674 u8 rsvd; 1675 __le16 rsvd1; 1676 1677 u8 gnt_val[RTW89_PHY_MAX][4]; 1678 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1679 1680 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1681 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1682 } __packed; 1683 1684 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1685 u8 fver; 1686 u8 rsvd; 1687 __le16 rsvd1; 1688 1689 u8 gnt_val[RTW89_PHY_MAX][4]; 1690 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1691 1692 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1693 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1694 } __packed; 1695 1696 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1697 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1698 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1699 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1700 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1701 }; 1702 1703 enum rtw89_fbtc_ext_ctrl_type { 1704 CXECTL_OFF = 0x0, /* tdma off */ 1705 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1706 CXECTL_EXT = 0x2, 1707 CXECTL_MAX 1708 }; 1709 1710 union rtw89_btc_fbtc_rxflct { 1711 u8 val; 1712 u8 type: 3; 1713 u8 tgln_n: 5; 1714 }; 1715 1716 enum rtw89_btc_cxst_state { 1717 CXST_OFF = 0x0, 1718 CXST_B2W = 0x1, 1719 CXST_W1 = 0x2, 1720 CXST_W2 = 0x3, 1721 CXST_W2B = 0x4, 1722 CXST_B1 = 0x5, 1723 CXST_B2 = 0x6, 1724 CXST_B3 = 0x7, 1725 CXST_B4 = 0x8, 1726 CXST_LK = 0x9, 1727 CXST_BLK = 0xa, 1728 CXST_E2G = 0xb, 1729 CXST_E5G = 0xc, 1730 CXST_EBT = 0xd, 1731 CXST_ENULL = 0xe, 1732 CXST_WLK = 0xf, 1733 CXST_W1FDD = 0x10, 1734 CXST_B1FDD = 0x11, 1735 CXST_MAX = 0x12, 1736 }; 1737 1738 enum rtw89_btc_cxevnt { 1739 CXEVNT_TDMA_ENTRY = 0x0, 1740 CXEVNT_WL_TMR, 1741 CXEVNT_B1_TMR, 1742 CXEVNT_B2_TMR, 1743 CXEVNT_B3_TMR, 1744 CXEVNT_B4_TMR, 1745 CXEVNT_W2B_TMR, 1746 CXEVNT_B2W_TMR, 1747 CXEVNT_BCN_EARLY, 1748 CXEVNT_A2DP_EMPTY, 1749 CXEVNT_LK_END, 1750 CXEVNT_RX_ISR, 1751 CXEVNT_RX_FC0, 1752 CXEVNT_RX_FC1, 1753 CXEVNT_BT_RELINK, 1754 CXEVNT_BT_RETRY, 1755 CXEVNT_E2G, 1756 CXEVNT_E5G, 1757 CXEVNT_EBT, 1758 CXEVNT_ENULL, 1759 CXEVNT_DRV_WLK, 1760 CXEVNT_BCN_OK, 1761 CXEVNT_BT_CHANGE, 1762 CXEVNT_EBT_EXTEND, 1763 CXEVNT_E2G_NULL1, 1764 CXEVNT_B1FDD_TMR, 1765 CXEVNT_MAX 1766 }; 1767 1768 enum { 1769 CXBCN_ALL = 0x0, 1770 CXBCN_ALL_OK, 1771 CXBCN_BT_SLOT, 1772 CXBCN_BT_OK, 1773 CXBCN_MAX 1774 }; 1775 1776 enum btc_slot_type { 1777 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1778 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1779 CXSTYPE_NUM, 1780 }; 1781 1782 enum { /* TIME */ 1783 CXT_BT = 0x0, 1784 CXT_WL = 0x1, 1785 CXT_MAX 1786 }; 1787 1788 enum { /* TIME-A2DP */ 1789 CXT_FLCTRL_OFF = 0x0, 1790 CXT_FLCTRL_ON = 0x1, 1791 CXT_FLCTRL_MAX 1792 }; 1793 1794 enum { /* STEP TYPE */ 1795 CXSTEP_NONE = 0x0, 1796 CXSTEP_EVNT = 0x1, 1797 CXSTEP_SLOT = 0x2, 1798 CXSTEP_MAX, 1799 }; 1800 1801 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 1802 RPT_BT_AFH_SEQ_LEGACY = 0x10, 1803 RPT_BT_AFH_SEQ_LE = 0x20 1804 }; 1805 1806 #define BTC_DBG_MAX1 32 1807 struct rtw89_btc_fbtc_gpio_dbg { 1808 u8 fver; /* btc_ver::fcxgpiodbg */ 1809 u8 rsvd; 1810 u16 rsvd2; 1811 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1812 u32 pre_state; /* the debug signal is 1 or 0 */ 1813 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1814 } __packed; 1815 1816 struct rtw89_btc_fbtc_mreg_val_v1 { 1817 u8 fver; /* btc_ver::fcxmreg */ 1818 u8 reg_num; 1819 __le16 rsvd; 1820 __le32 mreg_val[CXMREG_MAX]; 1821 } __packed; 1822 1823 struct rtw89_btc_fbtc_mreg_val_v2 { 1824 u8 fver; /* btc_ver::fcxmreg */ 1825 u8 reg_num; 1826 __le16 rsvd; 1827 __le32 mreg_val[CXMREG_MAX_V2]; 1828 } __packed; 1829 1830 union rtw89_btc_fbtc_mreg_val { 1831 struct rtw89_btc_fbtc_mreg_val_v1 v1; 1832 struct rtw89_btc_fbtc_mreg_val_v2 v2; 1833 }; 1834 1835 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1836 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1837 .offset = cpu_to_le32(__offset), } 1838 1839 struct rtw89_btc_fbtc_mreg { 1840 __le16 type; 1841 __le16 bytes; 1842 __le32 offset; 1843 } __packed; 1844 1845 struct rtw89_btc_fbtc_slot { 1846 __le16 dur; 1847 __le32 cxtbl; 1848 __le16 cxtype; 1849 } __packed; 1850 1851 struct rtw89_btc_fbtc_slots { 1852 u8 fver; /* btc_ver::fcxslots */ 1853 u8 tbl_num; 1854 __le16 rsvd; 1855 __le32 update_map; 1856 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1857 } __packed; 1858 1859 struct rtw89_btc_fbtc_step { 1860 u8 type; 1861 u8 val; 1862 __le16 difft; 1863 } __packed; 1864 1865 struct rtw89_btc_fbtc_steps_v2 { 1866 u8 fver; /* btc_ver::fcxstep */ 1867 u8 rsvd; 1868 __le16 cnt; 1869 __le16 pos_old; 1870 __le16 pos_new; 1871 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1872 } __packed; 1873 1874 struct rtw89_btc_fbtc_steps_v3 { 1875 u8 fver; 1876 u8 en; 1877 __le16 rsvd; 1878 __le32 cnt; 1879 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1880 } __packed; 1881 1882 union rtw89_btc_fbtc_steps_info { 1883 struct rtw89_btc_fbtc_steps_v2 v2; 1884 struct rtw89_btc_fbtc_steps_v3 v3; 1885 }; 1886 1887 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 1888 u8 fver; /* btc_ver::fcxcysta */ 1889 u8 rsvd; 1890 __le16 cycles; /* total cycle number */ 1891 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1892 __le16 a2dpept; /* a2dp empty cnt */ 1893 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1894 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1895 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1896 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1897 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1898 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1899 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1900 __le16 tmax_a2dpept; /* max a2dp empty time */ 1901 __le16 tavg_lk; /* avg leak-slot time */ 1902 __le16 tmax_lk; /* max leak-slot time */ 1903 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1904 __le32 bcn_cnt[CXBCN_MAX]; 1905 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1906 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1907 __le32 skip_cnt; 1908 __le32 exception; 1909 __le32 except_cnt; 1910 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1911 } __packed; 1912 1913 struct rtw89_btc_fbtc_fdd_try_info { 1914 __le16 cycles[CXT_FLCTRL_MAX]; 1915 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1916 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1917 } __packed; 1918 1919 struct rtw89_btc_fbtc_cycle_time_info { 1920 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1921 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1922 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1923 } __packed; 1924 1925 struct rtw89_btc_fbtc_cycle_time_info_v5 { 1926 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1927 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1928 } __packed; 1929 1930 struct rtw89_btc_fbtc_a2dp_trx_stat { 1931 u8 empty_cnt; 1932 u8 retry_cnt; 1933 u8 tx_rate; 1934 u8 tx_cnt; 1935 u8 ack_cnt; 1936 u8 nack_cnt; 1937 u8 rsvd1; 1938 u8 rsvd2; 1939 } __packed; 1940 1941 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 1942 u8 empty_cnt; 1943 u8 retry_cnt; 1944 u8 tx_rate; 1945 u8 tx_cnt; 1946 u8 ack_cnt; 1947 u8 nack_cnt; 1948 u8 no_empty_cnt; 1949 u8 rsvd; 1950 } __packed; 1951 1952 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1953 __le16 cnt; /* a2dp empty cnt */ 1954 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1955 __le16 tavg; /* avg a2dp empty time */ 1956 __le16 tmax; /* max a2dp empty time */ 1957 } __packed; 1958 1959 struct rtw89_btc_fbtc_cycle_leak_info { 1960 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1961 __le16 tavg; /* avg leak-slot time */ 1962 __le16 tmax; /* max leak-slot time */ 1963 } __packed; 1964 1965 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 1966 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 1967 1968 struct rtw89_btc_fbtc_cycle_fddt_info { 1969 __le16 train_cycle; 1970 __le16 tp; 1971 1972 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1973 s8 bt_tx_power; /* decrease Tx power (dB) */ 1974 s8 bt_rx_gain; /* LNA constrain level */ 1975 u8 no_empty_cnt; 1976 1977 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 1978 u8 cn; /* condition_num */ 1979 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 1980 u8 train_result; /* refer to enum btc_fddt_check_map */ 1981 } __packed; 1982 1983 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 1984 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 1985 1986 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 1987 __le16 train_cycle; 1988 __le16 tp; 1989 1990 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1991 s8 bt_tx_power; /* decrease Tx power (dB) */ 1992 s8 bt_rx_gain; /* LNA constrain level */ 1993 u8 no_empty_cnt; 1994 1995 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 1996 u8 cn; /* condition_num */ 1997 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 1998 u8 train_result; /* refer to enum btc_fddt_check_map */ 1999 } __packed; 2000 2001 struct rtw89_btc_fbtc_fddt_cell_status { 2002 s8 wl_tx_pwr; 2003 s8 bt_tx_pwr; 2004 s8 bt_rx_gain; 2005 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2006 } __packed; 2007 2008 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2009 s8 wl_tx_pwr; 2010 s8 bt_tx_pwr; 2011 s8 bt_rx_gain; 2012 } __packed; 2013 2014 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2015 u8 fver; 2016 u8 rsvd; 2017 __le16 cycles; /* total cycle number */ 2018 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2019 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2020 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2021 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2022 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2023 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2024 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2025 __le32 bcn_cnt[CXBCN_MAX]; 2026 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2027 __le32 skip_cnt; 2028 __le32 except_cnt; 2029 __le32 except_map; 2030 } __packed; 2031 2032 #define FDD_TRAIN_WL_DIRECTION 2 2033 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2034 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2035 2036 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2037 u8 fver; 2038 u8 rsvd; 2039 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2040 u8 except_cnt; 2041 2042 __le16 skip_cnt; 2043 __le16 cycles; /* total cycle number */ 2044 2045 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2046 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2047 __le16 bcn_cnt[CXBCN_MAX]; 2048 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2049 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2050 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2051 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2052 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2053 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2054 [FDD_TRAIN_WL_RSSI_LEVEL] 2055 [FDD_TRAIN_BT_RSSI_LEVEL]; 2056 __le32 except_map; 2057 } __packed; 2058 2059 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2060 u8 fver; 2061 u8 rsvd; 2062 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2063 u8 except_cnt; 2064 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2065 2066 __le16 skip_cnt; 2067 __le16 cycles; /* total cycle number */ 2068 2069 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2070 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2071 __le16 bcn_cnt[CXBCN_MAX]; 2072 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2073 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2074 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2075 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2076 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2077 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2078 [FDD_TRAIN_WL_RSSI_LEVEL] 2079 [FDD_TRAIN_BT_RSSI_LEVEL]; 2080 __le32 except_map; 2081 } __packed; 2082 2083 union rtw89_btc_fbtc_cysta_info { 2084 struct rtw89_btc_fbtc_cysta_v2 v2; 2085 struct rtw89_btc_fbtc_cysta_v3 v3; 2086 struct rtw89_btc_fbtc_cysta_v4 v4; 2087 struct rtw89_btc_fbtc_cysta_v5 v5; 2088 }; 2089 2090 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2091 u8 fver; /* btc_ver::fcxnullsta */ 2092 u8 rsvd; 2093 __le16 rsvd2; 2094 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2095 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2096 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2097 } __packed; 2098 2099 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2100 u8 fver; /* btc_ver::fcxnullsta */ 2101 u8 rsvd; 2102 __le16 rsvd2; 2103 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2104 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2105 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2106 } __packed; 2107 2108 union rtw89_btc_fbtc_cynullsta_info { 2109 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2110 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2111 }; 2112 2113 struct rtw89_btc_fbtc_btver { 2114 u8 fver; /* btc_ver::fcxbtver */ 2115 u8 rsvd; 2116 __le16 rsvd2; 2117 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2118 __le32 fw_ver; 2119 __le32 feature; 2120 } __packed; 2121 2122 struct rtw89_btc_fbtc_btafh { 2123 u8 fver; /* btc_ver::fcxbtafh */ 2124 u8 rsvd; 2125 __le16 rsvd2; 2126 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2127 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2128 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2129 } __packed; 2130 2131 struct rtw89_btc_fbtc_btafh_v2 { 2132 u8 fver; /* btc_ver::fcxbtafh */ 2133 u8 rsvd; 2134 u8 rsvd2; 2135 u8 map_type; 2136 u8 afh_l[4]; 2137 u8 afh_m[4]; 2138 u8 afh_h[4]; 2139 u8 afh_le_a[4]; 2140 u8 afh_le_b[4]; 2141 } __packed; 2142 2143 struct rtw89_btc_fbtc_btdevinfo { 2144 u8 fver; /* btc_ver::fcxbtdevinfo */ 2145 u8 rsvd; 2146 __le16 vendor_id; 2147 __le32 dev_name; /* only 24 bits valid */ 2148 __le32 flush_time; 2149 } __packed; 2150 2151 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2152 struct rtw89_btc_rf_trx_para { 2153 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2154 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2155 u8 bt_tx_power; /* decrease Tx power (dB) */ 2156 u8 bt_rx_gain; /* LNA constrain level */ 2157 }; 2158 2159 struct rtw89_btc_trx_info { 2160 u8 tx_lvl; 2161 u8 rx_lvl; 2162 u8 wl_rssi; 2163 u8 bt_rssi; 2164 2165 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2166 s8 rx_gain; /* rx gain table index (TBD.) */ 2167 s8 bt_tx_power; /* decrease Tx power (dB) */ 2168 s8 bt_rx_gain; /* LNA constrain level */ 2169 2170 u8 cn; /* condition_num */ 2171 s8 nhm; 2172 u8 bt_profile; 2173 u8 rsvd2; 2174 2175 u16 tx_rate; 2176 u16 rx_rate; 2177 2178 u32 tx_tp; 2179 u32 rx_tp; 2180 u32 rx_err_ratio; 2181 }; 2182 2183 struct rtw89_btc_dm { 2184 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2185 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2186 struct rtw89_btc_fbtc_tdma tdma; 2187 struct rtw89_btc_fbtc_tdma tdma_now; 2188 struct rtw89_mac_ax_coex_gnt gnt; 2189 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2190 struct rtw89_btc_rf_trx_para rf_trx_para; 2191 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2192 struct rtw89_btc_dm_step dm_step; 2193 struct rtw89_btc_wl_scc_ctrl wl_scc; 2194 struct rtw89_btc_trx_info trx_info; 2195 union rtw89_btc_dm_error_map error; 2196 u32 cnt_dm[BTC_DCNT_NUM]; 2197 u32 cnt_notify[BTC_NCNT_NUM]; 2198 2199 u32 update_slot_map; 2200 u32 set_ant_path; 2201 2202 u32 wl_only: 1; 2203 u32 wl_fw_cx_offload: 1; 2204 u32 freerun: 1; 2205 u32 fddt_train: 1; 2206 u32 wl_ps_ctrl: 2; 2207 u32 wl_mimo_ps: 1; 2208 u32 leak_ap: 1; 2209 u32 noisy_level: 3; 2210 u32 coex_info_map: 8; 2211 u32 bt_only: 1; 2212 u32 wl_btg_rx: 1; 2213 u32 trx_para_level: 8; 2214 u32 wl_stb_chg: 1; 2215 u32 pta_owner: 1; 2216 u32 tdma_instant_excute: 1; 2217 2218 u16 slot_dur[CXST_MAX]; 2219 2220 u8 run_reason; 2221 u8 run_action; 2222 2223 u8 wl_lna2: 1; 2224 }; 2225 2226 struct rtw89_btc_ctrl { 2227 u32 manual: 1; 2228 u32 igno_bt: 1; 2229 u32 always_freerun: 1; 2230 u32 trace_step: 16; 2231 u32 rsvd: 12; 2232 }; 2233 2234 struct rtw89_btc_dbg { 2235 /* cmd "rb" */ 2236 bool rb_done; 2237 u32 rb_val; 2238 }; 2239 2240 enum rtw89_btc_btf_fw_event { 2241 BTF_EVNT_RPT = 0, 2242 BTF_EVNT_BT_INFO = 1, 2243 BTF_EVNT_BT_SCBD = 2, 2244 BTF_EVNT_BT_REG = 3, 2245 BTF_EVNT_CX_RUNINFO = 4, 2246 BTF_EVNT_BT_PSD = 5, 2247 BTF_EVNT_BUF_OVERFLOW, 2248 BTF_EVNT_C2H_LOOPBACK, 2249 BTF_EVNT_MAX, 2250 }; 2251 2252 enum btf_fw_event_report { 2253 BTC_RPT_TYPE_CTRL = 0x0, 2254 BTC_RPT_TYPE_TDMA, 2255 BTC_RPT_TYPE_SLOT, 2256 BTC_RPT_TYPE_CYSTA, 2257 BTC_RPT_TYPE_STEP, 2258 BTC_RPT_TYPE_NULLSTA, 2259 BTC_RPT_TYPE_MREG, 2260 BTC_RPT_TYPE_GPIO_DBG, 2261 BTC_RPT_TYPE_BT_VER, 2262 BTC_RPT_TYPE_BT_SCAN, 2263 BTC_RPT_TYPE_BT_AFH, 2264 BTC_RPT_TYPE_BT_DEVICE, 2265 BTC_RPT_TYPE_TEST, 2266 BTC_RPT_TYPE_MAX = 31 2267 }; 2268 2269 enum rtw_btc_btf_reg_type { 2270 REG_MAC = 0x0, 2271 REG_BB = 0x1, 2272 REG_RF = 0x2, 2273 REG_BT_RF = 0x3, 2274 REG_BT_MODEM = 0x4, 2275 REG_BT_BLUEWIZE = 0x5, 2276 REG_BT_VENDOR = 0x6, 2277 REG_BT_LE = 0x7, 2278 REG_MAX_TYPE, 2279 }; 2280 2281 struct rtw89_btc_rpt_cmn_info { 2282 u32 rx_cnt; 2283 u32 rx_len; 2284 u32 req_len; /* expected rsp len */ 2285 u8 req_fver; /* expected rsp fver */ 2286 u8 rsp_fver; /* fver from fw */ 2287 u8 valid; 2288 } __packed; 2289 2290 union rtw89_btc_fbtc_btafh_info { 2291 struct rtw89_btc_fbtc_btafh v1; 2292 struct rtw89_btc_fbtc_btafh_v2 v2; 2293 }; 2294 2295 struct rtw89_btc_report_ctrl_state { 2296 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2297 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2298 }; 2299 2300 struct rtw89_btc_rpt_fbtc_tdma { 2301 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2302 union rtw89_btc_fbtc_tdma_le32 finfo; 2303 }; 2304 2305 struct rtw89_btc_rpt_fbtc_slots { 2306 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2307 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2308 }; 2309 2310 struct rtw89_btc_rpt_fbtc_cysta { 2311 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2312 union rtw89_btc_fbtc_cysta_info finfo; 2313 }; 2314 2315 struct rtw89_btc_rpt_fbtc_step { 2316 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2317 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2318 }; 2319 2320 struct rtw89_btc_rpt_fbtc_nullsta { 2321 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2322 union rtw89_btc_fbtc_cynullsta_info finfo; 2323 }; 2324 2325 struct rtw89_btc_rpt_fbtc_mreg { 2326 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2327 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2328 }; 2329 2330 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2331 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2332 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2333 }; 2334 2335 struct rtw89_btc_rpt_fbtc_btver { 2336 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2337 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2338 }; 2339 2340 struct rtw89_btc_rpt_fbtc_btscan { 2341 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2342 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2343 }; 2344 2345 struct rtw89_btc_rpt_fbtc_btafh { 2346 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2347 union rtw89_btc_fbtc_btafh_info finfo; 2348 }; 2349 2350 struct rtw89_btc_rpt_fbtc_btdev { 2351 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2352 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2353 }; 2354 2355 enum rtw89_btc_btfre_type { 2356 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2357 BTFRE_UNDEF_TYPE, 2358 BTFRE_EXCEPTION, 2359 BTFRE_MAX, 2360 }; 2361 2362 struct rtw89_btc_btf_fwinfo { 2363 u32 cnt_c2h; 2364 u32 cnt_h2c; 2365 u32 cnt_h2c_fail; 2366 u32 event[BTF_EVNT_MAX]; 2367 2368 u32 err[BTFRE_MAX]; 2369 u32 len_mismch; 2370 u32 fver_mismch; 2371 u32 rpt_en_map; 2372 2373 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2374 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2375 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2376 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2377 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2378 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2379 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2380 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2381 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2382 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2383 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2384 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2385 }; 2386 2387 struct rtw89_btc_ver { 2388 enum rtw89_core_chip_id chip_id; 2389 u32 fw_ver_code; 2390 2391 u8 fcxbtcrpt; 2392 u8 fcxtdma; 2393 u8 fcxslots; 2394 u8 fcxcysta; 2395 u8 fcxstep; 2396 u8 fcxnullsta; 2397 u8 fcxmreg; 2398 u8 fcxgpiodbg; 2399 u8 fcxbtver; 2400 u8 fcxbtscan; 2401 u8 fcxbtafh; 2402 u8 fcxbtdevinfo; 2403 u8 fwlrole; 2404 u8 frptmap; 2405 u8 fcxctrl; 2406 2407 u16 info_buf; 2408 u8 max_role_num; 2409 }; 2410 2411 #define RTW89_BTC_POLICY_MAXLEN 512 2412 2413 struct rtw89_btc { 2414 const struct rtw89_btc_ver *ver; 2415 2416 struct rtw89_btc_cx cx; 2417 struct rtw89_btc_dm dm; 2418 struct rtw89_btc_ctrl ctrl; 2419 struct rtw89_btc_module mdinfo; 2420 struct rtw89_btc_btf_fwinfo fwinfo; 2421 struct rtw89_btc_dbg dbg; 2422 2423 struct work_struct eapol_notify_work; 2424 struct work_struct arp_notify_work; 2425 struct work_struct dhcp_notify_work; 2426 struct work_struct icmp_notify_work; 2427 2428 u32 bt_req_len; 2429 2430 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2431 u16 policy_len; 2432 u16 policy_type; 2433 bool bt_req_en; 2434 bool update_policy_force; 2435 bool lps; 2436 }; 2437 2438 enum rtw89_ra_mode { 2439 RTW89_RA_MODE_CCK = BIT(0), 2440 RTW89_RA_MODE_OFDM = BIT(1), 2441 RTW89_RA_MODE_HT = BIT(2), 2442 RTW89_RA_MODE_VHT = BIT(3), 2443 RTW89_RA_MODE_HE = BIT(4), 2444 }; 2445 2446 enum rtw89_ra_report_mode { 2447 RTW89_RA_RPT_MODE_LEGACY, 2448 RTW89_RA_RPT_MODE_HT, 2449 RTW89_RA_RPT_MODE_VHT, 2450 RTW89_RA_RPT_MODE_HE, 2451 }; 2452 2453 enum rtw89_dig_noisy_level { 2454 RTW89_DIG_NOISY_LEVEL0 = -1, 2455 RTW89_DIG_NOISY_LEVEL1 = 0, 2456 RTW89_DIG_NOISY_LEVEL2 = 1, 2457 RTW89_DIG_NOISY_LEVEL3 = 2, 2458 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2459 }; 2460 2461 enum rtw89_gi_ltf { 2462 RTW89_GILTF_LGI_4XHE32 = 0, 2463 RTW89_GILTF_SGI_4XHE08 = 1, 2464 RTW89_GILTF_2XHE16 = 2, 2465 RTW89_GILTF_2XHE08 = 3, 2466 RTW89_GILTF_1XHE16 = 4, 2467 RTW89_GILTF_1XHE08 = 5, 2468 RTW89_GILTF_MAX 2469 }; 2470 2471 enum rtw89_rx_frame_type { 2472 RTW89_RX_TYPE_MGNT = 0, 2473 RTW89_RX_TYPE_CTRL = 1, 2474 RTW89_RX_TYPE_DATA = 2, 2475 RTW89_RX_TYPE_RSVD = 3, 2476 }; 2477 2478 struct rtw89_ra_info { 2479 u8 is_dis_ra:1; 2480 /* Bit0 : CCK 2481 * Bit1 : OFDM 2482 * Bit2 : HT 2483 * Bit3 : VHT 2484 * Bit4 : HE 2485 */ 2486 u8 mode_ctrl:5; 2487 u8 bw_cap:2; 2488 u8 macid; 2489 u8 dcm_cap:1; 2490 u8 er_cap:1; 2491 u8 init_rate_lv:2; 2492 u8 upd_all:1; 2493 u8 en_sgi:1; 2494 u8 ldpc_cap:1; 2495 u8 stbc_cap:1; 2496 u8 ss_num:3; 2497 u8 giltf:3; 2498 u8 upd_bw_nss_mask:1; 2499 u8 upd_mask:1; 2500 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2501 /* BFee CSI */ 2502 u8 band_num; 2503 u8 ra_csi_rate_en:1; 2504 u8 fixed_csi_rate_en:1; 2505 u8 cr_tbl_sel:1; 2506 u8 fix_giltf_en:1; 2507 u8 fix_giltf:3; 2508 u8 rsvd2:1; 2509 u8 csi_mcs_ss_idx; 2510 u8 csi_mode:2; 2511 u8 csi_gi_ltf:3; 2512 u8 csi_bw:3; 2513 }; 2514 2515 #define RTW89_PPDU_MAX_USR 4 2516 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2517 #define RTW89_PPDU_MAC_INFO_SIZE 8 2518 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2519 2520 #define RTW89_MAX_RX_AGG_NUM 64 2521 #define RTW89_MAX_TX_AGG_NUM 128 2522 2523 struct rtw89_ampdu_params { 2524 u16 agg_num; 2525 bool amsdu; 2526 }; 2527 2528 struct rtw89_ra_report { 2529 struct rate_info txrate; 2530 u32 bit_rate; 2531 u16 hw_rate; 2532 bool might_fallback_legacy; 2533 }; 2534 2535 DECLARE_EWMA(rssi, 10, 16); 2536 2537 struct rtw89_ba_cam_entry { 2538 struct list_head list; 2539 u8 tid; 2540 }; 2541 2542 #define RTW89_MAX_ADDR_CAM_NUM 128 2543 #define RTW89_MAX_BSSID_CAM_NUM 20 2544 #define RTW89_MAX_SEC_CAM_NUM 128 2545 #define RTW89_MAX_BA_CAM_NUM 8 2546 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2547 2548 struct rtw89_addr_cam_entry { 2549 u8 addr_cam_idx; 2550 u8 offset; 2551 u8 len; 2552 u8 valid : 1; 2553 u8 addr_mask : 6; 2554 u8 wapi : 1; 2555 u8 mask_sel : 2; 2556 u8 bssid_cam_idx: 6; 2557 2558 u8 sec_ent_mode; 2559 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2560 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2561 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2562 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2563 }; 2564 2565 struct rtw89_bssid_cam_entry { 2566 u8 bssid[ETH_ALEN]; 2567 u8 phy_idx; 2568 u8 bssid_cam_idx; 2569 u8 offset; 2570 u8 len; 2571 u8 valid : 1; 2572 u8 num; 2573 }; 2574 2575 struct rtw89_sec_cam_entry { 2576 u8 sec_cam_idx; 2577 u8 offset; 2578 u8 len; 2579 u8 type : 4; 2580 u8 ext_key : 1; 2581 u8 spp_mode : 1; 2582 /* 256 bits */ 2583 u8 key[32]; 2584 }; 2585 2586 struct rtw89_sta { 2587 u8 mac_id; 2588 bool disassoc; 2589 bool er_cap; 2590 struct rtw89_dev *rtwdev; 2591 struct rtw89_vif *rtwvif; 2592 struct rtw89_ra_info ra; 2593 struct rtw89_ra_report ra_report; 2594 int max_agg_wait; 2595 u8 prev_rssi; 2596 struct ewma_rssi avg_rssi; 2597 struct ewma_rssi rssi[RF_PATH_MAX]; 2598 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2599 struct ieee80211_rx_status rx_status; 2600 u16 rx_hw_rate; 2601 __le32 htc_template; 2602 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2603 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2604 struct list_head ba_cam_list; 2605 struct sk_buff_head roc_queue; 2606 2607 bool use_cfg_mask; 2608 struct cfg80211_bitrate_mask mask; 2609 2610 bool cctl_tx_time; 2611 u32 ampdu_max_time:4; 2612 bool cctl_tx_retry_limit; 2613 u32 data_tx_cnt_lmt:6; 2614 }; 2615 2616 struct rtw89_efuse { 2617 bool valid; 2618 bool power_k_valid; 2619 u8 xtal_cap; 2620 u8 addr[ETH_ALEN]; 2621 u8 rfe_type; 2622 char country_code[2]; 2623 }; 2624 2625 struct rtw89_phy_rate_pattern { 2626 u64 ra_mask; 2627 u16 rate; 2628 u8 ra_mode; 2629 bool enable; 2630 }; 2631 2632 struct rtw89_tx_wait_info { 2633 struct rcu_head rcu_head; 2634 struct completion completion; 2635 bool tx_done; 2636 }; 2637 2638 struct rtw89_tx_skb_data { 2639 struct rtw89_tx_wait_info __rcu *wait; 2640 u8 hci_priv[]; 2641 }; 2642 2643 #define RTW89_ROC_IDLE_TIMEOUT 500 2644 #define RTW89_ROC_TX_TIMEOUT 30 2645 enum rtw89_roc_state { 2646 RTW89_ROC_IDLE, 2647 RTW89_ROC_NORMAL, 2648 RTW89_ROC_MGMT, 2649 }; 2650 2651 struct rtw89_roc { 2652 struct ieee80211_channel chan; 2653 struct delayed_work roc_work; 2654 enum ieee80211_roc_type type; 2655 enum rtw89_roc_state state; 2656 int duration; 2657 }; 2658 2659 #define RTW89_P2P_MAX_NOA_NUM 2 2660 2661 struct rtw89_vif { 2662 struct list_head list; 2663 struct rtw89_dev *rtwdev; 2664 struct rtw89_roc roc; 2665 enum rtw89_sub_entity_idx sub_entity_idx; 2666 2667 u8 mac_id; 2668 u8 port; 2669 u8 mac_addr[ETH_ALEN]; 2670 u8 bssid[ETH_ALEN]; 2671 u8 phy_idx; 2672 u8 mac_idx; 2673 u8 net_type; 2674 u8 wifi_role; 2675 u8 self_role; 2676 u8 wmm; 2677 u8 bcn_hit_cond; 2678 u8 hit_rule; 2679 u8 last_noa_nr; 2680 bool offchan; 2681 bool trigger; 2682 bool lsig_txop; 2683 u8 tgt_ind; 2684 u8 frm_tgt_ind; 2685 bool wowlan_pattern; 2686 bool wowlan_uc; 2687 bool wowlan_magic; 2688 bool is_hesta; 2689 bool last_a_ctrl; 2690 bool dyn_tb_bedge_en; 2691 u8 def_tri_idx; 2692 u32 tdls_peer; 2693 struct work_struct update_beacon_work; 2694 struct rtw89_addr_cam_entry addr_cam; 2695 struct rtw89_bssid_cam_entry bssid_cam; 2696 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2697 struct rtw89_traffic_stats stats; 2698 struct rtw89_phy_rate_pattern rate_pattern; 2699 struct cfg80211_scan_request *scan_req; 2700 struct ieee80211_scan_ies *scan_ies; 2701 struct list_head general_pkt_list; 2702 }; 2703 2704 enum rtw89_lv1_rcvy_step { 2705 RTW89_LV1_RCVY_STEP_1, 2706 RTW89_LV1_RCVY_STEP_2, 2707 }; 2708 2709 struct rtw89_hci_ops { 2710 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2711 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2712 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2713 void (*reset)(struct rtw89_dev *rtwdev); 2714 int (*start)(struct rtw89_dev *rtwdev); 2715 void (*stop)(struct rtw89_dev *rtwdev); 2716 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2717 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2718 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2719 2720 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2721 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2722 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2723 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2724 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2725 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2726 2727 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2728 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2729 int (*deinit)(struct rtw89_dev *rtwdev); 2730 2731 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2732 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2733 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2734 int (*napi_poll)(struct napi_struct *napi, int budget); 2735 2736 /* Deal with locks inside recovery_start and recovery_complete callbacks 2737 * by hci instance, and handle things which need to consider under SER. 2738 * e.g. turn on/off interrupts except for the one for halt notification. 2739 */ 2740 void (*recovery_start)(struct rtw89_dev *rtwdev); 2741 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2742 2743 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 2744 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 2745 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 2746 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 2747 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 2748 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 2749 void (*disable_intr)(struct rtw89_dev *rtwdev); 2750 void (*enable_intr)(struct rtw89_dev *rtwdev); 2751 int (*rst_bdram)(struct rtw89_dev *rtwdev); 2752 }; 2753 2754 struct rtw89_hci_info { 2755 const struct rtw89_hci_ops *ops; 2756 enum rtw89_hci_type type; 2757 u32 rpwm_addr; 2758 u32 cpwm_addr; 2759 bool paused; 2760 }; 2761 2762 struct rtw89_chip_ops { 2763 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2764 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2765 void (*bb_reset)(struct rtw89_dev *rtwdev, 2766 enum rtw89_phy_idx phy_idx); 2767 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2768 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2769 u32 addr, u32 mask); 2770 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2771 u32 addr, u32 mask, u32 data); 2772 void (*set_channel)(struct rtw89_dev *rtwdev, 2773 const struct rtw89_chan *chan, 2774 enum rtw89_mac_idx mac_idx, 2775 enum rtw89_phy_idx phy_idx); 2776 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2777 struct rtw89_channel_help_params *p, 2778 const struct rtw89_chan *chan, 2779 enum rtw89_mac_idx mac_idx, 2780 enum rtw89_phy_idx phy_idx); 2781 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2782 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2783 void (*fem_setup)(struct rtw89_dev *rtwdev); 2784 void (*rfk_init)(struct rtw89_dev *rtwdev); 2785 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2786 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2787 enum rtw89_phy_idx phy_idx); 2788 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2789 void (*rfk_track)(struct rtw89_dev *rtwdev); 2790 void (*power_trim)(struct rtw89_dev *rtwdev); 2791 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2792 const struct rtw89_chan *chan, 2793 enum rtw89_phy_idx phy_idx); 2794 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2795 enum rtw89_phy_idx phy_idx); 2796 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2797 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2798 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2799 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2800 struct rtw89_rx_phy_ppdu *phy_ppdu, 2801 struct ieee80211_rx_status *status); 2802 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2803 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2804 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2805 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2806 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2807 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2808 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2809 struct rtw89_tx_desc_info *desc_info, 2810 void *txdesc); 2811 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2812 struct rtw89_tx_desc_info *desc_info, 2813 void *txdesc); 2814 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2815 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2816 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2817 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2818 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2819 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2820 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2821 struct rtw89_vif *rtwvif, 2822 struct rtw89_sta *rtwsta); 2823 2824 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2825 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2826 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2827 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2828 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2829 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2830 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2831 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2832 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2833 }; 2834 2835 enum rtw89_dma_ch { 2836 RTW89_DMA_ACH0 = 0, 2837 RTW89_DMA_ACH1 = 1, 2838 RTW89_DMA_ACH2 = 2, 2839 RTW89_DMA_ACH3 = 3, 2840 RTW89_DMA_ACH4 = 4, 2841 RTW89_DMA_ACH5 = 5, 2842 RTW89_DMA_ACH6 = 6, 2843 RTW89_DMA_ACH7 = 7, 2844 RTW89_DMA_B0MG = 8, 2845 RTW89_DMA_B0HI = 9, 2846 RTW89_DMA_B1MG = 10, 2847 RTW89_DMA_B1HI = 11, 2848 RTW89_DMA_H2C = 12, 2849 RTW89_DMA_CH_NUM = 13 2850 }; 2851 2852 enum rtw89_qta_mode { 2853 RTW89_QTA_SCC, 2854 RTW89_QTA_DLFW, 2855 RTW89_QTA_WOW, 2856 2857 /* keep last */ 2858 RTW89_QTA_INVALID, 2859 }; 2860 2861 struct rtw89_hfc_ch_cfg { 2862 u16 min; 2863 u16 max; 2864 #define grp_0 0 2865 #define grp_1 1 2866 #define grp_num 2 2867 u8 grp; 2868 }; 2869 2870 struct rtw89_hfc_ch_info { 2871 u16 aval; 2872 u16 used; 2873 }; 2874 2875 struct rtw89_hfc_pub_cfg { 2876 u16 grp0; 2877 u16 grp1; 2878 u16 pub_max; 2879 u16 wp_thrd; 2880 }; 2881 2882 struct rtw89_hfc_pub_info { 2883 u16 g0_used; 2884 u16 g1_used; 2885 u16 g0_aval; 2886 u16 g1_aval; 2887 u16 pub_aval; 2888 u16 wp_aval; 2889 }; 2890 2891 struct rtw89_hfc_prec_cfg { 2892 u16 ch011_prec; 2893 u16 h2c_prec; 2894 u16 wp_ch07_prec; 2895 u16 wp_ch811_prec; 2896 u8 ch011_full_cond; 2897 u8 h2c_full_cond; 2898 u8 wp_ch07_full_cond; 2899 u8 wp_ch811_full_cond; 2900 }; 2901 2902 struct rtw89_hfc_param { 2903 bool en; 2904 bool h2c_en; 2905 u8 mode; 2906 const struct rtw89_hfc_ch_cfg *ch_cfg; 2907 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2908 struct rtw89_hfc_pub_cfg pub_cfg; 2909 struct rtw89_hfc_pub_info pub_info; 2910 struct rtw89_hfc_prec_cfg prec_cfg; 2911 }; 2912 2913 struct rtw89_hfc_param_ini { 2914 const struct rtw89_hfc_ch_cfg *ch_cfg; 2915 const struct rtw89_hfc_pub_cfg *pub_cfg; 2916 const struct rtw89_hfc_prec_cfg *prec_cfg; 2917 u8 mode; 2918 }; 2919 2920 struct rtw89_dle_size { 2921 u16 pge_size; 2922 u16 lnk_pge_num; 2923 u16 unlnk_pge_num; 2924 }; 2925 2926 struct rtw89_wde_quota { 2927 u16 hif; 2928 u16 wcpu; 2929 u16 pkt_in; 2930 u16 cpu_io; 2931 }; 2932 2933 struct rtw89_ple_quota { 2934 u16 cma0_tx; 2935 u16 cma1_tx; 2936 u16 c2h; 2937 u16 h2c; 2938 u16 wcpu; 2939 u16 mpdu_proc; 2940 u16 cma0_dma; 2941 u16 cma1_dma; 2942 u16 bb_rpt; 2943 u16 wd_rel; 2944 u16 cpu_io; 2945 u16 tx_rpt; 2946 }; 2947 2948 struct rtw89_dle_mem { 2949 enum rtw89_qta_mode mode; 2950 const struct rtw89_dle_size *wde_size; 2951 const struct rtw89_dle_size *ple_size; 2952 const struct rtw89_wde_quota *wde_min_qt; 2953 const struct rtw89_wde_quota *wde_max_qt; 2954 const struct rtw89_ple_quota *ple_min_qt; 2955 const struct rtw89_ple_quota *ple_max_qt; 2956 }; 2957 2958 struct rtw89_reg_def { 2959 u32 addr; 2960 u32 mask; 2961 }; 2962 2963 struct rtw89_reg2_def { 2964 u32 addr; 2965 u32 data; 2966 }; 2967 2968 struct rtw89_reg3_def { 2969 u32 addr; 2970 u32 mask; 2971 u32 data; 2972 }; 2973 2974 struct rtw89_reg5_def { 2975 u8 flag; /* recognized by parsers */ 2976 u8 path; 2977 u32 addr; 2978 u32 mask; 2979 u32 data; 2980 }; 2981 2982 struct rtw89_phy_table { 2983 const struct rtw89_reg2_def *regs; 2984 u32 n_regs; 2985 enum rtw89_rf_path rf_path; 2986 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2987 enum rtw89_rf_path rf_path, void *data); 2988 }; 2989 2990 struct rtw89_txpwr_table { 2991 const void *data; 2992 u32 size; 2993 void (*load)(struct rtw89_dev *rtwdev, 2994 const struct rtw89_txpwr_table *tbl); 2995 }; 2996 2997 struct rtw89_txpwr_rule_2ghz { 2998 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2999 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3000 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3001 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3002 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3003 }; 3004 3005 struct rtw89_txpwr_rule_5ghz { 3006 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3007 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3008 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3009 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3010 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3011 }; 3012 3013 struct rtw89_txpwr_rule_6ghz { 3014 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3015 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3016 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 3017 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3018 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 3019 }; 3020 3021 struct rtw89_rfe_parms { 3022 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3023 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3024 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3025 }; 3026 3027 struct rtw89_rfe_parms_conf { 3028 const struct rtw89_rfe_parms *rfe_parms; 3029 u8 rfe_type; 3030 }; 3031 3032 struct rtw89_page_regs { 3033 u32 hci_fc_ctrl; 3034 u32 ch_page_ctrl; 3035 u32 ach_page_ctrl; 3036 u32 ach_page_info; 3037 u32 pub_page_info3; 3038 u32 pub_page_ctrl1; 3039 u32 pub_page_ctrl2; 3040 u32 pub_page_info1; 3041 u32 pub_page_info2; 3042 u32 wp_page_ctrl1; 3043 u32 wp_page_ctrl2; 3044 u32 wp_page_info1; 3045 }; 3046 3047 struct rtw89_imr_info { 3048 u32 wdrls_imr_set; 3049 u32 wsec_imr_reg; 3050 u32 wsec_imr_set; 3051 u32 mpdu_tx_imr_set; 3052 u32 mpdu_rx_imr_set; 3053 u32 sta_sch_imr_set; 3054 u32 txpktctl_imr_b0_reg; 3055 u32 txpktctl_imr_b0_clr; 3056 u32 txpktctl_imr_b0_set; 3057 u32 txpktctl_imr_b1_reg; 3058 u32 txpktctl_imr_b1_clr; 3059 u32 txpktctl_imr_b1_set; 3060 u32 wde_imr_clr; 3061 u32 wde_imr_set; 3062 u32 ple_imr_clr; 3063 u32 ple_imr_set; 3064 u32 host_disp_imr_clr; 3065 u32 host_disp_imr_set; 3066 u32 cpu_disp_imr_clr; 3067 u32 cpu_disp_imr_set; 3068 u32 other_disp_imr_clr; 3069 u32 other_disp_imr_set; 3070 u32 bbrpt_com_err_imr_reg; 3071 u32 bbrpt_chinfo_err_imr_reg; 3072 u32 bbrpt_err_imr_set; 3073 u32 bbrpt_dfs_err_imr_reg; 3074 u32 ptcl_imr_clr; 3075 u32 ptcl_imr_set; 3076 u32 cdma_imr_0_reg; 3077 u32 cdma_imr_0_clr; 3078 u32 cdma_imr_0_set; 3079 u32 cdma_imr_1_reg; 3080 u32 cdma_imr_1_clr; 3081 u32 cdma_imr_1_set; 3082 u32 phy_intf_imr_reg; 3083 u32 phy_intf_imr_clr; 3084 u32 phy_intf_imr_set; 3085 u32 rmac_imr_reg; 3086 u32 rmac_imr_clr; 3087 u32 rmac_imr_set; 3088 u32 tmac_imr_reg; 3089 u32 tmac_imr_clr; 3090 u32 tmac_imr_set; 3091 }; 3092 3093 struct rtw89_rrsr_cfgs { 3094 struct rtw89_reg3_def ref_rate; 3095 struct rtw89_reg3_def rsc; 3096 }; 3097 3098 struct rtw89_dig_regs { 3099 u32 seg0_pd_reg; 3100 u32 pd_lower_bound_mask; 3101 u32 pd_spatial_reuse_en; 3102 struct rtw89_reg_def p0_lna_init; 3103 struct rtw89_reg_def p1_lna_init; 3104 struct rtw89_reg_def p0_tia_init; 3105 struct rtw89_reg_def p1_tia_init; 3106 struct rtw89_reg_def p0_rxb_init; 3107 struct rtw89_reg_def p1_rxb_init; 3108 struct rtw89_reg_def p0_p20_pagcugc_en; 3109 struct rtw89_reg_def p0_s20_pagcugc_en; 3110 struct rtw89_reg_def p1_p20_pagcugc_en; 3111 struct rtw89_reg_def p1_s20_pagcugc_en; 3112 }; 3113 3114 struct rtw89_phy_ul_tb_info { 3115 bool dyn_tb_tri_en; 3116 u8 def_if_bandedge; 3117 }; 3118 3119 struct rtw89_chip_info { 3120 enum rtw89_core_chip_id chip_id; 3121 const struct rtw89_chip_ops *ops; 3122 const char *fw_basename; 3123 u8 fw_format_max; 3124 bool try_ce_fw; 3125 u32 fifo_size; 3126 u32 dle_scc_rsvd_size; 3127 u16 max_amsdu_limit; 3128 bool dis_2g_40m_ul_ofdma; 3129 u32 rsvd_ple_ofst; 3130 const struct rtw89_hfc_param_ini *hfc_param_ini; 3131 const struct rtw89_dle_mem *dle_mem; 3132 u8 wde_qempty_acq_num; 3133 u8 wde_qempty_mgq_sel; 3134 u32 rf_base_addr[2]; 3135 u8 support_chanctx_num; 3136 u8 support_bands; 3137 bool support_bw160; 3138 bool support_ul_tb_ctrl; 3139 bool hw_sec_hdr; 3140 u8 rf_path_num; 3141 u8 tx_nss; 3142 u8 rx_nss; 3143 u8 acam_num; 3144 u8 bcam_num; 3145 u8 scam_num; 3146 u8 bacam_num; 3147 u8 bacam_dynamic_num; 3148 bool bacam_v1; 3149 3150 u8 sec_ctrl_efuse_size; 3151 u32 physical_efuse_size; 3152 u32 logical_efuse_size; 3153 u32 limit_efuse_size; 3154 u32 dav_phy_efuse_size; 3155 u32 dav_log_efuse_size; 3156 u32 phycap_addr; 3157 u32 phycap_size; 3158 3159 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3160 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3161 const struct rtw89_phy_table *bb_table; 3162 const struct rtw89_phy_table *bb_gain_table; 3163 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3164 const struct rtw89_phy_table *nctl_table; 3165 const struct rtw89_txpwr_table *byr_table; 3166 const struct rtw89_phy_dig_gain_table *dig_table; 3167 const struct rtw89_dig_regs *dig_regs; 3168 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3169 3170 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3171 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3172 const struct rtw89_rfe_parms *dflt_parms; 3173 3174 u8 txpwr_factor_rf; 3175 u8 txpwr_factor_mac; 3176 3177 u32 para_ver; 3178 u32 wlcx_desired; 3179 u8 btcx_desired; 3180 u8 scbd; 3181 u8 mailbox; 3182 3183 u8 afh_guard_ch; 3184 const u8 *wl_rssi_thres; 3185 const u8 *bt_rssi_thres; 3186 u8 rssi_tol; 3187 3188 u8 mon_reg_num; 3189 const struct rtw89_btc_fbtc_mreg *mon_reg; 3190 u8 rf_para_ulink_num; 3191 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3192 u8 rf_para_dlink_num; 3193 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3194 u8 ps_mode_supported; 3195 u8 low_power_hci_modes; 3196 3197 u32 h2c_cctl_func_id; 3198 u32 hci_func_en_addr; 3199 u32 h2c_desc_size; 3200 u32 txwd_body_size; 3201 u32 h2c_ctrl_reg; 3202 const u32 *h2c_regs; 3203 struct rtw89_reg_def h2c_counter_reg; 3204 u32 c2h_ctrl_reg; 3205 const u32 *c2h_regs; 3206 struct rtw89_reg_def c2h_counter_reg; 3207 const struct rtw89_page_regs *page_regs; 3208 bool cfo_src_fd; 3209 bool cfo_hw_comp; 3210 const struct rtw89_reg_def *dcfo_comp; 3211 u8 dcfo_comp_sft; 3212 const struct rtw89_imr_info *imr_info; 3213 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3214 u32 bss_clr_map_reg; 3215 u32 dma_ch_mask; 3216 u32 edcca_lvl_reg; 3217 const struct wiphy_wowlan_support *wowlan_stub; 3218 }; 3219 3220 union rtw89_bus_info { 3221 const struct rtw89_pci_info *pci; 3222 }; 3223 3224 struct rtw89_driver_info { 3225 const struct rtw89_chip_info *chip; 3226 union rtw89_bus_info bus; 3227 }; 3228 3229 enum rtw89_hcifc_mode { 3230 RTW89_HCIFC_POH = 0, 3231 RTW89_HCIFC_STF = 1, 3232 RTW89_HCIFC_SDIO = 2, 3233 3234 /* keep last */ 3235 RTW89_HCIFC_MODE_INVALID, 3236 }; 3237 3238 struct rtw89_dle_info { 3239 enum rtw89_qta_mode qta_mode; 3240 u16 wde_pg_size; 3241 u16 ple_pg_size; 3242 u16 c0_rx_qta; 3243 u16 c1_rx_qta; 3244 }; 3245 3246 enum rtw89_host_rpr_mode { 3247 RTW89_RPR_MODE_POH = 0, 3248 RTW89_RPR_MODE_STF 3249 }; 3250 3251 struct rtw89_mac_info { 3252 struct rtw89_dle_info dle_info; 3253 struct rtw89_hfc_param hfc_param; 3254 enum rtw89_qta_mode qta_mode; 3255 u8 rpwm_seq_num; 3256 u8 cpwm_seq_num; 3257 }; 3258 3259 #define RTW89_COMPLETION_BUF_SIZE 24 3260 #define RTW89_WAIT_COND_IDLE UINT_MAX 3261 3262 struct rtw89_completion_data { 3263 bool err; 3264 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3265 }; 3266 3267 struct rtw89_wait_info { 3268 atomic_t cond; 3269 struct completion completion; 3270 struct rtw89_completion_data data; 3271 }; 3272 3273 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3274 3275 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3276 { 3277 init_completion(&wait->completion); 3278 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3279 } 3280 3281 enum rtw89_fw_type { 3282 RTW89_FW_NORMAL = 1, 3283 RTW89_FW_WOWLAN = 3, 3284 RTW89_FW_NORMAL_CE = 5, 3285 }; 3286 3287 enum rtw89_fw_feature { 3288 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3289 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3290 RTW89_FW_FEATURE_TX_WAKE, 3291 RTW89_FW_FEATURE_CRASH_TRIGGER, 3292 RTW89_FW_FEATURE_NO_PACKET_DROP, 3293 RTW89_FW_FEATURE_NO_DEEP_PS, 3294 RTW89_FW_FEATURE_NO_LPS_PG, 3295 RTW89_FW_FEATURE_BEACON_FILTER, 3296 }; 3297 3298 struct rtw89_fw_suit { 3299 const u8 *data; 3300 u32 size; 3301 u8 major_ver; 3302 u8 minor_ver; 3303 u8 sub_ver; 3304 u8 sub_idex; 3305 u16 build_year; 3306 u16 build_mon; 3307 u16 build_date; 3308 u16 build_hour; 3309 u16 build_min; 3310 u8 cmd_ver; 3311 }; 3312 3313 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3314 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3315 #define RTW89_FW_SUIT_VER_CODE(s) \ 3316 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3317 3318 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3319 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3320 (mfw_hdr)->ver.minor, \ 3321 (mfw_hdr)->ver.sub, \ 3322 (mfw_hdr)->ver.idx) 3323 3324 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3325 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 3326 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 3327 GET_FW_HDR_SUBVERSION(fw_hdr), \ 3328 GET_FW_HDR_SUBINDEX(fw_hdr)) 3329 3330 struct rtw89_fw_req_info { 3331 const struct firmware *firmware; 3332 struct completion completion; 3333 }; 3334 3335 struct rtw89_fw_info { 3336 struct rtw89_fw_req_info req; 3337 int fw_format; 3338 u8 h2c_seq; 3339 u8 rec_seq; 3340 u8 h2c_counter; 3341 u8 c2h_counter; 3342 struct rtw89_fw_suit normal; 3343 struct rtw89_fw_suit wowlan; 3344 bool fw_log_enable; 3345 u32 feature_map; 3346 }; 3347 3348 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3349 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3350 3351 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3352 ((_fw)->feature_map |= BIT(_fw_feature)) 3353 3354 struct rtw89_cam_info { 3355 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3356 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3357 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3358 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3359 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3360 }; 3361 3362 enum rtw89_sar_sources { 3363 RTW89_SAR_SOURCE_NONE, 3364 RTW89_SAR_SOURCE_COMMON, 3365 3366 RTW89_SAR_SOURCE_NR, 3367 }; 3368 3369 enum rtw89_sar_subband { 3370 RTW89_SAR_2GHZ_SUBBAND, 3371 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3372 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3373 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3374 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3375 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3376 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3377 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3378 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3379 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3380 3381 RTW89_SAR_SUBBAND_NR, 3382 }; 3383 3384 struct rtw89_sar_cfg_common { 3385 bool set[RTW89_SAR_SUBBAND_NR]; 3386 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3387 }; 3388 3389 struct rtw89_sar_info { 3390 /* used to decide how to acces SAR cfg union */ 3391 enum rtw89_sar_sources src; 3392 3393 /* reserved for different knids of SAR cfg struct. 3394 * supposed that a single cfg struct cannot handle various SAR sources. 3395 */ 3396 union { 3397 struct rtw89_sar_cfg_common cfg_common; 3398 }; 3399 }; 3400 3401 struct rtw89_chanctx_cfg { 3402 enum rtw89_sub_entity_idx idx; 3403 }; 3404 3405 enum rtw89_entity_mode { 3406 RTW89_ENTITY_MODE_SCC, 3407 }; 3408 3409 struct rtw89_sub_entity { 3410 struct cfg80211_chan_def chandef; 3411 struct rtw89_chan chan; 3412 struct rtw89_chan_rcd rcd; 3413 struct rtw89_chanctx_cfg *cfg; 3414 }; 3415 3416 struct rtw89_hal { 3417 u32 rx_fltr; 3418 u8 cv; 3419 u8 acv; 3420 u32 sw_amsdu_max_size; 3421 u32 antenna_tx; 3422 u32 antenna_rx; 3423 u8 tx_nss; 3424 u8 rx_nss; 3425 bool tx_path_diversity; 3426 bool support_cckpd; 3427 bool support_igi; 3428 atomic_t roc_entity_idx; 3429 3430 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 3431 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 3432 struct cfg80211_chan_def roc_chandef; 3433 3434 bool entity_active; 3435 enum rtw89_entity_mode entity_mode; 3436 3437 u32 edcca_bak; 3438 }; 3439 3440 #define RTW89_MAX_MAC_ID_NUM 128 3441 #define RTW89_MAX_PKT_OFLD_NUM 255 3442 3443 enum rtw89_flags { 3444 RTW89_FLAG_POWERON, 3445 RTW89_FLAG_FW_RDY, 3446 RTW89_FLAG_RUNNING, 3447 RTW89_FLAG_BFEE_MON, 3448 RTW89_FLAG_BFEE_EN, 3449 RTW89_FLAG_BFEE_TIMER_KEEP, 3450 RTW89_FLAG_NAPI_RUNNING, 3451 RTW89_FLAG_LEISURE_PS, 3452 RTW89_FLAG_LOW_POWER_MODE, 3453 RTW89_FLAG_INACTIVE_PS, 3454 RTW89_FLAG_CRASH_SIMULATING, 3455 RTW89_FLAG_WOWLAN, 3456 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 3457 RTW89_FLAG_CHANGING_INTERFACE, 3458 3459 NUM_OF_RTW89_FLAGS, 3460 }; 3461 3462 enum rtw89_pkt_drop_sel { 3463 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 3464 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 3465 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 3466 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 3467 RTW89_PKT_DROP_SEL_MACID_ALL, 3468 RTW89_PKT_DROP_SEL_MG0_ONCE, 3469 RTW89_PKT_DROP_SEL_HIQ_ONCE, 3470 RTW89_PKT_DROP_SEL_HIQ_PORT, 3471 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 3472 RTW89_PKT_DROP_SEL_BAND, 3473 RTW89_PKT_DROP_SEL_BAND_ONCE, 3474 RTW89_PKT_DROP_SEL_REL_MACID, 3475 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 3476 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 3477 }; 3478 3479 struct rtw89_pkt_drop_params { 3480 enum rtw89_pkt_drop_sel sel; 3481 enum rtw89_mac_idx mac_band; 3482 u8 macid; 3483 u8 port; 3484 u8 mbssid; 3485 bool tf_trs; 3486 u32 macid_band_sel[4]; 3487 }; 3488 3489 struct rtw89_pkt_stat { 3490 u16 beacon_nr; 3491 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 3492 }; 3493 3494 DECLARE_EWMA(thermal, 4, 4); 3495 3496 struct rtw89_phy_stat { 3497 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 3498 struct rtw89_pkt_stat cur_pkt_stat; 3499 struct rtw89_pkt_stat last_pkt_stat; 3500 }; 3501 3502 #define RTW89_DACK_PATH_NR 2 3503 #define RTW89_DACK_IDX_NR 2 3504 #define RTW89_DACK_MSBK_NR 16 3505 struct rtw89_dack_info { 3506 bool dack_done; 3507 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 3508 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3509 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3510 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3511 u32 dack_cnt; 3512 bool addck_timeout[RTW89_DACK_PATH_NR]; 3513 bool dadck_timeout[RTW89_DACK_PATH_NR]; 3514 bool msbk_timeout[RTW89_DACK_PATH_NR]; 3515 }; 3516 3517 #define RTW89_IQK_CHS_NR 2 3518 #define RTW89_IQK_PATH_NR 4 3519 3520 struct rtw89_rfk_mcc_info { 3521 u8 ch[RTW89_IQK_CHS_NR]; 3522 u8 band[RTW89_IQK_CHS_NR]; 3523 u8 table_idx; 3524 }; 3525 3526 struct rtw89_lck_info { 3527 u8 thermal[RF_PATH_MAX]; 3528 }; 3529 3530 struct rtw89_rx_dck_info { 3531 u8 thermal[RF_PATH_MAX]; 3532 }; 3533 3534 struct rtw89_iqk_info { 3535 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3536 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3537 bool lok_fail[RTW89_IQK_PATH_NR]; 3538 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3539 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3540 u32 iqk_fail_cnt; 3541 bool is_iqk_init; 3542 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3543 u8 iqk_band[RTW89_IQK_PATH_NR]; 3544 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3545 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3546 u8 kcount; 3547 u8 iqk_times; 3548 u8 version; 3549 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3550 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3551 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3552 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3553 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3554 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3555 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3556 bool is_nbiqk; 3557 bool iqk_fft_en; 3558 bool iqk_xym_en; 3559 bool iqk_sram_en; 3560 bool iqk_cfir_en; 3561 u8 thermal[RTW89_IQK_PATH_NR]; 3562 bool thermal_rek_en; 3563 u32 syn1to2; 3564 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3565 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3566 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3567 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3568 }; 3569 3570 #define RTW89_DPK_RF_PATH 2 3571 #define RTW89_DPK_AVG_THERMAL_NUM 8 3572 #define RTW89_DPK_BKUP_NUM 2 3573 struct rtw89_dpk_bkup_para { 3574 enum rtw89_band band; 3575 enum rtw89_bandwidth bw; 3576 u8 ch; 3577 bool path_ok; 3578 u8 mdpd_en; 3579 u8 txagc_dpk; 3580 u8 ther_dpk; 3581 u8 gs; 3582 u16 pwsf; 3583 }; 3584 3585 struct rtw89_dpk_info { 3586 bool is_dpk_enable; 3587 bool is_dpk_reload_en; 3588 u8 dpk_gs[RTW89_PHY_MAX]; 3589 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3590 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3591 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3592 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3593 u8 cur_idx[RTW89_DPK_RF_PATH]; 3594 u8 cur_k_set; 3595 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3596 }; 3597 3598 struct rtw89_fem_info { 3599 bool elna_2g; 3600 bool elna_5g; 3601 bool epa_2g; 3602 bool epa_5g; 3603 bool epa_6g; 3604 }; 3605 3606 struct rtw89_phy_ch_info { 3607 u8 rssi_min; 3608 u16 rssi_min_macid; 3609 u8 pre_rssi_min; 3610 u8 rssi_max; 3611 u16 rssi_max_macid; 3612 u8 rxsc_160; 3613 u8 rxsc_80; 3614 u8 rxsc_40; 3615 u8 rxsc_20; 3616 u8 rxsc_l; 3617 u8 is_noisy; 3618 }; 3619 3620 struct rtw89_agc_gaincode_set { 3621 u8 lna_idx; 3622 u8 tia_idx; 3623 u8 rxb_idx; 3624 }; 3625 3626 #define IGI_RSSI_TH_NUM 5 3627 #define FA_TH_NUM 4 3628 #define LNA_GAIN_NUM 7 3629 #define TIA_GAIN_NUM 2 3630 struct rtw89_dig_info { 3631 struct rtw89_agc_gaincode_set cur_gaincode; 3632 bool force_gaincode_idx_en; 3633 struct rtw89_agc_gaincode_set force_gaincode; 3634 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3635 u16 fa_th[FA_TH_NUM]; 3636 u8 igi_rssi; 3637 u8 igi_fa_rssi; 3638 u8 fa_rssi_ofst; 3639 u8 dyn_igi_max; 3640 u8 dyn_igi_min; 3641 bool dyn_pd_th_en; 3642 u8 dyn_pd_th_max; 3643 u8 pd_low_th_ofst; 3644 u8 ib_pbk; 3645 s8 ib_pkpwr; 3646 s8 lna_gain_a[LNA_GAIN_NUM]; 3647 s8 lna_gain_g[LNA_GAIN_NUM]; 3648 s8 *lna_gain; 3649 s8 tia_gain_a[TIA_GAIN_NUM]; 3650 s8 tia_gain_g[TIA_GAIN_NUM]; 3651 s8 *tia_gain; 3652 bool is_linked_pre; 3653 bool bypass_dig; 3654 }; 3655 3656 enum rtw89_multi_cfo_mode { 3657 RTW89_PKT_BASED_AVG_MODE = 0, 3658 RTW89_ENTRY_BASED_AVG_MODE = 1, 3659 RTW89_TP_BASED_AVG_MODE = 2, 3660 }; 3661 3662 enum rtw89_phy_cfo_status { 3663 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3664 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3665 RTW89_PHY_DCFO_STATE_HOLD = 2, 3666 RTW89_PHY_DCFO_STATE_MAX 3667 }; 3668 3669 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3670 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3671 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3672 }; 3673 3674 struct rtw89_cfo_tracking_info { 3675 u16 cfo_timer_ms; 3676 bool cfo_trig_by_timer_en; 3677 enum rtw89_phy_cfo_status phy_cfo_status; 3678 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3679 u8 phy_cfo_trk_cnt; 3680 bool is_adjust; 3681 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3682 bool apply_compensation; 3683 u8 crystal_cap; 3684 u8 crystal_cap_default; 3685 u8 def_x_cap; 3686 s8 x_cap_ofst; 3687 u32 sta_cfo_tolerance; 3688 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3689 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3690 s32 cfo_avg_pre; 3691 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3692 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3693 s32 dcfo_avg; 3694 s32 dcfo_avg_pre; 3695 u32 packet_count; 3696 u32 packet_count_pre; 3697 s32 residual_cfo_acc; 3698 u8 phy_cfotrk_state; 3699 u8 phy_cfotrk_cnt; 3700 bool divergence_lock_en; 3701 u8 x_cap_lb; 3702 u8 x_cap_ub; 3703 u8 lock_cnt; 3704 }; 3705 3706 enum rtw89_tssi_alimk_band { 3707 TSSI_ALIMK_2G = 0, 3708 TSSI_ALIMK_5GL, 3709 TSSI_ALIMK_5GM, 3710 TSSI_ALIMK_5GH, 3711 TSSI_ALIMK_MAX 3712 }; 3713 3714 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3715 #define TSSI_TRIM_CH_GROUP_NUM 8 3716 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3717 3718 #define TSSI_CCK_CH_GROUP_NUM 6 3719 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3720 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3721 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3722 #define TSSI_MCS_CH_GROUP_NUM \ 3723 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3724 #define TSSI_MAX_CH_NUM 67 3725 #define TSSI_ALIMK_VALUE_NUM 8 3726 3727 struct rtw89_tssi_info { 3728 u8 thermal[RF_PATH_MAX]; 3729 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3730 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3731 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3732 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3733 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3734 s8 extra_ofst[RF_PATH_MAX]; 3735 bool tssi_tracking_check[RF_PATH_MAX]; 3736 u8 default_txagc_offset[RF_PATH_MAX]; 3737 u32 base_thermal[RF_PATH_MAX]; 3738 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 3739 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 3740 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 3741 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 3742 u32 tssi_alimk_time; 3743 }; 3744 3745 struct rtw89_power_trim_info { 3746 bool pg_thermal_trim; 3747 bool pg_pa_bias_trim; 3748 u8 thermal_trim[RF_PATH_MAX]; 3749 u8 pa_bias_trim[RF_PATH_MAX]; 3750 }; 3751 3752 struct rtw89_regulatory { 3753 char alpha2[3]; 3754 u8 txpwr_regd[RTW89_BAND_MAX]; 3755 }; 3756 3757 enum rtw89_ifs_clm_application { 3758 RTW89_IFS_CLM_INIT = 0, 3759 RTW89_IFS_CLM_BACKGROUND = 1, 3760 RTW89_IFS_CLM_ACS = 2, 3761 RTW89_IFS_CLM_DIG = 3, 3762 RTW89_IFS_CLM_TDMA_DIG = 4, 3763 RTW89_IFS_CLM_DBG = 5, 3764 RTW89_IFS_CLM_DBG_MANUAL = 6 3765 }; 3766 3767 enum rtw89_env_racing_lv { 3768 RTW89_RAC_RELEASE = 0, 3769 RTW89_RAC_LV_1 = 1, 3770 RTW89_RAC_LV_2 = 2, 3771 RTW89_RAC_LV_3 = 3, 3772 RTW89_RAC_LV_4 = 4, 3773 RTW89_RAC_MAX_NUM = 5 3774 }; 3775 3776 struct rtw89_ccx_para_info { 3777 enum rtw89_env_racing_lv rac_lv; 3778 u16 mntr_time; 3779 u8 nhm_manual_th_ofst; 3780 u8 nhm_manual_th0; 3781 enum rtw89_ifs_clm_application ifs_clm_app; 3782 u32 ifs_clm_manual_th_times; 3783 u32 ifs_clm_manual_th0; 3784 u8 fahm_manual_th_ofst; 3785 u8 fahm_manual_th0; 3786 u8 fahm_numer_opt; 3787 u8 fahm_denom_opt; 3788 }; 3789 3790 enum rtw89_ccx_edcca_opt_sc_idx { 3791 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3792 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3793 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3794 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3795 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3796 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3797 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3798 RTW89_CCX_EDCCA_SEG1_S3 = 7 3799 }; 3800 3801 enum rtw89_ccx_edcca_opt_bw_idx { 3802 RTW89_CCX_EDCCA_BW20_0 = 0, 3803 RTW89_CCX_EDCCA_BW20_1 = 1, 3804 RTW89_CCX_EDCCA_BW20_2 = 2, 3805 RTW89_CCX_EDCCA_BW20_3 = 3, 3806 RTW89_CCX_EDCCA_BW20_4 = 4, 3807 RTW89_CCX_EDCCA_BW20_5 = 5, 3808 RTW89_CCX_EDCCA_BW20_6 = 6, 3809 RTW89_CCX_EDCCA_BW20_7 = 7 3810 }; 3811 3812 #define RTW89_NHM_TH_NUM 11 3813 #define RTW89_FAHM_TH_NUM 11 3814 #define RTW89_NHM_RPT_NUM 12 3815 #define RTW89_FAHM_RPT_NUM 12 3816 #define RTW89_IFS_CLM_NUM 4 3817 struct rtw89_env_monitor_info { 3818 u32 ccx_trigger_time; 3819 u64 start_time; 3820 u8 ccx_rpt_stamp; 3821 u8 ccx_watchdog_result; 3822 bool ccx_ongoing; 3823 u8 ccx_rac_lv; 3824 bool ccx_manual_ctrl; 3825 u8 ccx_pre_rssi; 3826 u16 clm_mntr_time; 3827 u16 nhm_mntr_time; 3828 u16 ifs_clm_mntr_time; 3829 enum rtw89_ifs_clm_application ifs_clm_app; 3830 u16 fahm_mntr_time; 3831 u16 edcca_clm_mntr_time; 3832 u16 ccx_period; 3833 u8 ccx_unit_idx; 3834 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3835 u8 nhm_th[RTW89_NHM_TH_NUM]; 3836 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3837 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3838 u8 fahm_numer_opt; 3839 u8 fahm_denom_opt; 3840 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3841 u16 clm_result; 3842 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3843 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3844 u16 nhm_tx_cnt; 3845 u16 nhm_cca_cnt; 3846 u16 nhm_idle_cnt; 3847 u16 ifs_clm_tx; 3848 u16 ifs_clm_edcca_excl_cca; 3849 u16 ifs_clm_ofdmfa; 3850 u16 ifs_clm_ofdmcca_excl_fa; 3851 u16 ifs_clm_cckfa; 3852 u16 ifs_clm_cckcca_excl_fa; 3853 u16 ifs_clm_total_ifs; 3854 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3855 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3856 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3857 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3858 u16 fahm_denom_result; 3859 u16 edcca_clm_result; 3860 u8 clm_ratio; 3861 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3862 u8 nhm_tx_ratio; 3863 u8 nhm_cca_ratio; 3864 u8 nhm_idle_ratio; 3865 u8 nhm_ratio; 3866 u16 nhm_result_sum; 3867 u8 nhm_pwr; 3868 u8 ifs_clm_tx_ratio; 3869 u8 ifs_clm_edcca_excl_cca_ratio; 3870 u8 ifs_clm_cck_fa_ratio; 3871 u8 ifs_clm_ofdm_fa_ratio; 3872 u8 ifs_clm_cck_cca_excl_fa_ratio; 3873 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3874 u16 ifs_clm_cck_fa_permil; 3875 u16 ifs_clm_ofdm_fa_permil; 3876 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3877 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3878 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3879 u16 fahm_result_sum; 3880 u8 fahm_ratio; 3881 u8 fahm_denom_ratio; 3882 u8 fahm_pwr; 3883 u8 edcca_clm_ratio; 3884 }; 3885 3886 enum rtw89_ser_rcvy_step { 3887 RTW89_SER_DRV_STOP_TX, 3888 RTW89_SER_DRV_STOP_RX, 3889 RTW89_SER_DRV_STOP_RUN, 3890 RTW89_SER_HAL_STOP_DMA, 3891 RTW89_NUM_OF_SER_FLAGS 3892 }; 3893 3894 struct rtw89_ser { 3895 u8 state; 3896 u8 alarm_event; 3897 3898 struct work_struct ser_hdl_work; 3899 struct delayed_work ser_alarm_work; 3900 const struct state_ent *st_tbl; 3901 const struct event_ent *ev_tbl; 3902 struct list_head msg_q; 3903 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3904 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3905 }; 3906 3907 enum rtw89_mac_ax_ps_mode { 3908 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3909 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3910 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3911 RTW89_MAC_AX_PS_MODE_MAX = 3, 3912 }; 3913 3914 enum rtw89_last_rpwm_mode { 3915 RTW89_LAST_RPWM_PS = 0x0, 3916 RTW89_LAST_RPWM_ACTIVE = 0x6, 3917 }; 3918 3919 struct rtw89_lps_parm { 3920 u8 macid; 3921 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3922 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3923 }; 3924 3925 struct rtw89_ppdu_sts_info { 3926 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3927 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3928 }; 3929 3930 struct rtw89_early_h2c { 3931 struct list_head list; 3932 u8 *h2c; 3933 u16 h2c_len; 3934 }; 3935 3936 struct rtw89_hw_scan_info { 3937 struct ieee80211_vif *scanning_vif; 3938 struct list_head pkt_list[NUM_NL80211_BANDS]; 3939 struct rtw89_chan op_chan; 3940 u32 last_chan_idx; 3941 }; 3942 3943 enum rtw89_phy_bb_gain_band { 3944 RTW89_BB_GAIN_BAND_2G = 0, 3945 RTW89_BB_GAIN_BAND_5G_L = 1, 3946 RTW89_BB_GAIN_BAND_5G_M = 2, 3947 RTW89_BB_GAIN_BAND_5G_H = 3, 3948 RTW89_BB_GAIN_BAND_6G_L = 4, 3949 RTW89_BB_GAIN_BAND_6G_M = 5, 3950 RTW89_BB_GAIN_BAND_6G_H = 6, 3951 RTW89_BB_GAIN_BAND_6G_UH = 7, 3952 3953 RTW89_BB_GAIN_BAND_NR, 3954 }; 3955 3956 enum rtw89_phy_bb_rxsc_num { 3957 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3958 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3959 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3960 }; 3961 3962 struct rtw89_phy_bb_gain_info { 3963 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3964 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3965 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3966 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3967 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3968 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3969 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3970 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3971 [RTW89_BB_RXSC_NUM_40]; 3972 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3973 [RTW89_BB_RXSC_NUM_80]; 3974 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3975 [RTW89_BB_RXSC_NUM_160]; 3976 }; 3977 3978 struct rtw89_phy_efuse_gain { 3979 bool offset_valid; 3980 bool comp_valid; 3981 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3982 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3983 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3984 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 3985 }; 3986 3987 #define RTW89_MAX_PATTERN_NUM 18 3988 #define RTW89_MAX_PATTERN_MASK_SIZE 4 3989 #define RTW89_MAX_PATTERN_SIZE 128 3990 3991 struct rtw89_wow_cam_info { 3992 bool r_w; 3993 u8 idx; 3994 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 3995 u16 crc; 3996 bool negative_pattern_match; 3997 bool skip_mac_hdr; 3998 bool uc; 3999 bool mc; 4000 bool bc; 4001 bool valid; 4002 }; 4003 4004 struct rtw89_wow_param { 4005 struct ieee80211_vif *wow_vif; 4006 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4007 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4008 u8 pattern_cnt; 4009 }; 4010 4011 struct rtw89_mcc_info { 4012 struct rtw89_wait_info wait; 4013 }; 4014 4015 struct rtw89_dev { 4016 struct ieee80211_hw *hw; 4017 struct device *dev; 4018 const struct ieee80211_ops *ops; 4019 4020 bool dbcc_en; 4021 struct rtw89_hw_scan_info scan_info; 4022 const struct rtw89_chip_info *chip; 4023 const struct rtw89_pci_info *pci_info; 4024 const struct rtw89_rfe_parms *rfe_parms; 4025 struct rtw89_hal hal; 4026 struct rtw89_mcc_info mcc; 4027 struct rtw89_mac_info mac; 4028 struct rtw89_fw_info fw; 4029 struct rtw89_hci_info hci; 4030 struct rtw89_efuse efuse; 4031 struct rtw89_traffic_stats stats; 4032 4033 /* ensures exclusive access from mac80211 callbacks */ 4034 struct mutex mutex; 4035 struct list_head rtwvifs_list; 4036 /* used to protect rf read write */ 4037 struct mutex rf_mutex; 4038 struct workqueue_struct *txq_wq; 4039 struct work_struct txq_work; 4040 struct delayed_work txq_reinvoke_work; 4041 /* used to protect ba_list and forbid_ba_list */ 4042 spinlock_t ba_lock; 4043 /* txqs to setup ba session */ 4044 struct list_head ba_list; 4045 /* txqs to forbid ba session */ 4046 struct list_head forbid_ba_list; 4047 struct work_struct ba_work; 4048 /* used to protect rpwm */ 4049 spinlock_t rpwm_lock; 4050 4051 struct rtw89_cam_info cam_info; 4052 4053 struct sk_buff_head c2h_queue; 4054 struct work_struct c2h_work; 4055 struct work_struct ips_work; 4056 struct work_struct load_firmware_work; 4057 4058 struct list_head early_h2c_list; 4059 4060 struct rtw89_ser ser; 4061 4062 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4063 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4064 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4065 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4066 4067 struct rtw89_phy_stat phystat; 4068 struct rtw89_dack_info dack; 4069 struct rtw89_iqk_info iqk; 4070 struct rtw89_dpk_info dpk; 4071 struct rtw89_rfk_mcc_info rfk_mcc; 4072 struct rtw89_lck_info lck; 4073 struct rtw89_rx_dck_info rx_dck; 4074 bool is_tssi_mode[RF_PATH_MAX]; 4075 bool is_bt_iqk_timeout; 4076 4077 struct rtw89_fem_info fem; 4078 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 4079 struct rtw89_tssi_info tssi; 4080 struct rtw89_power_trim_info pwr_trim; 4081 4082 struct rtw89_cfo_tracking_info cfo_tracking; 4083 struct rtw89_env_monitor_info env_monitor; 4084 struct rtw89_dig_info dig; 4085 struct rtw89_phy_ch_info ch_info; 4086 struct rtw89_phy_bb_gain_info bb_gain; 4087 struct rtw89_phy_efuse_gain efuse_gain; 4088 struct rtw89_phy_ul_tb_info ul_tb_info; 4089 4090 struct delayed_work track_work; 4091 struct delayed_work coex_act1_work; 4092 struct delayed_work coex_bt_devinfo_work; 4093 struct delayed_work coex_rfk_chk_work; 4094 struct delayed_work cfo_track_work; 4095 struct delayed_work forbid_ba_work; 4096 struct delayed_work roc_work; 4097 struct rtw89_ppdu_sts_info ppdu_sts; 4098 u8 total_sta_assoc; 4099 bool scanning; 4100 4101 const struct rtw89_regulatory *regd; 4102 struct rtw89_sar_info sar; 4103 4104 struct rtw89_btc btc; 4105 enum rtw89_ps_mode ps_mode; 4106 bool lps_enabled; 4107 4108 struct rtw89_wow_param wow; 4109 4110 /* napi structure */ 4111 struct net_device netdev; 4112 struct napi_struct napi; 4113 int napi_budget_countdown; 4114 4115 /* HCI related data, keep last */ 4116 u8 priv[] __aligned(sizeof(void *)); 4117 }; 4118 4119 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4120 struct rtw89_core_tx_request *tx_req) 4121 { 4122 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4123 } 4124 4125 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4126 { 4127 rtwdev->hci.ops->reset(rtwdev); 4128 } 4129 4130 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4131 { 4132 return rtwdev->hci.ops->start(rtwdev); 4133 } 4134 4135 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4136 { 4137 rtwdev->hci.ops->stop(rtwdev); 4138 } 4139 4140 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4141 { 4142 return rtwdev->hci.ops->deinit(rtwdev); 4143 } 4144 4145 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4146 { 4147 rtwdev->hci.ops->pause(rtwdev, pause); 4148 } 4149 4150 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4151 { 4152 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4153 } 4154 4155 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4156 { 4157 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4158 } 4159 4160 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4161 { 4162 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4163 } 4164 4165 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4166 { 4167 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4168 } 4169 4170 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4171 bool drop) 4172 { 4173 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4174 return; 4175 4176 if (rtwdev->hci.ops->flush_queues) 4177 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4178 } 4179 4180 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4181 { 4182 if (rtwdev->hci.ops->recovery_start) 4183 rtwdev->hci.ops->recovery_start(rtwdev); 4184 } 4185 4186 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4187 { 4188 if (rtwdev->hci.ops->recovery_complete) 4189 rtwdev->hci.ops->recovery_complete(rtwdev); 4190 } 4191 4192 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4193 { 4194 if (rtwdev->hci.ops->enable_intr) 4195 rtwdev->hci.ops->enable_intr(rtwdev); 4196 } 4197 4198 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4199 { 4200 if (rtwdev->hci.ops->disable_intr) 4201 rtwdev->hci.ops->disable_intr(rtwdev); 4202 } 4203 4204 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4205 { 4206 if (rtwdev->hci.ops->ctrl_txdma_ch) 4207 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4208 } 4209 4210 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4211 { 4212 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4213 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4214 } 4215 4216 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4217 { 4218 if (rtwdev->hci.ops->ctrl_trxhci) 4219 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4220 } 4221 4222 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4223 { 4224 int ret = 0; 4225 4226 if (rtwdev->hci.ops->poll_txdma_ch) 4227 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4228 return ret; 4229 } 4230 4231 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4232 { 4233 if (rtwdev->hci.ops->clr_idx_all) 4234 rtwdev->hci.ops->clr_idx_all(rtwdev); 4235 } 4236 4237 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4238 { 4239 int ret = 0; 4240 4241 if (rtwdev->hci.ops->rst_bdram) 4242 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4243 return ret; 4244 } 4245 4246 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4247 { 4248 if (rtwdev->hci.ops->clear) 4249 rtwdev->hci.ops->clear(rtwdev, pdev); 4250 } 4251 4252 static inline 4253 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 4254 { 4255 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 4256 4257 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 4258 } 4259 4260 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4261 { 4262 return rtwdev->hci.ops->read8(rtwdev, addr); 4263 } 4264 4265 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4266 { 4267 return rtwdev->hci.ops->read16(rtwdev, addr); 4268 } 4269 4270 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4271 { 4272 return rtwdev->hci.ops->read32(rtwdev, addr); 4273 } 4274 4275 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4276 { 4277 rtwdev->hci.ops->write8(rtwdev, addr, data); 4278 } 4279 4280 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4281 { 4282 rtwdev->hci.ops->write16(rtwdev, addr, data); 4283 } 4284 4285 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4286 { 4287 rtwdev->hci.ops->write32(rtwdev, addr, data); 4288 } 4289 4290 static inline void 4291 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4292 { 4293 u8 val; 4294 4295 val = rtw89_read8(rtwdev, addr); 4296 rtw89_write8(rtwdev, addr, val | bit); 4297 } 4298 4299 static inline void 4300 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4301 { 4302 u16 val; 4303 4304 val = rtw89_read16(rtwdev, addr); 4305 rtw89_write16(rtwdev, addr, val | bit); 4306 } 4307 4308 static inline void 4309 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4310 { 4311 u32 val; 4312 4313 val = rtw89_read32(rtwdev, addr); 4314 rtw89_write32(rtwdev, addr, val | bit); 4315 } 4316 4317 static inline void 4318 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4319 { 4320 u8 val; 4321 4322 val = rtw89_read8(rtwdev, addr); 4323 rtw89_write8(rtwdev, addr, val & ~bit); 4324 } 4325 4326 static inline void 4327 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4328 { 4329 u16 val; 4330 4331 val = rtw89_read16(rtwdev, addr); 4332 rtw89_write16(rtwdev, addr, val & ~bit); 4333 } 4334 4335 static inline void 4336 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4337 { 4338 u32 val; 4339 4340 val = rtw89_read32(rtwdev, addr); 4341 rtw89_write32(rtwdev, addr, val & ~bit); 4342 } 4343 4344 static inline u32 4345 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4346 { 4347 u32 shift = __ffs(mask); 4348 u32 orig; 4349 u32 ret; 4350 4351 orig = rtw89_read32(rtwdev, addr); 4352 ret = (orig & mask) >> shift; 4353 4354 return ret; 4355 } 4356 4357 static inline u16 4358 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4359 { 4360 u32 shift = __ffs(mask); 4361 u32 orig; 4362 u32 ret; 4363 4364 orig = rtw89_read16(rtwdev, addr); 4365 ret = (orig & mask) >> shift; 4366 4367 return ret; 4368 } 4369 4370 static inline u8 4371 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4372 { 4373 u32 shift = __ffs(mask); 4374 u32 orig; 4375 u32 ret; 4376 4377 orig = rtw89_read8(rtwdev, addr); 4378 ret = (orig & mask) >> shift; 4379 4380 return ret; 4381 } 4382 4383 static inline void 4384 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 4385 { 4386 u32 shift = __ffs(mask); 4387 u32 orig; 4388 u32 set; 4389 4390 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 4391 4392 orig = rtw89_read32(rtwdev, addr); 4393 set = (orig & ~mask) | ((data << shift) & mask); 4394 rtw89_write32(rtwdev, addr, set); 4395 } 4396 4397 static inline void 4398 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 4399 { 4400 u32 shift; 4401 u16 orig, set; 4402 4403 mask &= 0xffff; 4404 shift = __ffs(mask); 4405 4406 orig = rtw89_read16(rtwdev, addr); 4407 set = (orig & ~mask) | ((data << shift) & mask); 4408 rtw89_write16(rtwdev, addr, set); 4409 } 4410 4411 static inline void 4412 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 4413 { 4414 u32 shift; 4415 u8 orig, set; 4416 4417 mask &= 0xff; 4418 shift = __ffs(mask); 4419 4420 orig = rtw89_read8(rtwdev, addr); 4421 set = (orig & ~mask) | ((data << shift) & mask); 4422 rtw89_write8(rtwdev, addr, set); 4423 } 4424 4425 static inline u32 4426 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4427 u32 addr, u32 mask) 4428 { 4429 u32 val; 4430 4431 mutex_lock(&rtwdev->rf_mutex); 4432 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 4433 mutex_unlock(&rtwdev->rf_mutex); 4434 4435 return val; 4436 } 4437 4438 static inline void 4439 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4440 u32 addr, u32 mask, u32 data) 4441 { 4442 mutex_lock(&rtwdev->rf_mutex); 4443 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 4444 mutex_unlock(&rtwdev->rf_mutex); 4445 } 4446 4447 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 4448 { 4449 void *p = rtwtxq; 4450 4451 return container_of(p, struct ieee80211_txq, drv_priv); 4452 } 4453 4454 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 4455 struct ieee80211_txq *txq) 4456 { 4457 struct rtw89_txq *rtwtxq; 4458 4459 if (!txq) 4460 return; 4461 4462 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4463 INIT_LIST_HEAD(&rtwtxq->list); 4464 } 4465 4466 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 4467 { 4468 void *p = rtwvif; 4469 4470 return container_of(p, struct ieee80211_vif, drv_priv); 4471 } 4472 4473 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 4474 { 4475 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 4476 } 4477 4478 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 4479 { 4480 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4481 } 4482 4483 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 4484 { 4485 void *p = rtwsta; 4486 4487 return container_of(p, struct ieee80211_sta, drv_priv); 4488 } 4489 4490 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 4491 { 4492 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 4493 } 4494 4495 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 4496 { 4497 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 4498 } 4499 4500 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 4501 { 4502 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 4503 return RATE_INFO_BW_160; 4504 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 4505 return RATE_INFO_BW_80; 4506 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 4507 return RATE_INFO_BW_40; 4508 else 4509 return RATE_INFO_BW_20; 4510 } 4511 4512 static inline 4513 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 4514 { 4515 switch (hw_band) { 4516 default: 4517 case RTW89_BAND_2G: 4518 return NL80211_BAND_2GHZ; 4519 case RTW89_BAND_5G: 4520 return NL80211_BAND_5GHZ; 4521 case RTW89_BAND_6G: 4522 return NL80211_BAND_6GHZ; 4523 } 4524 } 4525 4526 static inline 4527 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 4528 { 4529 switch (nl_band) { 4530 default: 4531 case NL80211_BAND_2GHZ: 4532 return RTW89_BAND_2G; 4533 case NL80211_BAND_5GHZ: 4534 return RTW89_BAND_5G; 4535 case NL80211_BAND_6GHZ: 4536 return RTW89_BAND_6G; 4537 } 4538 } 4539 4540 static inline 4541 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 4542 { 4543 switch (width) { 4544 default: 4545 WARN(1, "Not support bandwidth %d\n", width); 4546 fallthrough; 4547 case NL80211_CHAN_WIDTH_20_NOHT: 4548 case NL80211_CHAN_WIDTH_20: 4549 return RTW89_CHANNEL_WIDTH_20; 4550 case NL80211_CHAN_WIDTH_40: 4551 return RTW89_CHANNEL_WIDTH_40; 4552 case NL80211_CHAN_WIDTH_80: 4553 return RTW89_CHANNEL_WIDTH_80; 4554 case NL80211_CHAN_WIDTH_160: 4555 return RTW89_CHANNEL_WIDTH_160; 4556 } 4557 } 4558 4559 static inline 4560 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 4561 struct rtw89_sta *rtwsta) 4562 { 4563 if (rtwsta) { 4564 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4565 4566 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 4567 return &rtwsta->addr_cam; 4568 } 4569 return &rtwvif->addr_cam; 4570 } 4571 4572 static inline 4573 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 4574 struct rtw89_sta *rtwsta) 4575 { 4576 if (rtwsta) { 4577 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4578 4579 if (sta->tdls) 4580 return &rtwsta->bssid_cam; 4581 } 4582 return &rtwvif->bssid_cam; 4583 } 4584 4585 static inline 4586 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 4587 struct rtw89_channel_help_params *p, 4588 const struct rtw89_chan *chan, 4589 enum rtw89_mac_idx mac_idx, 4590 enum rtw89_phy_idx phy_idx) 4591 { 4592 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 4593 mac_idx, phy_idx); 4594 } 4595 4596 static inline 4597 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 4598 struct rtw89_channel_help_params *p, 4599 const struct rtw89_chan *chan, 4600 enum rtw89_mac_idx mac_idx, 4601 enum rtw89_phy_idx phy_idx) 4602 { 4603 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 4604 mac_idx, phy_idx); 4605 } 4606 4607 static inline 4608 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 4609 enum rtw89_sub_entity_idx idx) 4610 { 4611 struct rtw89_hal *hal = &rtwdev->hal; 4612 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 4613 4614 if (roc_idx == idx) 4615 return &hal->roc_chandef; 4616 4617 return &hal->sub[idx].chandef; 4618 } 4619 4620 static inline 4621 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 4622 enum rtw89_sub_entity_idx idx) 4623 { 4624 struct rtw89_hal *hal = &rtwdev->hal; 4625 4626 return &hal->sub[idx].chan; 4627 } 4628 4629 static inline 4630 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 4631 enum rtw89_sub_entity_idx idx) 4632 { 4633 struct rtw89_hal *hal = &rtwdev->hal; 4634 4635 return &hal->sub[idx].rcd; 4636 } 4637 4638 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 4639 { 4640 const struct rtw89_chip_info *chip = rtwdev->chip; 4641 4642 if (chip->ops->fem_setup) 4643 chip->ops->fem_setup(rtwdev); 4644 } 4645 4646 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 4647 { 4648 const struct rtw89_chip_info *chip = rtwdev->chip; 4649 4650 if (chip->ops->bb_sethw) 4651 chip->ops->bb_sethw(rtwdev); 4652 } 4653 4654 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 4655 { 4656 const struct rtw89_chip_info *chip = rtwdev->chip; 4657 4658 if (chip->ops->rfk_init) 4659 chip->ops->rfk_init(rtwdev); 4660 } 4661 4662 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4663 { 4664 const struct rtw89_chip_info *chip = rtwdev->chip; 4665 4666 if (chip->ops->rfk_channel) 4667 chip->ops->rfk_channel(rtwdev); 4668 } 4669 4670 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4671 enum rtw89_phy_idx phy_idx) 4672 { 4673 const struct rtw89_chip_info *chip = rtwdev->chip; 4674 4675 if (chip->ops->rfk_band_changed) 4676 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4677 } 4678 4679 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4680 { 4681 const struct rtw89_chip_info *chip = rtwdev->chip; 4682 4683 if (chip->ops->rfk_scan) 4684 chip->ops->rfk_scan(rtwdev, start); 4685 } 4686 4687 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4688 { 4689 const struct rtw89_chip_info *chip = rtwdev->chip; 4690 4691 if (chip->ops->rfk_track) 4692 chip->ops->rfk_track(rtwdev); 4693 } 4694 4695 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4696 { 4697 const struct rtw89_chip_info *chip = rtwdev->chip; 4698 4699 if (chip->ops->set_txpwr_ctrl) 4700 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4701 } 4702 4703 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4704 { 4705 const struct rtw89_chip_info *chip = rtwdev->chip; 4706 4707 if (chip->ops->power_trim) 4708 chip->ops->power_trim(rtwdev); 4709 } 4710 4711 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4712 enum rtw89_phy_idx phy_idx) 4713 { 4714 const struct rtw89_chip_info *chip = rtwdev->chip; 4715 4716 if (chip->ops->init_txpwr_unit) 4717 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4718 } 4719 4720 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4721 enum rtw89_rf_path rf_path) 4722 { 4723 const struct rtw89_chip_info *chip = rtwdev->chip; 4724 4725 if (!chip->ops->get_thermal) 4726 return 0x10; 4727 4728 return chip->ops->get_thermal(rtwdev, rf_path); 4729 } 4730 4731 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4732 struct rtw89_rx_phy_ppdu *phy_ppdu, 4733 struct ieee80211_rx_status *status) 4734 { 4735 const struct rtw89_chip_info *chip = rtwdev->chip; 4736 4737 if (chip->ops->query_ppdu) 4738 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4739 } 4740 4741 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4742 bool bt_en) 4743 { 4744 const struct rtw89_chip_info *chip = rtwdev->chip; 4745 4746 if (chip->ops->bb_ctrl_btc_preagc) 4747 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4748 } 4749 4750 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4751 { 4752 const struct rtw89_chip_info *chip = rtwdev->chip; 4753 4754 if (chip->ops->cfg_txrx_path) 4755 chip->ops->cfg_txrx_path(rtwdev); 4756 } 4757 4758 static inline 4759 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4760 struct ieee80211_vif *vif) 4761 { 4762 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4763 const struct rtw89_chip_info *chip = rtwdev->chip; 4764 4765 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4766 return; 4767 4768 if (chip->ops->set_txpwr_ul_tb_offset) 4769 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4770 } 4771 4772 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4773 const struct rtw89_txpwr_table *tbl) 4774 { 4775 tbl->load(rtwdev, tbl); 4776 } 4777 4778 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4779 { 4780 return rtwdev->regd->txpwr_regd[band]; 4781 } 4782 4783 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4784 { 4785 const struct rtw89_chip_info *chip = rtwdev->chip; 4786 4787 if (chip->ops->ctrl_btg) 4788 chip->ops->ctrl_btg(rtwdev, btg); 4789 } 4790 4791 static inline 4792 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4793 struct rtw89_tx_desc_info *desc_info, 4794 void *txdesc) 4795 { 4796 const struct rtw89_chip_info *chip = rtwdev->chip; 4797 4798 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4799 } 4800 4801 static inline 4802 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4803 struct rtw89_tx_desc_info *desc_info, 4804 void *txdesc) 4805 { 4806 const struct rtw89_chip_info *chip = rtwdev->chip; 4807 4808 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4809 } 4810 4811 static inline 4812 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4813 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4814 { 4815 const struct rtw89_chip_info *chip = rtwdev->chip; 4816 4817 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4818 } 4819 4820 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4821 { 4822 const struct rtw89_chip_info *chip = rtwdev->chip; 4823 4824 chip->ops->cfg_ctrl_path(rtwdev, wl); 4825 } 4826 4827 static inline 4828 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4829 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4830 { 4831 const struct rtw89_chip_info *chip = rtwdev->chip; 4832 4833 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4834 } 4835 4836 static inline 4837 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4838 { 4839 const struct rtw89_chip_info *chip = rtwdev->chip; 4840 4841 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4842 } 4843 4844 static inline 4845 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4846 struct rtw89_vif *rtwvif, 4847 struct rtw89_sta *rtwsta) 4848 { 4849 const struct rtw89_chip_info *chip = rtwdev->chip; 4850 4851 if (!chip->ops->h2c_dctl_sec_cam) 4852 return 0; 4853 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4854 } 4855 4856 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4857 { 4858 __le16 fc = hdr->frame_control; 4859 4860 if (ieee80211_has_tods(fc)) 4861 return hdr->addr1; 4862 else if (ieee80211_has_fromds(fc)) 4863 return hdr->addr2; 4864 else 4865 return hdr->addr3; 4866 } 4867 4868 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4869 { 4870 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4871 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4872 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4873 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4874 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4875 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4876 return true; 4877 return false; 4878 } 4879 4880 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4881 enum rtw89_fw_type type) 4882 { 4883 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4884 4885 if (type == RTW89_FW_WOWLAN) 4886 return &fw_info->wowlan; 4887 return &fw_info->normal; 4888 } 4889 4890 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 4891 unsigned int length) 4892 { 4893 struct sk_buff *skb; 4894 4895 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 4896 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 4897 if (!skb) 4898 return NULL; 4899 4900 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 4901 return skb; 4902 } 4903 4904 return dev_alloc_skb(length); 4905 } 4906 4907 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 4908 struct rtw89_tx_skb_data *skb_data, 4909 bool tx_done) 4910 { 4911 struct rtw89_tx_wait_info *wait; 4912 4913 rcu_read_lock(); 4914 4915 wait = rcu_dereference(skb_data->wait); 4916 if (!wait) 4917 goto out; 4918 4919 wait->tx_done = tx_done; 4920 complete(&wait->completion); 4921 4922 out: 4923 rcu_read_unlock(); 4924 } 4925 4926 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4927 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4928 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4929 struct sk_buff *skb, bool fwdl); 4930 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4931 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4932 int qsel, unsigned int timeout); 4933 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4934 struct rtw89_tx_desc_info *desc_info, 4935 void *txdesc); 4936 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4937 struct rtw89_tx_desc_info *desc_info, 4938 void *txdesc); 4939 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4940 struct rtw89_tx_desc_info *desc_info, 4941 void *txdesc); 4942 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4943 struct rtw89_rx_desc_info *desc_info, 4944 struct sk_buff *skb); 4945 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4946 struct rtw89_rx_desc_info *desc_info, 4947 u8 *data, u32 data_offset); 4948 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4949 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4950 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4951 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4952 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4953 struct ieee80211_vif *vif, 4954 struct ieee80211_sta *sta); 4955 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4956 struct ieee80211_vif *vif, 4957 struct ieee80211_sta *sta); 4958 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4959 struct ieee80211_vif *vif, 4960 struct ieee80211_sta *sta); 4961 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4962 struct ieee80211_vif *vif, 4963 struct ieee80211_sta *sta); 4964 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4965 struct ieee80211_vif *vif, 4966 struct ieee80211_sta *sta); 4967 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4968 struct ieee80211_sta *sta, 4969 struct cfg80211_tid_config *tid_config); 4970 int rtw89_core_init(struct rtw89_dev *rtwdev); 4971 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4972 int rtw89_core_register(struct rtw89_dev *rtwdev); 4973 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4974 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4975 u32 bus_data_size, 4976 const struct rtw89_chip_info *chip); 4977 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4978 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4979 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4980 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4981 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4982 struct rtw89_chan *chan); 4983 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4984 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4985 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4986 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4987 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4988 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4989 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4990 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4991 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4992 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4993 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4994 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4995 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4996 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4997 struct rtw89_traffic_stats *stats); 4998 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 4999 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5000 const struct rtw89_completion_data *data); 5001 int rtw89_core_start(struct rtw89_dev *rtwdev); 5002 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5003 void rtw89_core_update_beacon_work(struct work_struct *work); 5004 void rtw89_roc_work(struct work_struct *work); 5005 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5006 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5007 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5008 const u8 *mac_addr, bool hw_scan); 5009 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5010 struct ieee80211_vif *vif, bool hw_scan); 5011 5012 #endif 5013