1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define CFO_TRACK_MAX_USER 64 33 #define MAX_RSSI 110 34 #define RSSI_FACTOR 1 35 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 36 37 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 38 #define RTW89_HTC_VARIANT_HE 3 39 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 40 #define RTW89_HTC_VARIANT_HE_CID_OM 1 41 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 42 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 43 44 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 45 enum htc_om_channel_width { 46 HTC_OM_CHANNEL_WIDTH_20 = 0, 47 HTC_OM_CHANNEL_WIDTH_40 = 1, 48 HTC_OM_CHANNEL_WIDTH_80 = 2, 49 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 50 }; 51 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 52 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 53 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 54 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 55 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 56 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 57 58 #define RTW89_TF_PAD GENMASK(11, 0) 59 #define RTW89_TF_BASIC_USER_INFO_SZ 6 60 61 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 62 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 63 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 64 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 65 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 66 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 67 68 enum rtw89_subband { 69 RTW89_CH_2G = 0, 70 RTW89_CH_5G_BAND_1 = 1, 71 /* RTW89_CH_5G_BAND_2 = 2, unused */ 72 RTW89_CH_5G_BAND_3 = 3, 73 RTW89_CH_5G_BAND_4 = 4, 74 75 RTW89_CH_6G_BAND_IDX0, /* Low */ 76 RTW89_CH_6G_BAND_IDX1, /* Low */ 77 RTW89_CH_6G_BAND_IDX2, /* Mid */ 78 RTW89_CH_6G_BAND_IDX3, /* Mid */ 79 RTW89_CH_6G_BAND_IDX4, /* High */ 80 RTW89_CH_6G_BAND_IDX5, /* High */ 81 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 82 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 83 84 RTW89_SUBBAND_NR, 85 }; 86 87 enum rtw89_gain_offset { 88 RTW89_GAIN_OFFSET_2G_CCK, 89 RTW89_GAIN_OFFSET_2G_OFDM, 90 RTW89_GAIN_OFFSET_5G_LOW, 91 RTW89_GAIN_OFFSET_5G_MID, 92 RTW89_GAIN_OFFSET_5G_HIGH, 93 94 RTW89_GAIN_OFFSET_NR, 95 }; 96 97 enum rtw89_hci_type { 98 RTW89_HCI_TYPE_PCIE, 99 RTW89_HCI_TYPE_USB, 100 RTW89_HCI_TYPE_SDIO, 101 }; 102 103 enum rtw89_core_chip_id { 104 RTL8852A, 105 RTL8852B, 106 RTL8852C, 107 }; 108 109 enum rtw89_cv { 110 CHIP_CAV, 111 CHIP_CBV, 112 CHIP_CCV, 113 CHIP_CDV, 114 CHIP_CEV, 115 CHIP_CFV, 116 CHIP_CV_MAX, 117 CHIP_CV_INVALID = CHIP_CV_MAX, 118 }; 119 120 enum rtw89_core_tx_type { 121 RTW89_CORE_TX_TYPE_DATA, 122 RTW89_CORE_TX_TYPE_MGMT, 123 RTW89_CORE_TX_TYPE_FWCMD, 124 }; 125 126 enum rtw89_core_rx_type { 127 RTW89_CORE_RX_TYPE_WIFI = 0, 128 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 129 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 130 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 131 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 132 RTW89_CORE_RX_TYPE_SS2FW = 5, 133 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 134 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 135 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 136 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 137 RTW89_CORE_RX_TYPE_C2H = 10, 138 RTW89_CORE_RX_TYPE_CSI = 11, 139 RTW89_CORE_RX_TYPE_CQI = 12, 140 RTW89_CORE_RX_TYPE_H2C = 13, 141 RTW89_CORE_RX_TYPE_FWDL = 14, 142 }; 143 144 enum rtw89_txq_flags { 145 RTW89_TXQ_F_AMPDU = 0, 146 RTW89_TXQ_F_BLOCK_BA = 1, 147 }; 148 149 enum rtw89_net_type { 150 RTW89_NET_TYPE_NO_LINK = 0, 151 RTW89_NET_TYPE_AD_HOC = 1, 152 RTW89_NET_TYPE_INFRA = 2, 153 RTW89_NET_TYPE_AP_MODE = 3, 154 }; 155 156 enum rtw89_wifi_role { 157 RTW89_WIFI_ROLE_NONE, 158 RTW89_WIFI_ROLE_STATION, 159 RTW89_WIFI_ROLE_AP, 160 RTW89_WIFI_ROLE_AP_VLAN, 161 RTW89_WIFI_ROLE_ADHOC, 162 RTW89_WIFI_ROLE_ADHOC_MASTER, 163 RTW89_WIFI_ROLE_MESH_POINT, 164 RTW89_WIFI_ROLE_MONITOR, 165 RTW89_WIFI_ROLE_P2P_DEVICE, 166 RTW89_WIFI_ROLE_P2P_CLIENT, 167 RTW89_WIFI_ROLE_P2P_GO, 168 RTW89_WIFI_ROLE_NAN, 169 RTW89_WIFI_ROLE_MLME_MAX 170 }; 171 172 enum rtw89_upd_mode { 173 RTW89_ROLE_CREATE, 174 RTW89_ROLE_REMOVE, 175 RTW89_ROLE_TYPE_CHANGE, 176 RTW89_ROLE_INFO_CHANGE, 177 RTW89_ROLE_CON_DISCONN 178 }; 179 180 enum rtw89_self_role { 181 RTW89_SELF_ROLE_CLIENT, 182 RTW89_SELF_ROLE_AP, 183 RTW89_SELF_ROLE_AP_CLIENT 184 }; 185 186 enum rtw89_msk_sO_el { 187 RTW89_NO_MSK, 188 RTW89_SMA, 189 RTW89_TMA, 190 RTW89_BSSID 191 }; 192 193 enum rtw89_sch_tx_sel { 194 RTW89_SCH_TX_SEL_ALL, 195 RTW89_SCH_TX_SEL_HIQ, 196 RTW89_SCH_TX_SEL_MG0, 197 RTW89_SCH_TX_SEL_MACID, 198 }; 199 200 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 201 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 202 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 203 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 204 */ 205 enum rtw89_add_cam_sec_mode { 206 RTW89_ADDR_CAM_SEC_NONE = 0, 207 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 208 RTW89_ADDR_CAM_SEC_NORMAL = 2, 209 RTW89_ADDR_CAM_SEC_4GROUP = 3, 210 }; 211 212 enum rtw89_sec_key_type { 213 RTW89_SEC_KEY_TYPE_NONE = 0, 214 RTW89_SEC_KEY_TYPE_WEP40 = 1, 215 RTW89_SEC_KEY_TYPE_WEP104 = 2, 216 RTW89_SEC_KEY_TYPE_TKIP = 3, 217 RTW89_SEC_KEY_TYPE_WAPI = 4, 218 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 219 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 220 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 221 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 222 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 223 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 224 }; 225 226 enum rtw89_port { 227 RTW89_PORT_0 = 0, 228 RTW89_PORT_1 = 1, 229 RTW89_PORT_2 = 2, 230 RTW89_PORT_3 = 3, 231 RTW89_PORT_4 = 4, 232 RTW89_PORT_NUM 233 }; 234 235 enum rtw89_band { 236 RTW89_BAND_2G = 0, 237 RTW89_BAND_5G = 1, 238 RTW89_BAND_6G = 2, 239 RTW89_BAND_MAX, 240 }; 241 242 enum rtw89_hw_rate { 243 RTW89_HW_RATE_CCK1 = 0x0, 244 RTW89_HW_RATE_CCK2 = 0x1, 245 RTW89_HW_RATE_CCK5_5 = 0x2, 246 RTW89_HW_RATE_CCK11 = 0x3, 247 RTW89_HW_RATE_OFDM6 = 0x4, 248 RTW89_HW_RATE_OFDM9 = 0x5, 249 RTW89_HW_RATE_OFDM12 = 0x6, 250 RTW89_HW_RATE_OFDM18 = 0x7, 251 RTW89_HW_RATE_OFDM24 = 0x8, 252 RTW89_HW_RATE_OFDM36 = 0x9, 253 RTW89_HW_RATE_OFDM48 = 0xA, 254 RTW89_HW_RATE_OFDM54 = 0xB, 255 RTW89_HW_RATE_MCS0 = 0x80, 256 RTW89_HW_RATE_MCS1 = 0x81, 257 RTW89_HW_RATE_MCS2 = 0x82, 258 RTW89_HW_RATE_MCS3 = 0x83, 259 RTW89_HW_RATE_MCS4 = 0x84, 260 RTW89_HW_RATE_MCS5 = 0x85, 261 RTW89_HW_RATE_MCS6 = 0x86, 262 RTW89_HW_RATE_MCS7 = 0x87, 263 RTW89_HW_RATE_MCS8 = 0x88, 264 RTW89_HW_RATE_MCS9 = 0x89, 265 RTW89_HW_RATE_MCS10 = 0x8A, 266 RTW89_HW_RATE_MCS11 = 0x8B, 267 RTW89_HW_RATE_MCS12 = 0x8C, 268 RTW89_HW_RATE_MCS13 = 0x8D, 269 RTW89_HW_RATE_MCS14 = 0x8E, 270 RTW89_HW_RATE_MCS15 = 0x8F, 271 RTW89_HW_RATE_MCS16 = 0x90, 272 RTW89_HW_RATE_MCS17 = 0x91, 273 RTW89_HW_RATE_MCS18 = 0x92, 274 RTW89_HW_RATE_MCS19 = 0x93, 275 RTW89_HW_RATE_MCS20 = 0x94, 276 RTW89_HW_RATE_MCS21 = 0x95, 277 RTW89_HW_RATE_MCS22 = 0x96, 278 RTW89_HW_RATE_MCS23 = 0x97, 279 RTW89_HW_RATE_MCS24 = 0x98, 280 RTW89_HW_RATE_MCS25 = 0x99, 281 RTW89_HW_RATE_MCS26 = 0x9A, 282 RTW89_HW_RATE_MCS27 = 0x9B, 283 RTW89_HW_RATE_MCS28 = 0x9C, 284 RTW89_HW_RATE_MCS29 = 0x9D, 285 RTW89_HW_RATE_MCS30 = 0x9E, 286 RTW89_HW_RATE_MCS31 = 0x9F, 287 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 288 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 289 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 290 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 291 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 292 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 293 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 294 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 295 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 296 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 297 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 298 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 299 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 300 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 301 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 302 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 303 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 304 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 305 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 306 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 307 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 308 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 309 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 310 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 311 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 312 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 313 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 314 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 315 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 316 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 317 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 318 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 319 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 320 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 321 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 322 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 323 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 324 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 325 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 326 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 327 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 328 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 329 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 330 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 331 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 332 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 333 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 334 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 335 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 336 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 337 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 338 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 339 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 340 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 341 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 342 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 343 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 344 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 345 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 346 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 347 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 348 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 349 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 350 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 351 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 352 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 353 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 354 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 355 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 356 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 357 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 358 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 359 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 360 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 361 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 362 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 363 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 364 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 365 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 366 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 367 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 368 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 369 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 370 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 371 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 372 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 373 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 374 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 375 RTW89_HW_RATE_NR, 376 377 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 378 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 379 }; 380 381 /* 2G channels, 382 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 383 */ 384 #define RTW89_2G_CH_NUM 14 385 386 /* 5G channels, 387 * 36, 38, 40, 42, 44, 46, 48, 50, 388 * 52, 54, 56, 58, 60, 62, 64, 389 * 100, 102, 104, 106, 108, 110, 112, 114, 390 * 116, 118, 120, 122, 124, 126, 128, 130, 391 * 132, 134, 136, 138, 140, 142, 144, 392 * 149, 151, 153, 155, 157, 159, 161, 163, 393 * 165, 167, 169, 171, 173, 175, 177 394 */ 395 #define RTW89_5G_CH_NUM 53 396 397 /* 6G channels, 398 * 1, 3, 5, 7, 9, 11, 13, 15, 399 * 17, 19, 21, 23, 25, 27, 29, 33, 400 * 35, 37, 39, 41, 43, 45, 47, 49, 401 * 51, 53, 55, 57, 59, 61, 65, 67, 402 * 69, 71, 73, 75, 77, 79, 81, 83, 403 * 85, 87, 89, 91, 93, 97, 99, 101, 404 * 103, 105, 107, 109, 111, 113, 115, 117, 405 * 119, 121, 123, 125, 129, 131, 133, 135, 406 * 137, 139, 141, 143, 145, 147, 149, 151, 407 * 153, 155, 157, 161, 163, 165, 167, 169, 408 * 171, 173, 175, 177, 179, 181, 183, 185, 409 * 187, 189, 193, 195, 197, 199, 201, 203, 410 * 205, 207, 209, 211, 213, 215, 217, 219, 411 * 221, 225, 227, 229, 231, 233, 235, 237, 412 * 239, 241, 243, 245, 247, 249, 251, 253, 413 */ 414 #define RTW89_6G_CH_NUM 120 415 416 enum rtw89_rate_section { 417 RTW89_RS_CCK, 418 RTW89_RS_OFDM, 419 RTW89_RS_MCS, /* for HT/VHT/HE */ 420 RTW89_RS_HEDCM, 421 RTW89_RS_OFFSET, 422 RTW89_RS_MAX, 423 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 424 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 425 }; 426 427 enum rtw89_rate_max { 428 RTW89_RATE_CCK_MAX = 4, 429 RTW89_RATE_OFDM_MAX = 8, 430 RTW89_RATE_MCS_MAX = 12, 431 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 432 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 433 }; 434 435 enum rtw89_nss { 436 RTW89_NSS_1 = 0, 437 RTW89_NSS_2 = 1, 438 /* HE DCM only support 1ss and 2ss */ 439 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 440 RTW89_NSS_3 = 2, 441 RTW89_NSS_4 = 3, 442 RTW89_NSS_MAX, 443 }; 444 445 enum rtw89_ntx { 446 RTW89_1TX = 0, 447 RTW89_2TX = 1, 448 RTW89_NTX_NUM, 449 }; 450 451 enum rtw89_beamforming_type { 452 RTW89_NONBF = 0, 453 RTW89_BF = 1, 454 RTW89_BF_NUM, 455 }; 456 457 enum rtw89_regulation_type { 458 RTW89_WW = 0, 459 RTW89_ETSI = 1, 460 RTW89_FCC = 2, 461 RTW89_MKK = 3, 462 RTW89_NA = 4, 463 RTW89_IC = 5, 464 RTW89_KCC = 6, 465 RTW89_ACMA = 7, 466 RTW89_NCC = 8, 467 RTW89_MEXICO = 9, 468 RTW89_CHILE = 10, 469 RTW89_UKRAINE = 11, 470 RTW89_CN = 12, 471 RTW89_QATAR = 13, 472 RTW89_UK = 14, 473 RTW89_REGD_NUM, 474 }; 475 476 struct rtw89_txpwr_byrate { 477 s8 cck[RTW89_RATE_CCK_MAX]; 478 s8 ofdm[RTW89_RATE_OFDM_MAX]; 479 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 480 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 481 s8 offset[RTW89_RATE_OFFSET_MAX]; 482 }; 483 484 enum rtw89_bandwidth_section_num { 485 RTW89_BW20_SEC_NUM = 8, 486 RTW89_BW40_SEC_NUM = 4, 487 RTW89_BW80_SEC_NUM = 2, 488 }; 489 490 struct rtw89_txpwr_limit { 491 s8 cck_20m[RTW89_BF_NUM]; 492 s8 cck_40m[RTW89_BF_NUM]; 493 s8 ofdm[RTW89_BF_NUM]; 494 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 495 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 496 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 497 s8 mcs_160m[RTW89_BF_NUM]; 498 s8 mcs_40m_0p5[RTW89_BF_NUM]; 499 s8 mcs_40m_2p5[RTW89_BF_NUM]; 500 }; 501 502 #define RTW89_RU_SEC_NUM 8 503 504 struct rtw89_txpwr_limit_ru { 505 s8 ru26[RTW89_RU_SEC_NUM]; 506 s8 ru52[RTW89_RU_SEC_NUM]; 507 s8 ru106[RTW89_RU_SEC_NUM]; 508 }; 509 510 struct rtw89_rate_desc { 511 enum rtw89_nss nss; 512 enum rtw89_rate_section rs; 513 u8 idx; 514 }; 515 516 #define PHY_STS_HDR_LEN 8 517 #define RF_PATH_MAX 4 518 #define RTW89_MAX_PPDU_CNT 8 519 struct rtw89_rx_phy_ppdu { 520 u8 *buf; 521 u32 len; 522 u8 rssi_avg; 523 s8 rssi[RF_PATH_MAX]; 524 u8 mac_id; 525 u8 chan_idx; 526 u8 ie; 527 u16 rate; 528 bool to_self; 529 bool valid; 530 }; 531 532 enum rtw89_mac_idx { 533 RTW89_MAC_0 = 0, 534 RTW89_MAC_1 = 1, 535 }; 536 537 enum rtw89_phy_idx { 538 RTW89_PHY_0 = 0, 539 RTW89_PHY_1 = 1, 540 RTW89_PHY_MAX 541 }; 542 543 enum rtw89_rf_path { 544 RF_PATH_A = 0, 545 RF_PATH_B = 1, 546 RF_PATH_C = 2, 547 RF_PATH_D = 3, 548 RF_PATH_AB, 549 RF_PATH_AC, 550 RF_PATH_AD, 551 RF_PATH_BC, 552 RF_PATH_BD, 553 RF_PATH_CD, 554 RF_PATH_ABC, 555 RF_PATH_ABD, 556 RF_PATH_ACD, 557 RF_PATH_BCD, 558 RF_PATH_ABCD, 559 }; 560 561 enum rtw89_rf_path_bit { 562 RF_A = BIT(0), 563 RF_B = BIT(1), 564 RF_C = BIT(2), 565 RF_D = BIT(3), 566 567 RF_AB = (RF_A | RF_B), 568 RF_AC = (RF_A | RF_C), 569 RF_AD = (RF_A | RF_D), 570 RF_BC = (RF_B | RF_C), 571 RF_BD = (RF_B | RF_D), 572 RF_CD = (RF_C | RF_D), 573 574 RF_ABC = (RF_A | RF_B | RF_C), 575 RF_ABD = (RF_A | RF_B | RF_D), 576 RF_ACD = (RF_A | RF_C | RF_D), 577 RF_BCD = (RF_B | RF_C | RF_D), 578 579 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 580 }; 581 582 enum rtw89_bandwidth { 583 RTW89_CHANNEL_WIDTH_20 = 0, 584 RTW89_CHANNEL_WIDTH_40 = 1, 585 RTW89_CHANNEL_WIDTH_80 = 2, 586 RTW89_CHANNEL_WIDTH_160 = 3, 587 RTW89_CHANNEL_WIDTH_80_80 = 4, 588 RTW89_CHANNEL_WIDTH_5 = 5, 589 RTW89_CHANNEL_WIDTH_10 = 6, 590 }; 591 592 enum rtw89_ps_mode { 593 RTW89_PS_MODE_NONE = 0, 594 RTW89_PS_MODE_RFOFF = 1, 595 RTW89_PS_MODE_CLK_GATED = 2, 596 RTW89_PS_MODE_PWR_GATED = 3, 597 }; 598 599 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 600 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 601 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 602 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 603 604 enum rtw89_ru_bandwidth { 605 RTW89_RU26 = 0, 606 RTW89_RU52 = 1, 607 RTW89_RU106 = 2, 608 RTW89_RU_NUM, 609 }; 610 611 enum rtw89_sc_offset { 612 RTW89_SC_DONT_CARE = 0, 613 RTW89_SC_20_UPPER = 1, 614 RTW89_SC_20_LOWER = 2, 615 RTW89_SC_20_UPMOST = 3, 616 RTW89_SC_20_LOWEST = 4, 617 RTW89_SC_20_UP2X = 5, 618 RTW89_SC_20_LOW2X = 6, 619 RTW89_SC_20_UP3X = 7, 620 RTW89_SC_20_LOW3X = 8, 621 RTW89_SC_40_UPPER = 9, 622 RTW89_SC_40_LOWER = 10, 623 }; 624 625 struct rtw89_channel_params { 626 u8 center_chan; 627 u32 center_freq; 628 u8 primary_chan; 629 u8 bandwidth; 630 u8 pri_ch_idx; 631 u8 band_type; 632 u8 subband_type; 633 }; 634 635 struct rtw89_channel_help_params { 636 u32 tx_en; 637 }; 638 639 struct rtw89_port_reg { 640 u32 port_cfg; 641 u32 tbtt_prohib; 642 u32 bcn_area; 643 u32 bcn_early; 644 u32 tbtt_early; 645 u32 tbtt_agg; 646 u32 bcn_space; 647 u32 bcn_forcetx; 648 u32 bcn_err_cnt; 649 u32 bcn_err_flag; 650 u32 dtim_ctrl; 651 u32 tbtt_shift; 652 u32 bcn_cnt_tmr; 653 u32 tsftr_l; 654 u32 tsftr_h; 655 }; 656 657 struct rtw89_txwd_body { 658 __le32 dword0; 659 __le32 dword1; 660 __le32 dword2; 661 __le32 dword3; 662 __le32 dword4; 663 __le32 dword5; 664 } __packed; 665 666 struct rtw89_txwd_body_v1 { 667 __le32 dword0; 668 __le32 dword1; 669 __le32 dword2; 670 __le32 dword3; 671 __le32 dword4; 672 __le32 dword5; 673 __le32 dword6; 674 __le32 dword7; 675 } __packed; 676 677 struct rtw89_txwd_info { 678 __le32 dword0; 679 __le32 dword1; 680 __le32 dword2; 681 __le32 dword3; 682 __le32 dword4; 683 __le32 dword5; 684 } __packed; 685 686 struct rtw89_rx_desc_info { 687 u16 pkt_size; 688 u8 pkt_type; 689 u8 drv_info_size; 690 u8 shift; 691 u8 wl_hd_iv_len; 692 bool long_rxdesc; 693 bool bb_sel; 694 bool mac_info_valid; 695 u16 data_rate; 696 u8 gi_ltf; 697 u8 bw; 698 u32 free_run_cnt; 699 u8 user_id; 700 bool sr_en; 701 u8 ppdu_cnt; 702 u8 ppdu_type; 703 bool icv_err; 704 bool crc32_err; 705 bool hw_dec; 706 bool sw_dec; 707 bool addr1_match; 708 u8 frag; 709 u16 seq; 710 u8 frame_type; 711 u8 rx_pl_id; 712 bool addr_cam_valid; 713 u8 addr_cam_id; 714 u8 sec_cam_id; 715 u8 mac_id; 716 u16 offset; 717 bool ready; 718 }; 719 720 struct rtw89_rxdesc_short { 721 __le32 dword0; 722 __le32 dword1; 723 __le32 dword2; 724 __le32 dword3; 725 } __packed; 726 727 struct rtw89_rxdesc_long { 728 __le32 dword0; 729 __le32 dword1; 730 __le32 dword2; 731 __le32 dword3; 732 __le32 dword4; 733 __le32 dword5; 734 __le32 dword6; 735 __le32 dword7; 736 } __packed; 737 738 struct rtw89_tx_desc_info { 739 u16 pkt_size; 740 u8 wp_offset; 741 u8 mac_id; 742 u8 qsel; 743 u8 ch_dma; 744 u8 hdr_llc_len; 745 bool is_bmc; 746 bool en_wd_info; 747 bool wd_page; 748 bool use_rate; 749 bool dis_data_fb; 750 bool tid_indicate; 751 bool agg_en; 752 bool bk; 753 u8 ampdu_density; 754 u8 ampdu_num; 755 bool sec_en; 756 u8 addr_info_nr; 757 u8 sec_keyid; 758 u8 sec_type; 759 u8 sec_cam_idx; 760 u8 sec_seq[6]; 761 u16 data_rate; 762 u16 data_retry_lowest_rate; 763 bool fw_dl; 764 u16 seq; 765 bool a_ctrl_bsr; 766 u8 hw_ssn_sel; 767 #define RTW89_MGMT_HW_SSN_SEL 1 768 u8 hw_seq_mode; 769 #define RTW89_MGMT_HW_SEQ_MODE 1 770 bool hiq; 771 u8 port; 772 }; 773 774 struct rtw89_core_tx_request { 775 enum rtw89_core_tx_type tx_type; 776 777 struct sk_buff *skb; 778 struct ieee80211_vif *vif; 779 struct ieee80211_sta *sta; 780 struct rtw89_tx_desc_info desc_info; 781 }; 782 783 struct rtw89_txq { 784 struct list_head list; 785 unsigned long flags; 786 int wait_cnt; 787 }; 788 789 struct rtw89_mac_ax_gnt { 790 u8 gnt_bt_sw_en; 791 u8 gnt_bt; 792 u8 gnt_wl_sw_en; 793 u8 gnt_wl; 794 }; 795 796 #define RTW89_MAC_AX_COEX_GNT_NR 2 797 struct rtw89_mac_ax_coex_gnt { 798 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 799 }; 800 801 enum rtw89_btc_ncnt { 802 BTC_NCNT_POWER_ON = 0x0, 803 BTC_NCNT_POWER_OFF, 804 BTC_NCNT_INIT_COEX, 805 BTC_NCNT_SCAN_START, 806 BTC_NCNT_SCAN_FINISH, 807 BTC_NCNT_SPECIAL_PACKET, 808 BTC_NCNT_SWITCH_BAND, 809 BTC_NCNT_RFK_TIMEOUT, 810 BTC_NCNT_SHOW_COEX_INFO, 811 BTC_NCNT_ROLE_INFO, 812 BTC_NCNT_CONTROL, 813 BTC_NCNT_RADIO_STATE, 814 BTC_NCNT_CUSTOMERIZE, 815 BTC_NCNT_WL_RFK, 816 BTC_NCNT_WL_STA, 817 BTC_NCNT_FWINFO, 818 BTC_NCNT_TIMER, 819 BTC_NCNT_NUM 820 }; 821 822 enum rtw89_btc_btinfo { 823 BTC_BTINFO_L0 = 0, 824 BTC_BTINFO_L1, 825 BTC_BTINFO_L2, 826 BTC_BTINFO_L3, 827 BTC_BTINFO_H0, 828 BTC_BTINFO_H1, 829 BTC_BTINFO_H2, 830 BTC_BTINFO_H3, 831 BTC_BTINFO_MAX 832 }; 833 834 enum rtw89_btc_dcnt { 835 BTC_DCNT_RUN = 0x0, 836 BTC_DCNT_CX_RUNINFO, 837 BTC_DCNT_RPT, 838 BTC_DCNT_RPT_FREEZE, 839 BTC_DCNT_CYCLE, 840 BTC_DCNT_CYCLE_FREEZE, 841 BTC_DCNT_W1, 842 BTC_DCNT_W1_FREEZE, 843 BTC_DCNT_B1, 844 BTC_DCNT_B1_FREEZE, 845 BTC_DCNT_TDMA_NONSYNC, 846 BTC_DCNT_SLOT_NONSYNC, 847 BTC_DCNT_BTCNT_FREEZE, 848 BTC_DCNT_WL_SLOT_DRIFT, 849 BTC_DCNT_WL_STA_LAST, 850 BTC_DCNT_NUM, 851 }; 852 853 enum rtw89_btc_wl_state_cnt { 854 BTC_WCNT_SCANAP = 0x0, 855 BTC_WCNT_DHCP, 856 BTC_WCNT_EAPOL, 857 BTC_WCNT_ARP, 858 BTC_WCNT_SCBDUPDATE, 859 BTC_WCNT_RFK_REQ, 860 BTC_WCNT_RFK_GO, 861 BTC_WCNT_RFK_REJECT, 862 BTC_WCNT_RFK_TIMEOUT, 863 BTC_WCNT_CH_UPDATE, 864 BTC_WCNT_NUM 865 }; 866 867 enum rtw89_btc_bt_state_cnt { 868 BTC_BCNT_RETRY = 0x0, 869 BTC_BCNT_REINIT, 870 BTC_BCNT_REENABLE, 871 BTC_BCNT_SCBDREAD, 872 BTC_BCNT_RELINK, 873 BTC_BCNT_IGNOWL, 874 BTC_BCNT_INQPAG, 875 BTC_BCNT_INQ, 876 BTC_BCNT_PAGE, 877 BTC_BCNT_ROLESW, 878 BTC_BCNT_AFH, 879 BTC_BCNT_INFOUPDATE, 880 BTC_BCNT_INFOSAME, 881 BTC_BCNT_SCBDUPDATE, 882 BTC_BCNT_HIPRI_TX, 883 BTC_BCNT_HIPRI_RX, 884 BTC_BCNT_LOPRI_TX, 885 BTC_BCNT_LOPRI_RX, 886 BTC_BCNT_POLUT, 887 BTC_BCNT_RATECHG, 888 BTC_BCNT_NUM 889 }; 890 891 enum rtw89_btc_bt_profile { 892 BTC_BT_NOPROFILE = 0, 893 BTC_BT_HFP = BIT(0), 894 BTC_BT_HID = BIT(1), 895 BTC_BT_A2DP = BIT(2), 896 BTC_BT_PAN = BIT(3), 897 BTC_PROFILE_MAX = 4, 898 }; 899 900 struct rtw89_btc_ant_info { 901 u8 type; /* shared, dedicated */ 902 u8 num; 903 u8 isolation; 904 905 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 906 u8 diversity: 1; 907 }; 908 909 enum rtw89_tfc_dir { 910 RTW89_TFC_UL, 911 RTW89_TFC_DL, 912 }; 913 914 struct rtw89_btc_wl_smap { 915 u32 busy: 1; 916 u32 scan: 1; 917 u32 connecting: 1; 918 u32 roaming: 1; 919 u32 _4way: 1; 920 u32 rf_off: 1; 921 u32 lps: 1; 922 u32 ips: 1; 923 u32 init_ok: 1; 924 u32 traffic_dir : 2; 925 u32 rf_off_pre: 1; 926 u32 lps_pre: 1; 927 }; 928 929 enum rtw89_tfc_lv { 930 RTW89_TFC_IDLE, 931 RTW89_TFC_ULTRA_LOW, 932 RTW89_TFC_LOW, 933 RTW89_TFC_MID, 934 RTW89_TFC_HIGH, 935 }; 936 937 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 938 DECLARE_EWMA(tp, 10, 2); 939 940 struct rtw89_traffic_stats { 941 /* units in bytes */ 942 u64 tx_unicast; 943 u64 rx_unicast; 944 u32 tx_avg_len; 945 u32 rx_avg_len; 946 947 /* count for packets */ 948 u64 tx_cnt; 949 u64 rx_cnt; 950 951 /* units in Mbps */ 952 u32 tx_throughput; 953 u32 rx_throughput; 954 u32 tx_throughput_raw; 955 u32 rx_throughput_raw; 956 957 u32 rx_tf_acc; 958 u32 rx_tf_periodic; 959 960 enum rtw89_tfc_lv tx_tfc_lv; 961 enum rtw89_tfc_lv rx_tfc_lv; 962 struct ewma_tp tx_ewma_tp; 963 struct ewma_tp rx_ewma_tp; 964 965 u16 tx_rate; 966 u16 rx_rate; 967 }; 968 969 struct rtw89_btc_statistic { 970 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 971 struct rtw89_traffic_stats traffic; 972 }; 973 974 #define BTC_WL_RSSI_THMAX 4 975 976 struct rtw89_btc_wl_link_info { 977 struct rtw89_btc_statistic stat; 978 enum rtw89_tfc_dir dir; 979 u8 rssi_state[BTC_WL_RSSI_THMAX]; 980 u8 mac_addr[ETH_ALEN]; 981 u8 busy; 982 u8 ch; 983 u8 bw; 984 u8 band; 985 u8 role; 986 u8 pid; 987 u8 phy; 988 u8 dtim_period; 989 u8 mode; 990 991 u8 mac_id; 992 u8 tx_retry; 993 994 u32 bcn_period; 995 u32 busy_t; 996 u32 tx_time; 997 u32 client_cnt; 998 u32 rx_rate_drop_cnt; 999 1000 u32 active: 1; 1001 u32 noa: 1; 1002 u32 client_ps: 1; 1003 u32 connected: 2; 1004 }; 1005 1006 union rtw89_btc_wl_state_map { 1007 u32 val; 1008 struct rtw89_btc_wl_smap map; 1009 }; 1010 1011 struct rtw89_btc_bt_hfp_desc { 1012 u32 exist: 1; 1013 u32 type: 2; 1014 u32 rsvd: 29; 1015 }; 1016 1017 struct rtw89_btc_bt_hid_desc { 1018 u32 exist: 1; 1019 u32 slot_info: 2; 1020 u32 pair_cnt: 2; 1021 u32 type: 8; 1022 u32 rsvd: 19; 1023 }; 1024 1025 struct rtw89_btc_bt_a2dp_desc { 1026 u8 exist: 1; 1027 u8 exist_last: 1; 1028 u8 play_latency: 1; 1029 u8 type: 3; 1030 u8 active: 1; 1031 u8 sink: 1; 1032 1033 u8 bitpool; 1034 u16 vendor_id; 1035 u32 device_name; 1036 u32 flush_time; 1037 }; 1038 1039 struct rtw89_btc_bt_pan_desc { 1040 u32 exist: 1; 1041 u32 type: 1; 1042 u32 active: 1; 1043 u32 rsvd: 29; 1044 }; 1045 1046 struct rtw89_btc_bt_rfk_info { 1047 u32 run: 1; 1048 u32 req: 1; 1049 u32 timeout: 1; 1050 u32 rsvd: 29; 1051 }; 1052 1053 union rtw89_btc_bt_rfk_info_map { 1054 u32 val; 1055 struct rtw89_btc_bt_rfk_info map; 1056 }; 1057 1058 struct rtw89_btc_bt_ver_info { 1059 u32 fw_coex; /* match with which coex_ver */ 1060 u32 fw; 1061 }; 1062 1063 struct rtw89_btc_bool_sta_chg { 1064 u32 now: 1; 1065 u32 last: 1; 1066 u32 remain: 1; 1067 u32 srvd: 29; 1068 }; 1069 1070 struct rtw89_btc_u8_sta_chg { 1071 u8 now; 1072 u8 last; 1073 u8 remain; 1074 u8 rsvd; 1075 }; 1076 1077 struct rtw89_btc_wl_scan_info { 1078 u8 band[RTW89_PHY_MAX]; 1079 u8 phy_map; 1080 u8 rsvd; 1081 }; 1082 1083 struct rtw89_btc_wl_dbcc_info { 1084 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1085 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1086 u8 real_band[RTW89_PHY_MAX]; 1087 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1088 }; 1089 1090 struct rtw89_btc_wl_active_role { 1091 u8 connected: 1; 1092 u8 pid: 3; 1093 u8 phy: 1; 1094 u8 noa: 1; 1095 u8 band: 2; 1096 1097 u8 client_ps: 1; 1098 u8 bw: 7; 1099 1100 u8 role; 1101 u8 ch; 1102 1103 u16 tx_lvl; 1104 u16 rx_lvl; 1105 u16 tx_rate; 1106 u16 rx_rate; 1107 }; 1108 1109 struct rtw89_btc_wl_role_info_bpos { 1110 u16 none: 1; 1111 u16 station: 1; 1112 u16 ap: 1; 1113 u16 vap: 1; 1114 u16 adhoc: 1; 1115 u16 adhoc_master: 1; 1116 u16 mesh: 1; 1117 u16 moniter: 1; 1118 u16 p2p_device: 1; 1119 u16 p2p_gc: 1; 1120 u16 p2p_go: 1; 1121 u16 nan: 1; 1122 }; 1123 1124 union rtw89_btc_wl_role_info_map { 1125 u16 val; 1126 struct rtw89_btc_wl_role_info_bpos role; 1127 }; 1128 1129 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1130 u8 connect_cnt; 1131 u8 link_mode; 1132 union rtw89_btc_wl_role_info_map role_map; 1133 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1134 }; 1135 1136 struct rtw89_btc_wl_ver_info { 1137 u32 fw_coex; /* match with which coex_ver */ 1138 u32 fw; 1139 u32 mac; 1140 u32 bb; 1141 u32 rf; 1142 }; 1143 1144 struct rtw89_btc_wl_afh_info { 1145 u8 en; 1146 u8 ch; 1147 u8 bw; 1148 u8 rsvd; 1149 } __packed; 1150 1151 struct rtw89_btc_wl_rfk_info { 1152 u32 state: 2; 1153 u32 path_map: 4; 1154 u32 phy_map: 2; 1155 u32 band: 2; 1156 u32 type: 8; 1157 u32 rsvd: 14; 1158 }; 1159 1160 struct rtw89_btc_bt_smap { 1161 u32 connect: 1; 1162 u32 ble_connect: 1; 1163 u32 acl_busy: 1; 1164 u32 sco_busy: 1; 1165 u32 mesh_busy: 1; 1166 u32 inq_pag: 1; 1167 }; 1168 1169 union rtw89_btc_bt_state_map { 1170 u32 val; 1171 struct rtw89_btc_bt_smap map; 1172 }; 1173 1174 #define BTC_BT_RSSI_THMAX 4 1175 #define BTC_BT_AFH_GROUP 12 1176 1177 struct rtw89_btc_bt_link_info { 1178 struct rtw89_btc_u8_sta_chg profile_cnt; 1179 struct rtw89_btc_bool_sta_chg multi_link; 1180 struct rtw89_btc_bool_sta_chg relink; 1181 struct rtw89_btc_bt_hfp_desc hfp_desc; 1182 struct rtw89_btc_bt_hid_desc hid_desc; 1183 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1184 struct rtw89_btc_bt_pan_desc pan_desc; 1185 union rtw89_btc_bt_state_map status; 1186 1187 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1188 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1189 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1190 u8 afh_map[BTC_BT_AFH_GROUP]; 1191 1192 u32 role_sw: 1; 1193 u32 slave_role: 1; 1194 u32 afh_update: 1; 1195 u32 cqddr: 1; 1196 u32 rssi: 8; 1197 u32 tx_3m: 1; 1198 u32 rsvd: 19; 1199 }; 1200 1201 struct rtw89_btc_3rdcx_info { 1202 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1203 u8 hw_coex; 1204 u16 rsvd; 1205 }; 1206 1207 struct rtw89_btc_dm_emap { 1208 u32 init: 1; 1209 u32 pta_owner: 1; 1210 u32 wl_rfk_timeout: 1; 1211 u32 bt_rfk_timeout: 1; 1212 1213 u32 wl_fw_hang: 1; 1214 u32 offload_mismatch: 1; 1215 u32 cycle_hang: 1; 1216 u32 w1_hang: 1; 1217 1218 u32 b1_hang: 1; 1219 u32 tdma_no_sync: 1; 1220 u32 wl_slot_drift: 1; 1221 }; 1222 1223 union rtw89_btc_dm_error_map { 1224 u32 val; 1225 struct rtw89_btc_dm_emap map; 1226 }; 1227 1228 struct rtw89_btc_rf_para { 1229 u32 tx_pwr_freerun; 1230 u32 rx_gain_freerun; 1231 u32 tx_pwr_perpkt; 1232 u32 rx_gain_perpkt; 1233 }; 1234 1235 struct rtw89_btc_wl_info { 1236 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1237 struct rtw89_btc_wl_rfk_info rfk_info; 1238 struct rtw89_btc_wl_ver_info ver_info; 1239 struct rtw89_btc_wl_afh_info afh_info; 1240 struct rtw89_btc_wl_role_info role_info; 1241 struct rtw89_btc_wl_scan_info scan_info; 1242 struct rtw89_btc_wl_dbcc_info dbcc_info; 1243 struct rtw89_btc_rf_para rf_para; 1244 union rtw89_btc_wl_state_map status; 1245 1246 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1247 u8 rssi_level; 1248 1249 u32 scbd; 1250 }; 1251 1252 struct rtw89_btc_module { 1253 struct rtw89_btc_ant_info ant; 1254 u8 rfe_type; 1255 u8 cv; 1256 1257 u8 bt_solo: 1; 1258 u8 bt_pos: 1; 1259 u8 switch_type: 1; 1260 1261 u8 rsvd; 1262 }; 1263 1264 #define RTW89_BTC_DM_MAXSTEP 30 1265 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1266 1267 struct rtw89_btc_dm_step { 1268 u16 step[RTW89_BTC_DM_MAXSTEP]; 1269 u8 step_pos; 1270 bool step_ov; 1271 }; 1272 1273 struct rtw89_btc_init_info { 1274 struct rtw89_btc_module module; 1275 u8 wl_guard_ch; 1276 1277 u8 wl_only: 1; 1278 u8 wl_init_ok: 1; 1279 u8 dbcc_en: 1; 1280 u8 cx_other: 1; 1281 u8 bt_only: 1; 1282 1283 u16 rsvd; 1284 }; 1285 1286 struct rtw89_btc_wl_tx_limit_para { 1287 u16 enable; 1288 u32 tx_time; /* unit: us */ 1289 u16 tx_retry; 1290 }; 1291 1292 struct rtw89_btc_bt_scan_info { 1293 u16 win; 1294 u16 intvl; 1295 u32 enable: 1; 1296 u32 interlace: 1; 1297 u32 rsvd: 30; 1298 }; 1299 1300 enum rtw89_btc_bt_scan_type { 1301 BTC_SCAN_INQ = 0, 1302 BTC_SCAN_PAGE, 1303 BTC_SCAN_BLE, 1304 BTC_SCAN_INIT, 1305 BTC_SCAN_TV, 1306 BTC_SCAN_ADV, 1307 BTC_SCAN_MAX1, 1308 }; 1309 1310 struct rtw89_btc_bt_info { 1311 struct rtw89_btc_bt_link_info link_info; 1312 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1313 struct rtw89_btc_bt_ver_info ver_info; 1314 struct rtw89_btc_bool_sta_chg enable; 1315 struct rtw89_btc_bool_sta_chg inq_pag; 1316 struct rtw89_btc_rf_para rf_para; 1317 union rtw89_btc_bt_rfk_info_map rfk_info; 1318 1319 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1320 1321 u32 scbd; 1322 u32 feature; 1323 1324 u32 mbx_avl: 1; 1325 u32 whql_test: 1; 1326 u32 igno_wl: 1; 1327 u32 reinit: 1; 1328 u32 ble_scan_en: 1; 1329 u32 btg_type: 1; 1330 u32 inq: 1; 1331 u32 pag: 1; 1332 u32 run_patch_code: 1; 1333 u32 hi_lna_rx: 1; 1334 u32 rsvd: 22; 1335 }; 1336 1337 struct rtw89_btc_cx { 1338 struct rtw89_btc_wl_info wl; 1339 struct rtw89_btc_bt_info bt; 1340 struct rtw89_btc_3rdcx_info other; 1341 u32 state_map; 1342 u32 cnt_bt[BTC_BCNT_NUM]; 1343 u32 cnt_wl[BTC_WCNT_NUM]; 1344 }; 1345 1346 struct rtw89_btc_fbtc_tdma { 1347 u8 type; 1348 u8 rxflctrl; 1349 u8 txpause; 1350 u8 wtgle_n; 1351 u8 leak_n; 1352 u8 ext_ctrl; 1353 u8 rsvd0; 1354 u8 rsvd1; 1355 } __packed; 1356 1357 #define CXMREG_MAX 30 1358 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1359 #define BTCRPT_VER 1 1360 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1361 1362 enum rtw89_btc_bt_rfk_counter { 1363 BTC_BCNT_RFK_REQ = 0, 1364 BTC_BCNT_RFK_GO = 1, 1365 BTC_BCNT_RFK_REJECT = 2, 1366 BTC_BCNT_RFK_FAIL = 3, 1367 BTC_BCNT_RFK_TIMEOUT = 4, 1368 BTC_BCNT_RFK_MAX 1369 }; 1370 1371 struct rtw89_btc_fbtc_rpt_ctrl { 1372 u16 fver; 1373 u16 rpt_cnt; /* tmr counters */ 1374 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1375 u32 wl_fw_cx_offload; 1376 u32 wl_fw_ver; 1377 u32 rpt_enable; 1378 u32 rpt_para; /* ms */ 1379 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1380 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1381 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1382 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1383 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1384 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1385 u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; 1386 u32 c2h_cnt; /* fw send c2h counter */ 1387 u32 h2c_cnt; /* fw recv h2c counter */ 1388 } __packed; 1389 1390 enum rtw89_fbtc_ext_ctrl_type { 1391 CXECTL_OFF = 0x0, /* tdma off */ 1392 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1393 CXECTL_EXT = 0x2, 1394 CXECTL_MAX 1395 }; 1396 1397 union rtw89_btc_fbtc_rxflct { 1398 u8 val; 1399 u8 type: 3; 1400 u8 tgln_n: 5; 1401 }; 1402 1403 enum rtw89_btc_cxst_state { 1404 CXST_OFF = 0x0, 1405 CXST_B2W = 0x1, 1406 CXST_W1 = 0x2, 1407 CXST_W2 = 0x3, 1408 CXST_W2B = 0x4, 1409 CXST_B1 = 0x5, 1410 CXST_B2 = 0x6, 1411 CXST_B3 = 0x7, 1412 CXST_B4 = 0x8, 1413 CXST_LK = 0x9, 1414 CXST_BLK = 0xa, 1415 CXST_E2G = 0xb, 1416 CXST_E5G = 0xc, 1417 CXST_EBT = 0xd, 1418 CXST_ENULL = 0xe, 1419 CXST_WLK = 0xf, 1420 CXST_W1FDD = 0x10, 1421 CXST_B1FDD = 0x11, 1422 CXST_MAX = 0x12, 1423 }; 1424 1425 enum { 1426 CXBCN_ALL = 0x0, 1427 CXBCN_ALL_OK, 1428 CXBCN_BT_SLOT, 1429 CXBCN_BT_OK, 1430 CXBCN_MAX 1431 }; 1432 1433 enum btc_slot_type { 1434 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1435 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1436 CXSTYPE_NUM, 1437 }; 1438 1439 enum { /* TIME */ 1440 CXT_BT = 0x0, 1441 CXT_WL = 0x1, 1442 CXT_MAX 1443 }; 1444 1445 enum { /* TIME-A2DP */ 1446 CXT_FLCTRL_OFF = 0x0, 1447 CXT_FLCTRL_ON = 0x1, 1448 CXT_FLCTRL_MAX 1449 }; 1450 1451 enum { /* STEP TYPE */ 1452 CXSTEP_NONE = 0x0, 1453 CXSTEP_EVNT = 0x1, 1454 CXSTEP_SLOT = 0x2, 1455 CXSTEP_MAX, 1456 }; 1457 1458 #define FCXGPIODBG_VER 1 1459 #define BTC_DBG_MAX1 32 1460 struct rtw89_btc_fbtc_gpio_dbg { 1461 u8 fver; 1462 u8 rsvd; 1463 u16 rsvd2; 1464 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1465 u32 pre_state; /* the debug signal is 1 or 0 */ 1466 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1467 } __packed; 1468 1469 #define FCXMREG_VER 1 1470 struct rtw89_btc_fbtc_mreg_val { 1471 u8 fver; 1472 u8 reg_num; 1473 __le16 rsvd; 1474 __le32 mreg_val[CXMREG_MAX]; 1475 } __packed; 1476 1477 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1478 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1479 .offset = cpu_to_le32(__offset), } 1480 1481 struct rtw89_btc_fbtc_mreg { 1482 __le16 type; 1483 __le16 bytes; 1484 __le32 offset; 1485 } __packed; 1486 1487 struct rtw89_btc_fbtc_slot { 1488 __le16 dur; 1489 __le32 cxtbl; 1490 __le16 cxtype; 1491 } __packed; 1492 1493 #define FCXSLOTS_VER 1 1494 struct rtw89_btc_fbtc_slots { 1495 u8 fver; 1496 u8 tbl_num; 1497 __le16 rsvd; 1498 __le32 update_map; 1499 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1500 } __packed; 1501 1502 #define FCXSTEP_VER 2 1503 struct rtw89_btc_fbtc_step { 1504 u8 type; 1505 u8 val; 1506 __le16 difft; 1507 } __packed; 1508 1509 struct rtw89_btc_fbtc_steps { 1510 u8 fver; 1511 u8 rsvd; 1512 __le16 cnt; 1513 __le16 pos_old; 1514 __le16 pos_new; 1515 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1516 } __packed; 1517 1518 #define FCXCYSTA_VER 2 1519 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1520 u8 fver; 1521 u8 rsvd; 1522 __le16 cycles; /* total cycle number */ 1523 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1524 __le16 a2dpept; /* a2dp empty cnt */ 1525 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1526 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1527 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1528 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1529 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1530 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1531 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1532 __le16 tmax_a2dpept; /* max a2dp empty time */ 1533 __le16 tavg_lk; /* avg leak-slot time */ 1534 __le16 tmax_lk; /* max leak-slot time */ 1535 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1536 __le32 bcn_cnt[CXBCN_MAX]; 1537 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1538 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1539 __le32 skip_cnt; 1540 __le32 exception; 1541 __le32 except_cnt; 1542 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1543 } __packed; 1544 1545 #define FCXNULLSTA_VER 1 1546 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1547 u8 fver; 1548 u8 rsvd; 1549 __le16 rsvd2; 1550 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1551 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1552 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1553 } __packed; 1554 1555 #define FCX_BTVER_VER 1 1556 struct rtw89_btc_fbtc_btver { 1557 u8 fver; 1558 u8 rsvd; 1559 __le16 rsvd2; 1560 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1561 __le32 fw_ver; 1562 __le32 feature; 1563 } __packed; 1564 1565 #define FCX_BTSCAN_VER 1 1566 struct rtw89_btc_fbtc_btscan { 1567 u8 fver; 1568 u8 rsvd; 1569 __le16 rsvd2; 1570 u8 scan[6]; 1571 } __packed; 1572 1573 #define FCX_BTAFH_VER 1 1574 struct rtw89_btc_fbtc_btafh { 1575 u8 fver; 1576 u8 rsvd; 1577 __le16 rsvd2; 1578 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1579 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1580 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1581 } __packed; 1582 1583 #define FCX_BTDEVINFO_VER 1 1584 struct rtw89_btc_fbtc_btdevinfo { 1585 u8 fver; 1586 u8 rsvd; 1587 __le16 vendor_id; 1588 __le32 dev_name; /* only 24 bits valid */ 1589 __le32 flush_time; 1590 } __packed; 1591 1592 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1593 struct rtw89_btc_rf_trx_para { 1594 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1595 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1596 u8 bt_tx_power; /* decrease Tx power (dB) */ 1597 u8 bt_rx_gain; /* LNA constrain level */ 1598 }; 1599 1600 struct rtw89_btc_dm { 1601 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1602 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1603 struct rtw89_btc_fbtc_tdma tdma; 1604 struct rtw89_btc_fbtc_tdma tdma_now; 1605 struct rtw89_mac_ax_coex_gnt gnt; 1606 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1607 struct rtw89_btc_rf_trx_para rf_trx_para; 1608 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1609 struct rtw89_btc_dm_step dm_step; 1610 union rtw89_btc_dm_error_map error; 1611 u32 cnt_dm[BTC_DCNT_NUM]; 1612 u32 cnt_notify[BTC_NCNT_NUM]; 1613 1614 u32 update_slot_map; 1615 u32 set_ant_path; 1616 1617 u32 wl_only: 1; 1618 u32 wl_fw_cx_offload: 1; 1619 u32 freerun: 1; 1620 u32 wl_ps_ctrl: 2; 1621 u32 wl_mimo_ps: 1; 1622 u32 leak_ap: 1; 1623 u32 noisy_level: 3; 1624 u32 coex_info_map: 8; 1625 u32 bt_only: 1; 1626 u32 wl_btg_rx: 1; 1627 u32 trx_para_level: 8; 1628 u32 wl_stb_chg: 1; 1629 u32 rsvd: 3; 1630 1631 u16 slot_dur[CXST_MAX]; 1632 1633 u8 run_reason; 1634 u8 run_action; 1635 }; 1636 1637 struct rtw89_btc_ctrl { 1638 u32 manual: 1; 1639 u32 igno_bt: 1; 1640 u32 always_freerun: 1; 1641 u32 trace_step: 16; 1642 u32 rsvd: 12; 1643 }; 1644 1645 struct rtw89_btc_dbg { 1646 /* cmd "rb" */ 1647 bool rb_done; 1648 u32 rb_val; 1649 }; 1650 1651 #define FCXTDMA_VER 1 1652 1653 enum rtw89_btc_btf_fw_event { 1654 BTF_EVNT_RPT = 0, 1655 BTF_EVNT_BT_INFO = 1, 1656 BTF_EVNT_BT_SCBD = 2, 1657 BTF_EVNT_BT_REG = 3, 1658 BTF_EVNT_CX_RUNINFO = 4, 1659 BTF_EVNT_BT_PSD = 5, 1660 BTF_EVNT_BUF_OVERFLOW, 1661 BTF_EVNT_C2H_LOOPBACK, 1662 BTF_EVNT_MAX, 1663 }; 1664 1665 enum btf_fw_event_report { 1666 BTC_RPT_TYPE_CTRL = 0x0, 1667 BTC_RPT_TYPE_TDMA, 1668 BTC_RPT_TYPE_SLOT, 1669 BTC_RPT_TYPE_CYSTA, 1670 BTC_RPT_TYPE_STEP, 1671 BTC_RPT_TYPE_NULLSTA, 1672 BTC_RPT_TYPE_MREG, 1673 BTC_RPT_TYPE_GPIO_DBG, 1674 BTC_RPT_TYPE_BT_VER, 1675 BTC_RPT_TYPE_BT_SCAN, 1676 BTC_RPT_TYPE_BT_AFH, 1677 BTC_RPT_TYPE_BT_DEVICE, 1678 BTC_RPT_TYPE_TEST, 1679 BTC_RPT_TYPE_MAX = 31 1680 }; 1681 1682 enum rtw_btc_btf_reg_type { 1683 REG_MAC = 0x0, 1684 REG_BB = 0x1, 1685 REG_RF = 0x2, 1686 REG_BT_RF = 0x3, 1687 REG_BT_MODEM = 0x4, 1688 REG_BT_BLUEWIZE = 0x5, 1689 REG_BT_VENDOR = 0x6, 1690 REG_BT_LE = 0x7, 1691 REG_MAX_TYPE, 1692 }; 1693 1694 struct rtw89_btc_rpt_cmn_info { 1695 u32 rx_cnt; 1696 u32 rx_len; 1697 u32 req_len; /* expected rsp len */ 1698 u8 req_fver; /* expected rsp fver */ 1699 u8 rsp_fver; /* fver from fw */ 1700 u8 valid; 1701 } __packed; 1702 1703 struct rtw89_btc_report_ctrl_state { 1704 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1705 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */ 1706 }; 1707 1708 struct rtw89_btc_rpt_fbtc_tdma { 1709 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1710 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1711 }; 1712 1713 struct rtw89_btc_rpt_fbtc_slots { 1714 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1715 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1716 }; 1717 1718 struct rtw89_btc_rpt_fbtc_cysta { 1719 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1720 struct rtw89_btc_fbtc_cysta finfo; /* info from fw */ 1721 }; 1722 1723 struct rtw89_btc_rpt_fbtc_step { 1724 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1725 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1726 }; 1727 1728 struct rtw89_btc_rpt_fbtc_nullsta { 1729 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1730 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1731 }; 1732 1733 struct rtw89_btc_rpt_fbtc_mreg { 1734 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1735 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1736 }; 1737 1738 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1739 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1740 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1741 }; 1742 1743 struct rtw89_btc_rpt_fbtc_btver { 1744 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1745 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1746 }; 1747 1748 struct rtw89_btc_rpt_fbtc_btscan { 1749 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1750 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1751 }; 1752 1753 struct rtw89_btc_rpt_fbtc_btafh { 1754 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1755 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1756 }; 1757 1758 struct rtw89_btc_rpt_fbtc_btdev { 1759 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1760 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1761 }; 1762 1763 enum rtw89_btc_btfre_type { 1764 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1765 BTFRE_UNDEF_TYPE, 1766 BTFRE_EXCEPTION, 1767 BTFRE_MAX, 1768 }; 1769 1770 struct rtw89_btc_btf_fwinfo { 1771 u32 cnt_c2h; 1772 u32 cnt_h2c; 1773 u32 cnt_h2c_fail; 1774 u32 event[BTF_EVNT_MAX]; 1775 1776 u32 err[BTFRE_MAX]; 1777 u32 len_mismch; 1778 u32 fver_mismch; 1779 u32 rpt_en_map; 1780 1781 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1782 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1783 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1784 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1785 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1786 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1787 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1788 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1789 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1790 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1791 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1792 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1793 }; 1794 1795 #define RTW89_BTC_POLICY_MAXLEN 512 1796 1797 struct rtw89_btc { 1798 struct rtw89_btc_cx cx; 1799 struct rtw89_btc_dm dm; 1800 struct rtw89_btc_ctrl ctrl; 1801 struct rtw89_btc_module mdinfo; 1802 struct rtw89_btc_btf_fwinfo fwinfo; 1803 struct rtw89_btc_dbg dbg; 1804 1805 struct work_struct eapol_notify_work; 1806 struct work_struct arp_notify_work; 1807 struct work_struct dhcp_notify_work; 1808 struct work_struct icmp_notify_work; 1809 1810 u32 bt_req_len; 1811 1812 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 1813 u16 policy_len; 1814 u16 policy_type; 1815 bool bt_req_en; 1816 bool update_policy_force; 1817 bool lps; 1818 }; 1819 1820 enum rtw89_ra_mode { 1821 RTW89_RA_MODE_CCK = BIT(0), 1822 RTW89_RA_MODE_OFDM = BIT(1), 1823 RTW89_RA_MODE_HT = BIT(2), 1824 RTW89_RA_MODE_VHT = BIT(3), 1825 RTW89_RA_MODE_HE = BIT(4), 1826 }; 1827 1828 enum rtw89_ra_report_mode { 1829 RTW89_RA_RPT_MODE_LEGACY, 1830 RTW89_RA_RPT_MODE_HT, 1831 RTW89_RA_RPT_MODE_VHT, 1832 RTW89_RA_RPT_MODE_HE, 1833 }; 1834 1835 enum rtw89_dig_noisy_level { 1836 RTW89_DIG_NOISY_LEVEL0 = -1, 1837 RTW89_DIG_NOISY_LEVEL1 = 0, 1838 RTW89_DIG_NOISY_LEVEL2 = 1, 1839 RTW89_DIG_NOISY_LEVEL3 = 2, 1840 RTW89_DIG_NOISY_LEVEL_MAX = 3, 1841 }; 1842 1843 enum rtw89_gi_ltf { 1844 RTW89_GILTF_LGI_4XHE32 = 0, 1845 RTW89_GILTF_SGI_4XHE08 = 1, 1846 RTW89_GILTF_2XHE16 = 2, 1847 RTW89_GILTF_2XHE08 = 3, 1848 RTW89_GILTF_1XHE16 = 4, 1849 RTW89_GILTF_1XHE08 = 5, 1850 RTW89_GILTF_MAX 1851 }; 1852 1853 enum rtw89_rx_frame_type { 1854 RTW89_RX_TYPE_MGNT = 0, 1855 RTW89_RX_TYPE_CTRL = 1, 1856 RTW89_RX_TYPE_DATA = 2, 1857 RTW89_RX_TYPE_RSVD = 3, 1858 }; 1859 1860 struct rtw89_ra_info { 1861 u8 is_dis_ra:1; 1862 /* Bit0 : CCK 1863 * Bit1 : OFDM 1864 * Bit2 : HT 1865 * Bit3 : VHT 1866 * Bit4 : HE 1867 */ 1868 u8 mode_ctrl:5; 1869 u8 bw_cap:2; 1870 u8 macid; 1871 u8 dcm_cap:1; 1872 u8 er_cap:1; 1873 u8 init_rate_lv:2; 1874 u8 upd_all:1; 1875 u8 en_sgi:1; 1876 u8 ldpc_cap:1; 1877 u8 stbc_cap:1; 1878 u8 ss_num:3; 1879 u8 giltf:3; 1880 u8 upd_bw_nss_mask:1; 1881 u8 upd_mask:1; 1882 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 1883 /* BFee CSI */ 1884 u8 band_num; 1885 u8 ra_csi_rate_en:1; 1886 u8 fixed_csi_rate_en:1; 1887 u8 cr_tbl_sel:1; 1888 u8 rsvd2:5; 1889 u8 csi_mcs_ss_idx; 1890 u8 csi_mode:2; 1891 u8 csi_gi_ltf:3; 1892 u8 csi_bw:3; 1893 }; 1894 1895 #define RTW89_PPDU_MAX_USR 4 1896 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 1897 #define RTW89_PPDU_MAC_INFO_SIZE 8 1898 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 1899 1900 #define RTW89_MAX_RX_AGG_NUM 64 1901 #define RTW89_MAX_TX_AGG_NUM 128 1902 1903 struct rtw89_ampdu_params { 1904 u16 agg_num; 1905 bool amsdu; 1906 }; 1907 1908 struct rtw89_ra_report { 1909 struct rate_info txrate; 1910 u32 bit_rate; 1911 u16 hw_rate; 1912 }; 1913 1914 DECLARE_EWMA(rssi, 10, 16); 1915 1916 #define RTW89_BA_CAM_NUM 2 1917 1918 struct rtw89_ba_cam_entry { 1919 u8 tid; 1920 }; 1921 1922 #define RTW89_MAX_ADDR_CAM_NUM 128 1923 #define RTW89_MAX_BSSID_CAM_NUM 20 1924 #define RTW89_MAX_SEC_CAM_NUM 128 1925 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 1926 1927 struct rtw89_addr_cam_entry { 1928 u8 addr_cam_idx; 1929 u8 offset; 1930 u8 len; 1931 u8 valid : 1; 1932 u8 addr_mask : 6; 1933 u8 wapi : 1; 1934 u8 mask_sel : 2; 1935 u8 bssid_cam_idx: 6; 1936 1937 u8 sec_ent_mode; 1938 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 1939 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 1940 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 1941 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 1942 }; 1943 1944 struct rtw89_bssid_cam_entry { 1945 u8 bssid[ETH_ALEN]; 1946 u8 phy_idx; 1947 u8 bssid_cam_idx; 1948 u8 offset; 1949 u8 len; 1950 u8 valid : 1; 1951 u8 num; 1952 }; 1953 1954 struct rtw89_sec_cam_entry { 1955 u8 sec_cam_idx; 1956 u8 offset; 1957 u8 len; 1958 u8 type : 4; 1959 u8 ext_key : 1; 1960 u8 spp_mode : 1; 1961 /* 256 bits */ 1962 u8 key[32]; 1963 }; 1964 1965 struct rtw89_sta { 1966 u8 mac_id; 1967 bool disassoc; 1968 struct rtw89_vif *rtwvif; 1969 struct rtw89_ra_info ra; 1970 struct rtw89_ra_report ra_report; 1971 int max_agg_wait; 1972 u8 prev_rssi; 1973 struct ewma_rssi avg_rssi; 1974 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 1975 struct ieee80211_rx_status rx_status; 1976 u16 rx_hw_rate; 1977 __le32 htc_template; 1978 struct rtw89_addr_cam_entry addr_cam; /* AP mode only */ 1979 1980 bool use_cfg_mask; 1981 struct cfg80211_bitrate_mask mask; 1982 1983 bool cctl_tx_time; 1984 u32 ampdu_max_time:4; 1985 bool cctl_tx_retry_limit; 1986 u32 data_tx_cnt_lmt:6; 1987 1988 DECLARE_BITMAP(ba_cam_map, RTW89_BA_CAM_NUM); 1989 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_BA_CAM_NUM]; 1990 }; 1991 1992 struct rtw89_efuse { 1993 bool valid; 1994 u8 xtal_cap; 1995 u8 addr[ETH_ALEN]; 1996 u8 rfe_type; 1997 char country_code[2]; 1998 }; 1999 2000 struct rtw89_phy_rate_pattern { 2001 u64 ra_mask; 2002 u16 rate; 2003 u8 ra_mode; 2004 bool enable; 2005 }; 2006 2007 struct rtw89_vif { 2008 struct list_head list; 2009 struct rtw89_dev *rtwdev; 2010 u8 mac_id; 2011 u8 port; 2012 u8 mac_addr[ETH_ALEN]; 2013 u8 bssid[ETH_ALEN]; 2014 u8 phy_idx; 2015 u8 mac_idx; 2016 u8 net_type; 2017 u8 wifi_role; 2018 u8 self_role; 2019 u8 wmm; 2020 u8 bcn_hit_cond; 2021 u8 hit_rule; 2022 bool trigger; 2023 bool lsig_txop; 2024 u8 tgt_ind; 2025 u8 frm_tgt_ind; 2026 bool wowlan_pattern; 2027 bool wowlan_uc; 2028 bool wowlan_magic; 2029 bool is_hesta; 2030 bool last_a_ctrl; 2031 struct work_struct update_beacon_work; 2032 struct rtw89_addr_cam_entry addr_cam; 2033 struct rtw89_bssid_cam_entry bssid_cam; 2034 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2035 struct rtw89_traffic_stats stats; 2036 struct rtw89_phy_rate_pattern rate_pattern; 2037 struct cfg80211_scan_request *scan_req; 2038 struct ieee80211_scan_ies *scan_ies; 2039 }; 2040 2041 enum rtw89_lv1_rcvy_step { 2042 RTW89_LV1_RCVY_STEP_1, 2043 RTW89_LV1_RCVY_STEP_2, 2044 }; 2045 2046 struct rtw89_hci_ops { 2047 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2048 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2049 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2050 void (*reset)(struct rtw89_dev *rtwdev); 2051 int (*start)(struct rtw89_dev *rtwdev); 2052 void (*stop)(struct rtw89_dev *rtwdev); 2053 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2054 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2055 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2056 2057 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2058 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2059 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2060 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2061 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2062 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2063 2064 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2065 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2066 int (*deinit)(struct rtw89_dev *rtwdev); 2067 2068 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2069 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2070 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2071 int (*napi_poll)(struct napi_struct *napi, int budget); 2072 2073 /* Deal with locks inside recovery_start and recovery_complete callbacks 2074 * by hci instance, and handle things which need to consider under SER. 2075 * e.g. turn on/off interrupts except for the one for halt notification. 2076 */ 2077 void (*recovery_start)(struct rtw89_dev *rtwdev); 2078 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2079 }; 2080 2081 struct rtw89_hci_info { 2082 const struct rtw89_hci_ops *ops; 2083 enum rtw89_hci_type type; 2084 u32 rpwm_addr; 2085 u32 cpwm_addr; 2086 bool paused; 2087 }; 2088 2089 struct rtw89_chip_ops { 2090 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2091 void (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2092 void (*bb_reset)(struct rtw89_dev *rtwdev, 2093 enum rtw89_phy_idx phy_idx); 2094 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2095 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2096 u32 addr, u32 mask); 2097 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2098 u32 addr, u32 mask, u32 data); 2099 void (*set_channel)(struct rtw89_dev *rtwdev, 2100 struct rtw89_channel_params *param); 2101 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2102 struct rtw89_channel_help_params *p); 2103 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2104 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2105 void (*fem_setup)(struct rtw89_dev *rtwdev); 2106 void (*rfk_init)(struct rtw89_dev *rtwdev); 2107 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2108 void (*rfk_band_changed)(struct rtw89_dev *rtwdev); 2109 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2110 void (*rfk_track)(struct rtw89_dev *rtwdev); 2111 void (*power_trim)(struct rtw89_dev *rtwdev); 2112 void (*set_txpwr)(struct rtw89_dev *rtwdev); 2113 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev); 2114 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2115 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2116 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2117 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2118 struct rtw89_rx_phy_ppdu *phy_ppdu, 2119 struct ieee80211_rx_status *status); 2120 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2121 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2122 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2123 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2124 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2125 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2126 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2127 struct rtw89_tx_desc_info *desc_info, 2128 void *txdesc); 2129 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2130 struct rtw89_tx_desc_info *desc_info, 2131 void *txdesc); 2132 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2133 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2134 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2135 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2136 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2137 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2138 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2139 struct rtw89_vif *rtwvif, 2140 struct rtw89_sta *rtwsta); 2141 2142 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2143 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2144 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2145 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2146 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2147 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2148 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2149 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2150 }; 2151 2152 enum rtw89_dma_ch { 2153 RTW89_DMA_ACH0 = 0, 2154 RTW89_DMA_ACH1 = 1, 2155 RTW89_DMA_ACH2 = 2, 2156 RTW89_DMA_ACH3 = 3, 2157 RTW89_DMA_ACH4 = 4, 2158 RTW89_DMA_ACH5 = 5, 2159 RTW89_DMA_ACH6 = 6, 2160 RTW89_DMA_ACH7 = 7, 2161 RTW89_DMA_B0MG = 8, 2162 RTW89_DMA_B0HI = 9, 2163 RTW89_DMA_B1MG = 10, 2164 RTW89_DMA_B1HI = 11, 2165 RTW89_DMA_H2C = 12, 2166 RTW89_DMA_CH_NUM = 13 2167 }; 2168 2169 enum rtw89_qta_mode { 2170 RTW89_QTA_SCC, 2171 RTW89_QTA_DLFW, 2172 2173 /* keep last */ 2174 RTW89_QTA_INVALID, 2175 }; 2176 2177 struct rtw89_hfc_ch_cfg { 2178 u16 min; 2179 u16 max; 2180 #define grp_0 0 2181 #define grp_1 1 2182 #define grp_num 2 2183 u8 grp; 2184 }; 2185 2186 struct rtw89_hfc_ch_info { 2187 u16 aval; 2188 u16 used; 2189 }; 2190 2191 struct rtw89_hfc_pub_cfg { 2192 u16 grp0; 2193 u16 grp1; 2194 u16 pub_max; 2195 u16 wp_thrd; 2196 }; 2197 2198 struct rtw89_hfc_pub_info { 2199 u16 g0_used; 2200 u16 g1_used; 2201 u16 g0_aval; 2202 u16 g1_aval; 2203 u16 pub_aval; 2204 u16 wp_aval; 2205 }; 2206 2207 struct rtw89_hfc_prec_cfg { 2208 u16 ch011_prec; 2209 u16 h2c_prec; 2210 u16 wp_ch07_prec; 2211 u16 wp_ch811_prec; 2212 u8 ch011_full_cond; 2213 u8 h2c_full_cond; 2214 u8 wp_ch07_full_cond; 2215 u8 wp_ch811_full_cond; 2216 }; 2217 2218 struct rtw89_hfc_param { 2219 bool en; 2220 bool h2c_en; 2221 u8 mode; 2222 const struct rtw89_hfc_ch_cfg *ch_cfg; 2223 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2224 struct rtw89_hfc_pub_cfg pub_cfg; 2225 struct rtw89_hfc_pub_info pub_info; 2226 struct rtw89_hfc_prec_cfg prec_cfg; 2227 }; 2228 2229 struct rtw89_hfc_param_ini { 2230 const struct rtw89_hfc_ch_cfg *ch_cfg; 2231 const struct rtw89_hfc_pub_cfg *pub_cfg; 2232 const struct rtw89_hfc_prec_cfg *prec_cfg; 2233 u8 mode; 2234 }; 2235 2236 struct rtw89_dle_size { 2237 u16 pge_size; 2238 u16 lnk_pge_num; 2239 u16 unlnk_pge_num; 2240 }; 2241 2242 struct rtw89_wde_quota { 2243 u16 hif; 2244 u16 wcpu; 2245 u16 pkt_in; 2246 u16 cpu_io; 2247 }; 2248 2249 struct rtw89_ple_quota { 2250 u16 cma0_tx; 2251 u16 cma1_tx; 2252 u16 c2h; 2253 u16 h2c; 2254 u16 wcpu; 2255 u16 mpdu_proc; 2256 u16 cma0_dma; 2257 u16 cma1_dma; 2258 u16 bb_rpt; 2259 u16 wd_rel; 2260 u16 cpu_io; 2261 u16 tx_rpt; 2262 }; 2263 2264 struct rtw89_dle_mem { 2265 enum rtw89_qta_mode mode; 2266 const struct rtw89_dle_size *wde_size; 2267 const struct rtw89_dle_size *ple_size; 2268 const struct rtw89_wde_quota *wde_min_qt; 2269 const struct rtw89_wde_quota *wde_max_qt; 2270 const struct rtw89_ple_quota *ple_min_qt; 2271 const struct rtw89_ple_quota *ple_max_qt; 2272 }; 2273 2274 struct rtw89_reg_def { 2275 u32 addr; 2276 u32 mask; 2277 }; 2278 2279 struct rtw89_reg2_def { 2280 u32 addr; 2281 u32 data; 2282 }; 2283 2284 struct rtw89_reg3_def { 2285 u32 addr; 2286 u32 mask; 2287 u32 data; 2288 }; 2289 2290 struct rtw89_reg5_def { 2291 u8 flag; /* recognized by parsers */ 2292 u8 path; 2293 u32 addr; 2294 u32 mask; 2295 u32 data; 2296 }; 2297 2298 struct rtw89_phy_table { 2299 const struct rtw89_reg2_def *regs; 2300 u32 n_regs; 2301 enum rtw89_rf_path rf_path; 2302 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2303 enum rtw89_rf_path rf_path, void *data); 2304 }; 2305 2306 struct rtw89_txpwr_table { 2307 const void *data; 2308 u32 size; 2309 void (*load)(struct rtw89_dev *rtwdev, 2310 const struct rtw89_txpwr_table *tbl); 2311 }; 2312 2313 struct rtw89_page_regs { 2314 u32 hci_fc_ctrl; 2315 u32 ch_page_ctrl; 2316 u32 ach_page_ctrl; 2317 u32 ach_page_info; 2318 u32 pub_page_info3; 2319 u32 pub_page_ctrl1; 2320 u32 pub_page_ctrl2; 2321 u32 pub_page_info1; 2322 u32 pub_page_info2; 2323 u32 wp_page_ctrl1; 2324 u32 wp_page_ctrl2; 2325 u32 wp_page_info1; 2326 }; 2327 2328 struct rtw89_imr_info { 2329 u32 wdrls_imr_set; 2330 u32 wsec_imr_reg; 2331 u32 wsec_imr_set; 2332 u32 mpdu_tx_imr_set; 2333 u32 mpdu_rx_imr_set; 2334 u32 sta_sch_imr_set; 2335 u32 txpktctl_imr_b0_reg; 2336 u32 txpktctl_imr_b0_clr; 2337 u32 txpktctl_imr_b0_set; 2338 u32 txpktctl_imr_b1_reg; 2339 u32 txpktctl_imr_b1_clr; 2340 u32 txpktctl_imr_b1_set; 2341 u32 wde_imr_clr; 2342 u32 wde_imr_set; 2343 u32 ple_imr_clr; 2344 u32 ple_imr_set; 2345 u32 host_disp_imr_clr; 2346 u32 host_disp_imr_set; 2347 u32 cpu_disp_imr_clr; 2348 u32 cpu_disp_imr_set; 2349 u32 other_disp_imr_clr; 2350 u32 other_disp_imr_set; 2351 u32 bbrpt_chinfo_err_imr_reg; 2352 u32 bbrpt_err_imr_set; 2353 u32 bbrpt_dfs_err_imr_reg; 2354 u32 ptcl_imr_clr; 2355 u32 ptcl_imr_set; 2356 u32 cdma_imr_0_reg; 2357 u32 cdma_imr_0_clr; 2358 u32 cdma_imr_0_set; 2359 u32 cdma_imr_1_reg; 2360 u32 cdma_imr_1_clr; 2361 u32 cdma_imr_1_set; 2362 u32 phy_intf_imr_reg; 2363 u32 phy_intf_imr_clr; 2364 u32 phy_intf_imr_set; 2365 u32 rmac_imr_reg; 2366 u32 rmac_imr_clr; 2367 u32 rmac_imr_set; 2368 u32 tmac_imr_reg; 2369 u32 tmac_imr_clr; 2370 u32 tmac_imr_set; 2371 }; 2372 2373 struct rtw89_chip_info { 2374 enum rtw89_core_chip_id chip_id; 2375 const struct rtw89_chip_ops *ops; 2376 const char *fw_name; 2377 u32 fifo_size; 2378 u16 max_amsdu_limit; 2379 bool dis_2g_40m_ul_ofdma; 2380 u32 rsvd_ple_ofst; 2381 const struct rtw89_hfc_param_ini *hfc_param_ini; 2382 const struct rtw89_dle_mem *dle_mem; 2383 u32 rf_base_addr[2]; 2384 u8 support_bands; 2385 bool support_bw160; 2386 bool hw_sec_hdr; 2387 u8 rf_path_num; 2388 u8 tx_nss; 2389 u8 rx_nss; 2390 u8 acam_num; 2391 u8 bcam_num; 2392 u8 scam_num; 2393 2394 u8 sec_ctrl_efuse_size; 2395 u32 physical_efuse_size; 2396 u32 logical_efuse_size; 2397 u32 limit_efuse_size; 2398 u32 dav_phy_efuse_size; 2399 u32 dav_log_efuse_size; 2400 u32 phycap_addr; 2401 u32 phycap_size; 2402 2403 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2404 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2405 const struct rtw89_phy_table *bb_table; 2406 const struct rtw89_phy_table *bb_gain_table; 2407 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2408 const struct rtw89_phy_table *nctl_table; 2409 const struct rtw89_txpwr_table *byr_table; 2410 const struct rtw89_phy_dig_gain_table *dig_table; 2411 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2412 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2413 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2414 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2415 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2416 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2417 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2418 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2419 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2420 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2421 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2422 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2423 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2424 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2425 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2426 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2427 2428 u8 txpwr_factor_rf; 2429 u8 txpwr_factor_mac; 2430 2431 u32 para_ver; 2432 u32 wlcx_desired; 2433 u8 btcx_desired; 2434 u8 scbd; 2435 u8 mailbox; 2436 2437 u8 afh_guard_ch; 2438 const u8 *wl_rssi_thres; 2439 const u8 *bt_rssi_thres; 2440 u8 rssi_tol; 2441 2442 u8 mon_reg_num; 2443 const struct rtw89_btc_fbtc_mreg *mon_reg; 2444 u8 rf_para_ulink_num; 2445 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2446 u8 rf_para_dlink_num; 2447 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2448 u8 ps_mode_supported; 2449 u8 low_power_hci_modes; 2450 2451 u32 h2c_cctl_func_id; 2452 u32 hci_func_en_addr; 2453 u32 h2c_desc_size; 2454 u32 txwd_body_size; 2455 u32 h2c_ctrl_reg; 2456 const u32 *h2c_regs; 2457 u32 c2h_ctrl_reg; 2458 const u32 *c2h_regs; 2459 const struct rtw89_page_regs *page_regs; 2460 const struct rtw89_reg_def *dcfo_comp; 2461 u8 dcfo_comp_sft; 2462 const struct rtw89_imr_info *imr_info; 2463 }; 2464 2465 union rtw89_bus_info { 2466 const struct rtw89_pci_info *pci; 2467 }; 2468 2469 struct rtw89_driver_info { 2470 const struct rtw89_chip_info *chip; 2471 union rtw89_bus_info bus; 2472 }; 2473 2474 enum rtw89_hcifc_mode { 2475 RTW89_HCIFC_POH = 0, 2476 RTW89_HCIFC_STF = 1, 2477 RTW89_HCIFC_SDIO = 2, 2478 2479 /* keep last */ 2480 RTW89_HCIFC_MODE_INVALID, 2481 }; 2482 2483 struct rtw89_dle_info { 2484 enum rtw89_qta_mode qta_mode; 2485 u16 wde_pg_size; 2486 u16 ple_pg_size; 2487 u16 c0_rx_qta; 2488 u16 c1_rx_qta; 2489 }; 2490 2491 enum rtw89_host_rpr_mode { 2492 RTW89_RPR_MODE_POH = 0, 2493 RTW89_RPR_MODE_STF 2494 }; 2495 2496 struct rtw89_mac_info { 2497 struct rtw89_dle_info dle_info; 2498 struct rtw89_hfc_param hfc_param; 2499 enum rtw89_qta_mode qta_mode; 2500 u8 rpwm_seq_num; 2501 u8 cpwm_seq_num; 2502 }; 2503 2504 enum rtw89_fw_type { 2505 RTW89_FW_NORMAL = 1, 2506 RTW89_FW_WOWLAN = 3, 2507 }; 2508 2509 enum rtw89_fw_feature { 2510 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 2511 RTW89_FW_FEATURE_SCAN_OFFLOAD, 2512 RTW89_FW_FEATURE_TX_WAKE, 2513 RTW89_FW_FEATURE_CRASH_TRIGGER, 2514 }; 2515 2516 struct rtw89_fw_suit { 2517 const u8 *data; 2518 u32 size; 2519 u8 major_ver; 2520 u8 minor_ver; 2521 u8 sub_ver; 2522 u8 sub_idex; 2523 u16 build_year; 2524 u16 build_mon; 2525 u16 build_date; 2526 u16 build_hour; 2527 u16 build_min; 2528 u8 cmd_ver; 2529 }; 2530 2531 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2532 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2533 #define RTW89_FW_SUIT_VER_CODE(s) \ 2534 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2535 2536 struct rtw89_fw_info { 2537 const struct firmware *firmware; 2538 struct rtw89_dev *rtwdev; 2539 struct completion completion; 2540 u8 h2c_seq; 2541 u8 rec_seq; 2542 struct rtw89_fw_suit normal; 2543 struct rtw89_fw_suit wowlan; 2544 bool fw_log_enable; 2545 u32 feature_map; 2546 }; 2547 2548 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 2549 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 2550 2551 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 2552 ((_fw)->feature_map |= BIT(_fw_feature)) 2553 2554 struct rtw89_cam_info { 2555 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2556 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2557 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2558 }; 2559 2560 enum rtw89_sar_sources { 2561 RTW89_SAR_SOURCE_NONE, 2562 RTW89_SAR_SOURCE_COMMON, 2563 2564 RTW89_SAR_SOURCE_NR, 2565 }; 2566 2567 enum rtw89_sar_subband { 2568 RTW89_SAR_2GHZ_SUBBAND, 2569 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 2570 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 2571 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 2572 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 2573 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 2574 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 2575 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 2576 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 2577 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 2578 2579 RTW89_SAR_SUBBAND_NR, 2580 }; 2581 2582 struct rtw89_sar_cfg_common { 2583 bool set[RTW89_SAR_SUBBAND_NR]; 2584 s32 cfg[RTW89_SAR_SUBBAND_NR]; 2585 }; 2586 2587 struct rtw89_sar_info { 2588 /* used to decide how to acces SAR cfg union */ 2589 enum rtw89_sar_sources src; 2590 2591 /* reserved for different knids of SAR cfg struct. 2592 * supposed that a single cfg struct cannot handle various SAR sources. 2593 */ 2594 union { 2595 struct rtw89_sar_cfg_common cfg_common; 2596 }; 2597 }; 2598 2599 struct rtw89_hal { 2600 u32 rx_fltr; 2601 u8 cv; 2602 u8 current_channel; 2603 u32 current_freq; 2604 u8 prev_primary_channel; 2605 u8 current_primary_channel; 2606 enum rtw89_subband current_subband; 2607 u8 current_band_width; 2608 u8 prev_band_type; 2609 u8 current_band_type; 2610 u32 sw_amsdu_max_size; 2611 u32 antenna_tx; 2612 u32 antenna_rx; 2613 u8 tx_nss; 2614 u8 rx_nss; 2615 bool support_cckpd; 2616 bool support_igi; 2617 }; 2618 2619 #define RTW89_MAX_MAC_ID_NUM 128 2620 #define RTW89_MAX_PKT_OFLD_NUM 255 2621 2622 enum rtw89_flags { 2623 RTW89_FLAG_POWERON, 2624 RTW89_FLAG_FW_RDY, 2625 RTW89_FLAG_RUNNING, 2626 RTW89_FLAG_BFEE_MON, 2627 RTW89_FLAG_BFEE_EN, 2628 RTW89_FLAG_NAPI_RUNNING, 2629 RTW89_FLAG_LEISURE_PS, 2630 RTW89_FLAG_LOW_POWER_MODE, 2631 RTW89_FLAG_INACTIVE_PS, 2632 RTW89_FLAG_RESTART_TRIGGER, 2633 2634 NUM_OF_RTW89_FLAGS, 2635 }; 2636 2637 struct rtw89_pkt_stat { 2638 u16 beacon_nr; 2639 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2640 }; 2641 2642 DECLARE_EWMA(thermal, 4, 4); 2643 2644 struct rtw89_phy_stat { 2645 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2646 struct rtw89_pkt_stat cur_pkt_stat; 2647 struct rtw89_pkt_stat last_pkt_stat; 2648 }; 2649 2650 #define RTW89_DACK_PATH_NR 2 2651 #define RTW89_DACK_IDX_NR 2 2652 #define RTW89_DACK_MSBK_NR 16 2653 struct rtw89_dack_info { 2654 bool dack_done; 2655 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2656 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2657 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2658 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2659 u32 dack_cnt; 2660 bool addck_timeout[RTW89_DACK_PATH_NR]; 2661 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2662 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2663 }; 2664 2665 #define RTW89_IQK_CHS_NR 2 2666 #define RTW89_IQK_PATH_NR 4 2667 2668 struct rtw89_mcc_info { 2669 u8 ch[RTW89_IQK_CHS_NR]; 2670 u8 band[RTW89_IQK_CHS_NR]; 2671 u8 table_idx; 2672 }; 2673 2674 struct rtw89_lck_info { 2675 u8 thermal[RF_PATH_MAX]; 2676 }; 2677 2678 struct rtw89_rx_dck_info { 2679 u8 thermal[RF_PATH_MAX]; 2680 }; 2681 2682 struct rtw89_iqk_info { 2683 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2684 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2685 bool lok_fail[RTW89_IQK_PATH_NR]; 2686 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2687 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2688 u32 iqk_fail_cnt; 2689 bool is_iqk_init; 2690 u32 iqk_channel[RTW89_IQK_CHS_NR]; 2691 u8 iqk_band[RTW89_IQK_PATH_NR]; 2692 u8 iqk_ch[RTW89_IQK_PATH_NR]; 2693 u8 iqk_bw[RTW89_IQK_PATH_NR]; 2694 u8 kcount; 2695 u8 iqk_times; 2696 u8 version; 2697 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 2698 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 2699 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 2700 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 2701 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 2702 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 2703 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 2704 bool is_nbiqk; 2705 bool iqk_fft_en; 2706 bool iqk_xym_en; 2707 bool iqk_sram_en; 2708 bool iqk_cfir_en; 2709 u8 thermal[RTW89_IQK_PATH_NR]; 2710 bool thermal_rek_en; 2711 u32 syn1to2; 2712 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2713 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 2714 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2715 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2716 }; 2717 2718 #define RTW89_DPK_RF_PATH 2 2719 #define RTW89_DPK_AVG_THERMAL_NUM 8 2720 #define RTW89_DPK_BKUP_NUM 2 2721 struct rtw89_dpk_bkup_para { 2722 enum rtw89_band band; 2723 enum rtw89_bandwidth bw; 2724 u8 ch; 2725 bool path_ok; 2726 u8 mdpd_en; 2727 u8 txagc_dpk; 2728 u8 ther_dpk; 2729 u8 gs; 2730 u16 pwsf; 2731 }; 2732 2733 struct rtw89_dpk_info { 2734 bool is_dpk_enable; 2735 bool is_dpk_reload_en; 2736 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2737 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2738 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2739 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2740 u8 cur_idx[RTW89_DPK_RF_PATH]; 2741 u8 cur_k_set; 2742 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2743 }; 2744 2745 struct rtw89_fem_info { 2746 bool elna_2g; 2747 bool elna_5g; 2748 bool epa_2g; 2749 bool epa_5g; 2750 bool epa_6g; 2751 }; 2752 2753 struct rtw89_phy_ch_info { 2754 u8 rssi_min; 2755 u16 rssi_min_macid; 2756 u8 pre_rssi_min; 2757 u8 rssi_max; 2758 u16 rssi_max_macid; 2759 u8 rxsc_160; 2760 u8 rxsc_80; 2761 u8 rxsc_40; 2762 u8 rxsc_20; 2763 u8 rxsc_l; 2764 u8 is_noisy; 2765 }; 2766 2767 struct rtw89_agc_gaincode_set { 2768 u8 lna_idx; 2769 u8 tia_idx; 2770 u8 rxb_idx; 2771 }; 2772 2773 #define IGI_RSSI_TH_NUM 5 2774 #define FA_TH_NUM 4 2775 #define LNA_GAIN_NUM 7 2776 #define TIA_GAIN_NUM 2 2777 struct rtw89_dig_info { 2778 struct rtw89_agc_gaincode_set cur_gaincode; 2779 bool force_gaincode_idx_en; 2780 struct rtw89_agc_gaincode_set force_gaincode; 2781 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 2782 u16 fa_th[FA_TH_NUM]; 2783 u8 igi_rssi; 2784 u8 igi_fa_rssi; 2785 u8 fa_rssi_ofst; 2786 u8 dyn_igi_max; 2787 u8 dyn_igi_min; 2788 bool dyn_pd_th_en; 2789 u8 dyn_pd_th_max; 2790 u8 pd_low_th_ofst; 2791 u8 ib_pbk; 2792 s8 ib_pkpwr; 2793 s8 lna_gain_a[LNA_GAIN_NUM]; 2794 s8 lna_gain_g[LNA_GAIN_NUM]; 2795 s8 *lna_gain; 2796 s8 tia_gain_a[TIA_GAIN_NUM]; 2797 s8 tia_gain_g[TIA_GAIN_NUM]; 2798 s8 *tia_gain; 2799 bool is_linked_pre; 2800 bool bypass_dig; 2801 }; 2802 2803 enum rtw89_multi_cfo_mode { 2804 RTW89_PKT_BASED_AVG_MODE = 0, 2805 RTW89_ENTRY_BASED_AVG_MODE = 1, 2806 RTW89_TP_BASED_AVG_MODE = 2, 2807 }; 2808 2809 enum rtw89_phy_cfo_status { 2810 RTW89_PHY_DCFO_STATE_NORMAL = 0, 2811 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 2812 RTW89_PHY_DCFO_STATE_HOLD = 2, 2813 RTW89_PHY_DCFO_STATE_MAX 2814 }; 2815 2816 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 2817 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 2818 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 2819 }; 2820 2821 struct rtw89_cfo_tracking_info { 2822 u16 cfo_timer_ms; 2823 bool cfo_trig_by_timer_en; 2824 enum rtw89_phy_cfo_status phy_cfo_status; 2825 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 2826 u8 phy_cfo_trk_cnt; 2827 bool is_adjust; 2828 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 2829 bool apply_compensation; 2830 u8 crystal_cap; 2831 u8 crystal_cap_default; 2832 u8 def_x_cap; 2833 s8 x_cap_ofst; 2834 u32 sta_cfo_tolerance; 2835 s32 cfo_tail[CFO_TRACK_MAX_USER]; 2836 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 2837 s32 cfo_avg_pre; 2838 s32 cfo_avg[CFO_TRACK_MAX_USER]; 2839 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 2840 u32 packet_count; 2841 u32 packet_count_pre; 2842 s32 residual_cfo_acc; 2843 u8 phy_cfotrk_state; 2844 u8 phy_cfotrk_cnt; 2845 bool divergence_lock_en; 2846 u8 x_cap_lb; 2847 u8 x_cap_ub; 2848 u8 lock_cnt; 2849 }; 2850 2851 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 2852 #define TSSI_TRIM_CH_GROUP_NUM 8 2853 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 2854 2855 #define TSSI_CCK_CH_GROUP_NUM 6 2856 #define TSSI_MCS_2G_CH_GROUP_NUM 5 2857 #define TSSI_MCS_5G_CH_GROUP_NUM 14 2858 #define TSSI_MCS_6G_CH_GROUP_NUM 32 2859 #define TSSI_MCS_CH_GROUP_NUM \ 2860 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 2861 2862 struct rtw89_tssi_info { 2863 u8 thermal[RF_PATH_MAX]; 2864 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 2865 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 2866 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 2867 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 2868 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 2869 s8 extra_ofst[RF_PATH_MAX]; 2870 bool tssi_tracking_check[RF_PATH_MAX]; 2871 u8 default_txagc_offset[RF_PATH_MAX]; 2872 u32 base_thermal[RF_PATH_MAX]; 2873 }; 2874 2875 struct rtw89_power_trim_info { 2876 bool pg_thermal_trim; 2877 bool pg_pa_bias_trim; 2878 u8 thermal_trim[RF_PATH_MAX]; 2879 u8 pa_bias_trim[RF_PATH_MAX]; 2880 }; 2881 2882 struct rtw89_regulatory { 2883 char alpha2[3]; 2884 u8 txpwr_regd[RTW89_BAND_MAX]; 2885 }; 2886 2887 enum rtw89_ifs_clm_application { 2888 RTW89_IFS_CLM_INIT = 0, 2889 RTW89_IFS_CLM_BACKGROUND = 1, 2890 RTW89_IFS_CLM_ACS = 2, 2891 RTW89_IFS_CLM_DIG = 3, 2892 RTW89_IFS_CLM_TDMA_DIG = 4, 2893 RTW89_IFS_CLM_DBG = 5, 2894 RTW89_IFS_CLM_DBG_MANUAL = 6 2895 }; 2896 2897 enum rtw89_env_racing_lv { 2898 RTW89_RAC_RELEASE = 0, 2899 RTW89_RAC_LV_1 = 1, 2900 RTW89_RAC_LV_2 = 2, 2901 RTW89_RAC_LV_3 = 3, 2902 RTW89_RAC_LV_4 = 4, 2903 RTW89_RAC_MAX_NUM = 5 2904 }; 2905 2906 struct rtw89_ccx_para_info { 2907 enum rtw89_env_racing_lv rac_lv; 2908 u16 mntr_time; 2909 u8 nhm_manual_th_ofst; 2910 u8 nhm_manual_th0; 2911 enum rtw89_ifs_clm_application ifs_clm_app; 2912 u32 ifs_clm_manual_th_times; 2913 u32 ifs_clm_manual_th0; 2914 u8 fahm_manual_th_ofst; 2915 u8 fahm_manual_th0; 2916 u8 fahm_numer_opt; 2917 u8 fahm_denom_opt; 2918 }; 2919 2920 enum rtw89_ccx_edcca_opt_sc_idx { 2921 RTW89_CCX_EDCCA_SEG0_P0 = 0, 2922 RTW89_CCX_EDCCA_SEG0_S1 = 1, 2923 RTW89_CCX_EDCCA_SEG0_S2 = 2, 2924 RTW89_CCX_EDCCA_SEG0_S3 = 3, 2925 RTW89_CCX_EDCCA_SEG1_P0 = 4, 2926 RTW89_CCX_EDCCA_SEG1_S1 = 5, 2927 RTW89_CCX_EDCCA_SEG1_S2 = 6, 2928 RTW89_CCX_EDCCA_SEG1_S3 = 7 2929 }; 2930 2931 enum rtw89_ccx_edcca_opt_bw_idx { 2932 RTW89_CCX_EDCCA_BW20_0 = 0, 2933 RTW89_CCX_EDCCA_BW20_1 = 1, 2934 RTW89_CCX_EDCCA_BW20_2 = 2, 2935 RTW89_CCX_EDCCA_BW20_3 = 3, 2936 RTW89_CCX_EDCCA_BW20_4 = 4, 2937 RTW89_CCX_EDCCA_BW20_5 = 5, 2938 RTW89_CCX_EDCCA_BW20_6 = 6, 2939 RTW89_CCX_EDCCA_BW20_7 = 7 2940 }; 2941 2942 #define RTW89_NHM_TH_NUM 11 2943 #define RTW89_FAHM_TH_NUM 11 2944 #define RTW89_NHM_RPT_NUM 12 2945 #define RTW89_FAHM_RPT_NUM 12 2946 #define RTW89_IFS_CLM_NUM 4 2947 struct rtw89_env_monitor_info { 2948 u32 ccx_trigger_time; 2949 u64 start_time; 2950 u8 ccx_rpt_stamp; 2951 u8 ccx_watchdog_result; 2952 bool ccx_ongoing; 2953 u8 ccx_rac_lv; 2954 bool ccx_manual_ctrl; 2955 u8 ccx_pre_rssi; 2956 u16 clm_mntr_time; 2957 u16 nhm_mntr_time; 2958 u16 ifs_clm_mntr_time; 2959 enum rtw89_ifs_clm_application ifs_clm_app; 2960 u16 fahm_mntr_time; 2961 u16 edcca_clm_mntr_time; 2962 u16 ccx_period; 2963 u8 ccx_unit_idx; 2964 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 2965 u8 nhm_th[RTW89_NHM_TH_NUM]; 2966 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 2967 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 2968 u8 fahm_numer_opt; 2969 u8 fahm_denom_opt; 2970 u8 fahm_th[RTW89_FAHM_TH_NUM]; 2971 u16 clm_result; 2972 u16 nhm_result[RTW89_NHM_RPT_NUM]; 2973 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 2974 u16 nhm_tx_cnt; 2975 u16 nhm_cca_cnt; 2976 u16 nhm_idle_cnt; 2977 u16 ifs_clm_tx; 2978 u16 ifs_clm_edcca_excl_cca; 2979 u16 ifs_clm_ofdmfa; 2980 u16 ifs_clm_ofdmcca_excl_fa; 2981 u16 ifs_clm_cckfa; 2982 u16 ifs_clm_cckcca_excl_fa; 2983 u16 ifs_clm_total_ifs; 2984 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 2985 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 2986 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 2987 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 2988 u16 fahm_denom_result; 2989 u16 edcca_clm_result; 2990 u8 clm_ratio; 2991 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 2992 u8 nhm_tx_ratio; 2993 u8 nhm_cca_ratio; 2994 u8 nhm_idle_ratio; 2995 u8 nhm_ratio; 2996 u16 nhm_result_sum; 2997 u8 nhm_pwr; 2998 u8 ifs_clm_tx_ratio; 2999 u8 ifs_clm_edcca_excl_cca_ratio; 3000 u8 ifs_clm_cck_fa_ratio; 3001 u8 ifs_clm_ofdm_fa_ratio; 3002 u8 ifs_clm_cck_cca_excl_fa_ratio; 3003 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3004 u16 ifs_clm_cck_fa_permil; 3005 u16 ifs_clm_ofdm_fa_permil; 3006 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3007 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3008 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3009 u16 fahm_result_sum; 3010 u8 fahm_ratio; 3011 u8 fahm_denom_ratio; 3012 u8 fahm_pwr; 3013 u8 edcca_clm_ratio; 3014 }; 3015 3016 enum rtw89_ser_rcvy_step { 3017 RTW89_SER_DRV_STOP_TX, 3018 RTW89_SER_DRV_STOP_RX, 3019 RTW89_SER_DRV_STOP_RUN, 3020 RTW89_SER_HAL_STOP_DMA, 3021 RTW89_NUM_OF_SER_FLAGS 3022 }; 3023 3024 struct rtw89_ser { 3025 u8 state; 3026 u8 alarm_event; 3027 3028 struct work_struct ser_hdl_work; 3029 struct delayed_work ser_alarm_work; 3030 const struct state_ent *st_tbl; 3031 const struct event_ent *ev_tbl; 3032 struct list_head msg_q; 3033 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3034 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3035 }; 3036 3037 enum rtw89_mac_ax_ps_mode { 3038 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3039 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3040 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3041 RTW89_MAC_AX_PS_MODE_MAX = 3, 3042 }; 3043 3044 enum rtw89_last_rpwm_mode { 3045 RTW89_LAST_RPWM_PS = 0x0, 3046 RTW89_LAST_RPWM_ACTIVE = 0x6, 3047 }; 3048 3049 struct rtw89_lps_parm { 3050 u8 macid; 3051 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3052 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3053 }; 3054 3055 struct rtw89_ppdu_sts_info { 3056 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3057 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3058 }; 3059 3060 struct rtw89_early_h2c { 3061 struct list_head list; 3062 u8 *h2c; 3063 u16 h2c_len; 3064 }; 3065 3066 struct rtw89_hw_scan_info { 3067 struct ieee80211_vif *scanning_vif; 3068 struct list_head pkt_list[NUM_NL80211_BANDS]; 3069 u8 op_pri_ch; 3070 u8 op_chan; 3071 u8 op_bw; 3072 u8 op_band; 3073 }; 3074 3075 enum rtw89_phy_bb_gain_band { 3076 RTW89_BB_GAIN_BAND_2G = 0, 3077 RTW89_BB_GAIN_BAND_5G_L = 1, 3078 RTW89_BB_GAIN_BAND_5G_M = 2, 3079 RTW89_BB_GAIN_BAND_5G_H = 3, 3080 RTW89_BB_GAIN_BAND_6G_L = 4, 3081 RTW89_BB_GAIN_BAND_6G_M = 5, 3082 RTW89_BB_GAIN_BAND_6G_H = 6, 3083 RTW89_BB_GAIN_BAND_6G_UH = 7, 3084 3085 RTW89_BB_GAIN_BAND_NR, 3086 }; 3087 3088 enum rtw89_phy_bb_rxsc_num { 3089 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3090 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3091 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3092 }; 3093 3094 struct rtw89_phy_bb_gain_info { 3095 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3096 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3097 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3098 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3099 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3100 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3101 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3102 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3103 [RTW89_BB_RXSC_NUM_40]; 3104 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3105 [RTW89_BB_RXSC_NUM_80]; 3106 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3107 [RTW89_BB_RXSC_NUM_160]; 3108 }; 3109 3110 struct rtw89_phy_efuse_gain { 3111 bool offset_valid; 3112 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3113 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3114 }; 3115 3116 struct rtw89_dev { 3117 struct ieee80211_hw *hw; 3118 struct device *dev; 3119 3120 bool dbcc_en; 3121 struct rtw89_hw_scan_info scan_info; 3122 const struct rtw89_chip_info *chip; 3123 const struct rtw89_pci_info *pci_info; 3124 struct rtw89_hal hal; 3125 struct rtw89_mac_info mac; 3126 struct rtw89_fw_info fw; 3127 struct rtw89_hci_info hci; 3128 struct rtw89_efuse efuse; 3129 struct rtw89_traffic_stats stats; 3130 3131 /* ensures exclusive access from mac80211 callbacks */ 3132 struct mutex mutex; 3133 struct list_head rtwvifs_list; 3134 /* used to protect rf read write */ 3135 struct mutex rf_mutex; 3136 struct workqueue_struct *txq_wq; 3137 struct work_struct txq_work; 3138 struct delayed_work txq_reinvoke_work; 3139 /* used to protect ba_list */ 3140 spinlock_t ba_lock; 3141 /* txqs to setup ba session */ 3142 struct list_head ba_list; 3143 struct work_struct ba_work; 3144 /* used to protect rpwm */ 3145 spinlock_t rpwm_lock; 3146 3147 struct rtw89_cam_info cam_info; 3148 3149 struct sk_buff_head c2h_queue; 3150 struct work_struct c2h_work; 3151 struct work_struct ips_work; 3152 3153 struct list_head early_h2c_list; 3154 3155 struct rtw89_ser ser; 3156 3157 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3158 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3159 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3160 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3161 3162 struct rtw89_phy_stat phystat; 3163 struct rtw89_dack_info dack; 3164 struct rtw89_iqk_info iqk; 3165 struct rtw89_dpk_info dpk; 3166 struct rtw89_mcc_info mcc; 3167 struct rtw89_lck_info lck; 3168 struct rtw89_rx_dck_info rx_dck; 3169 bool is_tssi_mode[RF_PATH_MAX]; 3170 bool is_bt_iqk_timeout; 3171 3172 struct rtw89_fem_info fem; 3173 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3174 struct rtw89_tssi_info tssi; 3175 struct rtw89_power_trim_info pwr_trim; 3176 3177 struct rtw89_cfo_tracking_info cfo_tracking; 3178 struct rtw89_env_monitor_info env_monitor; 3179 struct rtw89_dig_info dig; 3180 struct rtw89_phy_ch_info ch_info; 3181 struct rtw89_phy_bb_gain_info bb_gain; 3182 struct rtw89_phy_efuse_gain efuse_gain; 3183 3184 struct delayed_work track_work; 3185 struct delayed_work coex_act1_work; 3186 struct delayed_work coex_bt_devinfo_work; 3187 struct delayed_work coex_rfk_chk_work; 3188 struct delayed_work cfo_track_work; 3189 struct rtw89_ppdu_sts_info ppdu_sts; 3190 u8 total_sta_assoc; 3191 bool scanning; 3192 3193 const struct rtw89_regulatory *regd; 3194 struct rtw89_sar_info sar; 3195 3196 struct rtw89_btc btc; 3197 enum rtw89_ps_mode ps_mode; 3198 bool lps_enabled; 3199 3200 /* napi structure */ 3201 struct net_device netdev; 3202 struct napi_struct napi; 3203 int napi_budget_countdown; 3204 3205 /* HCI related data, keep last */ 3206 u8 priv[] __aligned(sizeof(void *)); 3207 }; 3208 3209 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3210 struct rtw89_core_tx_request *tx_req) 3211 { 3212 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3213 } 3214 3215 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3216 { 3217 rtwdev->hci.ops->reset(rtwdev); 3218 } 3219 3220 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3221 { 3222 return rtwdev->hci.ops->start(rtwdev); 3223 } 3224 3225 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3226 { 3227 rtwdev->hci.ops->stop(rtwdev); 3228 } 3229 3230 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3231 { 3232 return rtwdev->hci.ops->deinit(rtwdev); 3233 } 3234 3235 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3236 { 3237 rtwdev->hci.ops->pause(rtwdev, pause); 3238 } 3239 3240 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3241 { 3242 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3243 } 3244 3245 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3246 { 3247 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3248 } 3249 3250 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3251 { 3252 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3253 } 3254 3255 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3256 { 3257 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3258 } 3259 3260 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3261 bool drop) 3262 { 3263 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3264 return; 3265 3266 if (rtwdev->hci.ops->flush_queues) 3267 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3268 } 3269 3270 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3271 { 3272 if (rtwdev->hci.ops->recovery_start) 3273 rtwdev->hci.ops->recovery_start(rtwdev); 3274 } 3275 3276 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3277 { 3278 if (rtwdev->hci.ops->recovery_complete) 3279 rtwdev->hci.ops->recovery_complete(rtwdev); 3280 } 3281 3282 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3283 { 3284 return rtwdev->hci.ops->read8(rtwdev, addr); 3285 } 3286 3287 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3288 { 3289 return rtwdev->hci.ops->read16(rtwdev, addr); 3290 } 3291 3292 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3293 { 3294 return rtwdev->hci.ops->read32(rtwdev, addr); 3295 } 3296 3297 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3298 { 3299 rtwdev->hci.ops->write8(rtwdev, addr, data); 3300 } 3301 3302 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3303 { 3304 rtwdev->hci.ops->write16(rtwdev, addr, data); 3305 } 3306 3307 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3308 { 3309 rtwdev->hci.ops->write32(rtwdev, addr, data); 3310 } 3311 3312 static inline void 3313 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3314 { 3315 u8 val; 3316 3317 val = rtw89_read8(rtwdev, addr); 3318 rtw89_write8(rtwdev, addr, val | bit); 3319 } 3320 3321 static inline void 3322 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3323 { 3324 u16 val; 3325 3326 val = rtw89_read16(rtwdev, addr); 3327 rtw89_write16(rtwdev, addr, val | bit); 3328 } 3329 3330 static inline void 3331 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3332 { 3333 u32 val; 3334 3335 val = rtw89_read32(rtwdev, addr); 3336 rtw89_write32(rtwdev, addr, val | bit); 3337 } 3338 3339 static inline void 3340 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3341 { 3342 u8 val; 3343 3344 val = rtw89_read8(rtwdev, addr); 3345 rtw89_write8(rtwdev, addr, val & ~bit); 3346 } 3347 3348 static inline void 3349 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3350 { 3351 u16 val; 3352 3353 val = rtw89_read16(rtwdev, addr); 3354 rtw89_write16(rtwdev, addr, val & ~bit); 3355 } 3356 3357 static inline void 3358 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3359 { 3360 u32 val; 3361 3362 val = rtw89_read32(rtwdev, addr); 3363 rtw89_write32(rtwdev, addr, val & ~bit); 3364 } 3365 3366 static inline u32 3367 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3368 { 3369 u32 shift = __ffs(mask); 3370 u32 orig; 3371 u32 ret; 3372 3373 orig = rtw89_read32(rtwdev, addr); 3374 ret = (orig & mask) >> shift; 3375 3376 return ret; 3377 } 3378 3379 static inline u16 3380 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3381 { 3382 u32 shift = __ffs(mask); 3383 u32 orig; 3384 u32 ret; 3385 3386 orig = rtw89_read16(rtwdev, addr); 3387 ret = (orig & mask) >> shift; 3388 3389 return ret; 3390 } 3391 3392 static inline u8 3393 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3394 { 3395 u32 shift = __ffs(mask); 3396 u32 orig; 3397 u32 ret; 3398 3399 orig = rtw89_read8(rtwdev, addr); 3400 ret = (orig & mask) >> shift; 3401 3402 return ret; 3403 } 3404 3405 static inline void 3406 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3407 { 3408 u32 shift = __ffs(mask); 3409 u32 orig; 3410 u32 set; 3411 3412 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3413 3414 orig = rtw89_read32(rtwdev, addr); 3415 set = (orig & ~mask) | ((data << shift) & mask); 3416 rtw89_write32(rtwdev, addr, set); 3417 } 3418 3419 static inline void 3420 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3421 { 3422 u32 shift; 3423 u16 orig, set; 3424 3425 mask &= 0xffff; 3426 shift = __ffs(mask); 3427 3428 orig = rtw89_read16(rtwdev, addr); 3429 set = (orig & ~mask) | ((data << shift) & mask); 3430 rtw89_write16(rtwdev, addr, set); 3431 } 3432 3433 static inline void 3434 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3435 { 3436 u32 shift; 3437 u8 orig, set; 3438 3439 mask &= 0xff; 3440 shift = __ffs(mask); 3441 3442 orig = rtw89_read8(rtwdev, addr); 3443 set = (orig & ~mask) | ((data << shift) & mask); 3444 rtw89_write8(rtwdev, addr, set); 3445 } 3446 3447 static inline u32 3448 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3449 u32 addr, u32 mask) 3450 { 3451 u32 val; 3452 3453 mutex_lock(&rtwdev->rf_mutex); 3454 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3455 mutex_unlock(&rtwdev->rf_mutex); 3456 3457 return val; 3458 } 3459 3460 static inline void 3461 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3462 u32 addr, u32 mask, u32 data) 3463 { 3464 mutex_lock(&rtwdev->rf_mutex); 3465 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3466 mutex_unlock(&rtwdev->rf_mutex); 3467 } 3468 3469 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3470 { 3471 void *p = rtwtxq; 3472 3473 return container_of(p, struct ieee80211_txq, drv_priv); 3474 } 3475 3476 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3477 struct ieee80211_txq *txq) 3478 { 3479 struct rtw89_txq *rtwtxq; 3480 3481 if (!txq) 3482 return; 3483 3484 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3485 INIT_LIST_HEAD(&rtwtxq->list); 3486 } 3487 3488 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3489 { 3490 void *p = rtwvif; 3491 3492 return container_of(p, struct ieee80211_vif, drv_priv); 3493 } 3494 3495 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3496 { 3497 void *p = rtwsta; 3498 3499 return container_of(p, struct ieee80211_sta, drv_priv); 3500 } 3501 3502 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3503 { 3504 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3505 } 3506 3507 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3508 { 3509 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3510 } 3511 3512 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3513 { 3514 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3515 return RATE_INFO_BW_160; 3516 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3517 return RATE_INFO_BW_80; 3518 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3519 return RATE_INFO_BW_40; 3520 else 3521 return RATE_INFO_BW_20; 3522 } 3523 3524 static inline 3525 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 3526 { 3527 switch (hw_band) { 3528 default: 3529 case RTW89_BAND_2G: 3530 return NL80211_BAND_2GHZ; 3531 case RTW89_BAND_5G: 3532 return NL80211_BAND_5GHZ; 3533 case RTW89_BAND_6G: 3534 return NL80211_BAND_6GHZ; 3535 } 3536 } 3537 3538 static inline 3539 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 3540 { 3541 switch (width) { 3542 default: 3543 WARN(1, "Not support bandwidth %d\n", width); 3544 fallthrough; 3545 case NL80211_CHAN_WIDTH_20_NOHT: 3546 case NL80211_CHAN_WIDTH_20: 3547 return RTW89_CHANNEL_WIDTH_20; 3548 case NL80211_CHAN_WIDTH_40: 3549 return RTW89_CHANNEL_WIDTH_40; 3550 case NL80211_CHAN_WIDTH_80: 3551 return RTW89_CHANNEL_WIDTH_80; 3552 case NL80211_CHAN_WIDTH_160: 3553 return RTW89_CHANNEL_WIDTH_160; 3554 } 3555 } 3556 3557 static inline 3558 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3559 struct rtw89_sta *rtwsta) 3560 { 3561 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE && rtwsta) 3562 return &rtwsta->addr_cam; 3563 return &rtwvif->addr_cam; 3564 } 3565 3566 static inline 3567 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3568 struct rtw89_channel_help_params *p) 3569 { 3570 rtwdev->chip->ops->set_channel_help(rtwdev, true, p); 3571 } 3572 3573 static inline 3574 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3575 struct rtw89_channel_help_params *p) 3576 { 3577 rtwdev->chip->ops->set_channel_help(rtwdev, false, p); 3578 } 3579 3580 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3581 { 3582 const struct rtw89_chip_info *chip = rtwdev->chip; 3583 3584 if (chip->ops->fem_setup) 3585 chip->ops->fem_setup(rtwdev); 3586 } 3587 3588 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3589 { 3590 const struct rtw89_chip_info *chip = rtwdev->chip; 3591 3592 if (chip->ops->bb_sethw) 3593 chip->ops->bb_sethw(rtwdev); 3594 } 3595 3596 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3597 { 3598 const struct rtw89_chip_info *chip = rtwdev->chip; 3599 3600 if (chip->ops->rfk_init) 3601 chip->ops->rfk_init(rtwdev); 3602 } 3603 3604 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 3605 { 3606 const struct rtw89_chip_info *chip = rtwdev->chip; 3607 3608 if (chip->ops->rfk_channel) 3609 chip->ops->rfk_channel(rtwdev); 3610 } 3611 3612 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev) 3613 { 3614 const struct rtw89_chip_info *chip = rtwdev->chip; 3615 3616 if (chip->ops->rfk_band_changed) 3617 chip->ops->rfk_band_changed(rtwdev); 3618 } 3619 3620 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 3621 { 3622 const struct rtw89_chip_info *chip = rtwdev->chip; 3623 3624 if (chip->ops->rfk_scan) 3625 chip->ops->rfk_scan(rtwdev, start); 3626 } 3627 3628 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 3629 { 3630 const struct rtw89_chip_info *chip = rtwdev->chip; 3631 3632 if (chip->ops->rfk_track) 3633 chip->ops->rfk_track(rtwdev); 3634 } 3635 3636 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 3637 { 3638 const struct rtw89_chip_info *chip = rtwdev->chip; 3639 3640 if (chip->ops->set_txpwr_ctrl) 3641 chip->ops->set_txpwr_ctrl(rtwdev); 3642 } 3643 3644 static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev) 3645 { 3646 const struct rtw89_chip_info *chip = rtwdev->chip; 3647 u8 ch = rtwdev->hal.current_channel; 3648 3649 if (!ch) 3650 return; 3651 3652 if (chip->ops->set_txpwr) 3653 chip->ops->set_txpwr(rtwdev); 3654 } 3655 3656 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 3657 { 3658 const struct rtw89_chip_info *chip = rtwdev->chip; 3659 3660 if (chip->ops->power_trim) 3661 chip->ops->power_trim(rtwdev); 3662 } 3663 3664 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 3665 enum rtw89_phy_idx phy_idx) 3666 { 3667 const struct rtw89_chip_info *chip = rtwdev->chip; 3668 3669 if (chip->ops->init_txpwr_unit) 3670 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 3671 } 3672 3673 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 3674 enum rtw89_rf_path rf_path) 3675 { 3676 const struct rtw89_chip_info *chip = rtwdev->chip; 3677 3678 if (!chip->ops->get_thermal) 3679 return 0x10; 3680 3681 return chip->ops->get_thermal(rtwdev, rf_path); 3682 } 3683 3684 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 3685 struct rtw89_rx_phy_ppdu *phy_ppdu, 3686 struct ieee80211_rx_status *status) 3687 { 3688 const struct rtw89_chip_info *chip = rtwdev->chip; 3689 3690 if (chip->ops->query_ppdu) 3691 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 3692 } 3693 3694 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 3695 bool bt_en) 3696 { 3697 const struct rtw89_chip_info *chip = rtwdev->chip; 3698 3699 if (chip->ops->bb_ctrl_btc_preagc) 3700 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 3701 } 3702 3703 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 3704 { 3705 const struct rtw89_chip_info *chip = rtwdev->chip; 3706 3707 if (chip->ops->cfg_txrx_path) 3708 chip->ops->cfg_txrx_path(rtwdev); 3709 } 3710 3711 static inline 3712 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 3713 struct ieee80211_vif *vif) 3714 { 3715 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3716 const struct rtw89_chip_info *chip = rtwdev->chip; 3717 3718 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3719 return; 3720 3721 if (chip->ops->set_txpwr_ul_tb_offset) 3722 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 3723 } 3724 3725 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 3726 const struct rtw89_txpwr_table *tbl) 3727 { 3728 tbl->load(rtwdev, tbl); 3729 } 3730 3731 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 3732 { 3733 return rtwdev->regd->txpwr_regd[band]; 3734 } 3735 3736 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 3737 { 3738 const struct rtw89_chip_info *chip = rtwdev->chip; 3739 3740 if (chip->ops->ctrl_btg) 3741 chip->ops->ctrl_btg(rtwdev, btg); 3742 } 3743 3744 static inline 3745 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 3746 struct rtw89_tx_desc_info *desc_info, 3747 void *txdesc) 3748 { 3749 const struct rtw89_chip_info *chip = rtwdev->chip; 3750 3751 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 3752 } 3753 3754 static inline 3755 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 3756 struct rtw89_tx_desc_info *desc_info, 3757 void *txdesc) 3758 { 3759 const struct rtw89_chip_info *chip = rtwdev->chip; 3760 3761 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 3762 } 3763 3764 static inline 3765 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 3766 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3767 { 3768 const struct rtw89_chip_info *chip = rtwdev->chip; 3769 3770 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 3771 } 3772 3773 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 3774 { 3775 const struct rtw89_chip_info *chip = rtwdev->chip; 3776 3777 chip->ops->cfg_ctrl_path(rtwdev, wl); 3778 } 3779 3780 static inline 3781 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3782 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3783 { 3784 const struct rtw89_chip_info *chip = rtwdev->chip; 3785 3786 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 3787 } 3788 3789 static inline 3790 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3791 { 3792 const struct rtw89_chip_info *chip = rtwdev->chip; 3793 3794 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 3795 } 3796 3797 static inline 3798 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 3799 struct rtw89_vif *rtwvif, 3800 struct rtw89_sta *rtwsta) 3801 { 3802 const struct rtw89_chip_info *chip = rtwdev->chip; 3803 3804 if (!chip->ops->h2c_dctl_sec_cam) 3805 return 0; 3806 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 3807 } 3808 3809 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 3810 { 3811 __le16 fc = hdr->frame_control; 3812 3813 if (ieee80211_has_tods(fc)) 3814 return hdr->addr1; 3815 else if (ieee80211_has_fromds(fc)) 3816 return hdr->addr2; 3817 else 3818 return hdr->addr3; 3819 } 3820 3821 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 3822 { 3823 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 3824 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 3825 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 3826 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 3827 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 3828 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 3829 return true; 3830 return false; 3831 } 3832 3833 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 3834 enum rtw89_fw_type type) 3835 { 3836 struct rtw89_fw_info *fw_info = &rtwdev->fw; 3837 3838 if (type == RTW89_FW_WOWLAN) 3839 return &fw_info->wowlan; 3840 return &fw_info->normal; 3841 } 3842 3843 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3844 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 3845 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 3846 struct sk_buff *skb, bool fwdl); 3847 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 3848 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 3849 struct rtw89_tx_desc_info *desc_info, 3850 void *txdesc); 3851 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 3852 struct rtw89_tx_desc_info *desc_info, 3853 void *txdesc); 3854 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 3855 struct rtw89_tx_desc_info *desc_info, 3856 void *txdesc); 3857 void rtw89_core_rx(struct rtw89_dev *rtwdev, 3858 struct rtw89_rx_desc_info *desc_info, 3859 struct sk_buff *skb); 3860 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 3861 struct rtw89_rx_desc_info *desc_info, 3862 u8 *data, u32 data_offset); 3863 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 3864 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 3865 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 3866 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 3867 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3868 struct ieee80211_vif *vif, 3869 struct ieee80211_sta *sta); 3870 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3871 struct ieee80211_vif *vif, 3872 struct ieee80211_sta *sta); 3873 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3874 struct ieee80211_vif *vif, 3875 struct ieee80211_sta *sta); 3876 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3877 struct ieee80211_vif *vif, 3878 struct ieee80211_sta *sta); 3879 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3880 struct ieee80211_vif *vif, 3881 struct ieee80211_sta *sta); 3882 int rtw89_core_init(struct rtw89_dev *rtwdev); 3883 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 3884 int rtw89_core_register(struct rtw89_dev *rtwdev); 3885 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 3886 void rtw89_set_channel(struct rtw89_dev *rtwdev); 3887 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 3888 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 3889 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 3890 int rtw89_core_acquire_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3891 int rtw89_core_release_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3892 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 3893 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 3894 u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate); 3895 int rtw89_regd_init(struct rtw89_dev *rtwdev, 3896 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 3897 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 3898 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3899 struct rtw89_traffic_stats *stats); 3900 int rtw89_core_start(struct rtw89_dev *rtwdev); 3901 void rtw89_core_stop(struct rtw89_dev *rtwdev); 3902 void rtw89_core_update_beacon_work(struct work_struct *work); 3903 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3904 const u8 *mac_addr, bool hw_scan); 3905 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3906 struct ieee80211_vif *vif, bool hw_scan); 3907 3908 #endif 3909