1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 38 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 39 #define RTW89_HTC_VARIANT_HE 3 40 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 41 #define RTW89_HTC_VARIANT_HE_CID_OM 1 42 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 43 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 44 45 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 46 enum htc_om_channel_width { 47 HTC_OM_CHANNEL_WIDTH_20 = 0, 48 HTC_OM_CHANNEL_WIDTH_40 = 1, 49 HTC_OM_CHANNEL_WIDTH_80 = 2, 50 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 51 }; 52 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 53 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 54 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 55 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 56 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 57 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 58 59 #define RTW89_TF_PAD GENMASK(11, 0) 60 #define RTW89_TF_BASIC_USER_INFO_SZ 6 61 62 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 63 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 64 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 66 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 68 69 enum rtw89_subband { 70 RTW89_CH_2G = 0, 71 RTW89_CH_5G_BAND_1 = 1, 72 /* RTW89_CH_5G_BAND_2 = 2, unused */ 73 RTW89_CH_5G_BAND_3 = 3, 74 RTW89_CH_5G_BAND_4 = 4, 75 76 RTW89_CH_6G_BAND_IDX0, /* Low */ 77 RTW89_CH_6G_BAND_IDX1, /* Low */ 78 RTW89_CH_6G_BAND_IDX2, /* Mid */ 79 RTW89_CH_6G_BAND_IDX3, /* Mid */ 80 RTW89_CH_6G_BAND_IDX4, /* High */ 81 RTW89_CH_6G_BAND_IDX5, /* High */ 82 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 83 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 84 85 RTW89_SUBBAND_NR, 86 }; 87 88 enum rtw89_gain_offset { 89 RTW89_GAIN_OFFSET_2G_CCK, 90 RTW89_GAIN_OFFSET_2G_OFDM, 91 RTW89_GAIN_OFFSET_5G_LOW, 92 RTW89_GAIN_OFFSET_5G_MID, 93 RTW89_GAIN_OFFSET_5G_HIGH, 94 95 RTW89_GAIN_OFFSET_NR, 96 }; 97 98 enum rtw89_hci_type { 99 RTW89_HCI_TYPE_PCIE, 100 RTW89_HCI_TYPE_USB, 101 RTW89_HCI_TYPE_SDIO, 102 }; 103 104 enum rtw89_core_chip_id { 105 RTL8852A, 106 RTL8852B, 107 RTL8852C, 108 }; 109 110 enum rtw89_cv { 111 CHIP_CAV, 112 CHIP_CBV, 113 CHIP_CCV, 114 CHIP_CDV, 115 CHIP_CEV, 116 CHIP_CFV, 117 CHIP_CV_MAX, 118 CHIP_CV_INVALID = CHIP_CV_MAX, 119 }; 120 121 enum rtw89_core_tx_type { 122 RTW89_CORE_TX_TYPE_DATA, 123 RTW89_CORE_TX_TYPE_MGMT, 124 RTW89_CORE_TX_TYPE_FWCMD, 125 }; 126 127 enum rtw89_core_rx_type { 128 RTW89_CORE_RX_TYPE_WIFI = 0, 129 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 130 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 131 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 132 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 133 RTW89_CORE_RX_TYPE_SS2FW = 5, 134 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 135 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 136 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 137 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 138 RTW89_CORE_RX_TYPE_C2H = 10, 139 RTW89_CORE_RX_TYPE_CSI = 11, 140 RTW89_CORE_RX_TYPE_CQI = 12, 141 RTW89_CORE_RX_TYPE_H2C = 13, 142 RTW89_CORE_RX_TYPE_FWDL = 14, 143 }; 144 145 enum rtw89_txq_flags { 146 RTW89_TXQ_F_AMPDU = 0, 147 RTW89_TXQ_F_BLOCK_BA = 1, 148 RTW89_TXQ_F_FORBID_BA = 2, 149 }; 150 151 enum rtw89_net_type { 152 RTW89_NET_TYPE_NO_LINK = 0, 153 RTW89_NET_TYPE_AD_HOC = 1, 154 RTW89_NET_TYPE_INFRA = 2, 155 RTW89_NET_TYPE_AP_MODE = 3, 156 }; 157 158 enum rtw89_wifi_role { 159 RTW89_WIFI_ROLE_NONE, 160 RTW89_WIFI_ROLE_STATION, 161 RTW89_WIFI_ROLE_AP, 162 RTW89_WIFI_ROLE_AP_VLAN, 163 RTW89_WIFI_ROLE_ADHOC, 164 RTW89_WIFI_ROLE_ADHOC_MASTER, 165 RTW89_WIFI_ROLE_MESH_POINT, 166 RTW89_WIFI_ROLE_MONITOR, 167 RTW89_WIFI_ROLE_P2P_DEVICE, 168 RTW89_WIFI_ROLE_P2P_CLIENT, 169 RTW89_WIFI_ROLE_P2P_GO, 170 RTW89_WIFI_ROLE_NAN, 171 RTW89_WIFI_ROLE_MLME_MAX 172 }; 173 174 enum rtw89_upd_mode { 175 RTW89_ROLE_CREATE, 176 RTW89_ROLE_REMOVE, 177 RTW89_ROLE_TYPE_CHANGE, 178 RTW89_ROLE_INFO_CHANGE, 179 RTW89_ROLE_CON_DISCONN 180 }; 181 182 enum rtw89_self_role { 183 RTW89_SELF_ROLE_CLIENT, 184 RTW89_SELF_ROLE_AP, 185 RTW89_SELF_ROLE_AP_CLIENT 186 }; 187 188 enum rtw89_msk_sO_el { 189 RTW89_NO_MSK, 190 RTW89_SMA, 191 RTW89_TMA, 192 RTW89_BSSID 193 }; 194 195 enum rtw89_sch_tx_sel { 196 RTW89_SCH_TX_SEL_ALL, 197 RTW89_SCH_TX_SEL_HIQ, 198 RTW89_SCH_TX_SEL_MG0, 199 RTW89_SCH_TX_SEL_MACID, 200 }; 201 202 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 203 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 204 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 205 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 206 */ 207 enum rtw89_add_cam_sec_mode { 208 RTW89_ADDR_CAM_SEC_NONE = 0, 209 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 210 RTW89_ADDR_CAM_SEC_NORMAL = 2, 211 RTW89_ADDR_CAM_SEC_4GROUP = 3, 212 }; 213 214 enum rtw89_sec_key_type { 215 RTW89_SEC_KEY_TYPE_NONE = 0, 216 RTW89_SEC_KEY_TYPE_WEP40 = 1, 217 RTW89_SEC_KEY_TYPE_WEP104 = 2, 218 RTW89_SEC_KEY_TYPE_TKIP = 3, 219 RTW89_SEC_KEY_TYPE_WAPI = 4, 220 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 221 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 222 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 223 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 224 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 225 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 226 }; 227 228 enum rtw89_port { 229 RTW89_PORT_0 = 0, 230 RTW89_PORT_1 = 1, 231 RTW89_PORT_2 = 2, 232 RTW89_PORT_3 = 3, 233 RTW89_PORT_4 = 4, 234 RTW89_PORT_NUM 235 }; 236 237 enum rtw89_band { 238 RTW89_BAND_2G = 0, 239 RTW89_BAND_5G = 1, 240 RTW89_BAND_6G = 2, 241 RTW89_BAND_MAX, 242 }; 243 244 enum rtw89_hw_rate { 245 RTW89_HW_RATE_CCK1 = 0x0, 246 RTW89_HW_RATE_CCK2 = 0x1, 247 RTW89_HW_RATE_CCK5_5 = 0x2, 248 RTW89_HW_RATE_CCK11 = 0x3, 249 RTW89_HW_RATE_OFDM6 = 0x4, 250 RTW89_HW_RATE_OFDM9 = 0x5, 251 RTW89_HW_RATE_OFDM12 = 0x6, 252 RTW89_HW_RATE_OFDM18 = 0x7, 253 RTW89_HW_RATE_OFDM24 = 0x8, 254 RTW89_HW_RATE_OFDM36 = 0x9, 255 RTW89_HW_RATE_OFDM48 = 0xA, 256 RTW89_HW_RATE_OFDM54 = 0xB, 257 RTW89_HW_RATE_MCS0 = 0x80, 258 RTW89_HW_RATE_MCS1 = 0x81, 259 RTW89_HW_RATE_MCS2 = 0x82, 260 RTW89_HW_RATE_MCS3 = 0x83, 261 RTW89_HW_RATE_MCS4 = 0x84, 262 RTW89_HW_RATE_MCS5 = 0x85, 263 RTW89_HW_RATE_MCS6 = 0x86, 264 RTW89_HW_RATE_MCS7 = 0x87, 265 RTW89_HW_RATE_MCS8 = 0x88, 266 RTW89_HW_RATE_MCS9 = 0x89, 267 RTW89_HW_RATE_MCS10 = 0x8A, 268 RTW89_HW_RATE_MCS11 = 0x8B, 269 RTW89_HW_RATE_MCS12 = 0x8C, 270 RTW89_HW_RATE_MCS13 = 0x8D, 271 RTW89_HW_RATE_MCS14 = 0x8E, 272 RTW89_HW_RATE_MCS15 = 0x8F, 273 RTW89_HW_RATE_MCS16 = 0x90, 274 RTW89_HW_RATE_MCS17 = 0x91, 275 RTW89_HW_RATE_MCS18 = 0x92, 276 RTW89_HW_RATE_MCS19 = 0x93, 277 RTW89_HW_RATE_MCS20 = 0x94, 278 RTW89_HW_RATE_MCS21 = 0x95, 279 RTW89_HW_RATE_MCS22 = 0x96, 280 RTW89_HW_RATE_MCS23 = 0x97, 281 RTW89_HW_RATE_MCS24 = 0x98, 282 RTW89_HW_RATE_MCS25 = 0x99, 283 RTW89_HW_RATE_MCS26 = 0x9A, 284 RTW89_HW_RATE_MCS27 = 0x9B, 285 RTW89_HW_RATE_MCS28 = 0x9C, 286 RTW89_HW_RATE_MCS29 = 0x9D, 287 RTW89_HW_RATE_MCS30 = 0x9E, 288 RTW89_HW_RATE_MCS31 = 0x9F, 289 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 290 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 291 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 292 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 293 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 294 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 295 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 296 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 297 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 298 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 299 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 300 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 301 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 302 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 303 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 304 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 305 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 306 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 307 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 308 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 309 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 310 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 311 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 312 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 313 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 314 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 315 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 316 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 317 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 318 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 319 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 320 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 321 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 322 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 323 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 324 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 325 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 326 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 327 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 328 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 329 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 330 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 331 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 332 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 333 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 334 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 335 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 336 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 337 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 338 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 339 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 340 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 341 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 342 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 343 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 344 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 345 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 346 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 347 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 348 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 349 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 350 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 351 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 352 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 353 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 354 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 355 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 356 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 357 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 358 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 359 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 360 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 361 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 362 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 363 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 364 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 365 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 366 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 367 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 368 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 369 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 370 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 371 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 372 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 373 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 374 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 375 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 376 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 377 RTW89_HW_RATE_NR, 378 379 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 380 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 381 }; 382 383 /* 2G channels, 384 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 385 */ 386 #define RTW89_2G_CH_NUM 14 387 388 /* 5G channels, 389 * 36, 38, 40, 42, 44, 46, 48, 50, 390 * 52, 54, 56, 58, 60, 62, 64, 391 * 100, 102, 104, 106, 108, 110, 112, 114, 392 * 116, 118, 120, 122, 124, 126, 128, 130, 393 * 132, 134, 136, 138, 140, 142, 144, 394 * 149, 151, 153, 155, 157, 159, 161, 163, 395 * 165, 167, 169, 171, 173, 175, 177 396 */ 397 #define RTW89_5G_CH_NUM 53 398 399 /* 6G channels, 400 * 1, 3, 5, 7, 9, 11, 13, 15, 401 * 17, 19, 21, 23, 25, 27, 29, 33, 402 * 35, 37, 39, 41, 43, 45, 47, 49, 403 * 51, 53, 55, 57, 59, 61, 65, 67, 404 * 69, 71, 73, 75, 77, 79, 81, 83, 405 * 85, 87, 89, 91, 93, 97, 99, 101, 406 * 103, 105, 107, 109, 111, 113, 115, 117, 407 * 119, 121, 123, 125, 129, 131, 133, 135, 408 * 137, 139, 141, 143, 145, 147, 149, 151, 409 * 153, 155, 157, 161, 163, 165, 167, 169, 410 * 171, 173, 175, 177, 179, 181, 183, 185, 411 * 187, 189, 193, 195, 197, 199, 201, 203, 412 * 205, 207, 209, 211, 213, 215, 217, 219, 413 * 221, 225, 227, 229, 231, 233, 235, 237, 414 * 239, 241, 243, 245, 247, 249, 251, 253, 415 */ 416 #define RTW89_6G_CH_NUM 120 417 418 enum rtw89_rate_section { 419 RTW89_RS_CCK, 420 RTW89_RS_OFDM, 421 RTW89_RS_MCS, /* for HT/VHT/HE */ 422 RTW89_RS_HEDCM, 423 RTW89_RS_OFFSET, 424 RTW89_RS_MAX, 425 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 426 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 427 }; 428 429 enum rtw89_rate_max { 430 RTW89_RATE_CCK_MAX = 4, 431 RTW89_RATE_OFDM_MAX = 8, 432 RTW89_RATE_MCS_MAX = 12, 433 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 434 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 435 }; 436 437 enum rtw89_nss { 438 RTW89_NSS_1 = 0, 439 RTW89_NSS_2 = 1, 440 /* HE DCM only support 1ss and 2ss */ 441 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 442 RTW89_NSS_3 = 2, 443 RTW89_NSS_4 = 3, 444 RTW89_NSS_MAX, 445 }; 446 447 enum rtw89_ntx { 448 RTW89_1TX = 0, 449 RTW89_2TX = 1, 450 RTW89_NTX_NUM, 451 }; 452 453 enum rtw89_beamforming_type { 454 RTW89_NONBF = 0, 455 RTW89_BF = 1, 456 RTW89_BF_NUM, 457 }; 458 459 enum rtw89_regulation_type { 460 RTW89_WW = 0, 461 RTW89_ETSI = 1, 462 RTW89_FCC = 2, 463 RTW89_MKK = 3, 464 RTW89_NA = 4, 465 RTW89_IC = 5, 466 RTW89_KCC = 6, 467 RTW89_ACMA = 7, 468 RTW89_NCC = 8, 469 RTW89_MEXICO = 9, 470 RTW89_CHILE = 10, 471 RTW89_UKRAINE = 11, 472 RTW89_CN = 12, 473 RTW89_QATAR = 13, 474 RTW89_UK = 14, 475 RTW89_REGD_NUM, 476 }; 477 478 struct rtw89_txpwr_byrate { 479 s8 cck[RTW89_RATE_CCK_MAX]; 480 s8 ofdm[RTW89_RATE_OFDM_MAX]; 481 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 482 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 483 s8 offset[RTW89_RATE_OFFSET_MAX]; 484 }; 485 486 enum rtw89_bandwidth_section_num { 487 RTW89_BW20_SEC_NUM = 8, 488 RTW89_BW40_SEC_NUM = 4, 489 RTW89_BW80_SEC_NUM = 2, 490 }; 491 492 struct rtw89_txpwr_limit { 493 s8 cck_20m[RTW89_BF_NUM]; 494 s8 cck_40m[RTW89_BF_NUM]; 495 s8 ofdm[RTW89_BF_NUM]; 496 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 497 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 498 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 499 s8 mcs_160m[RTW89_BF_NUM]; 500 s8 mcs_40m_0p5[RTW89_BF_NUM]; 501 s8 mcs_40m_2p5[RTW89_BF_NUM]; 502 }; 503 504 #define RTW89_RU_SEC_NUM 8 505 506 struct rtw89_txpwr_limit_ru { 507 s8 ru26[RTW89_RU_SEC_NUM]; 508 s8 ru52[RTW89_RU_SEC_NUM]; 509 s8 ru106[RTW89_RU_SEC_NUM]; 510 }; 511 512 struct rtw89_rate_desc { 513 enum rtw89_nss nss; 514 enum rtw89_rate_section rs; 515 u8 idx; 516 }; 517 518 #define PHY_STS_HDR_LEN 8 519 #define RF_PATH_MAX 4 520 #define RTW89_MAX_PPDU_CNT 8 521 struct rtw89_rx_phy_ppdu { 522 u8 *buf; 523 u32 len; 524 u8 rssi_avg; 525 s8 rssi[RF_PATH_MAX]; 526 u8 mac_id; 527 u8 chan_idx; 528 u8 ie; 529 u16 rate; 530 bool to_self; 531 bool valid; 532 }; 533 534 enum rtw89_mac_idx { 535 RTW89_MAC_0 = 0, 536 RTW89_MAC_1 = 1, 537 }; 538 539 enum rtw89_phy_idx { 540 RTW89_PHY_0 = 0, 541 RTW89_PHY_1 = 1, 542 RTW89_PHY_MAX 543 }; 544 545 enum rtw89_rf_path { 546 RF_PATH_A = 0, 547 RF_PATH_B = 1, 548 RF_PATH_C = 2, 549 RF_PATH_D = 3, 550 RF_PATH_AB, 551 RF_PATH_AC, 552 RF_PATH_AD, 553 RF_PATH_BC, 554 RF_PATH_BD, 555 RF_PATH_CD, 556 RF_PATH_ABC, 557 RF_PATH_ABD, 558 RF_PATH_ACD, 559 RF_PATH_BCD, 560 RF_PATH_ABCD, 561 }; 562 563 enum rtw89_rf_path_bit { 564 RF_A = BIT(0), 565 RF_B = BIT(1), 566 RF_C = BIT(2), 567 RF_D = BIT(3), 568 569 RF_AB = (RF_A | RF_B), 570 RF_AC = (RF_A | RF_C), 571 RF_AD = (RF_A | RF_D), 572 RF_BC = (RF_B | RF_C), 573 RF_BD = (RF_B | RF_D), 574 RF_CD = (RF_C | RF_D), 575 576 RF_ABC = (RF_A | RF_B | RF_C), 577 RF_ABD = (RF_A | RF_B | RF_D), 578 RF_ACD = (RF_A | RF_C | RF_D), 579 RF_BCD = (RF_B | RF_C | RF_D), 580 581 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 582 }; 583 584 enum rtw89_bandwidth { 585 RTW89_CHANNEL_WIDTH_20 = 0, 586 RTW89_CHANNEL_WIDTH_40 = 1, 587 RTW89_CHANNEL_WIDTH_80 = 2, 588 RTW89_CHANNEL_WIDTH_160 = 3, 589 RTW89_CHANNEL_WIDTH_80_80 = 4, 590 RTW89_CHANNEL_WIDTH_5 = 5, 591 RTW89_CHANNEL_WIDTH_10 = 6, 592 }; 593 594 enum rtw89_ps_mode { 595 RTW89_PS_MODE_NONE = 0, 596 RTW89_PS_MODE_RFOFF = 1, 597 RTW89_PS_MODE_CLK_GATED = 2, 598 RTW89_PS_MODE_PWR_GATED = 3, 599 }; 600 601 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 602 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 603 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 604 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 605 606 enum rtw89_ru_bandwidth { 607 RTW89_RU26 = 0, 608 RTW89_RU52 = 1, 609 RTW89_RU106 = 2, 610 RTW89_RU_NUM, 611 }; 612 613 enum rtw89_sc_offset { 614 RTW89_SC_DONT_CARE = 0, 615 RTW89_SC_20_UPPER = 1, 616 RTW89_SC_20_LOWER = 2, 617 RTW89_SC_20_UPMOST = 3, 618 RTW89_SC_20_LOWEST = 4, 619 RTW89_SC_20_UP2X = 5, 620 RTW89_SC_20_LOW2X = 6, 621 RTW89_SC_20_UP3X = 7, 622 RTW89_SC_20_LOW3X = 8, 623 RTW89_SC_40_UPPER = 9, 624 RTW89_SC_40_LOWER = 10, 625 }; 626 627 struct rtw89_channel_params { 628 u8 center_chan; 629 u32 center_freq; 630 u8 primary_chan; 631 u8 bandwidth; 632 u8 pri_ch_idx; 633 u8 band_type; 634 u8 subband_type; 635 }; 636 637 struct rtw89_channel_help_params { 638 u32 tx_en; 639 }; 640 641 struct rtw89_port_reg { 642 u32 port_cfg; 643 u32 tbtt_prohib; 644 u32 bcn_area; 645 u32 bcn_early; 646 u32 tbtt_early; 647 u32 tbtt_agg; 648 u32 bcn_space; 649 u32 bcn_forcetx; 650 u32 bcn_err_cnt; 651 u32 bcn_err_flag; 652 u32 dtim_ctrl; 653 u32 tbtt_shift; 654 u32 bcn_cnt_tmr; 655 u32 tsftr_l; 656 u32 tsftr_h; 657 }; 658 659 struct rtw89_txwd_body { 660 __le32 dword0; 661 __le32 dword1; 662 __le32 dword2; 663 __le32 dword3; 664 __le32 dword4; 665 __le32 dword5; 666 } __packed; 667 668 struct rtw89_txwd_body_v1 { 669 __le32 dword0; 670 __le32 dword1; 671 __le32 dword2; 672 __le32 dword3; 673 __le32 dword4; 674 __le32 dword5; 675 __le32 dword6; 676 __le32 dword7; 677 } __packed; 678 679 struct rtw89_txwd_info { 680 __le32 dword0; 681 __le32 dword1; 682 __le32 dword2; 683 __le32 dword3; 684 __le32 dword4; 685 __le32 dword5; 686 } __packed; 687 688 struct rtw89_rx_desc_info { 689 u16 pkt_size; 690 u8 pkt_type; 691 u8 drv_info_size; 692 u8 shift; 693 u8 wl_hd_iv_len; 694 bool long_rxdesc; 695 bool bb_sel; 696 bool mac_info_valid; 697 u16 data_rate; 698 u8 gi_ltf; 699 u8 bw; 700 u32 free_run_cnt; 701 u8 user_id; 702 bool sr_en; 703 u8 ppdu_cnt; 704 u8 ppdu_type; 705 bool icv_err; 706 bool crc32_err; 707 bool hw_dec; 708 bool sw_dec; 709 bool addr1_match; 710 u8 frag; 711 u16 seq; 712 u8 frame_type; 713 u8 rx_pl_id; 714 bool addr_cam_valid; 715 u8 addr_cam_id; 716 u8 sec_cam_id; 717 u8 mac_id; 718 u16 offset; 719 bool ready; 720 }; 721 722 struct rtw89_rxdesc_short { 723 __le32 dword0; 724 __le32 dword1; 725 __le32 dword2; 726 __le32 dword3; 727 } __packed; 728 729 struct rtw89_rxdesc_long { 730 __le32 dword0; 731 __le32 dword1; 732 __le32 dword2; 733 __le32 dword3; 734 __le32 dword4; 735 __le32 dword5; 736 __le32 dword6; 737 __le32 dword7; 738 } __packed; 739 740 struct rtw89_tx_desc_info { 741 u16 pkt_size; 742 u8 wp_offset; 743 u8 mac_id; 744 u8 qsel; 745 u8 ch_dma; 746 u8 hdr_llc_len; 747 bool is_bmc; 748 bool en_wd_info; 749 bool wd_page; 750 bool use_rate; 751 bool dis_data_fb; 752 bool tid_indicate; 753 bool agg_en; 754 bool bk; 755 u8 ampdu_density; 756 u8 ampdu_num; 757 bool sec_en; 758 u8 addr_info_nr; 759 u8 sec_keyid; 760 u8 sec_type; 761 u8 sec_cam_idx; 762 u8 sec_seq[6]; 763 u16 data_rate; 764 u16 data_retry_lowest_rate; 765 bool fw_dl; 766 u16 seq; 767 bool a_ctrl_bsr; 768 u8 hw_ssn_sel; 769 #define RTW89_MGMT_HW_SSN_SEL 1 770 u8 hw_seq_mode; 771 #define RTW89_MGMT_HW_SEQ_MODE 1 772 bool hiq; 773 u8 port; 774 }; 775 776 struct rtw89_core_tx_request { 777 enum rtw89_core_tx_type tx_type; 778 779 struct sk_buff *skb; 780 struct ieee80211_vif *vif; 781 struct ieee80211_sta *sta; 782 struct rtw89_tx_desc_info desc_info; 783 }; 784 785 struct rtw89_txq { 786 struct list_head list; 787 unsigned long flags; 788 int wait_cnt; 789 }; 790 791 struct rtw89_mac_ax_gnt { 792 u8 gnt_bt_sw_en; 793 u8 gnt_bt; 794 u8 gnt_wl_sw_en; 795 u8 gnt_wl; 796 }; 797 798 #define RTW89_MAC_AX_COEX_GNT_NR 2 799 struct rtw89_mac_ax_coex_gnt { 800 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 801 }; 802 803 enum rtw89_btc_ncnt { 804 BTC_NCNT_POWER_ON = 0x0, 805 BTC_NCNT_POWER_OFF, 806 BTC_NCNT_INIT_COEX, 807 BTC_NCNT_SCAN_START, 808 BTC_NCNT_SCAN_FINISH, 809 BTC_NCNT_SPECIAL_PACKET, 810 BTC_NCNT_SWITCH_BAND, 811 BTC_NCNT_RFK_TIMEOUT, 812 BTC_NCNT_SHOW_COEX_INFO, 813 BTC_NCNT_ROLE_INFO, 814 BTC_NCNT_CONTROL, 815 BTC_NCNT_RADIO_STATE, 816 BTC_NCNT_CUSTOMERIZE, 817 BTC_NCNT_WL_RFK, 818 BTC_NCNT_WL_STA, 819 BTC_NCNT_FWINFO, 820 BTC_NCNT_TIMER, 821 BTC_NCNT_NUM 822 }; 823 824 enum rtw89_btc_btinfo { 825 BTC_BTINFO_L0 = 0, 826 BTC_BTINFO_L1, 827 BTC_BTINFO_L2, 828 BTC_BTINFO_L3, 829 BTC_BTINFO_H0, 830 BTC_BTINFO_H1, 831 BTC_BTINFO_H2, 832 BTC_BTINFO_H3, 833 BTC_BTINFO_MAX 834 }; 835 836 enum rtw89_btc_dcnt { 837 BTC_DCNT_RUN = 0x0, 838 BTC_DCNT_CX_RUNINFO, 839 BTC_DCNT_RPT, 840 BTC_DCNT_RPT_FREEZE, 841 BTC_DCNT_CYCLE, 842 BTC_DCNT_CYCLE_FREEZE, 843 BTC_DCNT_W1, 844 BTC_DCNT_W1_FREEZE, 845 BTC_DCNT_B1, 846 BTC_DCNT_B1_FREEZE, 847 BTC_DCNT_TDMA_NONSYNC, 848 BTC_DCNT_SLOT_NONSYNC, 849 BTC_DCNT_BTCNT_FREEZE, 850 BTC_DCNT_WL_SLOT_DRIFT, 851 BTC_DCNT_WL_STA_LAST, 852 BTC_DCNT_NUM, 853 }; 854 855 enum rtw89_btc_wl_state_cnt { 856 BTC_WCNT_SCANAP = 0x0, 857 BTC_WCNT_DHCP, 858 BTC_WCNT_EAPOL, 859 BTC_WCNT_ARP, 860 BTC_WCNT_SCBDUPDATE, 861 BTC_WCNT_RFK_REQ, 862 BTC_WCNT_RFK_GO, 863 BTC_WCNT_RFK_REJECT, 864 BTC_WCNT_RFK_TIMEOUT, 865 BTC_WCNT_CH_UPDATE, 866 BTC_WCNT_NUM 867 }; 868 869 enum rtw89_btc_bt_state_cnt { 870 BTC_BCNT_RETRY = 0x0, 871 BTC_BCNT_REINIT, 872 BTC_BCNT_REENABLE, 873 BTC_BCNT_SCBDREAD, 874 BTC_BCNT_RELINK, 875 BTC_BCNT_IGNOWL, 876 BTC_BCNT_INQPAG, 877 BTC_BCNT_INQ, 878 BTC_BCNT_PAGE, 879 BTC_BCNT_ROLESW, 880 BTC_BCNT_AFH, 881 BTC_BCNT_INFOUPDATE, 882 BTC_BCNT_INFOSAME, 883 BTC_BCNT_SCBDUPDATE, 884 BTC_BCNT_HIPRI_TX, 885 BTC_BCNT_HIPRI_RX, 886 BTC_BCNT_LOPRI_TX, 887 BTC_BCNT_LOPRI_RX, 888 BTC_BCNT_POLUT, 889 BTC_BCNT_RATECHG, 890 BTC_BCNT_NUM 891 }; 892 893 enum rtw89_btc_bt_profile { 894 BTC_BT_NOPROFILE = 0, 895 BTC_BT_HFP = BIT(0), 896 BTC_BT_HID = BIT(1), 897 BTC_BT_A2DP = BIT(2), 898 BTC_BT_PAN = BIT(3), 899 BTC_PROFILE_MAX = 4, 900 }; 901 902 struct rtw89_btc_ant_info { 903 u8 type; /* shared, dedicated */ 904 u8 num; 905 u8 isolation; 906 907 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 908 u8 diversity: 1; 909 }; 910 911 enum rtw89_tfc_dir { 912 RTW89_TFC_UL, 913 RTW89_TFC_DL, 914 }; 915 916 struct rtw89_btc_wl_smap { 917 u32 busy: 1; 918 u32 scan: 1; 919 u32 connecting: 1; 920 u32 roaming: 1; 921 u32 _4way: 1; 922 u32 rf_off: 1; 923 u32 lps: 1; 924 u32 ips: 1; 925 u32 init_ok: 1; 926 u32 traffic_dir : 2; 927 u32 rf_off_pre: 1; 928 u32 lps_pre: 1; 929 }; 930 931 enum rtw89_tfc_lv { 932 RTW89_TFC_IDLE, 933 RTW89_TFC_ULTRA_LOW, 934 RTW89_TFC_LOW, 935 RTW89_TFC_MID, 936 RTW89_TFC_HIGH, 937 }; 938 939 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 940 DECLARE_EWMA(tp, 10, 2); 941 942 struct rtw89_traffic_stats { 943 /* units in bytes */ 944 u64 tx_unicast; 945 u64 rx_unicast; 946 u32 tx_avg_len; 947 u32 rx_avg_len; 948 949 /* count for packets */ 950 u64 tx_cnt; 951 u64 rx_cnt; 952 953 /* units in Mbps */ 954 u32 tx_throughput; 955 u32 rx_throughput; 956 u32 tx_throughput_raw; 957 u32 rx_throughput_raw; 958 959 u32 rx_tf_acc; 960 u32 rx_tf_periodic; 961 962 enum rtw89_tfc_lv tx_tfc_lv; 963 enum rtw89_tfc_lv rx_tfc_lv; 964 struct ewma_tp tx_ewma_tp; 965 struct ewma_tp rx_ewma_tp; 966 967 u16 tx_rate; 968 u16 rx_rate; 969 }; 970 971 struct rtw89_btc_statistic { 972 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 973 struct rtw89_traffic_stats traffic; 974 }; 975 976 #define BTC_WL_RSSI_THMAX 4 977 978 struct rtw89_btc_wl_link_info { 979 struct rtw89_btc_statistic stat; 980 enum rtw89_tfc_dir dir; 981 u8 rssi_state[BTC_WL_RSSI_THMAX]; 982 u8 mac_addr[ETH_ALEN]; 983 u8 busy; 984 u8 ch; 985 u8 bw; 986 u8 band; 987 u8 role; 988 u8 pid; 989 u8 phy; 990 u8 dtim_period; 991 u8 mode; 992 993 u8 mac_id; 994 u8 tx_retry; 995 996 u32 bcn_period; 997 u32 busy_t; 998 u32 tx_time; 999 u32 client_cnt; 1000 u32 rx_rate_drop_cnt; 1001 1002 u32 active: 1; 1003 u32 noa: 1; 1004 u32 client_ps: 1; 1005 u32 connected: 2; 1006 }; 1007 1008 union rtw89_btc_wl_state_map { 1009 u32 val; 1010 struct rtw89_btc_wl_smap map; 1011 }; 1012 1013 struct rtw89_btc_bt_hfp_desc { 1014 u32 exist: 1; 1015 u32 type: 2; 1016 u32 rsvd: 29; 1017 }; 1018 1019 struct rtw89_btc_bt_hid_desc { 1020 u32 exist: 1; 1021 u32 slot_info: 2; 1022 u32 pair_cnt: 2; 1023 u32 type: 8; 1024 u32 rsvd: 19; 1025 }; 1026 1027 struct rtw89_btc_bt_a2dp_desc { 1028 u8 exist: 1; 1029 u8 exist_last: 1; 1030 u8 play_latency: 1; 1031 u8 type: 3; 1032 u8 active: 1; 1033 u8 sink: 1; 1034 1035 u8 bitpool; 1036 u16 vendor_id; 1037 u32 device_name; 1038 u32 flush_time; 1039 }; 1040 1041 struct rtw89_btc_bt_pan_desc { 1042 u32 exist: 1; 1043 u32 type: 1; 1044 u32 active: 1; 1045 u32 rsvd: 29; 1046 }; 1047 1048 struct rtw89_btc_bt_rfk_info { 1049 u32 run: 1; 1050 u32 req: 1; 1051 u32 timeout: 1; 1052 u32 rsvd: 29; 1053 }; 1054 1055 union rtw89_btc_bt_rfk_info_map { 1056 u32 val; 1057 struct rtw89_btc_bt_rfk_info map; 1058 }; 1059 1060 struct rtw89_btc_bt_ver_info { 1061 u32 fw_coex; /* match with which coex_ver */ 1062 u32 fw; 1063 }; 1064 1065 struct rtw89_btc_bool_sta_chg { 1066 u32 now: 1; 1067 u32 last: 1; 1068 u32 remain: 1; 1069 u32 srvd: 29; 1070 }; 1071 1072 struct rtw89_btc_u8_sta_chg { 1073 u8 now; 1074 u8 last; 1075 u8 remain; 1076 u8 rsvd; 1077 }; 1078 1079 struct rtw89_btc_wl_scan_info { 1080 u8 band[RTW89_PHY_MAX]; 1081 u8 phy_map; 1082 u8 rsvd; 1083 }; 1084 1085 struct rtw89_btc_wl_dbcc_info { 1086 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1087 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1088 u8 real_band[RTW89_PHY_MAX]; 1089 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1090 }; 1091 1092 struct rtw89_btc_wl_active_role { 1093 u8 connected: 1; 1094 u8 pid: 3; 1095 u8 phy: 1; 1096 u8 noa: 1; 1097 u8 band: 2; 1098 1099 u8 client_ps: 1; 1100 u8 bw: 7; 1101 1102 u8 role; 1103 u8 ch; 1104 1105 u16 tx_lvl; 1106 u16 rx_lvl; 1107 u16 tx_rate; 1108 u16 rx_rate; 1109 }; 1110 1111 struct rtw89_btc_wl_role_info_bpos { 1112 u16 none: 1; 1113 u16 station: 1; 1114 u16 ap: 1; 1115 u16 vap: 1; 1116 u16 adhoc: 1; 1117 u16 adhoc_master: 1; 1118 u16 mesh: 1; 1119 u16 moniter: 1; 1120 u16 p2p_device: 1; 1121 u16 p2p_gc: 1; 1122 u16 p2p_go: 1; 1123 u16 nan: 1; 1124 }; 1125 1126 union rtw89_btc_wl_role_info_map { 1127 u16 val; 1128 struct rtw89_btc_wl_role_info_bpos role; 1129 }; 1130 1131 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1132 u8 connect_cnt; 1133 u8 link_mode; 1134 union rtw89_btc_wl_role_info_map role_map; 1135 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1136 }; 1137 1138 struct rtw89_btc_wl_ver_info { 1139 u32 fw_coex; /* match with which coex_ver */ 1140 u32 fw; 1141 u32 mac; 1142 u32 bb; 1143 u32 rf; 1144 }; 1145 1146 struct rtw89_btc_wl_afh_info { 1147 u8 en; 1148 u8 ch; 1149 u8 bw; 1150 u8 rsvd; 1151 } __packed; 1152 1153 struct rtw89_btc_wl_rfk_info { 1154 u32 state: 2; 1155 u32 path_map: 4; 1156 u32 phy_map: 2; 1157 u32 band: 2; 1158 u32 type: 8; 1159 u32 rsvd: 14; 1160 }; 1161 1162 struct rtw89_btc_bt_smap { 1163 u32 connect: 1; 1164 u32 ble_connect: 1; 1165 u32 acl_busy: 1; 1166 u32 sco_busy: 1; 1167 u32 mesh_busy: 1; 1168 u32 inq_pag: 1; 1169 }; 1170 1171 union rtw89_btc_bt_state_map { 1172 u32 val; 1173 struct rtw89_btc_bt_smap map; 1174 }; 1175 1176 #define BTC_BT_RSSI_THMAX 4 1177 #define BTC_BT_AFH_GROUP 12 1178 1179 struct rtw89_btc_bt_link_info { 1180 struct rtw89_btc_u8_sta_chg profile_cnt; 1181 struct rtw89_btc_bool_sta_chg multi_link; 1182 struct rtw89_btc_bool_sta_chg relink; 1183 struct rtw89_btc_bt_hfp_desc hfp_desc; 1184 struct rtw89_btc_bt_hid_desc hid_desc; 1185 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1186 struct rtw89_btc_bt_pan_desc pan_desc; 1187 union rtw89_btc_bt_state_map status; 1188 1189 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1190 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1191 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1192 u8 afh_map[BTC_BT_AFH_GROUP]; 1193 1194 u32 role_sw: 1; 1195 u32 slave_role: 1; 1196 u32 afh_update: 1; 1197 u32 cqddr: 1; 1198 u32 rssi: 8; 1199 u32 tx_3m: 1; 1200 u32 rsvd: 19; 1201 }; 1202 1203 struct rtw89_btc_3rdcx_info { 1204 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1205 u8 hw_coex; 1206 u16 rsvd; 1207 }; 1208 1209 struct rtw89_btc_dm_emap { 1210 u32 init: 1; 1211 u32 pta_owner: 1; 1212 u32 wl_rfk_timeout: 1; 1213 u32 bt_rfk_timeout: 1; 1214 1215 u32 wl_fw_hang: 1; 1216 u32 offload_mismatch: 1; 1217 u32 cycle_hang: 1; 1218 u32 w1_hang: 1; 1219 1220 u32 b1_hang: 1; 1221 u32 tdma_no_sync: 1; 1222 u32 wl_slot_drift: 1; 1223 }; 1224 1225 union rtw89_btc_dm_error_map { 1226 u32 val; 1227 struct rtw89_btc_dm_emap map; 1228 }; 1229 1230 struct rtw89_btc_rf_para { 1231 u32 tx_pwr_freerun; 1232 u32 rx_gain_freerun; 1233 u32 tx_pwr_perpkt; 1234 u32 rx_gain_perpkt; 1235 }; 1236 1237 struct rtw89_btc_wl_info { 1238 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1239 struct rtw89_btc_wl_rfk_info rfk_info; 1240 struct rtw89_btc_wl_ver_info ver_info; 1241 struct rtw89_btc_wl_afh_info afh_info; 1242 struct rtw89_btc_wl_role_info role_info; 1243 struct rtw89_btc_wl_scan_info scan_info; 1244 struct rtw89_btc_wl_dbcc_info dbcc_info; 1245 struct rtw89_btc_rf_para rf_para; 1246 union rtw89_btc_wl_state_map status; 1247 1248 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1249 u8 rssi_level; 1250 1251 u32 scbd; 1252 }; 1253 1254 struct rtw89_btc_module { 1255 struct rtw89_btc_ant_info ant; 1256 u8 rfe_type; 1257 u8 cv; 1258 1259 u8 bt_solo: 1; 1260 u8 bt_pos: 1; 1261 u8 switch_type: 1; 1262 1263 u8 rsvd; 1264 }; 1265 1266 #define RTW89_BTC_DM_MAXSTEP 30 1267 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1268 1269 struct rtw89_btc_dm_step { 1270 u16 step[RTW89_BTC_DM_MAXSTEP]; 1271 u8 step_pos; 1272 bool step_ov; 1273 }; 1274 1275 struct rtw89_btc_init_info { 1276 struct rtw89_btc_module module; 1277 u8 wl_guard_ch; 1278 1279 u8 wl_only: 1; 1280 u8 wl_init_ok: 1; 1281 u8 dbcc_en: 1; 1282 u8 cx_other: 1; 1283 u8 bt_only: 1; 1284 1285 u16 rsvd; 1286 }; 1287 1288 struct rtw89_btc_wl_tx_limit_para { 1289 u16 enable; 1290 u32 tx_time; /* unit: us */ 1291 u16 tx_retry; 1292 }; 1293 1294 struct rtw89_btc_bt_scan_info { 1295 u16 win; 1296 u16 intvl; 1297 u32 enable: 1; 1298 u32 interlace: 1; 1299 u32 rsvd: 30; 1300 }; 1301 1302 enum rtw89_btc_bt_scan_type { 1303 BTC_SCAN_INQ = 0, 1304 BTC_SCAN_PAGE, 1305 BTC_SCAN_BLE, 1306 BTC_SCAN_INIT, 1307 BTC_SCAN_TV, 1308 BTC_SCAN_ADV, 1309 BTC_SCAN_MAX1, 1310 }; 1311 1312 struct rtw89_btc_bt_info { 1313 struct rtw89_btc_bt_link_info link_info; 1314 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1315 struct rtw89_btc_bt_ver_info ver_info; 1316 struct rtw89_btc_bool_sta_chg enable; 1317 struct rtw89_btc_bool_sta_chg inq_pag; 1318 struct rtw89_btc_rf_para rf_para; 1319 union rtw89_btc_bt_rfk_info_map rfk_info; 1320 1321 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1322 1323 u32 scbd; 1324 u32 feature; 1325 1326 u32 mbx_avl: 1; 1327 u32 whql_test: 1; 1328 u32 igno_wl: 1; 1329 u32 reinit: 1; 1330 u32 ble_scan_en: 1; 1331 u32 btg_type: 1; 1332 u32 inq: 1; 1333 u32 pag: 1; 1334 u32 run_patch_code: 1; 1335 u32 hi_lna_rx: 1; 1336 u32 rsvd: 22; 1337 }; 1338 1339 struct rtw89_btc_cx { 1340 struct rtw89_btc_wl_info wl; 1341 struct rtw89_btc_bt_info bt; 1342 struct rtw89_btc_3rdcx_info other; 1343 u32 state_map; 1344 u32 cnt_bt[BTC_BCNT_NUM]; 1345 u32 cnt_wl[BTC_WCNT_NUM]; 1346 }; 1347 1348 struct rtw89_btc_fbtc_tdma { 1349 u8 type; 1350 u8 rxflctrl; 1351 u8 txpause; 1352 u8 wtgle_n; 1353 u8 leak_n; 1354 u8 ext_ctrl; 1355 u8 rsvd0; 1356 u8 rsvd1; 1357 } __packed; 1358 1359 #define CXMREG_MAX 30 1360 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1361 #define BTCRPT_VER 1 1362 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1363 1364 enum rtw89_btc_bt_rfk_counter { 1365 BTC_BCNT_RFK_REQ = 0, 1366 BTC_BCNT_RFK_GO = 1, 1367 BTC_BCNT_RFK_REJECT = 2, 1368 BTC_BCNT_RFK_FAIL = 3, 1369 BTC_BCNT_RFK_TIMEOUT = 4, 1370 BTC_BCNT_RFK_MAX 1371 }; 1372 1373 struct rtw89_btc_fbtc_rpt_ctrl { 1374 u16 fver; 1375 u16 rpt_cnt; /* tmr counters */ 1376 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1377 u32 wl_fw_cx_offload; 1378 u32 wl_fw_ver; 1379 u32 rpt_enable; 1380 u32 rpt_para; /* ms */ 1381 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1382 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1383 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1384 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1385 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1386 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1387 u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; 1388 u32 c2h_cnt; /* fw send c2h counter */ 1389 u32 h2c_cnt; /* fw recv h2c counter */ 1390 } __packed; 1391 1392 enum rtw89_fbtc_ext_ctrl_type { 1393 CXECTL_OFF = 0x0, /* tdma off */ 1394 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1395 CXECTL_EXT = 0x2, 1396 CXECTL_MAX 1397 }; 1398 1399 union rtw89_btc_fbtc_rxflct { 1400 u8 val; 1401 u8 type: 3; 1402 u8 tgln_n: 5; 1403 }; 1404 1405 enum rtw89_btc_cxst_state { 1406 CXST_OFF = 0x0, 1407 CXST_B2W = 0x1, 1408 CXST_W1 = 0x2, 1409 CXST_W2 = 0x3, 1410 CXST_W2B = 0x4, 1411 CXST_B1 = 0x5, 1412 CXST_B2 = 0x6, 1413 CXST_B3 = 0x7, 1414 CXST_B4 = 0x8, 1415 CXST_LK = 0x9, 1416 CXST_BLK = 0xa, 1417 CXST_E2G = 0xb, 1418 CXST_E5G = 0xc, 1419 CXST_EBT = 0xd, 1420 CXST_ENULL = 0xe, 1421 CXST_WLK = 0xf, 1422 CXST_W1FDD = 0x10, 1423 CXST_B1FDD = 0x11, 1424 CXST_MAX = 0x12, 1425 }; 1426 1427 enum { 1428 CXBCN_ALL = 0x0, 1429 CXBCN_ALL_OK, 1430 CXBCN_BT_SLOT, 1431 CXBCN_BT_OK, 1432 CXBCN_MAX 1433 }; 1434 1435 enum btc_slot_type { 1436 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1437 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1438 CXSTYPE_NUM, 1439 }; 1440 1441 enum { /* TIME */ 1442 CXT_BT = 0x0, 1443 CXT_WL = 0x1, 1444 CXT_MAX 1445 }; 1446 1447 enum { /* TIME-A2DP */ 1448 CXT_FLCTRL_OFF = 0x0, 1449 CXT_FLCTRL_ON = 0x1, 1450 CXT_FLCTRL_MAX 1451 }; 1452 1453 enum { /* STEP TYPE */ 1454 CXSTEP_NONE = 0x0, 1455 CXSTEP_EVNT = 0x1, 1456 CXSTEP_SLOT = 0x2, 1457 CXSTEP_MAX, 1458 }; 1459 1460 #define FCXGPIODBG_VER 1 1461 #define BTC_DBG_MAX1 32 1462 struct rtw89_btc_fbtc_gpio_dbg { 1463 u8 fver; 1464 u8 rsvd; 1465 u16 rsvd2; 1466 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1467 u32 pre_state; /* the debug signal is 1 or 0 */ 1468 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1469 } __packed; 1470 1471 #define FCXMREG_VER 1 1472 struct rtw89_btc_fbtc_mreg_val { 1473 u8 fver; 1474 u8 reg_num; 1475 __le16 rsvd; 1476 __le32 mreg_val[CXMREG_MAX]; 1477 } __packed; 1478 1479 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1480 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1481 .offset = cpu_to_le32(__offset), } 1482 1483 struct rtw89_btc_fbtc_mreg { 1484 __le16 type; 1485 __le16 bytes; 1486 __le32 offset; 1487 } __packed; 1488 1489 struct rtw89_btc_fbtc_slot { 1490 __le16 dur; 1491 __le32 cxtbl; 1492 __le16 cxtype; 1493 } __packed; 1494 1495 #define FCXSLOTS_VER 1 1496 struct rtw89_btc_fbtc_slots { 1497 u8 fver; 1498 u8 tbl_num; 1499 __le16 rsvd; 1500 __le32 update_map; 1501 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1502 } __packed; 1503 1504 #define FCXSTEP_VER 2 1505 struct rtw89_btc_fbtc_step { 1506 u8 type; 1507 u8 val; 1508 __le16 difft; 1509 } __packed; 1510 1511 struct rtw89_btc_fbtc_steps { 1512 u8 fver; 1513 u8 rsvd; 1514 __le16 cnt; 1515 __le16 pos_old; 1516 __le16 pos_new; 1517 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1518 } __packed; 1519 1520 #define FCXCYSTA_VER 2 1521 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1522 u8 fver; 1523 u8 rsvd; 1524 __le16 cycles; /* total cycle number */ 1525 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1526 __le16 a2dpept; /* a2dp empty cnt */ 1527 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1528 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1529 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1530 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1531 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1532 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1533 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1534 __le16 tmax_a2dpept; /* max a2dp empty time */ 1535 __le16 tavg_lk; /* avg leak-slot time */ 1536 __le16 tmax_lk; /* max leak-slot time */ 1537 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1538 __le32 bcn_cnt[CXBCN_MAX]; 1539 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1540 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1541 __le32 skip_cnt; 1542 __le32 exception; 1543 __le32 except_cnt; 1544 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1545 } __packed; 1546 1547 #define FCXNULLSTA_VER 1 1548 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1549 u8 fver; 1550 u8 rsvd; 1551 __le16 rsvd2; 1552 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1553 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1554 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1555 } __packed; 1556 1557 #define FCX_BTVER_VER 1 1558 struct rtw89_btc_fbtc_btver { 1559 u8 fver; 1560 u8 rsvd; 1561 __le16 rsvd2; 1562 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1563 __le32 fw_ver; 1564 __le32 feature; 1565 } __packed; 1566 1567 #define FCX_BTSCAN_VER 1 1568 struct rtw89_btc_fbtc_btscan { 1569 u8 fver; 1570 u8 rsvd; 1571 __le16 rsvd2; 1572 u8 scan[6]; 1573 } __packed; 1574 1575 #define FCX_BTAFH_VER 1 1576 struct rtw89_btc_fbtc_btafh { 1577 u8 fver; 1578 u8 rsvd; 1579 __le16 rsvd2; 1580 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1581 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1582 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1583 } __packed; 1584 1585 #define FCX_BTDEVINFO_VER 1 1586 struct rtw89_btc_fbtc_btdevinfo { 1587 u8 fver; 1588 u8 rsvd; 1589 __le16 vendor_id; 1590 __le32 dev_name; /* only 24 bits valid */ 1591 __le32 flush_time; 1592 } __packed; 1593 1594 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1595 struct rtw89_btc_rf_trx_para { 1596 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1597 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1598 u8 bt_tx_power; /* decrease Tx power (dB) */ 1599 u8 bt_rx_gain; /* LNA constrain level */ 1600 }; 1601 1602 struct rtw89_btc_dm { 1603 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1604 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1605 struct rtw89_btc_fbtc_tdma tdma; 1606 struct rtw89_btc_fbtc_tdma tdma_now; 1607 struct rtw89_mac_ax_coex_gnt gnt; 1608 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1609 struct rtw89_btc_rf_trx_para rf_trx_para; 1610 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1611 struct rtw89_btc_dm_step dm_step; 1612 union rtw89_btc_dm_error_map error; 1613 u32 cnt_dm[BTC_DCNT_NUM]; 1614 u32 cnt_notify[BTC_NCNT_NUM]; 1615 1616 u32 update_slot_map; 1617 u32 set_ant_path; 1618 1619 u32 wl_only: 1; 1620 u32 wl_fw_cx_offload: 1; 1621 u32 freerun: 1; 1622 u32 wl_ps_ctrl: 2; 1623 u32 wl_mimo_ps: 1; 1624 u32 leak_ap: 1; 1625 u32 noisy_level: 3; 1626 u32 coex_info_map: 8; 1627 u32 bt_only: 1; 1628 u32 wl_btg_rx: 1; 1629 u32 trx_para_level: 8; 1630 u32 wl_stb_chg: 1; 1631 u32 rsvd: 3; 1632 1633 u16 slot_dur[CXST_MAX]; 1634 1635 u8 run_reason; 1636 u8 run_action; 1637 }; 1638 1639 struct rtw89_btc_ctrl { 1640 u32 manual: 1; 1641 u32 igno_bt: 1; 1642 u32 always_freerun: 1; 1643 u32 trace_step: 16; 1644 u32 rsvd: 12; 1645 }; 1646 1647 struct rtw89_btc_dbg { 1648 /* cmd "rb" */ 1649 bool rb_done; 1650 u32 rb_val; 1651 }; 1652 1653 #define FCXTDMA_VER 1 1654 1655 enum rtw89_btc_btf_fw_event { 1656 BTF_EVNT_RPT = 0, 1657 BTF_EVNT_BT_INFO = 1, 1658 BTF_EVNT_BT_SCBD = 2, 1659 BTF_EVNT_BT_REG = 3, 1660 BTF_EVNT_CX_RUNINFO = 4, 1661 BTF_EVNT_BT_PSD = 5, 1662 BTF_EVNT_BUF_OVERFLOW, 1663 BTF_EVNT_C2H_LOOPBACK, 1664 BTF_EVNT_MAX, 1665 }; 1666 1667 enum btf_fw_event_report { 1668 BTC_RPT_TYPE_CTRL = 0x0, 1669 BTC_RPT_TYPE_TDMA, 1670 BTC_RPT_TYPE_SLOT, 1671 BTC_RPT_TYPE_CYSTA, 1672 BTC_RPT_TYPE_STEP, 1673 BTC_RPT_TYPE_NULLSTA, 1674 BTC_RPT_TYPE_MREG, 1675 BTC_RPT_TYPE_GPIO_DBG, 1676 BTC_RPT_TYPE_BT_VER, 1677 BTC_RPT_TYPE_BT_SCAN, 1678 BTC_RPT_TYPE_BT_AFH, 1679 BTC_RPT_TYPE_BT_DEVICE, 1680 BTC_RPT_TYPE_TEST, 1681 BTC_RPT_TYPE_MAX = 31 1682 }; 1683 1684 enum rtw_btc_btf_reg_type { 1685 REG_MAC = 0x0, 1686 REG_BB = 0x1, 1687 REG_RF = 0x2, 1688 REG_BT_RF = 0x3, 1689 REG_BT_MODEM = 0x4, 1690 REG_BT_BLUEWIZE = 0x5, 1691 REG_BT_VENDOR = 0x6, 1692 REG_BT_LE = 0x7, 1693 REG_MAX_TYPE, 1694 }; 1695 1696 struct rtw89_btc_rpt_cmn_info { 1697 u32 rx_cnt; 1698 u32 rx_len; 1699 u32 req_len; /* expected rsp len */ 1700 u8 req_fver; /* expected rsp fver */ 1701 u8 rsp_fver; /* fver from fw */ 1702 u8 valid; 1703 } __packed; 1704 1705 struct rtw89_btc_report_ctrl_state { 1706 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1707 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */ 1708 }; 1709 1710 struct rtw89_btc_rpt_fbtc_tdma { 1711 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1712 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1713 }; 1714 1715 struct rtw89_btc_rpt_fbtc_slots { 1716 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1717 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1718 }; 1719 1720 struct rtw89_btc_rpt_fbtc_cysta { 1721 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1722 struct rtw89_btc_fbtc_cysta finfo; /* info from fw */ 1723 }; 1724 1725 struct rtw89_btc_rpt_fbtc_step { 1726 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1727 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1728 }; 1729 1730 struct rtw89_btc_rpt_fbtc_nullsta { 1731 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1732 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1733 }; 1734 1735 struct rtw89_btc_rpt_fbtc_mreg { 1736 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1737 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1738 }; 1739 1740 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1741 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1742 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1743 }; 1744 1745 struct rtw89_btc_rpt_fbtc_btver { 1746 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1747 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1748 }; 1749 1750 struct rtw89_btc_rpt_fbtc_btscan { 1751 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1752 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1753 }; 1754 1755 struct rtw89_btc_rpt_fbtc_btafh { 1756 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1757 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1758 }; 1759 1760 struct rtw89_btc_rpt_fbtc_btdev { 1761 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1762 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1763 }; 1764 1765 enum rtw89_btc_btfre_type { 1766 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1767 BTFRE_UNDEF_TYPE, 1768 BTFRE_EXCEPTION, 1769 BTFRE_MAX, 1770 }; 1771 1772 struct rtw89_btc_btf_fwinfo { 1773 u32 cnt_c2h; 1774 u32 cnt_h2c; 1775 u32 cnt_h2c_fail; 1776 u32 event[BTF_EVNT_MAX]; 1777 1778 u32 err[BTFRE_MAX]; 1779 u32 len_mismch; 1780 u32 fver_mismch; 1781 u32 rpt_en_map; 1782 1783 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1784 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1785 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1786 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1787 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1788 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1789 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1790 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1791 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1792 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1793 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1794 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1795 }; 1796 1797 #define RTW89_BTC_POLICY_MAXLEN 512 1798 1799 struct rtw89_btc { 1800 struct rtw89_btc_cx cx; 1801 struct rtw89_btc_dm dm; 1802 struct rtw89_btc_ctrl ctrl; 1803 struct rtw89_btc_module mdinfo; 1804 struct rtw89_btc_btf_fwinfo fwinfo; 1805 struct rtw89_btc_dbg dbg; 1806 1807 struct work_struct eapol_notify_work; 1808 struct work_struct arp_notify_work; 1809 struct work_struct dhcp_notify_work; 1810 struct work_struct icmp_notify_work; 1811 1812 u32 bt_req_len; 1813 1814 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 1815 u16 policy_len; 1816 u16 policy_type; 1817 bool bt_req_en; 1818 bool update_policy_force; 1819 bool lps; 1820 }; 1821 1822 enum rtw89_ra_mode { 1823 RTW89_RA_MODE_CCK = BIT(0), 1824 RTW89_RA_MODE_OFDM = BIT(1), 1825 RTW89_RA_MODE_HT = BIT(2), 1826 RTW89_RA_MODE_VHT = BIT(3), 1827 RTW89_RA_MODE_HE = BIT(4), 1828 }; 1829 1830 enum rtw89_ra_report_mode { 1831 RTW89_RA_RPT_MODE_LEGACY, 1832 RTW89_RA_RPT_MODE_HT, 1833 RTW89_RA_RPT_MODE_VHT, 1834 RTW89_RA_RPT_MODE_HE, 1835 }; 1836 1837 enum rtw89_dig_noisy_level { 1838 RTW89_DIG_NOISY_LEVEL0 = -1, 1839 RTW89_DIG_NOISY_LEVEL1 = 0, 1840 RTW89_DIG_NOISY_LEVEL2 = 1, 1841 RTW89_DIG_NOISY_LEVEL3 = 2, 1842 RTW89_DIG_NOISY_LEVEL_MAX = 3, 1843 }; 1844 1845 enum rtw89_gi_ltf { 1846 RTW89_GILTF_LGI_4XHE32 = 0, 1847 RTW89_GILTF_SGI_4XHE08 = 1, 1848 RTW89_GILTF_2XHE16 = 2, 1849 RTW89_GILTF_2XHE08 = 3, 1850 RTW89_GILTF_1XHE16 = 4, 1851 RTW89_GILTF_1XHE08 = 5, 1852 RTW89_GILTF_MAX 1853 }; 1854 1855 enum rtw89_rx_frame_type { 1856 RTW89_RX_TYPE_MGNT = 0, 1857 RTW89_RX_TYPE_CTRL = 1, 1858 RTW89_RX_TYPE_DATA = 2, 1859 RTW89_RX_TYPE_RSVD = 3, 1860 }; 1861 1862 struct rtw89_ra_info { 1863 u8 is_dis_ra:1; 1864 /* Bit0 : CCK 1865 * Bit1 : OFDM 1866 * Bit2 : HT 1867 * Bit3 : VHT 1868 * Bit4 : HE 1869 */ 1870 u8 mode_ctrl:5; 1871 u8 bw_cap:2; 1872 u8 macid; 1873 u8 dcm_cap:1; 1874 u8 er_cap:1; 1875 u8 init_rate_lv:2; 1876 u8 upd_all:1; 1877 u8 en_sgi:1; 1878 u8 ldpc_cap:1; 1879 u8 stbc_cap:1; 1880 u8 ss_num:3; 1881 u8 giltf:3; 1882 u8 upd_bw_nss_mask:1; 1883 u8 upd_mask:1; 1884 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 1885 /* BFee CSI */ 1886 u8 band_num; 1887 u8 ra_csi_rate_en:1; 1888 u8 fixed_csi_rate_en:1; 1889 u8 cr_tbl_sel:1; 1890 u8 rsvd2:5; 1891 u8 csi_mcs_ss_idx; 1892 u8 csi_mode:2; 1893 u8 csi_gi_ltf:3; 1894 u8 csi_bw:3; 1895 }; 1896 1897 #define RTW89_PPDU_MAX_USR 4 1898 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 1899 #define RTW89_PPDU_MAC_INFO_SIZE 8 1900 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 1901 1902 #define RTW89_MAX_RX_AGG_NUM 64 1903 #define RTW89_MAX_TX_AGG_NUM 128 1904 1905 struct rtw89_ampdu_params { 1906 u16 agg_num; 1907 bool amsdu; 1908 }; 1909 1910 struct rtw89_ra_report { 1911 struct rate_info txrate; 1912 u32 bit_rate; 1913 u16 hw_rate; 1914 }; 1915 1916 DECLARE_EWMA(rssi, 10, 16); 1917 1918 #define RTW89_BA_CAM_NUM 2 1919 1920 struct rtw89_ba_cam_entry { 1921 u8 tid; 1922 }; 1923 1924 #define RTW89_MAX_ADDR_CAM_NUM 128 1925 #define RTW89_MAX_BSSID_CAM_NUM 20 1926 #define RTW89_MAX_SEC_CAM_NUM 128 1927 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 1928 1929 struct rtw89_addr_cam_entry { 1930 u8 addr_cam_idx; 1931 u8 offset; 1932 u8 len; 1933 u8 valid : 1; 1934 u8 addr_mask : 6; 1935 u8 wapi : 1; 1936 u8 mask_sel : 2; 1937 u8 bssid_cam_idx: 6; 1938 1939 u8 sec_ent_mode; 1940 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 1941 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 1942 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 1943 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 1944 }; 1945 1946 struct rtw89_bssid_cam_entry { 1947 u8 bssid[ETH_ALEN]; 1948 u8 phy_idx; 1949 u8 bssid_cam_idx; 1950 u8 offset; 1951 u8 len; 1952 u8 valid : 1; 1953 u8 num; 1954 }; 1955 1956 struct rtw89_sec_cam_entry { 1957 u8 sec_cam_idx; 1958 u8 offset; 1959 u8 len; 1960 u8 type : 4; 1961 u8 ext_key : 1; 1962 u8 spp_mode : 1; 1963 /* 256 bits */ 1964 u8 key[32]; 1965 }; 1966 1967 struct rtw89_sta { 1968 u8 mac_id; 1969 bool disassoc; 1970 struct rtw89_vif *rtwvif; 1971 struct rtw89_ra_info ra; 1972 struct rtw89_ra_report ra_report; 1973 int max_agg_wait; 1974 u8 prev_rssi; 1975 struct ewma_rssi avg_rssi; 1976 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 1977 struct ieee80211_rx_status rx_status; 1978 u16 rx_hw_rate; 1979 __le32 htc_template; 1980 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 1981 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 1982 1983 bool use_cfg_mask; 1984 struct cfg80211_bitrate_mask mask; 1985 1986 bool cctl_tx_time; 1987 u32 ampdu_max_time:4; 1988 bool cctl_tx_retry_limit; 1989 u32 data_tx_cnt_lmt:6; 1990 1991 DECLARE_BITMAP(ba_cam_map, RTW89_BA_CAM_NUM); 1992 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_BA_CAM_NUM]; 1993 }; 1994 1995 struct rtw89_efuse { 1996 bool valid; 1997 u8 xtal_cap; 1998 u8 addr[ETH_ALEN]; 1999 u8 rfe_type; 2000 char country_code[2]; 2001 }; 2002 2003 struct rtw89_phy_rate_pattern { 2004 u64 ra_mask; 2005 u16 rate; 2006 u8 ra_mode; 2007 bool enable; 2008 }; 2009 2010 struct rtw89_vif { 2011 struct list_head list; 2012 struct rtw89_dev *rtwdev; 2013 u8 mac_id; 2014 u8 port; 2015 u8 mac_addr[ETH_ALEN]; 2016 u8 bssid[ETH_ALEN]; 2017 u8 phy_idx; 2018 u8 mac_idx; 2019 u8 net_type; 2020 u8 wifi_role; 2021 u8 self_role; 2022 u8 wmm; 2023 u8 bcn_hit_cond; 2024 u8 hit_rule; 2025 bool trigger; 2026 bool lsig_txop; 2027 u8 tgt_ind; 2028 u8 frm_tgt_ind; 2029 bool wowlan_pattern; 2030 bool wowlan_uc; 2031 bool wowlan_magic; 2032 bool is_hesta; 2033 bool last_a_ctrl; 2034 struct work_struct update_beacon_work; 2035 struct rtw89_addr_cam_entry addr_cam; 2036 struct rtw89_bssid_cam_entry bssid_cam; 2037 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2038 struct rtw89_traffic_stats stats; 2039 struct rtw89_phy_rate_pattern rate_pattern; 2040 struct cfg80211_scan_request *scan_req; 2041 struct ieee80211_scan_ies *scan_ies; 2042 }; 2043 2044 enum rtw89_lv1_rcvy_step { 2045 RTW89_LV1_RCVY_STEP_1, 2046 RTW89_LV1_RCVY_STEP_2, 2047 }; 2048 2049 struct rtw89_hci_ops { 2050 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2051 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2052 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2053 void (*reset)(struct rtw89_dev *rtwdev); 2054 int (*start)(struct rtw89_dev *rtwdev); 2055 void (*stop)(struct rtw89_dev *rtwdev); 2056 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2057 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2058 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2059 2060 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2061 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2062 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2063 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2064 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2065 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2066 2067 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2068 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2069 int (*deinit)(struct rtw89_dev *rtwdev); 2070 2071 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2072 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2073 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2074 int (*napi_poll)(struct napi_struct *napi, int budget); 2075 2076 /* Deal with locks inside recovery_start and recovery_complete callbacks 2077 * by hci instance, and handle things which need to consider under SER. 2078 * e.g. turn on/off interrupts except for the one for halt notification. 2079 */ 2080 void (*recovery_start)(struct rtw89_dev *rtwdev); 2081 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2082 }; 2083 2084 struct rtw89_hci_info { 2085 const struct rtw89_hci_ops *ops; 2086 enum rtw89_hci_type type; 2087 u32 rpwm_addr; 2088 u32 cpwm_addr; 2089 bool paused; 2090 }; 2091 2092 struct rtw89_chip_ops { 2093 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2094 void (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2095 void (*bb_reset)(struct rtw89_dev *rtwdev, 2096 enum rtw89_phy_idx phy_idx); 2097 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2098 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2099 u32 addr, u32 mask); 2100 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2101 u32 addr, u32 mask, u32 data); 2102 void (*set_channel)(struct rtw89_dev *rtwdev, 2103 struct rtw89_channel_params *param); 2104 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2105 struct rtw89_channel_help_params *p); 2106 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2107 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2108 void (*fem_setup)(struct rtw89_dev *rtwdev); 2109 void (*rfk_init)(struct rtw89_dev *rtwdev); 2110 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2111 void (*rfk_band_changed)(struct rtw89_dev *rtwdev); 2112 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2113 void (*rfk_track)(struct rtw89_dev *rtwdev); 2114 void (*power_trim)(struct rtw89_dev *rtwdev); 2115 void (*set_txpwr)(struct rtw89_dev *rtwdev); 2116 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev); 2117 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2118 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2119 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2120 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2121 struct rtw89_rx_phy_ppdu *phy_ppdu, 2122 struct ieee80211_rx_status *status); 2123 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2124 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2125 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2126 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2127 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2128 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2129 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2130 struct rtw89_tx_desc_info *desc_info, 2131 void *txdesc); 2132 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2133 struct rtw89_tx_desc_info *desc_info, 2134 void *txdesc); 2135 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2136 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2137 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2138 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2139 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2140 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2141 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2142 struct rtw89_vif *rtwvif, 2143 struct rtw89_sta *rtwsta); 2144 2145 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2146 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2147 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2148 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2149 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2150 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2151 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2152 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2153 }; 2154 2155 enum rtw89_dma_ch { 2156 RTW89_DMA_ACH0 = 0, 2157 RTW89_DMA_ACH1 = 1, 2158 RTW89_DMA_ACH2 = 2, 2159 RTW89_DMA_ACH3 = 3, 2160 RTW89_DMA_ACH4 = 4, 2161 RTW89_DMA_ACH5 = 5, 2162 RTW89_DMA_ACH6 = 6, 2163 RTW89_DMA_ACH7 = 7, 2164 RTW89_DMA_B0MG = 8, 2165 RTW89_DMA_B0HI = 9, 2166 RTW89_DMA_B1MG = 10, 2167 RTW89_DMA_B1HI = 11, 2168 RTW89_DMA_H2C = 12, 2169 RTW89_DMA_CH_NUM = 13 2170 }; 2171 2172 enum rtw89_qta_mode { 2173 RTW89_QTA_SCC, 2174 RTW89_QTA_DLFW, 2175 2176 /* keep last */ 2177 RTW89_QTA_INVALID, 2178 }; 2179 2180 struct rtw89_hfc_ch_cfg { 2181 u16 min; 2182 u16 max; 2183 #define grp_0 0 2184 #define grp_1 1 2185 #define grp_num 2 2186 u8 grp; 2187 }; 2188 2189 struct rtw89_hfc_ch_info { 2190 u16 aval; 2191 u16 used; 2192 }; 2193 2194 struct rtw89_hfc_pub_cfg { 2195 u16 grp0; 2196 u16 grp1; 2197 u16 pub_max; 2198 u16 wp_thrd; 2199 }; 2200 2201 struct rtw89_hfc_pub_info { 2202 u16 g0_used; 2203 u16 g1_used; 2204 u16 g0_aval; 2205 u16 g1_aval; 2206 u16 pub_aval; 2207 u16 wp_aval; 2208 }; 2209 2210 struct rtw89_hfc_prec_cfg { 2211 u16 ch011_prec; 2212 u16 h2c_prec; 2213 u16 wp_ch07_prec; 2214 u16 wp_ch811_prec; 2215 u8 ch011_full_cond; 2216 u8 h2c_full_cond; 2217 u8 wp_ch07_full_cond; 2218 u8 wp_ch811_full_cond; 2219 }; 2220 2221 struct rtw89_hfc_param { 2222 bool en; 2223 bool h2c_en; 2224 u8 mode; 2225 const struct rtw89_hfc_ch_cfg *ch_cfg; 2226 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2227 struct rtw89_hfc_pub_cfg pub_cfg; 2228 struct rtw89_hfc_pub_info pub_info; 2229 struct rtw89_hfc_prec_cfg prec_cfg; 2230 }; 2231 2232 struct rtw89_hfc_param_ini { 2233 const struct rtw89_hfc_ch_cfg *ch_cfg; 2234 const struct rtw89_hfc_pub_cfg *pub_cfg; 2235 const struct rtw89_hfc_prec_cfg *prec_cfg; 2236 u8 mode; 2237 }; 2238 2239 struct rtw89_dle_size { 2240 u16 pge_size; 2241 u16 lnk_pge_num; 2242 u16 unlnk_pge_num; 2243 }; 2244 2245 struct rtw89_wde_quota { 2246 u16 hif; 2247 u16 wcpu; 2248 u16 pkt_in; 2249 u16 cpu_io; 2250 }; 2251 2252 struct rtw89_ple_quota { 2253 u16 cma0_tx; 2254 u16 cma1_tx; 2255 u16 c2h; 2256 u16 h2c; 2257 u16 wcpu; 2258 u16 mpdu_proc; 2259 u16 cma0_dma; 2260 u16 cma1_dma; 2261 u16 bb_rpt; 2262 u16 wd_rel; 2263 u16 cpu_io; 2264 u16 tx_rpt; 2265 }; 2266 2267 struct rtw89_dle_mem { 2268 enum rtw89_qta_mode mode; 2269 const struct rtw89_dle_size *wde_size; 2270 const struct rtw89_dle_size *ple_size; 2271 const struct rtw89_wde_quota *wde_min_qt; 2272 const struct rtw89_wde_quota *wde_max_qt; 2273 const struct rtw89_ple_quota *ple_min_qt; 2274 const struct rtw89_ple_quota *ple_max_qt; 2275 }; 2276 2277 struct rtw89_reg_def { 2278 u32 addr; 2279 u32 mask; 2280 }; 2281 2282 struct rtw89_reg2_def { 2283 u32 addr; 2284 u32 data; 2285 }; 2286 2287 struct rtw89_reg3_def { 2288 u32 addr; 2289 u32 mask; 2290 u32 data; 2291 }; 2292 2293 struct rtw89_reg5_def { 2294 u8 flag; /* recognized by parsers */ 2295 u8 path; 2296 u32 addr; 2297 u32 mask; 2298 u32 data; 2299 }; 2300 2301 struct rtw89_phy_table { 2302 const struct rtw89_reg2_def *regs; 2303 u32 n_regs; 2304 enum rtw89_rf_path rf_path; 2305 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2306 enum rtw89_rf_path rf_path, void *data); 2307 }; 2308 2309 struct rtw89_txpwr_table { 2310 const void *data; 2311 u32 size; 2312 void (*load)(struct rtw89_dev *rtwdev, 2313 const struct rtw89_txpwr_table *tbl); 2314 }; 2315 2316 struct rtw89_page_regs { 2317 u32 hci_fc_ctrl; 2318 u32 ch_page_ctrl; 2319 u32 ach_page_ctrl; 2320 u32 ach_page_info; 2321 u32 pub_page_info3; 2322 u32 pub_page_ctrl1; 2323 u32 pub_page_ctrl2; 2324 u32 pub_page_info1; 2325 u32 pub_page_info2; 2326 u32 wp_page_ctrl1; 2327 u32 wp_page_ctrl2; 2328 u32 wp_page_info1; 2329 }; 2330 2331 struct rtw89_imr_info { 2332 u32 wdrls_imr_set; 2333 u32 wsec_imr_reg; 2334 u32 wsec_imr_set; 2335 u32 mpdu_tx_imr_set; 2336 u32 mpdu_rx_imr_set; 2337 u32 sta_sch_imr_set; 2338 u32 txpktctl_imr_b0_reg; 2339 u32 txpktctl_imr_b0_clr; 2340 u32 txpktctl_imr_b0_set; 2341 u32 txpktctl_imr_b1_reg; 2342 u32 txpktctl_imr_b1_clr; 2343 u32 txpktctl_imr_b1_set; 2344 u32 wde_imr_clr; 2345 u32 wde_imr_set; 2346 u32 ple_imr_clr; 2347 u32 ple_imr_set; 2348 u32 host_disp_imr_clr; 2349 u32 host_disp_imr_set; 2350 u32 cpu_disp_imr_clr; 2351 u32 cpu_disp_imr_set; 2352 u32 other_disp_imr_clr; 2353 u32 other_disp_imr_set; 2354 u32 bbrpt_chinfo_err_imr_reg; 2355 u32 bbrpt_err_imr_set; 2356 u32 bbrpt_dfs_err_imr_reg; 2357 u32 ptcl_imr_clr; 2358 u32 ptcl_imr_set; 2359 u32 cdma_imr_0_reg; 2360 u32 cdma_imr_0_clr; 2361 u32 cdma_imr_0_set; 2362 u32 cdma_imr_1_reg; 2363 u32 cdma_imr_1_clr; 2364 u32 cdma_imr_1_set; 2365 u32 phy_intf_imr_reg; 2366 u32 phy_intf_imr_clr; 2367 u32 phy_intf_imr_set; 2368 u32 rmac_imr_reg; 2369 u32 rmac_imr_clr; 2370 u32 rmac_imr_set; 2371 u32 tmac_imr_reg; 2372 u32 tmac_imr_clr; 2373 u32 tmac_imr_set; 2374 }; 2375 2376 struct rtw89_chip_info { 2377 enum rtw89_core_chip_id chip_id; 2378 const struct rtw89_chip_ops *ops; 2379 const char *fw_name; 2380 u32 fifo_size; 2381 u16 max_amsdu_limit; 2382 bool dis_2g_40m_ul_ofdma; 2383 u32 rsvd_ple_ofst; 2384 const struct rtw89_hfc_param_ini *hfc_param_ini; 2385 const struct rtw89_dle_mem *dle_mem; 2386 u32 rf_base_addr[2]; 2387 u8 support_bands; 2388 bool support_bw160; 2389 bool hw_sec_hdr; 2390 u8 rf_path_num; 2391 u8 tx_nss; 2392 u8 rx_nss; 2393 u8 acam_num; 2394 u8 bcam_num; 2395 u8 scam_num; 2396 2397 u8 sec_ctrl_efuse_size; 2398 u32 physical_efuse_size; 2399 u32 logical_efuse_size; 2400 u32 limit_efuse_size; 2401 u32 dav_phy_efuse_size; 2402 u32 dav_log_efuse_size; 2403 u32 phycap_addr; 2404 u32 phycap_size; 2405 2406 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2407 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2408 const struct rtw89_phy_table *bb_table; 2409 const struct rtw89_phy_table *bb_gain_table; 2410 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2411 const struct rtw89_phy_table *nctl_table; 2412 const struct rtw89_txpwr_table *byr_table; 2413 const struct rtw89_phy_dig_gain_table *dig_table; 2414 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2415 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2416 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2417 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2418 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2419 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2420 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2421 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2422 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2423 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2424 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2425 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2426 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2427 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2428 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2429 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2430 2431 u8 txpwr_factor_rf; 2432 u8 txpwr_factor_mac; 2433 2434 u32 para_ver; 2435 u32 wlcx_desired; 2436 u8 btcx_desired; 2437 u8 scbd; 2438 u8 mailbox; 2439 2440 u8 afh_guard_ch; 2441 const u8 *wl_rssi_thres; 2442 const u8 *bt_rssi_thres; 2443 u8 rssi_tol; 2444 2445 u8 mon_reg_num; 2446 const struct rtw89_btc_fbtc_mreg *mon_reg; 2447 u8 rf_para_ulink_num; 2448 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2449 u8 rf_para_dlink_num; 2450 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2451 u8 ps_mode_supported; 2452 u8 low_power_hci_modes; 2453 2454 u32 h2c_cctl_func_id; 2455 u32 hci_func_en_addr; 2456 u32 h2c_desc_size; 2457 u32 txwd_body_size; 2458 u32 h2c_ctrl_reg; 2459 const u32 *h2c_regs; 2460 u32 c2h_ctrl_reg; 2461 const u32 *c2h_regs; 2462 const struct rtw89_page_regs *page_regs; 2463 const struct rtw89_reg_def *dcfo_comp; 2464 u8 dcfo_comp_sft; 2465 const struct rtw89_imr_info *imr_info; 2466 }; 2467 2468 union rtw89_bus_info { 2469 const struct rtw89_pci_info *pci; 2470 }; 2471 2472 struct rtw89_driver_info { 2473 const struct rtw89_chip_info *chip; 2474 union rtw89_bus_info bus; 2475 }; 2476 2477 enum rtw89_hcifc_mode { 2478 RTW89_HCIFC_POH = 0, 2479 RTW89_HCIFC_STF = 1, 2480 RTW89_HCIFC_SDIO = 2, 2481 2482 /* keep last */ 2483 RTW89_HCIFC_MODE_INVALID, 2484 }; 2485 2486 struct rtw89_dle_info { 2487 enum rtw89_qta_mode qta_mode; 2488 u16 wde_pg_size; 2489 u16 ple_pg_size; 2490 u16 c0_rx_qta; 2491 u16 c1_rx_qta; 2492 }; 2493 2494 enum rtw89_host_rpr_mode { 2495 RTW89_RPR_MODE_POH = 0, 2496 RTW89_RPR_MODE_STF 2497 }; 2498 2499 struct rtw89_mac_info { 2500 struct rtw89_dle_info dle_info; 2501 struct rtw89_hfc_param hfc_param; 2502 enum rtw89_qta_mode qta_mode; 2503 u8 rpwm_seq_num; 2504 u8 cpwm_seq_num; 2505 }; 2506 2507 enum rtw89_fw_type { 2508 RTW89_FW_NORMAL = 1, 2509 RTW89_FW_WOWLAN = 3, 2510 }; 2511 2512 enum rtw89_fw_feature { 2513 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 2514 RTW89_FW_FEATURE_SCAN_OFFLOAD, 2515 RTW89_FW_FEATURE_TX_WAKE, 2516 RTW89_FW_FEATURE_CRASH_TRIGGER, 2517 }; 2518 2519 struct rtw89_fw_suit { 2520 const u8 *data; 2521 u32 size; 2522 u8 major_ver; 2523 u8 minor_ver; 2524 u8 sub_ver; 2525 u8 sub_idex; 2526 u16 build_year; 2527 u16 build_mon; 2528 u16 build_date; 2529 u16 build_hour; 2530 u16 build_min; 2531 u8 cmd_ver; 2532 }; 2533 2534 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2535 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2536 #define RTW89_FW_SUIT_VER_CODE(s) \ 2537 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2538 2539 struct rtw89_fw_info { 2540 const struct firmware *firmware; 2541 struct rtw89_dev *rtwdev; 2542 struct completion completion; 2543 u8 h2c_seq; 2544 u8 rec_seq; 2545 struct rtw89_fw_suit normal; 2546 struct rtw89_fw_suit wowlan; 2547 bool fw_log_enable; 2548 u32 feature_map; 2549 }; 2550 2551 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 2552 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 2553 2554 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 2555 ((_fw)->feature_map |= BIT(_fw_feature)) 2556 2557 struct rtw89_cam_info { 2558 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2559 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2560 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2561 }; 2562 2563 enum rtw89_sar_sources { 2564 RTW89_SAR_SOURCE_NONE, 2565 RTW89_SAR_SOURCE_COMMON, 2566 2567 RTW89_SAR_SOURCE_NR, 2568 }; 2569 2570 enum rtw89_sar_subband { 2571 RTW89_SAR_2GHZ_SUBBAND, 2572 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 2573 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 2574 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 2575 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 2576 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 2577 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 2578 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 2579 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 2580 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 2581 2582 RTW89_SAR_SUBBAND_NR, 2583 }; 2584 2585 struct rtw89_sar_cfg_common { 2586 bool set[RTW89_SAR_SUBBAND_NR]; 2587 s32 cfg[RTW89_SAR_SUBBAND_NR]; 2588 }; 2589 2590 struct rtw89_sar_info { 2591 /* used to decide how to acces SAR cfg union */ 2592 enum rtw89_sar_sources src; 2593 2594 /* reserved for different knids of SAR cfg struct. 2595 * supposed that a single cfg struct cannot handle various SAR sources. 2596 */ 2597 union { 2598 struct rtw89_sar_cfg_common cfg_common; 2599 }; 2600 }; 2601 2602 struct rtw89_hal { 2603 u32 rx_fltr; 2604 u8 cv; 2605 u8 current_channel; 2606 u32 current_freq; 2607 u8 prev_primary_channel; 2608 u8 current_primary_channel; 2609 enum rtw89_subband current_subband; 2610 u8 current_band_width; 2611 u8 prev_band_type; 2612 u8 current_band_type; 2613 u32 sw_amsdu_max_size; 2614 u32 antenna_tx; 2615 u32 antenna_rx; 2616 u8 tx_nss; 2617 u8 rx_nss; 2618 bool support_cckpd; 2619 bool support_igi; 2620 }; 2621 2622 #define RTW89_MAX_MAC_ID_NUM 128 2623 #define RTW89_MAX_PKT_OFLD_NUM 255 2624 2625 enum rtw89_flags { 2626 RTW89_FLAG_POWERON, 2627 RTW89_FLAG_FW_RDY, 2628 RTW89_FLAG_RUNNING, 2629 RTW89_FLAG_BFEE_MON, 2630 RTW89_FLAG_BFEE_EN, 2631 RTW89_FLAG_NAPI_RUNNING, 2632 RTW89_FLAG_LEISURE_PS, 2633 RTW89_FLAG_LOW_POWER_MODE, 2634 RTW89_FLAG_INACTIVE_PS, 2635 RTW89_FLAG_RESTART_TRIGGER, 2636 2637 NUM_OF_RTW89_FLAGS, 2638 }; 2639 2640 struct rtw89_pkt_stat { 2641 u16 beacon_nr; 2642 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2643 }; 2644 2645 DECLARE_EWMA(thermal, 4, 4); 2646 2647 struct rtw89_phy_stat { 2648 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2649 struct rtw89_pkt_stat cur_pkt_stat; 2650 struct rtw89_pkt_stat last_pkt_stat; 2651 }; 2652 2653 #define RTW89_DACK_PATH_NR 2 2654 #define RTW89_DACK_IDX_NR 2 2655 #define RTW89_DACK_MSBK_NR 16 2656 struct rtw89_dack_info { 2657 bool dack_done; 2658 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2659 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2660 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2661 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2662 u32 dack_cnt; 2663 bool addck_timeout[RTW89_DACK_PATH_NR]; 2664 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2665 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2666 }; 2667 2668 #define RTW89_IQK_CHS_NR 2 2669 #define RTW89_IQK_PATH_NR 4 2670 2671 struct rtw89_mcc_info { 2672 u8 ch[RTW89_IQK_CHS_NR]; 2673 u8 band[RTW89_IQK_CHS_NR]; 2674 u8 table_idx; 2675 }; 2676 2677 struct rtw89_lck_info { 2678 u8 thermal[RF_PATH_MAX]; 2679 }; 2680 2681 struct rtw89_rx_dck_info { 2682 u8 thermal[RF_PATH_MAX]; 2683 }; 2684 2685 struct rtw89_iqk_info { 2686 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2687 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2688 bool lok_fail[RTW89_IQK_PATH_NR]; 2689 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2690 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2691 u32 iqk_fail_cnt; 2692 bool is_iqk_init; 2693 u32 iqk_channel[RTW89_IQK_CHS_NR]; 2694 u8 iqk_band[RTW89_IQK_PATH_NR]; 2695 u8 iqk_ch[RTW89_IQK_PATH_NR]; 2696 u8 iqk_bw[RTW89_IQK_PATH_NR]; 2697 u8 kcount; 2698 u8 iqk_times; 2699 u8 version; 2700 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 2701 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 2702 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 2703 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 2704 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 2705 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 2706 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 2707 bool is_nbiqk; 2708 bool iqk_fft_en; 2709 bool iqk_xym_en; 2710 bool iqk_sram_en; 2711 bool iqk_cfir_en; 2712 u8 thermal[RTW89_IQK_PATH_NR]; 2713 bool thermal_rek_en; 2714 u32 syn1to2; 2715 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2716 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 2717 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2718 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2719 }; 2720 2721 #define RTW89_DPK_RF_PATH 2 2722 #define RTW89_DPK_AVG_THERMAL_NUM 8 2723 #define RTW89_DPK_BKUP_NUM 2 2724 struct rtw89_dpk_bkup_para { 2725 enum rtw89_band band; 2726 enum rtw89_bandwidth bw; 2727 u8 ch; 2728 bool path_ok; 2729 u8 mdpd_en; 2730 u8 txagc_dpk; 2731 u8 ther_dpk; 2732 u8 gs; 2733 u16 pwsf; 2734 }; 2735 2736 struct rtw89_dpk_info { 2737 bool is_dpk_enable; 2738 bool is_dpk_reload_en; 2739 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2740 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2741 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2742 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2743 u8 cur_idx[RTW89_DPK_RF_PATH]; 2744 u8 cur_k_set; 2745 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2746 }; 2747 2748 struct rtw89_fem_info { 2749 bool elna_2g; 2750 bool elna_5g; 2751 bool epa_2g; 2752 bool epa_5g; 2753 bool epa_6g; 2754 }; 2755 2756 struct rtw89_phy_ch_info { 2757 u8 rssi_min; 2758 u16 rssi_min_macid; 2759 u8 pre_rssi_min; 2760 u8 rssi_max; 2761 u16 rssi_max_macid; 2762 u8 rxsc_160; 2763 u8 rxsc_80; 2764 u8 rxsc_40; 2765 u8 rxsc_20; 2766 u8 rxsc_l; 2767 u8 is_noisy; 2768 }; 2769 2770 struct rtw89_agc_gaincode_set { 2771 u8 lna_idx; 2772 u8 tia_idx; 2773 u8 rxb_idx; 2774 }; 2775 2776 #define IGI_RSSI_TH_NUM 5 2777 #define FA_TH_NUM 4 2778 #define LNA_GAIN_NUM 7 2779 #define TIA_GAIN_NUM 2 2780 struct rtw89_dig_info { 2781 struct rtw89_agc_gaincode_set cur_gaincode; 2782 bool force_gaincode_idx_en; 2783 struct rtw89_agc_gaincode_set force_gaincode; 2784 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 2785 u16 fa_th[FA_TH_NUM]; 2786 u8 igi_rssi; 2787 u8 igi_fa_rssi; 2788 u8 fa_rssi_ofst; 2789 u8 dyn_igi_max; 2790 u8 dyn_igi_min; 2791 bool dyn_pd_th_en; 2792 u8 dyn_pd_th_max; 2793 u8 pd_low_th_ofst; 2794 u8 ib_pbk; 2795 s8 ib_pkpwr; 2796 s8 lna_gain_a[LNA_GAIN_NUM]; 2797 s8 lna_gain_g[LNA_GAIN_NUM]; 2798 s8 *lna_gain; 2799 s8 tia_gain_a[TIA_GAIN_NUM]; 2800 s8 tia_gain_g[TIA_GAIN_NUM]; 2801 s8 *tia_gain; 2802 bool is_linked_pre; 2803 bool bypass_dig; 2804 }; 2805 2806 enum rtw89_multi_cfo_mode { 2807 RTW89_PKT_BASED_AVG_MODE = 0, 2808 RTW89_ENTRY_BASED_AVG_MODE = 1, 2809 RTW89_TP_BASED_AVG_MODE = 2, 2810 }; 2811 2812 enum rtw89_phy_cfo_status { 2813 RTW89_PHY_DCFO_STATE_NORMAL = 0, 2814 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 2815 RTW89_PHY_DCFO_STATE_HOLD = 2, 2816 RTW89_PHY_DCFO_STATE_MAX 2817 }; 2818 2819 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 2820 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 2821 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 2822 }; 2823 2824 struct rtw89_cfo_tracking_info { 2825 u16 cfo_timer_ms; 2826 bool cfo_trig_by_timer_en; 2827 enum rtw89_phy_cfo_status phy_cfo_status; 2828 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 2829 u8 phy_cfo_trk_cnt; 2830 bool is_adjust; 2831 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 2832 bool apply_compensation; 2833 u8 crystal_cap; 2834 u8 crystal_cap_default; 2835 u8 def_x_cap; 2836 s8 x_cap_ofst; 2837 u32 sta_cfo_tolerance; 2838 s32 cfo_tail[CFO_TRACK_MAX_USER]; 2839 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 2840 s32 cfo_avg_pre; 2841 s32 cfo_avg[CFO_TRACK_MAX_USER]; 2842 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 2843 u32 packet_count; 2844 u32 packet_count_pre; 2845 s32 residual_cfo_acc; 2846 u8 phy_cfotrk_state; 2847 u8 phy_cfotrk_cnt; 2848 bool divergence_lock_en; 2849 u8 x_cap_lb; 2850 u8 x_cap_ub; 2851 u8 lock_cnt; 2852 }; 2853 2854 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 2855 #define TSSI_TRIM_CH_GROUP_NUM 8 2856 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 2857 2858 #define TSSI_CCK_CH_GROUP_NUM 6 2859 #define TSSI_MCS_2G_CH_GROUP_NUM 5 2860 #define TSSI_MCS_5G_CH_GROUP_NUM 14 2861 #define TSSI_MCS_6G_CH_GROUP_NUM 32 2862 #define TSSI_MCS_CH_GROUP_NUM \ 2863 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 2864 2865 struct rtw89_tssi_info { 2866 u8 thermal[RF_PATH_MAX]; 2867 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 2868 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 2869 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 2870 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 2871 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 2872 s8 extra_ofst[RF_PATH_MAX]; 2873 bool tssi_tracking_check[RF_PATH_MAX]; 2874 u8 default_txagc_offset[RF_PATH_MAX]; 2875 u32 base_thermal[RF_PATH_MAX]; 2876 }; 2877 2878 struct rtw89_power_trim_info { 2879 bool pg_thermal_trim; 2880 bool pg_pa_bias_trim; 2881 u8 thermal_trim[RF_PATH_MAX]; 2882 u8 pa_bias_trim[RF_PATH_MAX]; 2883 }; 2884 2885 struct rtw89_regulatory { 2886 char alpha2[3]; 2887 u8 txpwr_regd[RTW89_BAND_MAX]; 2888 }; 2889 2890 enum rtw89_ifs_clm_application { 2891 RTW89_IFS_CLM_INIT = 0, 2892 RTW89_IFS_CLM_BACKGROUND = 1, 2893 RTW89_IFS_CLM_ACS = 2, 2894 RTW89_IFS_CLM_DIG = 3, 2895 RTW89_IFS_CLM_TDMA_DIG = 4, 2896 RTW89_IFS_CLM_DBG = 5, 2897 RTW89_IFS_CLM_DBG_MANUAL = 6 2898 }; 2899 2900 enum rtw89_env_racing_lv { 2901 RTW89_RAC_RELEASE = 0, 2902 RTW89_RAC_LV_1 = 1, 2903 RTW89_RAC_LV_2 = 2, 2904 RTW89_RAC_LV_3 = 3, 2905 RTW89_RAC_LV_4 = 4, 2906 RTW89_RAC_MAX_NUM = 5 2907 }; 2908 2909 struct rtw89_ccx_para_info { 2910 enum rtw89_env_racing_lv rac_lv; 2911 u16 mntr_time; 2912 u8 nhm_manual_th_ofst; 2913 u8 nhm_manual_th0; 2914 enum rtw89_ifs_clm_application ifs_clm_app; 2915 u32 ifs_clm_manual_th_times; 2916 u32 ifs_clm_manual_th0; 2917 u8 fahm_manual_th_ofst; 2918 u8 fahm_manual_th0; 2919 u8 fahm_numer_opt; 2920 u8 fahm_denom_opt; 2921 }; 2922 2923 enum rtw89_ccx_edcca_opt_sc_idx { 2924 RTW89_CCX_EDCCA_SEG0_P0 = 0, 2925 RTW89_CCX_EDCCA_SEG0_S1 = 1, 2926 RTW89_CCX_EDCCA_SEG0_S2 = 2, 2927 RTW89_CCX_EDCCA_SEG0_S3 = 3, 2928 RTW89_CCX_EDCCA_SEG1_P0 = 4, 2929 RTW89_CCX_EDCCA_SEG1_S1 = 5, 2930 RTW89_CCX_EDCCA_SEG1_S2 = 6, 2931 RTW89_CCX_EDCCA_SEG1_S3 = 7 2932 }; 2933 2934 enum rtw89_ccx_edcca_opt_bw_idx { 2935 RTW89_CCX_EDCCA_BW20_0 = 0, 2936 RTW89_CCX_EDCCA_BW20_1 = 1, 2937 RTW89_CCX_EDCCA_BW20_2 = 2, 2938 RTW89_CCX_EDCCA_BW20_3 = 3, 2939 RTW89_CCX_EDCCA_BW20_4 = 4, 2940 RTW89_CCX_EDCCA_BW20_5 = 5, 2941 RTW89_CCX_EDCCA_BW20_6 = 6, 2942 RTW89_CCX_EDCCA_BW20_7 = 7 2943 }; 2944 2945 #define RTW89_NHM_TH_NUM 11 2946 #define RTW89_FAHM_TH_NUM 11 2947 #define RTW89_NHM_RPT_NUM 12 2948 #define RTW89_FAHM_RPT_NUM 12 2949 #define RTW89_IFS_CLM_NUM 4 2950 struct rtw89_env_monitor_info { 2951 u32 ccx_trigger_time; 2952 u64 start_time; 2953 u8 ccx_rpt_stamp; 2954 u8 ccx_watchdog_result; 2955 bool ccx_ongoing; 2956 u8 ccx_rac_lv; 2957 bool ccx_manual_ctrl; 2958 u8 ccx_pre_rssi; 2959 u16 clm_mntr_time; 2960 u16 nhm_mntr_time; 2961 u16 ifs_clm_mntr_time; 2962 enum rtw89_ifs_clm_application ifs_clm_app; 2963 u16 fahm_mntr_time; 2964 u16 edcca_clm_mntr_time; 2965 u16 ccx_period; 2966 u8 ccx_unit_idx; 2967 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 2968 u8 nhm_th[RTW89_NHM_TH_NUM]; 2969 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 2970 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 2971 u8 fahm_numer_opt; 2972 u8 fahm_denom_opt; 2973 u8 fahm_th[RTW89_FAHM_TH_NUM]; 2974 u16 clm_result; 2975 u16 nhm_result[RTW89_NHM_RPT_NUM]; 2976 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 2977 u16 nhm_tx_cnt; 2978 u16 nhm_cca_cnt; 2979 u16 nhm_idle_cnt; 2980 u16 ifs_clm_tx; 2981 u16 ifs_clm_edcca_excl_cca; 2982 u16 ifs_clm_ofdmfa; 2983 u16 ifs_clm_ofdmcca_excl_fa; 2984 u16 ifs_clm_cckfa; 2985 u16 ifs_clm_cckcca_excl_fa; 2986 u16 ifs_clm_total_ifs; 2987 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 2988 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 2989 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 2990 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 2991 u16 fahm_denom_result; 2992 u16 edcca_clm_result; 2993 u8 clm_ratio; 2994 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 2995 u8 nhm_tx_ratio; 2996 u8 nhm_cca_ratio; 2997 u8 nhm_idle_ratio; 2998 u8 nhm_ratio; 2999 u16 nhm_result_sum; 3000 u8 nhm_pwr; 3001 u8 ifs_clm_tx_ratio; 3002 u8 ifs_clm_edcca_excl_cca_ratio; 3003 u8 ifs_clm_cck_fa_ratio; 3004 u8 ifs_clm_ofdm_fa_ratio; 3005 u8 ifs_clm_cck_cca_excl_fa_ratio; 3006 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3007 u16 ifs_clm_cck_fa_permil; 3008 u16 ifs_clm_ofdm_fa_permil; 3009 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3010 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3011 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3012 u16 fahm_result_sum; 3013 u8 fahm_ratio; 3014 u8 fahm_denom_ratio; 3015 u8 fahm_pwr; 3016 u8 edcca_clm_ratio; 3017 }; 3018 3019 enum rtw89_ser_rcvy_step { 3020 RTW89_SER_DRV_STOP_TX, 3021 RTW89_SER_DRV_STOP_RX, 3022 RTW89_SER_DRV_STOP_RUN, 3023 RTW89_SER_HAL_STOP_DMA, 3024 RTW89_NUM_OF_SER_FLAGS 3025 }; 3026 3027 struct rtw89_ser { 3028 u8 state; 3029 u8 alarm_event; 3030 3031 struct work_struct ser_hdl_work; 3032 struct delayed_work ser_alarm_work; 3033 const struct state_ent *st_tbl; 3034 const struct event_ent *ev_tbl; 3035 struct list_head msg_q; 3036 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3037 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3038 }; 3039 3040 enum rtw89_mac_ax_ps_mode { 3041 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3042 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3043 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3044 RTW89_MAC_AX_PS_MODE_MAX = 3, 3045 }; 3046 3047 enum rtw89_last_rpwm_mode { 3048 RTW89_LAST_RPWM_PS = 0x0, 3049 RTW89_LAST_RPWM_ACTIVE = 0x6, 3050 }; 3051 3052 struct rtw89_lps_parm { 3053 u8 macid; 3054 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3055 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3056 }; 3057 3058 struct rtw89_ppdu_sts_info { 3059 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3060 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3061 }; 3062 3063 struct rtw89_early_h2c { 3064 struct list_head list; 3065 u8 *h2c; 3066 u16 h2c_len; 3067 }; 3068 3069 struct rtw89_hw_scan_info { 3070 struct ieee80211_vif *scanning_vif; 3071 struct list_head pkt_list[NUM_NL80211_BANDS]; 3072 u8 op_pri_ch; 3073 u8 op_chan; 3074 u8 op_bw; 3075 u8 op_band; 3076 }; 3077 3078 enum rtw89_phy_bb_gain_band { 3079 RTW89_BB_GAIN_BAND_2G = 0, 3080 RTW89_BB_GAIN_BAND_5G_L = 1, 3081 RTW89_BB_GAIN_BAND_5G_M = 2, 3082 RTW89_BB_GAIN_BAND_5G_H = 3, 3083 RTW89_BB_GAIN_BAND_6G_L = 4, 3084 RTW89_BB_GAIN_BAND_6G_M = 5, 3085 RTW89_BB_GAIN_BAND_6G_H = 6, 3086 RTW89_BB_GAIN_BAND_6G_UH = 7, 3087 3088 RTW89_BB_GAIN_BAND_NR, 3089 }; 3090 3091 enum rtw89_phy_bb_rxsc_num { 3092 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3093 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3094 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3095 }; 3096 3097 struct rtw89_phy_bb_gain_info { 3098 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3099 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3100 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3101 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3102 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3103 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3104 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3105 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3106 [RTW89_BB_RXSC_NUM_40]; 3107 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3108 [RTW89_BB_RXSC_NUM_80]; 3109 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3110 [RTW89_BB_RXSC_NUM_160]; 3111 }; 3112 3113 struct rtw89_phy_efuse_gain { 3114 bool offset_valid; 3115 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3116 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3117 }; 3118 3119 struct rtw89_dev { 3120 struct ieee80211_hw *hw; 3121 struct device *dev; 3122 3123 bool dbcc_en; 3124 struct rtw89_hw_scan_info scan_info; 3125 const struct rtw89_chip_info *chip; 3126 const struct rtw89_pci_info *pci_info; 3127 struct rtw89_hal hal; 3128 struct rtw89_mac_info mac; 3129 struct rtw89_fw_info fw; 3130 struct rtw89_hci_info hci; 3131 struct rtw89_efuse efuse; 3132 struct rtw89_traffic_stats stats; 3133 3134 /* ensures exclusive access from mac80211 callbacks */ 3135 struct mutex mutex; 3136 struct list_head rtwvifs_list; 3137 /* used to protect rf read write */ 3138 struct mutex rf_mutex; 3139 struct workqueue_struct *txq_wq; 3140 struct work_struct txq_work; 3141 struct delayed_work txq_reinvoke_work; 3142 /* used to protect ba_list and forbid_ba_list */ 3143 spinlock_t ba_lock; 3144 /* txqs to setup ba session */ 3145 struct list_head ba_list; 3146 /* txqs to forbid ba session */ 3147 struct list_head forbid_ba_list; 3148 struct work_struct ba_work; 3149 /* used to protect rpwm */ 3150 spinlock_t rpwm_lock; 3151 3152 struct rtw89_cam_info cam_info; 3153 3154 struct sk_buff_head c2h_queue; 3155 struct work_struct c2h_work; 3156 struct work_struct ips_work; 3157 3158 struct list_head early_h2c_list; 3159 3160 struct rtw89_ser ser; 3161 3162 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3163 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3164 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3165 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3166 3167 struct rtw89_phy_stat phystat; 3168 struct rtw89_dack_info dack; 3169 struct rtw89_iqk_info iqk; 3170 struct rtw89_dpk_info dpk; 3171 struct rtw89_mcc_info mcc; 3172 struct rtw89_lck_info lck; 3173 struct rtw89_rx_dck_info rx_dck; 3174 bool is_tssi_mode[RF_PATH_MAX]; 3175 bool is_bt_iqk_timeout; 3176 3177 struct rtw89_fem_info fem; 3178 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3179 struct rtw89_tssi_info tssi; 3180 struct rtw89_power_trim_info pwr_trim; 3181 3182 struct rtw89_cfo_tracking_info cfo_tracking; 3183 struct rtw89_env_monitor_info env_monitor; 3184 struct rtw89_dig_info dig; 3185 struct rtw89_phy_ch_info ch_info; 3186 struct rtw89_phy_bb_gain_info bb_gain; 3187 struct rtw89_phy_efuse_gain efuse_gain; 3188 3189 struct delayed_work track_work; 3190 struct delayed_work coex_act1_work; 3191 struct delayed_work coex_bt_devinfo_work; 3192 struct delayed_work coex_rfk_chk_work; 3193 struct delayed_work cfo_track_work; 3194 struct delayed_work forbid_ba_work; 3195 struct rtw89_ppdu_sts_info ppdu_sts; 3196 u8 total_sta_assoc; 3197 bool scanning; 3198 3199 const struct rtw89_regulatory *regd; 3200 struct rtw89_sar_info sar; 3201 3202 struct rtw89_btc btc; 3203 enum rtw89_ps_mode ps_mode; 3204 bool lps_enabled; 3205 3206 /* napi structure */ 3207 struct net_device netdev; 3208 struct napi_struct napi; 3209 int napi_budget_countdown; 3210 3211 /* HCI related data, keep last */ 3212 u8 priv[] __aligned(sizeof(void *)); 3213 }; 3214 3215 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3216 struct rtw89_core_tx_request *tx_req) 3217 { 3218 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3219 } 3220 3221 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3222 { 3223 rtwdev->hci.ops->reset(rtwdev); 3224 } 3225 3226 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3227 { 3228 return rtwdev->hci.ops->start(rtwdev); 3229 } 3230 3231 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3232 { 3233 rtwdev->hci.ops->stop(rtwdev); 3234 } 3235 3236 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3237 { 3238 return rtwdev->hci.ops->deinit(rtwdev); 3239 } 3240 3241 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3242 { 3243 rtwdev->hci.ops->pause(rtwdev, pause); 3244 } 3245 3246 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3247 { 3248 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3249 } 3250 3251 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3252 { 3253 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3254 } 3255 3256 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3257 { 3258 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3259 } 3260 3261 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3262 { 3263 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3264 } 3265 3266 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3267 bool drop) 3268 { 3269 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3270 return; 3271 3272 if (rtwdev->hci.ops->flush_queues) 3273 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3274 } 3275 3276 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3277 { 3278 if (rtwdev->hci.ops->recovery_start) 3279 rtwdev->hci.ops->recovery_start(rtwdev); 3280 } 3281 3282 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3283 { 3284 if (rtwdev->hci.ops->recovery_complete) 3285 rtwdev->hci.ops->recovery_complete(rtwdev); 3286 } 3287 3288 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3289 { 3290 return rtwdev->hci.ops->read8(rtwdev, addr); 3291 } 3292 3293 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3294 { 3295 return rtwdev->hci.ops->read16(rtwdev, addr); 3296 } 3297 3298 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3299 { 3300 return rtwdev->hci.ops->read32(rtwdev, addr); 3301 } 3302 3303 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3304 { 3305 rtwdev->hci.ops->write8(rtwdev, addr, data); 3306 } 3307 3308 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3309 { 3310 rtwdev->hci.ops->write16(rtwdev, addr, data); 3311 } 3312 3313 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3314 { 3315 rtwdev->hci.ops->write32(rtwdev, addr, data); 3316 } 3317 3318 static inline void 3319 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3320 { 3321 u8 val; 3322 3323 val = rtw89_read8(rtwdev, addr); 3324 rtw89_write8(rtwdev, addr, val | bit); 3325 } 3326 3327 static inline void 3328 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3329 { 3330 u16 val; 3331 3332 val = rtw89_read16(rtwdev, addr); 3333 rtw89_write16(rtwdev, addr, val | bit); 3334 } 3335 3336 static inline void 3337 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3338 { 3339 u32 val; 3340 3341 val = rtw89_read32(rtwdev, addr); 3342 rtw89_write32(rtwdev, addr, val | bit); 3343 } 3344 3345 static inline void 3346 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3347 { 3348 u8 val; 3349 3350 val = rtw89_read8(rtwdev, addr); 3351 rtw89_write8(rtwdev, addr, val & ~bit); 3352 } 3353 3354 static inline void 3355 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3356 { 3357 u16 val; 3358 3359 val = rtw89_read16(rtwdev, addr); 3360 rtw89_write16(rtwdev, addr, val & ~bit); 3361 } 3362 3363 static inline void 3364 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3365 { 3366 u32 val; 3367 3368 val = rtw89_read32(rtwdev, addr); 3369 rtw89_write32(rtwdev, addr, val & ~bit); 3370 } 3371 3372 static inline u32 3373 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3374 { 3375 u32 shift = __ffs(mask); 3376 u32 orig; 3377 u32 ret; 3378 3379 orig = rtw89_read32(rtwdev, addr); 3380 ret = (orig & mask) >> shift; 3381 3382 return ret; 3383 } 3384 3385 static inline u16 3386 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3387 { 3388 u32 shift = __ffs(mask); 3389 u32 orig; 3390 u32 ret; 3391 3392 orig = rtw89_read16(rtwdev, addr); 3393 ret = (orig & mask) >> shift; 3394 3395 return ret; 3396 } 3397 3398 static inline u8 3399 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3400 { 3401 u32 shift = __ffs(mask); 3402 u32 orig; 3403 u32 ret; 3404 3405 orig = rtw89_read8(rtwdev, addr); 3406 ret = (orig & mask) >> shift; 3407 3408 return ret; 3409 } 3410 3411 static inline void 3412 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3413 { 3414 u32 shift = __ffs(mask); 3415 u32 orig; 3416 u32 set; 3417 3418 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3419 3420 orig = rtw89_read32(rtwdev, addr); 3421 set = (orig & ~mask) | ((data << shift) & mask); 3422 rtw89_write32(rtwdev, addr, set); 3423 } 3424 3425 static inline void 3426 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3427 { 3428 u32 shift; 3429 u16 orig, set; 3430 3431 mask &= 0xffff; 3432 shift = __ffs(mask); 3433 3434 orig = rtw89_read16(rtwdev, addr); 3435 set = (orig & ~mask) | ((data << shift) & mask); 3436 rtw89_write16(rtwdev, addr, set); 3437 } 3438 3439 static inline void 3440 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3441 { 3442 u32 shift; 3443 u8 orig, set; 3444 3445 mask &= 0xff; 3446 shift = __ffs(mask); 3447 3448 orig = rtw89_read8(rtwdev, addr); 3449 set = (orig & ~mask) | ((data << shift) & mask); 3450 rtw89_write8(rtwdev, addr, set); 3451 } 3452 3453 static inline u32 3454 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3455 u32 addr, u32 mask) 3456 { 3457 u32 val; 3458 3459 mutex_lock(&rtwdev->rf_mutex); 3460 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3461 mutex_unlock(&rtwdev->rf_mutex); 3462 3463 return val; 3464 } 3465 3466 static inline void 3467 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3468 u32 addr, u32 mask, u32 data) 3469 { 3470 mutex_lock(&rtwdev->rf_mutex); 3471 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3472 mutex_unlock(&rtwdev->rf_mutex); 3473 } 3474 3475 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3476 { 3477 void *p = rtwtxq; 3478 3479 return container_of(p, struct ieee80211_txq, drv_priv); 3480 } 3481 3482 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3483 struct ieee80211_txq *txq) 3484 { 3485 struct rtw89_txq *rtwtxq; 3486 3487 if (!txq) 3488 return; 3489 3490 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3491 INIT_LIST_HEAD(&rtwtxq->list); 3492 } 3493 3494 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3495 { 3496 void *p = rtwvif; 3497 3498 return container_of(p, struct ieee80211_vif, drv_priv); 3499 } 3500 3501 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3502 { 3503 void *p = rtwsta; 3504 3505 return container_of(p, struct ieee80211_sta, drv_priv); 3506 } 3507 3508 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3509 { 3510 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3511 } 3512 3513 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3514 { 3515 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3516 } 3517 3518 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3519 { 3520 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3521 return RATE_INFO_BW_160; 3522 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3523 return RATE_INFO_BW_80; 3524 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3525 return RATE_INFO_BW_40; 3526 else 3527 return RATE_INFO_BW_20; 3528 } 3529 3530 static inline 3531 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 3532 { 3533 switch (hw_band) { 3534 default: 3535 case RTW89_BAND_2G: 3536 return NL80211_BAND_2GHZ; 3537 case RTW89_BAND_5G: 3538 return NL80211_BAND_5GHZ; 3539 case RTW89_BAND_6G: 3540 return NL80211_BAND_6GHZ; 3541 } 3542 } 3543 3544 static inline 3545 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 3546 { 3547 switch (width) { 3548 default: 3549 WARN(1, "Not support bandwidth %d\n", width); 3550 fallthrough; 3551 case NL80211_CHAN_WIDTH_20_NOHT: 3552 case NL80211_CHAN_WIDTH_20: 3553 return RTW89_CHANNEL_WIDTH_20; 3554 case NL80211_CHAN_WIDTH_40: 3555 return RTW89_CHANNEL_WIDTH_40; 3556 case NL80211_CHAN_WIDTH_80: 3557 return RTW89_CHANNEL_WIDTH_80; 3558 case NL80211_CHAN_WIDTH_160: 3559 return RTW89_CHANNEL_WIDTH_160; 3560 } 3561 } 3562 3563 static inline 3564 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3565 struct rtw89_sta *rtwsta) 3566 { 3567 if (rtwsta) { 3568 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3569 3570 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 3571 return &rtwsta->addr_cam; 3572 } 3573 return &rtwvif->addr_cam; 3574 } 3575 3576 static inline 3577 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 3578 struct rtw89_sta *rtwsta) 3579 { 3580 if (rtwsta) { 3581 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3582 3583 if (sta->tdls) 3584 return &rtwsta->bssid_cam; 3585 } 3586 return &rtwvif->bssid_cam; 3587 } 3588 3589 static inline 3590 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3591 struct rtw89_channel_help_params *p) 3592 { 3593 rtwdev->chip->ops->set_channel_help(rtwdev, true, p); 3594 } 3595 3596 static inline 3597 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3598 struct rtw89_channel_help_params *p) 3599 { 3600 rtwdev->chip->ops->set_channel_help(rtwdev, false, p); 3601 } 3602 3603 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3604 { 3605 const struct rtw89_chip_info *chip = rtwdev->chip; 3606 3607 if (chip->ops->fem_setup) 3608 chip->ops->fem_setup(rtwdev); 3609 } 3610 3611 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3612 { 3613 const struct rtw89_chip_info *chip = rtwdev->chip; 3614 3615 if (chip->ops->bb_sethw) 3616 chip->ops->bb_sethw(rtwdev); 3617 } 3618 3619 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3620 { 3621 const struct rtw89_chip_info *chip = rtwdev->chip; 3622 3623 if (chip->ops->rfk_init) 3624 chip->ops->rfk_init(rtwdev); 3625 } 3626 3627 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 3628 { 3629 const struct rtw89_chip_info *chip = rtwdev->chip; 3630 3631 if (chip->ops->rfk_channel) 3632 chip->ops->rfk_channel(rtwdev); 3633 } 3634 3635 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev) 3636 { 3637 const struct rtw89_chip_info *chip = rtwdev->chip; 3638 3639 if (chip->ops->rfk_band_changed) 3640 chip->ops->rfk_band_changed(rtwdev); 3641 } 3642 3643 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 3644 { 3645 const struct rtw89_chip_info *chip = rtwdev->chip; 3646 3647 if (chip->ops->rfk_scan) 3648 chip->ops->rfk_scan(rtwdev, start); 3649 } 3650 3651 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 3652 { 3653 const struct rtw89_chip_info *chip = rtwdev->chip; 3654 3655 if (chip->ops->rfk_track) 3656 chip->ops->rfk_track(rtwdev); 3657 } 3658 3659 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 3660 { 3661 const struct rtw89_chip_info *chip = rtwdev->chip; 3662 3663 if (chip->ops->set_txpwr_ctrl) 3664 chip->ops->set_txpwr_ctrl(rtwdev); 3665 } 3666 3667 static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev) 3668 { 3669 const struct rtw89_chip_info *chip = rtwdev->chip; 3670 u8 ch = rtwdev->hal.current_channel; 3671 3672 if (!ch) 3673 return; 3674 3675 if (chip->ops->set_txpwr) 3676 chip->ops->set_txpwr(rtwdev); 3677 } 3678 3679 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 3680 { 3681 const struct rtw89_chip_info *chip = rtwdev->chip; 3682 3683 if (chip->ops->power_trim) 3684 chip->ops->power_trim(rtwdev); 3685 } 3686 3687 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 3688 enum rtw89_phy_idx phy_idx) 3689 { 3690 const struct rtw89_chip_info *chip = rtwdev->chip; 3691 3692 if (chip->ops->init_txpwr_unit) 3693 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 3694 } 3695 3696 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 3697 enum rtw89_rf_path rf_path) 3698 { 3699 const struct rtw89_chip_info *chip = rtwdev->chip; 3700 3701 if (!chip->ops->get_thermal) 3702 return 0x10; 3703 3704 return chip->ops->get_thermal(rtwdev, rf_path); 3705 } 3706 3707 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 3708 struct rtw89_rx_phy_ppdu *phy_ppdu, 3709 struct ieee80211_rx_status *status) 3710 { 3711 const struct rtw89_chip_info *chip = rtwdev->chip; 3712 3713 if (chip->ops->query_ppdu) 3714 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 3715 } 3716 3717 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 3718 bool bt_en) 3719 { 3720 const struct rtw89_chip_info *chip = rtwdev->chip; 3721 3722 if (chip->ops->bb_ctrl_btc_preagc) 3723 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 3724 } 3725 3726 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 3727 { 3728 const struct rtw89_chip_info *chip = rtwdev->chip; 3729 3730 if (chip->ops->cfg_txrx_path) 3731 chip->ops->cfg_txrx_path(rtwdev); 3732 } 3733 3734 static inline 3735 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 3736 struct ieee80211_vif *vif) 3737 { 3738 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3739 const struct rtw89_chip_info *chip = rtwdev->chip; 3740 3741 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3742 return; 3743 3744 if (chip->ops->set_txpwr_ul_tb_offset) 3745 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 3746 } 3747 3748 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 3749 const struct rtw89_txpwr_table *tbl) 3750 { 3751 tbl->load(rtwdev, tbl); 3752 } 3753 3754 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 3755 { 3756 return rtwdev->regd->txpwr_regd[band]; 3757 } 3758 3759 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 3760 { 3761 const struct rtw89_chip_info *chip = rtwdev->chip; 3762 3763 if (chip->ops->ctrl_btg) 3764 chip->ops->ctrl_btg(rtwdev, btg); 3765 } 3766 3767 static inline 3768 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 3769 struct rtw89_tx_desc_info *desc_info, 3770 void *txdesc) 3771 { 3772 const struct rtw89_chip_info *chip = rtwdev->chip; 3773 3774 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 3775 } 3776 3777 static inline 3778 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 3779 struct rtw89_tx_desc_info *desc_info, 3780 void *txdesc) 3781 { 3782 const struct rtw89_chip_info *chip = rtwdev->chip; 3783 3784 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 3785 } 3786 3787 static inline 3788 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 3789 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3790 { 3791 const struct rtw89_chip_info *chip = rtwdev->chip; 3792 3793 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 3794 } 3795 3796 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 3797 { 3798 const struct rtw89_chip_info *chip = rtwdev->chip; 3799 3800 chip->ops->cfg_ctrl_path(rtwdev, wl); 3801 } 3802 3803 static inline 3804 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3805 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3806 { 3807 const struct rtw89_chip_info *chip = rtwdev->chip; 3808 3809 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 3810 } 3811 3812 static inline 3813 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3814 { 3815 const struct rtw89_chip_info *chip = rtwdev->chip; 3816 3817 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 3818 } 3819 3820 static inline 3821 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 3822 struct rtw89_vif *rtwvif, 3823 struct rtw89_sta *rtwsta) 3824 { 3825 const struct rtw89_chip_info *chip = rtwdev->chip; 3826 3827 if (!chip->ops->h2c_dctl_sec_cam) 3828 return 0; 3829 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 3830 } 3831 3832 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 3833 { 3834 __le16 fc = hdr->frame_control; 3835 3836 if (ieee80211_has_tods(fc)) 3837 return hdr->addr1; 3838 else if (ieee80211_has_fromds(fc)) 3839 return hdr->addr2; 3840 else 3841 return hdr->addr3; 3842 } 3843 3844 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 3845 { 3846 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 3847 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 3848 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 3849 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 3850 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 3851 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 3852 return true; 3853 return false; 3854 } 3855 3856 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 3857 enum rtw89_fw_type type) 3858 { 3859 struct rtw89_fw_info *fw_info = &rtwdev->fw; 3860 3861 if (type == RTW89_FW_WOWLAN) 3862 return &fw_info->wowlan; 3863 return &fw_info->normal; 3864 } 3865 3866 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3867 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 3868 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 3869 struct sk_buff *skb, bool fwdl); 3870 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 3871 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 3872 struct rtw89_tx_desc_info *desc_info, 3873 void *txdesc); 3874 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 3875 struct rtw89_tx_desc_info *desc_info, 3876 void *txdesc); 3877 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 3878 struct rtw89_tx_desc_info *desc_info, 3879 void *txdesc); 3880 void rtw89_core_rx(struct rtw89_dev *rtwdev, 3881 struct rtw89_rx_desc_info *desc_info, 3882 struct sk_buff *skb); 3883 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 3884 struct rtw89_rx_desc_info *desc_info, 3885 u8 *data, u32 data_offset); 3886 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 3887 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 3888 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 3889 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 3890 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3891 struct ieee80211_vif *vif, 3892 struct ieee80211_sta *sta); 3893 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3894 struct ieee80211_vif *vif, 3895 struct ieee80211_sta *sta); 3896 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3897 struct ieee80211_vif *vif, 3898 struct ieee80211_sta *sta); 3899 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3900 struct ieee80211_vif *vif, 3901 struct ieee80211_sta *sta); 3902 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3903 struct ieee80211_vif *vif, 3904 struct ieee80211_sta *sta); 3905 int rtw89_core_init(struct rtw89_dev *rtwdev); 3906 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 3907 int rtw89_core_register(struct rtw89_dev *rtwdev); 3908 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 3909 void rtw89_set_channel(struct rtw89_dev *rtwdev); 3910 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 3911 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 3912 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 3913 int rtw89_core_acquire_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3914 int rtw89_core_release_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3915 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 3916 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 3917 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 3918 int rtw89_regd_init(struct rtw89_dev *rtwdev, 3919 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 3920 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 3921 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3922 struct rtw89_traffic_stats *stats); 3923 int rtw89_core_start(struct rtw89_dev *rtwdev); 3924 void rtw89_core_stop(struct rtw89_dev *rtwdev); 3925 void rtw89_core_update_beacon_work(struct work_struct *work); 3926 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3927 const u8 *mac_addr, bool hw_scan); 3928 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3929 struct ieee80211_vif *vif, bool hw_scan); 3930 3931 #endif 3932