1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 38 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 39 #define RTW89_HTC_VARIANT_HE 3 40 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 41 #define RTW89_HTC_VARIANT_HE_CID_OM 1 42 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 43 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 44 45 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 46 enum htc_om_channel_width { 47 HTC_OM_CHANNEL_WIDTH_20 = 0, 48 HTC_OM_CHANNEL_WIDTH_40 = 1, 49 HTC_OM_CHANNEL_WIDTH_80 = 2, 50 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 51 }; 52 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 53 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 54 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 55 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 56 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 57 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 58 59 #define RTW89_TF_PAD GENMASK(11, 0) 60 #define RTW89_TF_BASIC_USER_INFO_SZ 6 61 62 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 63 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 64 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 66 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 68 69 enum rtw89_subband { 70 RTW89_CH_2G = 0, 71 RTW89_CH_5G_BAND_1 = 1, 72 /* RTW89_CH_5G_BAND_2 = 2, unused */ 73 RTW89_CH_5G_BAND_3 = 3, 74 RTW89_CH_5G_BAND_4 = 4, 75 76 RTW89_CH_6G_BAND_IDX0, /* Low */ 77 RTW89_CH_6G_BAND_IDX1, /* Low */ 78 RTW89_CH_6G_BAND_IDX2, /* Mid */ 79 RTW89_CH_6G_BAND_IDX3, /* Mid */ 80 RTW89_CH_6G_BAND_IDX4, /* High */ 81 RTW89_CH_6G_BAND_IDX5, /* High */ 82 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 83 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 84 85 RTW89_SUBBAND_NR, 86 }; 87 88 enum rtw89_gain_offset { 89 RTW89_GAIN_OFFSET_2G_CCK, 90 RTW89_GAIN_OFFSET_2G_OFDM, 91 RTW89_GAIN_OFFSET_5G_LOW, 92 RTW89_GAIN_OFFSET_5G_MID, 93 RTW89_GAIN_OFFSET_5G_HIGH, 94 95 RTW89_GAIN_OFFSET_NR, 96 }; 97 98 enum rtw89_hci_type { 99 RTW89_HCI_TYPE_PCIE, 100 RTW89_HCI_TYPE_USB, 101 RTW89_HCI_TYPE_SDIO, 102 }; 103 104 enum rtw89_core_chip_id { 105 RTL8852A, 106 RTL8852B, 107 RTL8852C, 108 }; 109 110 enum rtw89_cv { 111 CHIP_CAV, 112 CHIP_CBV, 113 CHIP_CCV, 114 CHIP_CDV, 115 CHIP_CEV, 116 CHIP_CFV, 117 CHIP_CV_MAX, 118 CHIP_CV_INVALID = CHIP_CV_MAX, 119 }; 120 121 enum rtw89_core_tx_type { 122 RTW89_CORE_TX_TYPE_DATA, 123 RTW89_CORE_TX_TYPE_MGMT, 124 RTW89_CORE_TX_TYPE_FWCMD, 125 }; 126 127 enum rtw89_core_rx_type { 128 RTW89_CORE_RX_TYPE_WIFI = 0, 129 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 130 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 131 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 132 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 133 RTW89_CORE_RX_TYPE_SS2FW = 5, 134 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 135 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 136 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 137 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 138 RTW89_CORE_RX_TYPE_C2H = 10, 139 RTW89_CORE_RX_TYPE_CSI = 11, 140 RTW89_CORE_RX_TYPE_CQI = 12, 141 RTW89_CORE_RX_TYPE_H2C = 13, 142 RTW89_CORE_RX_TYPE_FWDL = 14, 143 }; 144 145 enum rtw89_txq_flags { 146 RTW89_TXQ_F_AMPDU = 0, 147 RTW89_TXQ_F_BLOCK_BA = 1, 148 RTW89_TXQ_F_FORBID_BA = 2, 149 }; 150 151 enum rtw89_net_type { 152 RTW89_NET_TYPE_NO_LINK = 0, 153 RTW89_NET_TYPE_AD_HOC = 1, 154 RTW89_NET_TYPE_INFRA = 2, 155 RTW89_NET_TYPE_AP_MODE = 3, 156 }; 157 158 enum rtw89_wifi_role { 159 RTW89_WIFI_ROLE_NONE, 160 RTW89_WIFI_ROLE_STATION, 161 RTW89_WIFI_ROLE_AP, 162 RTW89_WIFI_ROLE_AP_VLAN, 163 RTW89_WIFI_ROLE_ADHOC, 164 RTW89_WIFI_ROLE_ADHOC_MASTER, 165 RTW89_WIFI_ROLE_MESH_POINT, 166 RTW89_WIFI_ROLE_MONITOR, 167 RTW89_WIFI_ROLE_P2P_DEVICE, 168 RTW89_WIFI_ROLE_P2P_CLIENT, 169 RTW89_WIFI_ROLE_P2P_GO, 170 RTW89_WIFI_ROLE_NAN, 171 RTW89_WIFI_ROLE_MLME_MAX 172 }; 173 174 enum rtw89_upd_mode { 175 RTW89_ROLE_CREATE, 176 RTW89_ROLE_REMOVE, 177 RTW89_ROLE_TYPE_CHANGE, 178 RTW89_ROLE_INFO_CHANGE, 179 RTW89_ROLE_CON_DISCONN 180 }; 181 182 enum rtw89_self_role { 183 RTW89_SELF_ROLE_CLIENT, 184 RTW89_SELF_ROLE_AP, 185 RTW89_SELF_ROLE_AP_CLIENT 186 }; 187 188 enum rtw89_msk_sO_el { 189 RTW89_NO_MSK, 190 RTW89_SMA, 191 RTW89_TMA, 192 RTW89_BSSID 193 }; 194 195 enum rtw89_sch_tx_sel { 196 RTW89_SCH_TX_SEL_ALL, 197 RTW89_SCH_TX_SEL_HIQ, 198 RTW89_SCH_TX_SEL_MG0, 199 RTW89_SCH_TX_SEL_MACID, 200 }; 201 202 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 203 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 204 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 205 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 206 */ 207 enum rtw89_add_cam_sec_mode { 208 RTW89_ADDR_CAM_SEC_NONE = 0, 209 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 210 RTW89_ADDR_CAM_SEC_NORMAL = 2, 211 RTW89_ADDR_CAM_SEC_4GROUP = 3, 212 }; 213 214 enum rtw89_sec_key_type { 215 RTW89_SEC_KEY_TYPE_NONE = 0, 216 RTW89_SEC_KEY_TYPE_WEP40 = 1, 217 RTW89_SEC_KEY_TYPE_WEP104 = 2, 218 RTW89_SEC_KEY_TYPE_TKIP = 3, 219 RTW89_SEC_KEY_TYPE_WAPI = 4, 220 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 221 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 222 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 223 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 224 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 225 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 226 }; 227 228 enum rtw89_port { 229 RTW89_PORT_0 = 0, 230 RTW89_PORT_1 = 1, 231 RTW89_PORT_2 = 2, 232 RTW89_PORT_3 = 3, 233 RTW89_PORT_4 = 4, 234 RTW89_PORT_NUM 235 }; 236 237 enum rtw89_band { 238 RTW89_BAND_2G = 0, 239 RTW89_BAND_5G = 1, 240 RTW89_BAND_6G = 2, 241 RTW89_BAND_MAX, 242 }; 243 244 enum rtw89_hw_rate { 245 RTW89_HW_RATE_CCK1 = 0x0, 246 RTW89_HW_RATE_CCK2 = 0x1, 247 RTW89_HW_RATE_CCK5_5 = 0x2, 248 RTW89_HW_RATE_CCK11 = 0x3, 249 RTW89_HW_RATE_OFDM6 = 0x4, 250 RTW89_HW_RATE_OFDM9 = 0x5, 251 RTW89_HW_RATE_OFDM12 = 0x6, 252 RTW89_HW_RATE_OFDM18 = 0x7, 253 RTW89_HW_RATE_OFDM24 = 0x8, 254 RTW89_HW_RATE_OFDM36 = 0x9, 255 RTW89_HW_RATE_OFDM48 = 0xA, 256 RTW89_HW_RATE_OFDM54 = 0xB, 257 RTW89_HW_RATE_MCS0 = 0x80, 258 RTW89_HW_RATE_MCS1 = 0x81, 259 RTW89_HW_RATE_MCS2 = 0x82, 260 RTW89_HW_RATE_MCS3 = 0x83, 261 RTW89_HW_RATE_MCS4 = 0x84, 262 RTW89_HW_RATE_MCS5 = 0x85, 263 RTW89_HW_RATE_MCS6 = 0x86, 264 RTW89_HW_RATE_MCS7 = 0x87, 265 RTW89_HW_RATE_MCS8 = 0x88, 266 RTW89_HW_RATE_MCS9 = 0x89, 267 RTW89_HW_RATE_MCS10 = 0x8A, 268 RTW89_HW_RATE_MCS11 = 0x8B, 269 RTW89_HW_RATE_MCS12 = 0x8C, 270 RTW89_HW_RATE_MCS13 = 0x8D, 271 RTW89_HW_RATE_MCS14 = 0x8E, 272 RTW89_HW_RATE_MCS15 = 0x8F, 273 RTW89_HW_RATE_MCS16 = 0x90, 274 RTW89_HW_RATE_MCS17 = 0x91, 275 RTW89_HW_RATE_MCS18 = 0x92, 276 RTW89_HW_RATE_MCS19 = 0x93, 277 RTW89_HW_RATE_MCS20 = 0x94, 278 RTW89_HW_RATE_MCS21 = 0x95, 279 RTW89_HW_RATE_MCS22 = 0x96, 280 RTW89_HW_RATE_MCS23 = 0x97, 281 RTW89_HW_RATE_MCS24 = 0x98, 282 RTW89_HW_RATE_MCS25 = 0x99, 283 RTW89_HW_RATE_MCS26 = 0x9A, 284 RTW89_HW_RATE_MCS27 = 0x9B, 285 RTW89_HW_RATE_MCS28 = 0x9C, 286 RTW89_HW_RATE_MCS29 = 0x9D, 287 RTW89_HW_RATE_MCS30 = 0x9E, 288 RTW89_HW_RATE_MCS31 = 0x9F, 289 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 290 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 291 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 292 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 293 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 294 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 295 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 296 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 297 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 298 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 299 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 300 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 301 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 302 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 303 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 304 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 305 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 306 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 307 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 308 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 309 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 310 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 311 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 312 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 313 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 314 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 315 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 316 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 317 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 318 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 319 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 320 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 321 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 322 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 323 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 324 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 325 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 326 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 327 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 328 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 329 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 330 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 331 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 332 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 333 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 334 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 335 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 336 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 337 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 338 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 339 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 340 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 341 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 342 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 343 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 344 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 345 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 346 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 347 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 348 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 349 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 350 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 351 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 352 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 353 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 354 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 355 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 356 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 357 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 358 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 359 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 360 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 361 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 362 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 363 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 364 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 365 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 366 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 367 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 368 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 369 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 370 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 371 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 372 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 373 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 374 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 375 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 376 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 377 RTW89_HW_RATE_NR, 378 379 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 380 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 381 }; 382 383 /* 2G channels, 384 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 385 */ 386 #define RTW89_2G_CH_NUM 14 387 388 /* 5G channels, 389 * 36, 38, 40, 42, 44, 46, 48, 50, 390 * 52, 54, 56, 58, 60, 62, 64, 391 * 100, 102, 104, 106, 108, 110, 112, 114, 392 * 116, 118, 120, 122, 124, 126, 128, 130, 393 * 132, 134, 136, 138, 140, 142, 144, 394 * 149, 151, 153, 155, 157, 159, 161, 163, 395 * 165, 167, 169, 171, 173, 175, 177 396 */ 397 #define RTW89_5G_CH_NUM 53 398 399 /* 6G channels, 400 * 1, 3, 5, 7, 9, 11, 13, 15, 401 * 17, 19, 21, 23, 25, 27, 29, 33, 402 * 35, 37, 39, 41, 43, 45, 47, 49, 403 * 51, 53, 55, 57, 59, 61, 65, 67, 404 * 69, 71, 73, 75, 77, 79, 81, 83, 405 * 85, 87, 89, 91, 93, 97, 99, 101, 406 * 103, 105, 107, 109, 111, 113, 115, 117, 407 * 119, 121, 123, 125, 129, 131, 133, 135, 408 * 137, 139, 141, 143, 145, 147, 149, 151, 409 * 153, 155, 157, 161, 163, 165, 167, 169, 410 * 171, 173, 175, 177, 179, 181, 183, 185, 411 * 187, 189, 193, 195, 197, 199, 201, 203, 412 * 205, 207, 209, 211, 213, 215, 217, 219, 413 * 221, 225, 227, 229, 231, 233, 235, 237, 414 * 239, 241, 243, 245, 247, 249, 251, 253, 415 */ 416 #define RTW89_6G_CH_NUM 120 417 418 enum rtw89_rate_section { 419 RTW89_RS_CCK, 420 RTW89_RS_OFDM, 421 RTW89_RS_MCS, /* for HT/VHT/HE */ 422 RTW89_RS_HEDCM, 423 RTW89_RS_OFFSET, 424 RTW89_RS_MAX, 425 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 426 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 427 }; 428 429 enum rtw89_rate_max { 430 RTW89_RATE_CCK_MAX = 4, 431 RTW89_RATE_OFDM_MAX = 8, 432 RTW89_RATE_MCS_MAX = 12, 433 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 434 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 435 }; 436 437 enum rtw89_nss { 438 RTW89_NSS_1 = 0, 439 RTW89_NSS_2 = 1, 440 /* HE DCM only support 1ss and 2ss */ 441 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 442 RTW89_NSS_3 = 2, 443 RTW89_NSS_4 = 3, 444 RTW89_NSS_MAX, 445 }; 446 447 enum rtw89_ntx { 448 RTW89_1TX = 0, 449 RTW89_2TX = 1, 450 RTW89_NTX_NUM, 451 }; 452 453 enum rtw89_beamforming_type { 454 RTW89_NONBF = 0, 455 RTW89_BF = 1, 456 RTW89_BF_NUM, 457 }; 458 459 enum rtw89_regulation_type { 460 RTW89_WW = 0, 461 RTW89_ETSI = 1, 462 RTW89_FCC = 2, 463 RTW89_MKK = 3, 464 RTW89_NA = 4, 465 RTW89_IC = 5, 466 RTW89_KCC = 6, 467 RTW89_ACMA = 7, 468 RTW89_NCC = 8, 469 RTW89_MEXICO = 9, 470 RTW89_CHILE = 10, 471 RTW89_UKRAINE = 11, 472 RTW89_CN = 12, 473 RTW89_QATAR = 13, 474 RTW89_UK = 14, 475 RTW89_REGD_NUM, 476 }; 477 478 struct rtw89_txpwr_byrate { 479 s8 cck[RTW89_RATE_CCK_MAX]; 480 s8 ofdm[RTW89_RATE_OFDM_MAX]; 481 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 482 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 483 s8 offset[RTW89_RATE_OFFSET_MAX]; 484 }; 485 486 enum rtw89_bandwidth_section_num { 487 RTW89_BW20_SEC_NUM = 8, 488 RTW89_BW40_SEC_NUM = 4, 489 RTW89_BW80_SEC_NUM = 2, 490 }; 491 492 struct rtw89_txpwr_limit { 493 s8 cck_20m[RTW89_BF_NUM]; 494 s8 cck_40m[RTW89_BF_NUM]; 495 s8 ofdm[RTW89_BF_NUM]; 496 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 497 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 498 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 499 s8 mcs_160m[RTW89_BF_NUM]; 500 s8 mcs_40m_0p5[RTW89_BF_NUM]; 501 s8 mcs_40m_2p5[RTW89_BF_NUM]; 502 }; 503 504 #define RTW89_RU_SEC_NUM 8 505 506 struct rtw89_txpwr_limit_ru { 507 s8 ru26[RTW89_RU_SEC_NUM]; 508 s8 ru52[RTW89_RU_SEC_NUM]; 509 s8 ru106[RTW89_RU_SEC_NUM]; 510 }; 511 512 struct rtw89_rate_desc { 513 enum rtw89_nss nss; 514 enum rtw89_rate_section rs; 515 u8 idx; 516 }; 517 518 #define PHY_STS_HDR_LEN 8 519 #define RF_PATH_MAX 4 520 #define RTW89_MAX_PPDU_CNT 8 521 struct rtw89_rx_phy_ppdu { 522 u8 *buf; 523 u32 len; 524 u8 rssi_avg; 525 s8 rssi[RF_PATH_MAX]; 526 u8 mac_id; 527 u8 chan_idx; 528 u8 ie; 529 u16 rate; 530 bool to_self; 531 bool valid; 532 }; 533 534 enum rtw89_mac_idx { 535 RTW89_MAC_0 = 0, 536 RTW89_MAC_1 = 1, 537 }; 538 539 enum rtw89_phy_idx { 540 RTW89_PHY_0 = 0, 541 RTW89_PHY_1 = 1, 542 RTW89_PHY_MAX 543 }; 544 545 enum rtw89_sub_entity_idx { 546 RTW89_SUB_ENTITY_0 = 0, 547 548 NUM_OF_RTW89_SUB_ENTITY, 549 }; 550 551 enum rtw89_rf_path { 552 RF_PATH_A = 0, 553 RF_PATH_B = 1, 554 RF_PATH_C = 2, 555 RF_PATH_D = 3, 556 RF_PATH_AB, 557 RF_PATH_AC, 558 RF_PATH_AD, 559 RF_PATH_BC, 560 RF_PATH_BD, 561 RF_PATH_CD, 562 RF_PATH_ABC, 563 RF_PATH_ABD, 564 RF_PATH_ACD, 565 RF_PATH_BCD, 566 RF_PATH_ABCD, 567 }; 568 569 enum rtw89_rf_path_bit { 570 RF_A = BIT(0), 571 RF_B = BIT(1), 572 RF_C = BIT(2), 573 RF_D = BIT(3), 574 575 RF_AB = (RF_A | RF_B), 576 RF_AC = (RF_A | RF_C), 577 RF_AD = (RF_A | RF_D), 578 RF_BC = (RF_B | RF_C), 579 RF_BD = (RF_B | RF_D), 580 RF_CD = (RF_C | RF_D), 581 582 RF_ABC = (RF_A | RF_B | RF_C), 583 RF_ABD = (RF_A | RF_B | RF_D), 584 RF_ACD = (RF_A | RF_C | RF_D), 585 RF_BCD = (RF_B | RF_C | RF_D), 586 587 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 588 }; 589 590 enum rtw89_bandwidth { 591 RTW89_CHANNEL_WIDTH_20 = 0, 592 RTW89_CHANNEL_WIDTH_40 = 1, 593 RTW89_CHANNEL_WIDTH_80 = 2, 594 RTW89_CHANNEL_WIDTH_160 = 3, 595 RTW89_CHANNEL_WIDTH_80_80 = 4, 596 RTW89_CHANNEL_WIDTH_5 = 5, 597 RTW89_CHANNEL_WIDTH_10 = 6, 598 }; 599 600 enum rtw89_ps_mode { 601 RTW89_PS_MODE_NONE = 0, 602 RTW89_PS_MODE_RFOFF = 1, 603 RTW89_PS_MODE_CLK_GATED = 2, 604 RTW89_PS_MODE_PWR_GATED = 3, 605 }; 606 607 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 608 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 609 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 610 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 611 612 enum rtw89_ru_bandwidth { 613 RTW89_RU26 = 0, 614 RTW89_RU52 = 1, 615 RTW89_RU106 = 2, 616 RTW89_RU_NUM, 617 }; 618 619 enum rtw89_sc_offset { 620 RTW89_SC_DONT_CARE = 0, 621 RTW89_SC_20_UPPER = 1, 622 RTW89_SC_20_LOWER = 2, 623 RTW89_SC_20_UPMOST = 3, 624 RTW89_SC_20_LOWEST = 4, 625 RTW89_SC_20_UP2X = 5, 626 RTW89_SC_20_LOW2X = 6, 627 RTW89_SC_20_UP3X = 7, 628 RTW89_SC_20_LOW3X = 8, 629 RTW89_SC_40_UPPER = 9, 630 RTW89_SC_40_LOWER = 10, 631 }; 632 633 struct rtw89_chan { 634 u8 channel; 635 u8 primary_channel; 636 enum rtw89_band band_type; 637 enum rtw89_bandwidth band_width; 638 639 /* The follow-up are derived from the above. We must ensure that it 640 * is assigned correctly in rtw89_chan_create() if new one is added. 641 */ 642 u32 freq; 643 enum rtw89_subband subband_type; 644 enum rtw89_sc_offset pri_ch_idx; 645 }; 646 647 struct rtw89_chan_rcd { 648 u8 prev_primary_channel; 649 enum rtw89_band prev_band_type; 650 }; 651 652 struct rtw89_channel_help_params { 653 u32 tx_en; 654 }; 655 656 struct rtw89_port_reg { 657 u32 port_cfg; 658 u32 tbtt_prohib; 659 u32 bcn_area; 660 u32 bcn_early; 661 u32 tbtt_early; 662 u32 tbtt_agg; 663 u32 bcn_space; 664 u32 bcn_forcetx; 665 u32 bcn_err_cnt; 666 u32 bcn_err_flag; 667 u32 dtim_ctrl; 668 u32 tbtt_shift; 669 u32 bcn_cnt_tmr; 670 u32 tsftr_l; 671 u32 tsftr_h; 672 }; 673 674 struct rtw89_txwd_body { 675 __le32 dword0; 676 __le32 dword1; 677 __le32 dword2; 678 __le32 dword3; 679 __le32 dword4; 680 __le32 dword5; 681 } __packed; 682 683 struct rtw89_txwd_body_v1 { 684 __le32 dword0; 685 __le32 dword1; 686 __le32 dword2; 687 __le32 dword3; 688 __le32 dword4; 689 __le32 dword5; 690 __le32 dword6; 691 __le32 dword7; 692 } __packed; 693 694 struct rtw89_txwd_info { 695 __le32 dword0; 696 __le32 dword1; 697 __le32 dword2; 698 __le32 dword3; 699 __le32 dword4; 700 __le32 dword5; 701 } __packed; 702 703 struct rtw89_rx_desc_info { 704 u16 pkt_size; 705 u8 pkt_type; 706 u8 drv_info_size; 707 u8 shift; 708 u8 wl_hd_iv_len; 709 bool long_rxdesc; 710 bool bb_sel; 711 bool mac_info_valid; 712 u16 data_rate; 713 u8 gi_ltf; 714 u8 bw; 715 u32 free_run_cnt; 716 u8 user_id; 717 bool sr_en; 718 u8 ppdu_cnt; 719 u8 ppdu_type; 720 bool icv_err; 721 bool crc32_err; 722 bool hw_dec; 723 bool sw_dec; 724 bool addr1_match; 725 u8 frag; 726 u16 seq; 727 u8 frame_type; 728 u8 rx_pl_id; 729 bool addr_cam_valid; 730 u8 addr_cam_id; 731 u8 sec_cam_id; 732 u8 mac_id; 733 u16 offset; 734 bool ready; 735 }; 736 737 struct rtw89_rxdesc_short { 738 __le32 dword0; 739 __le32 dword1; 740 __le32 dword2; 741 __le32 dword3; 742 } __packed; 743 744 struct rtw89_rxdesc_long { 745 __le32 dword0; 746 __le32 dword1; 747 __le32 dword2; 748 __le32 dword3; 749 __le32 dword4; 750 __le32 dword5; 751 __le32 dword6; 752 __le32 dword7; 753 } __packed; 754 755 struct rtw89_tx_desc_info { 756 u16 pkt_size; 757 u8 wp_offset; 758 u8 mac_id; 759 u8 qsel; 760 u8 ch_dma; 761 u8 hdr_llc_len; 762 bool is_bmc; 763 bool en_wd_info; 764 bool wd_page; 765 bool use_rate; 766 bool dis_data_fb; 767 bool tid_indicate; 768 bool agg_en; 769 bool bk; 770 u8 ampdu_density; 771 u8 ampdu_num; 772 bool sec_en; 773 u8 addr_info_nr; 774 u8 sec_keyid; 775 u8 sec_type; 776 u8 sec_cam_idx; 777 u8 sec_seq[6]; 778 u16 data_rate; 779 u16 data_retry_lowest_rate; 780 bool fw_dl; 781 u16 seq; 782 bool a_ctrl_bsr; 783 u8 hw_ssn_sel; 784 #define RTW89_MGMT_HW_SSN_SEL 1 785 u8 hw_seq_mode; 786 #define RTW89_MGMT_HW_SEQ_MODE 1 787 bool hiq; 788 u8 port; 789 }; 790 791 struct rtw89_core_tx_request { 792 enum rtw89_core_tx_type tx_type; 793 794 struct sk_buff *skb; 795 struct ieee80211_vif *vif; 796 struct ieee80211_sta *sta; 797 struct rtw89_tx_desc_info desc_info; 798 }; 799 800 struct rtw89_txq { 801 struct list_head list; 802 unsigned long flags; 803 int wait_cnt; 804 }; 805 806 struct rtw89_mac_ax_gnt { 807 u8 gnt_bt_sw_en; 808 u8 gnt_bt; 809 u8 gnt_wl_sw_en; 810 u8 gnt_wl; 811 } __packed; 812 813 #define RTW89_MAC_AX_COEX_GNT_NR 2 814 struct rtw89_mac_ax_coex_gnt { 815 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 816 }; 817 818 enum rtw89_btc_ncnt { 819 BTC_NCNT_POWER_ON = 0x0, 820 BTC_NCNT_POWER_OFF, 821 BTC_NCNT_INIT_COEX, 822 BTC_NCNT_SCAN_START, 823 BTC_NCNT_SCAN_FINISH, 824 BTC_NCNT_SPECIAL_PACKET, 825 BTC_NCNT_SWITCH_BAND, 826 BTC_NCNT_RFK_TIMEOUT, 827 BTC_NCNT_SHOW_COEX_INFO, 828 BTC_NCNT_ROLE_INFO, 829 BTC_NCNT_CONTROL, 830 BTC_NCNT_RADIO_STATE, 831 BTC_NCNT_CUSTOMERIZE, 832 BTC_NCNT_WL_RFK, 833 BTC_NCNT_WL_STA, 834 BTC_NCNT_FWINFO, 835 BTC_NCNT_TIMER, 836 BTC_NCNT_NUM 837 }; 838 839 enum rtw89_btc_btinfo { 840 BTC_BTINFO_L0 = 0, 841 BTC_BTINFO_L1, 842 BTC_BTINFO_L2, 843 BTC_BTINFO_L3, 844 BTC_BTINFO_H0, 845 BTC_BTINFO_H1, 846 BTC_BTINFO_H2, 847 BTC_BTINFO_H3, 848 BTC_BTINFO_MAX 849 }; 850 851 enum rtw89_btc_dcnt { 852 BTC_DCNT_RUN = 0x0, 853 BTC_DCNT_CX_RUNINFO, 854 BTC_DCNT_RPT, 855 BTC_DCNT_RPT_FREEZE, 856 BTC_DCNT_CYCLE, 857 BTC_DCNT_CYCLE_FREEZE, 858 BTC_DCNT_W1, 859 BTC_DCNT_W1_FREEZE, 860 BTC_DCNT_B1, 861 BTC_DCNT_B1_FREEZE, 862 BTC_DCNT_TDMA_NONSYNC, 863 BTC_DCNT_SLOT_NONSYNC, 864 BTC_DCNT_BTCNT_FREEZE, 865 BTC_DCNT_WL_SLOT_DRIFT, 866 BTC_DCNT_BT_SLOT_DRIFT, 867 BTC_DCNT_WL_STA_LAST, 868 BTC_DCNT_NUM, 869 }; 870 871 enum rtw89_btc_wl_state_cnt { 872 BTC_WCNT_SCANAP = 0x0, 873 BTC_WCNT_DHCP, 874 BTC_WCNT_EAPOL, 875 BTC_WCNT_ARP, 876 BTC_WCNT_SCBDUPDATE, 877 BTC_WCNT_RFK_REQ, 878 BTC_WCNT_RFK_GO, 879 BTC_WCNT_RFK_REJECT, 880 BTC_WCNT_RFK_TIMEOUT, 881 BTC_WCNT_CH_UPDATE, 882 BTC_WCNT_NUM 883 }; 884 885 enum rtw89_btc_bt_state_cnt { 886 BTC_BCNT_RETRY = 0x0, 887 BTC_BCNT_REINIT, 888 BTC_BCNT_REENABLE, 889 BTC_BCNT_SCBDREAD, 890 BTC_BCNT_RELINK, 891 BTC_BCNT_IGNOWL, 892 BTC_BCNT_INQPAG, 893 BTC_BCNT_INQ, 894 BTC_BCNT_PAGE, 895 BTC_BCNT_ROLESW, 896 BTC_BCNT_AFH, 897 BTC_BCNT_INFOUPDATE, 898 BTC_BCNT_INFOSAME, 899 BTC_BCNT_SCBDUPDATE, 900 BTC_BCNT_HIPRI_TX, 901 BTC_BCNT_HIPRI_RX, 902 BTC_BCNT_LOPRI_TX, 903 BTC_BCNT_LOPRI_RX, 904 BTC_BCNT_POLUT, 905 BTC_BCNT_RATECHG, 906 BTC_BCNT_NUM 907 }; 908 909 enum rtw89_btc_bt_profile { 910 BTC_BT_NOPROFILE = 0, 911 BTC_BT_HFP = BIT(0), 912 BTC_BT_HID = BIT(1), 913 BTC_BT_A2DP = BIT(2), 914 BTC_BT_PAN = BIT(3), 915 BTC_PROFILE_MAX = 4, 916 }; 917 918 struct rtw89_btc_ant_info { 919 u8 type; /* shared, dedicated */ 920 u8 num; 921 u8 isolation; 922 923 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 924 u8 diversity: 1; 925 }; 926 927 enum rtw89_tfc_dir { 928 RTW89_TFC_UL, 929 RTW89_TFC_DL, 930 }; 931 932 struct rtw89_btc_wl_smap { 933 u32 busy: 1; 934 u32 scan: 1; 935 u32 connecting: 1; 936 u32 roaming: 1; 937 u32 _4way: 1; 938 u32 rf_off: 1; 939 u32 lps: 2; 940 u32 ips: 1; 941 u32 init_ok: 1; 942 u32 traffic_dir : 2; 943 u32 rf_off_pre: 1; 944 u32 lps_pre: 2; 945 }; 946 947 enum rtw89_tfc_lv { 948 RTW89_TFC_IDLE, 949 RTW89_TFC_ULTRA_LOW, 950 RTW89_TFC_LOW, 951 RTW89_TFC_MID, 952 RTW89_TFC_HIGH, 953 }; 954 955 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 956 DECLARE_EWMA(tp, 10, 2); 957 958 struct rtw89_traffic_stats { 959 /* units in bytes */ 960 u64 tx_unicast; 961 u64 rx_unicast; 962 u32 tx_avg_len; 963 u32 rx_avg_len; 964 965 /* count for packets */ 966 u64 tx_cnt; 967 u64 rx_cnt; 968 969 /* units in Mbps */ 970 u32 tx_throughput; 971 u32 rx_throughput; 972 u32 tx_throughput_raw; 973 u32 rx_throughput_raw; 974 975 u32 rx_tf_acc; 976 u32 rx_tf_periodic; 977 978 enum rtw89_tfc_lv tx_tfc_lv; 979 enum rtw89_tfc_lv rx_tfc_lv; 980 struct ewma_tp tx_ewma_tp; 981 struct ewma_tp rx_ewma_tp; 982 983 u16 tx_rate; 984 u16 rx_rate; 985 }; 986 987 struct rtw89_btc_statistic { 988 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 989 struct rtw89_traffic_stats traffic; 990 }; 991 992 #define BTC_WL_RSSI_THMAX 4 993 994 struct rtw89_btc_wl_link_info { 995 struct rtw89_btc_statistic stat; 996 enum rtw89_tfc_dir dir; 997 u8 rssi_state[BTC_WL_RSSI_THMAX]; 998 u8 mac_addr[ETH_ALEN]; 999 u8 busy; 1000 u8 ch; 1001 u8 bw; 1002 u8 band; 1003 u8 role; 1004 u8 pid; 1005 u8 phy; 1006 u8 dtim_period; 1007 u8 mode; 1008 1009 u8 mac_id; 1010 u8 tx_retry; 1011 1012 u32 bcn_period; 1013 u32 busy_t; 1014 u32 tx_time; 1015 u32 client_cnt; 1016 u32 rx_rate_drop_cnt; 1017 1018 u32 active: 1; 1019 u32 noa: 1; 1020 u32 client_ps: 1; 1021 u32 connected: 2; 1022 }; 1023 1024 union rtw89_btc_wl_state_map { 1025 u32 val; 1026 struct rtw89_btc_wl_smap map; 1027 }; 1028 1029 struct rtw89_btc_bt_hfp_desc { 1030 u32 exist: 1; 1031 u32 type: 2; 1032 u32 rsvd: 29; 1033 }; 1034 1035 struct rtw89_btc_bt_hid_desc { 1036 u32 exist: 1; 1037 u32 slot_info: 2; 1038 u32 pair_cnt: 2; 1039 u32 type: 8; 1040 u32 rsvd: 19; 1041 }; 1042 1043 struct rtw89_btc_bt_a2dp_desc { 1044 u8 exist: 1; 1045 u8 exist_last: 1; 1046 u8 play_latency: 1; 1047 u8 type: 3; 1048 u8 active: 1; 1049 u8 sink: 1; 1050 1051 u8 bitpool; 1052 u16 vendor_id; 1053 u32 device_name; 1054 u32 flush_time; 1055 }; 1056 1057 struct rtw89_btc_bt_pan_desc { 1058 u32 exist: 1; 1059 u32 type: 1; 1060 u32 active: 1; 1061 u32 rsvd: 29; 1062 }; 1063 1064 struct rtw89_btc_bt_rfk_info { 1065 u32 run: 1; 1066 u32 req: 1; 1067 u32 timeout: 1; 1068 u32 rsvd: 29; 1069 }; 1070 1071 union rtw89_btc_bt_rfk_info_map { 1072 u32 val; 1073 struct rtw89_btc_bt_rfk_info map; 1074 }; 1075 1076 struct rtw89_btc_bt_ver_info { 1077 u32 fw_coex; /* match with which coex_ver */ 1078 u32 fw; 1079 }; 1080 1081 struct rtw89_btc_bool_sta_chg { 1082 u32 now: 1; 1083 u32 last: 1; 1084 u32 remain: 1; 1085 u32 srvd: 29; 1086 }; 1087 1088 struct rtw89_btc_u8_sta_chg { 1089 u8 now; 1090 u8 last; 1091 u8 remain; 1092 u8 rsvd; 1093 }; 1094 1095 struct rtw89_btc_wl_scan_info { 1096 u8 band[RTW89_PHY_MAX]; 1097 u8 phy_map; 1098 u8 rsvd; 1099 }; 1100 1101 struct rtw89_btc_wl_dbcc_info { 1102 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1103 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1104 u8 real_band[RTW89_PHY_MAX]; 1105 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1106 }; 1107 1108 struct rtw89_btc_wl_active_role { 1109 u8 connected: 1; 1110 u8 pid: 3; 1111 u8 phy: 1; 1112 u8 noa: 1; 1113 u8 band: 2; 1114 1115 u8 client_ps: 1; 1116 u8 bw: 7; 1117 1118 u8 role; 1119 u8 ch; 1120 1121 u16 tx_lvl; 1122 u16 rx_lvl; 1123 u16 tx_rate; 1124 u16 rx_rate; 1125 }; 1126 1127 struct rtw89_btc_wl_active_role_v1 { 1128 u8 connected: 1; 1129 u8 pid: 3; 1130 u8 phy: 1; 1131 u8 noa: 1; 1132 u8 band: 2; 1133 1134 u8 client_ps: 1; 1135 u8 bw: 7; 1136 1137 u8 role; 1138 u8 ch; 1139 1140 u16 tx_lvl; 1141 u16 rx_lvl; 1142 u16 tx_rate; 1143 u16 rx_rate; 1144 1145 u32 noa_duration; /* ms */ 1146 }; 1147 1148 struct rtw89_btc_wl_role_info_bpos { 1149 u16 none: 1; 1150 u16 station: 1; 1151 u16 ap: 1; 1152 u16 vap: 1; 1153 u16 adhoc: 1; 1154 u16 adhoc_master: 1; 1155 u16 mesh: 1; 1156 u16 moniter: 1; 1157 u16 p2p_device: 1; 1158 u16 p2p_gc: 1; 1159 u16 p2p_go: 1; 1160 u16 nan: 1; 1161 }; 1162 1163 struct rtw89_btc_wl_scc_ctrl { 1164 u8 null_role1; 1165 u8 null_role2; 1166 u8 ebt_null; /* if tx null at EBT slot */ 1167 }; 1168 1169 union rtw89_btc_wl_role_info_map { 1170 u16 val; 1171 struct rtw89_btc_wl_role_info_bpos role; 1172 }; 1173 1174 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1175 u8 connect_cnt; 1176 u8 link_mode; 1177 union rtw89_btc_wl_role_info_map role_map; 1178 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1179 }; 1180 1181 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1182 u8 connect_cnt; 1183 u8 link_mode; 1184 union rtw89_btc_wl_role_info_map role_map; 1185 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1186 u32 mrole_type; /* btc_wl_mrole_type */ 1187 u32 mrole_noa_duration; /* ms */ 1188 1189 u32 dbcc_en: 1; 1190 u32 dbcc_chg: 1; 1191 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1192 u32 link_mode_chg: 1; 1193 u32 rsvd: 27; 1194 }; 1195 1196 struct rtw89_btc_wl_ver_info { 1197 u32 fw_coex; /* match with which coex_ver */ 1198 u32 fw; 1199 u32 mac; 1200 u32 bb; 1201 u32 rf; 1202 }; 1203 1204 struct rtw89_btc_wl_afh_info { 1205 u8 en; 1206 u8 ch; 1207 u8 bw; 1208 u8 rsvd; 1209 } __packed; 1210 1211 struct rtw89_btc_wl_rfk_info { 1212 u32 state: 2; 1213 u32 path_map: 4; 1214 u32 phy_map: 2; 1215 u32 band: 2; 1216 u32 type: 8; 1217 u32 rsvd: 14; 1218 }; 1219 1220 struct rtw89_btc_bt_smap { 1221 u32 connect: 1; 1222 u32 ble_connect: 1; 1223 u32 acl_busy: 1; 1224 u32 sco_busy: 1; 1225 u32 mesh_busy: 1; 1226 u32 inq_pag: 1; 1227 }; 1228 1229 union rtw89_btc_bt_state_map { 1230 u32 val; 1231 struct rtw89_btc_bt_smap map; 1232 }; 1233 1234 #define BTC_BT_RSSI_THMAX 4 1235 #define BTC_BT_AFH_GROUP 12 1236 1237 struct rtw89_btc_bt_link_info { 1238 struct rtw89_btc_u8_sta_chg profile_cnt; 1239 struct rtw89_btc_bool_sta_chg multi_link; 1240 struct rtw89_btc_bool_sta_chg relink; 1241 struct rtw89_btc_bt_hfp_desc hfp_desc; 1242 struct rtw89_btc_bt_hid_desc hid_desc; 1243 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1244 struct rtw89_btc_bt_pan_desc pan_desc; 1245 union rtw89_btc_bt_state_map status; 1246 1247 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1248 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1249 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1250 u8 afh_map[BTC_BT_AFH_GROUP]; 1251 1252 u32 role_sw: 1; 1253 u32 slave_role: 1; 1254 u32 afh_update: 1; 1255 u32 cqddr: 1; 1256 u32 rssi: 8; 1257 u32 tx_3m: 1; 1258 u32 rsvd: 19; 1259 }; 1260 1261 struct rtw89_btc_3rdcx_info { 1262 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1263 u8 hw_coex; 1264 u16 rsvd; 1265 }; 1266 1267 struct rtw89_btc_dm_emap { 1268 u32 init: 1; 1269 u32 pta_owner: 1; 1270 u32 wl_rfk_timeout: 1; 1271 u32 bt_rfk_timeout: 1; 1272 1273 u32 wl_fw_hang: 1; 1274 u32 offload_mismatch: 1; 1275 u32 cycle_hang: 1; 1276 u32 w1_hang: 1; 1277 1278 u32 b1_hang: 1; 1279 u32 tdma_no_sync: 1; 1280 u32 wl_slot_drift: 1; 1281 }; 1282 1283 union rtw89_btc_dm_error_map { 1284 u32 val; 1285 struct rtw89_btc_dm_emap map; 1286 }; 1287 1288 struct rtw89_btc_rf_para { 1289 u32 tx_pwr_freerun; 1290 u32 rx_gain_freerun; 1291 u32 tx_pwr_perpkt; 1292 u32 rx_gain_perpkt; 1293 }; 1294 1295 struct rtw89_btc_wl_info { 1296 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1297 struct rtw89_btc_wl_rfk_info rfk_info; 1298 struct rtw89_btc_wl_ver_info ver_info; 1299 struct rtw89_btc_wl_afh_info afh_info; 1300 struct rtw89_btc_wl_role_info role_info; 1301 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1302 struct rtw89_btc_wl_scan_info scan_info; 1303 struct rtw89_btc_wl_dbcc_info dbcc_info; 1304 struct rtw89_btc_rf_para rf_para; 1305 union rtw89_btc_wl_state_map status; 1306 1307 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1308 u8 rssi_level; 1309 1310 u32 scbd; 1311 }; 1312 1313 struct rtw89_btc_module { 1314 struct rtw89_btc_ant_info ant; 1315 u8 rfe_type; 1316 u8 cv; 1317 1318 u8 bt_solo: 1; 1319 u8 bt_pos: 1; 1320 u8 switch_type: 1; 1321 1322 u8 rsvd; 1323 }; 1324 1325 #define RTW89_BTC_DM_MAXSTEP 30 1326 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1327 1328 struct rtw89_btc_dm_step { 1329 u16 step[RTW89_BTC_DM_MAXSTEP]; 1330 u8 step_pos; 1331 bool step_ov; 1332 }; 1333 1334 struct rtw89_btc_init_info { 1335 struct rtw89_btc_module module; 1336 u8 wl_guard_ch; 1337 1338 u8 wl_only: 1; 1339 u8 wl_init_ok: 1; 1340 u8 dbcc_en: 1; 1341 u8 cx_other: 1; 1342 u8 bt_only: 1; 1343 1344 u16 rsvd; 1345 }; 1346 1347 struct rtw89_btc_wl_tx_limit_para { 1348 u16 enable; 1349 u32 tx_time; /* unit: us */ 1350 u16 tx_retry; 1351 }; 1352 1353 struct rtw89_btc_bt_scan_info { 1354 u16 win; 1355 u16 intvl; 1356 u32 enable: 1; 1357 u32 interlace: 1; 1358 u32 rsvd: 30; 1359 }; 1360 1361 enum rtw89_btc_bt_scan_type { 1362 BTC_SCAN_INQ = 0, 1363 BTC_SCAN_PAGE, 1364 BTC_SCAN_BLE, 1365 BTC_SCAN_INIT, 1366 BTC_SCAN_TV, 1367 BTC_SCAN_ADV, 1368 BTC_SCAN_MAX1, 1369 }; 1370 1371 struct rtw89_btc_bt_info { 1372 struct rtw89_btc_bt_link_info link_info; 1373 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1374 struct rtw89_btc_bt_ver_info ver_info; 1375 struct rtw89_btc_bool_sta_chg enable; 1376 struct rtw89_btc_bool_sta_chg inq_pag; 1377 struct rtw89_btc_rf_para rf_para; 1378 union rtw89_btc_bt_rfk_info_map rfk_info; 1379 1380 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1381 1382 u32 scbd; 1383 u32 feature; 1384 1385 u32 mbx_avl: 1; 1386 u32 whql_test: 1; 1387 u32 igno_wl: 1; 1388 u32 reinit: 1; 1389 u32 ble_scan_en: 1; 1390 u32 btg_type: 1; 1391 u32 inq: 1; 1392 u32 pag: 1; 1393 u32 run_patch_code: 1; 1394 u32 hi_lna_rx: 1; 1395 u32 rsvd: 22; 1396 }; 1397 1398 struct rtw89_btc_cx { 1399 struct rtw89_btc_wl_info wl; 1400 struct rtw89_btc_bt_info bt; 1401 struct rtw89_btc_3rdcx_info other; 1402 u32 state_map; 1403 u32 cnt_bt[BTC_BCNT_NUM]; 1404 u32 cnt_wl[BTC_WCNT_NUM]; 1405 }; 1406 1407 struct rtw89_btc_fbtc_tdma { 1408 u8 type; /* chip_info::fcxtdma_ver */ 1409 u8 rxflctrl; 1410 u8 txpause; 1411 u8 wtgle_n; 1412 u8 leak_n; 1413 u8 ext_ctrl; 1414 u8 rxflctrl_role; 1415 u8 option_ctrl; 1416 } __packed; 1417 1418 struct rtw89_btc_fbtc_tdma_v1 { 1419 u8 fver; /* chip_info::fcxtdma_ver */ 1420 u8 rsvd; 1421 __le16 rsvd1; 1422 struct rtw89_btc_fbtc_tdma tdma; 1423 } __packed; 1424 1425 #define CXMREG_MAX 30 1426 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1427 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1428 1429 enum rtw89_btc_bt_sta_counter { 1430 BTC_BCNT_RFK_REQ = 0, 1431 BTC_BCNT_RFK_GO = 1, 1432 BTC_BCNT_RFK_REJECT = 2, 1433 BTC_BCNT_RFK_FAIL = 3, 1434 BTC_BCNT_RFK_TIMEOUT = 4, 1435 BTC_BCNT_HI_TX = 5, 1436 BTC_BCNT_HI_RX = 6, 1437 BTC_BCNT_LO_TX = 7, 1438 BTC_BCNT_LO_RX = 8, 1439 BTC_BCNT_POLLUTED = 9, 1440 BTC_BCNT_STA_MAX 1441 }; 1442 1443 struct rtw89_btc_fbtc_rpt_ctrl { 1444 u16 fver; /* chip_info::fcxbtcrpt_ver */ 1445 u16 rpt_cnt; /* tmr counters */ 1446 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1447 u32 wl_fw_cx_offload; 1448 u32 wl_fw_ver; 1449 u32 rpt_enable; 1450 u32 rpt_para; /* ms */ 1451 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1452 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1453 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1454 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1455 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1456 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1457 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1458 u32 c2h_cnt; /* fw send c2h counter */ 1459 u32 h2c_cnt; /* fw recv h2c counter */ 1460 } __packed; 1461 1462 struct rtw89_btc_fbtc_rpt_ctrl_info { 1463 __le32 cnt; /* fw report counter */ 1464 __le32 en; /* report map */ 1465 __le32 para; /* not used */ 1466 1467 __le32 cnt_c2h; /* fw send c2h counter */ 1468 __le32 cnt_h2c; /* fw recv h2c counter */ 1469 __le32 len_c2h; /* The total length of the last C2H */ 1470 1471 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1472 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1473 } __packed; 1474 1475 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1476 __le32 cx_ver; /* match which driver's coex version */ 1477 __le32 cx_offload; 1478 __le32 fw_ver; 1479 } __packed; 1480 1481 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1482 __le32 cnt_empty; /* a2dp empty count */ 1483 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1484 __le32 cnt_tx; 1485 __le32 cnt_ack; 1486 __le32 cnt_nack; 1487 } __packed; 1488 1489 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1490 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1491 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1492 __le32 cnt_recv; /* fw recv mailbox counter */ 1493 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1494 } __packed; 1495 1496 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1497 u8 fver; 1498 u8 rsvd; 1499 __le16 rsvd1; 1500 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1501 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1502 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1503 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1504 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1505 } __packed; 1506 1507 enum rtw89_fbtc_ext_ctrl_type { 1508 CXECTL_OFF = 0x0, /* tdma off */ 1509 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1510 CXECTL_EXT = 0x2, 1511 CXECTL_MAX 1512 }; 1513 1514 union rtw89_btc_fbtc_rxflct { 1515 u8 val; 1516 u8 type: 3; 1517 u8 tgln_n: 5; 1518 }; 1519 1520 enum rtw89_btc_cxst_state { 1521 CXST_OFF = 0x0, 1522 CXST_B2W = 0x1, 1523 CXST_W1 = 0x2, 1524 CXST_W2 = 0x3, 1525 CXST_W2B = 0x4, 1526 CXST_B1 = 0x5, 1527 CXST_B2 = 0x6, 1528 CXST_B3 = 0x7, 1529 CXST_B4 = 0x8, 1530 CXST_LK = 0x9, 1531 CXST_BLK = 0xa, 1532 CXST_E2G = 0xb, 1533 CXST_E5G = 0xc, 1534 CXST_EBT = 0xd, 1535 CXST_ENULL = 0xe, 1536 CXST_WLK = 0xf, 1537 CXST_W1FDD = 0x10, 1538 CXST_B1FDD = 0x11, 1539 CXST_MAX = 0x12, 1540 }; 1541 1542 enum { 1543 CXBCN_ALL = 0x0, 1544 CXBCN_ALL_OK, 1545 CXBCN_BT_SLOT, 1546 CXBCN_BT_OK, 1547 CXBCN_MAX 1548 }; 1549 1550 enum btc_slot_type { 1551 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1552 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1553 CXSTYPE_NUM, 1554 }; 1555 1556 enum { /* TIME */ 1557 CXT_BT = 0x0, 1558 CXT_WL = 0x1, 1559 CXT_MAX 1560 }; 1561 1562 enum { /* TIME-A2DP */ 1563 CXT_FLCTRL_OFF = 0x0, 1564 CXT_FLCTRL_ON = 0x1, 1565 CXT_FLCTRL_MAX 1566 }; 1567 1568 enum { /* STEP TYPE */ 1569 CXSTEP_NONE = 0x0, 1570 CXSTEP_EVNT = 0x1, 1571 CXSTEP_SLOT = 0x2, 1572 CXSTEP_MAX, 1573 }; 1574 1575 #define BTC_DBG_MAX1 32 1576 struct rtw89_btc_fbtc_gpio_dbg { 1577 u8 fver; /* chip_info::fcxgpiodbg_ver */ 1578 u8 rsvd; 1579 u16 rsvd2; 1580 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1581 u32 pre_state; /* the debug signal is 1 or 0 */ 1582 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1583 } __packed; 1584 1585 struct rtw89_btc_fbtc_mreg_val { 1586 u8 fver; /* chip_info::fcxmreg_ver */ 1587 u8 reg_num; 1588 __le16 rsvd; 1589 __le32 mreg_val[CXMREG_MAX]; 1590 } __packed; 1591 1592 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1593 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1594 .offset = cpu_to_le32(__offset), } 1595 1596 struct rtw89_btc_fbtc_mreg { 1597 __le16 type; 1598 __le16 bytes; 1599 __le32 offset; 1600 } __packed; 1601 1602 struct rtw89_btc_fbtc_slot { 1603 __le16 dur; 1604 __le32 cxtbl; 1605 __le16 cxtype; 1606 } __packed; 1607 1608 struct rtw89_btc_fbtc_slots { 1609 u8 fver; /* chip_info::fcxslots_ver */ 1610 u8 tbl_num; 1611 __le16 rsvd; 1612 __le32 update_map; 1613 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1614 } __packed; 1615 1616 struct rtw89_btc_fbtc_step { 1617 u8 type; 1618 u8 val; 1619 __le16 difft; 1620 } __packed; 1621 1622 struct rtw89_btc_fbtc_steps { 1623 u8 fver; /* chip_info::fcxstep_ver */ 1624 u8 rsvd; 1625 __le16 cnt; 1626 __le16 pos_old; 1627 __le16 pos_new; 1628 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1629 } __packed; 1630 1631 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1632 u8 fver; /* chip_info::fcxcysta_ver */ 1633 u8 rsvd; 1634 __le16 cycles; /* total cycle number */ 1635 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1636 __le16 a2dpept; /* a2dp empty cnt */ 1637 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1638 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1639 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1640 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1641 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1642 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1643 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1644 __le16 tmax_a2dpept; /* max a2dp empty time */ 1645 __le16 tavg_lk; /* avg leak-slot time */ 1646 __le16 tmax_lk; /* max leak-slot time */ 1647 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1648 __le32 bcn_cnt[CXBCN_MAX]; 1649 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1650 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1651 __le32 skip_cnt; 1652 __le32 exception; 1653 __le32 except_cnt; 1654 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1655 } __packed; 1656 1657 struct rtw89_btc_fbtc_fdd_try_info { 1658 __le16 cycles[CXT_FLCTRL_MAX]; 1659 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1660 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1661 } __packed; 1662 1663 struct rtw89_btc_fbtc_cycle_time_info { 1664 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1665 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1666 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1667 } __packed; 1668 1669 struct rtw89_btc_fbtc_a2dp_trx_stat { 1670 u8 empty_cnt; 1671 u8 retry_cnt; 1672 u8 tx_rate; 1673 u8 tx_cnt; 1674 u8 ack_cnt; 1675 u8 nack_cnt; 1676 u8 rsvd1; 1677 u8 rsvd2; 1678 } __packed; 1679 1680 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1681 __le16 cnt; /* a2dp empty cnt */ 1682 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1683 __le16 tavg; /* avg a2dp empty time */ 1684 __le16 tmax; /* max a2dp empty time */ 1685 } __packed; 1686 1687 struct rtw89_btc_fbtc_cycle_leak_info { 1688 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1689 __le16 tavg; /* avg leak-slot time */ 1690 __le16 tmax; /* max leak-slot time */ 1691 } __packed; 1692 1693 struct rtw89_btc_fbtc_cysta_v1 { /* statistics for cycles */ 1694 u8 fver; 1695 u8 rsvd; 1696 __le16 cycles; /* total cycle number */ 1697 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 1698 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 1699 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 1700 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 1701 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 1702 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 1703 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1704 __le32 bcn_cnt[CXBCN_MAX]; 1705 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 1706 __le32 skip_cnt; 1707 __le32 except_cnt; 1708 __le32 except_map; 1709 } __packed; 1710 1711 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1712 u8 fver; /* chip_info::fcxnullsta_ver */ 1713 u8 rsvd; 1714 __le16 rsvd2; 1715 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1716 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1717 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1718 } __packed; 1719 1720 struct rtw89_btc_fbtc_btver { 1721 u8 fver; /* chip_info::fcxbtver_ver */ 1722 u8 rsvd; 1723 __le16 rsvd2; 1724 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1725 __le32 fw_ver; 1726 __le32 feature; 1727 } __packed; 1728 1729 struct rtw89_btc_fbtc_btscan { 1730 u8 fver; /* chip_info::fcxbtscan_ver */ 1731 u8 rsvd; 1732 __le16 rsvd2; 1733 u8 scan[6]; 1734 } __packed; 1735 1736 struct rtw89_btc_fbtc_btafh { 1737 u8 fver; /* chip_info::fcxbtafh_ver */ 1738 u8 rsvd; 1739 __le16 rsvd2; 1740 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1741 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1742 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1743 } __packed; 1744 1745 struct rtw89_btc_fbtc_btdevinfo { 1746 u8 fver; /* chip_info::fcxbtdevinfo_ver */ 1747 u8 rsvd; 1748 __le16 vendor_id; 1749 __le32 dev_name; /* only 24 bits valid */ 1750 __le32 flush_time; 1751 } __packed; 1752 1753 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1754 struct rtw89_btc_rf_trx_para { 1755 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1756 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1757 u8 bt_tx_power; /* decrease Tx power (dB) */ 1758 u8 bt_rx_gain; /* LNA constrain level */ 1759 }; 1760 1761 struct rtw89_btc_dm { 1762 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1763 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1764 struct rtw89_btc_fbtc_tdma tdma; 1765 struct rtw89_btc_fbtc_tdma tdma_now; 1766 struct rtw89_mac_ax_coex_gnt gnt; 1767 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1768 struct rtw89_btc_rf_trx_para rf_trx_para; 1769 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1770 struct rtw89_btc_dm_step dm_step; 1771 struct rtw89_btc_wl_scc_ctrl wl_scc; 1772 union rtw89_btc_dm_error_map error; 1773 u32 cnt_dm[BTC_DCNT_NUM]; 1774 u32 cnt_notify[BTC_NCNT_NUM]; 1775 1776 u32 update_slot_map; 1777 u32 set_ant_path; 1778 1779 u32 wl_only: 1; 1780 u32 wl_fw_cx_offload: 1; 1781 u32 freerun: 1; 1782 u32 wl_ps_ctrl: 2; 1783 u32 wl_mimo_ps: 1; 1784 u32 leak_ap: 1; 1785 u32 noisy_level: 3; 1786 u32 coex_info_map: 8; 1787 u32 bt_only: 1; 1788 u32 wl_btg_rx: 1; 1789 u32 trx_para_level: 8; 1790 u32 wl_stb_chg: 1; 1791 u32 tdma_instant_excute: 1; 1792 u32 rsvd: 2; 1793 1794 u16 slot_dur[CXST_MAX]; 1795 1796 u8 run_reason; 1797 u8 run_action; 1798 }; 1799 1800 struct rtw89_btc_ctrl { 1801 u32 manual: 1; 1802 u32 igno_bt: 1; 1803 u32 always_freerun: 1; 1804 u32 trace_step: 16; 1805 u32 rsvd: 12; 1806 }; 1807 1808 struct rtw89_btc_dbg { 1809 /* cmd "rb" */ 1810 bool rb_done; 1811 u32 rb_val; 1812 }; 1813 1814 enum rtw89_btc_btf_fw_event { 1815 BTF_EVNT_RPT = 0, 1816 BTF_EVNT_BT_INFO = 1, 1817 BTF_EVNT_BT_SCBD = 2, 1818 BTF_EVNT_BT_REG = 3, 1819 BTF_EVNT_CX_RUNINFO = 4, 1820 BTF_EVNT_BT_PSD = 5, 1821 BTF_EVNT_BUF_OVERFLOW, 1822 BTF_EVNT_C2H_LOOPBACK, 1823 BTF_EVNT_MAX, 1824 }; 1825 1826 enum btf_fw_event_report { 1827 BTC_RPT_TYPE_CTRL = 0x0, 1828 BTC_RPT_TYPE_TDMA, 1829 BTC_RPT_TYPE_SLOT, 1830 BTC_RPT_TYPE_CYSTA, 1831 BTC_RPT_TYPE_STEP, 1832 BTC_RPT_TYPE_NULLSTA, 1833 BTC_RPT_TYPE_MREG, 1834 BTC_RPT_TYPE_GPIO_DBG, 1835 BTC_RPT_TYPE_BT_VER, 1836 BTC_RPT_TYPE_BT_SCAN, 1837 BTC_RPT_TYPE_BT_AFH, 1838 BTC_RPT_TYPE_BT_DEVICE, 1839 BTC_RPT_TYPE_TEST, 1840 BTC_RPT_TYPE_MAX = 31 1841 }; 1842 1843 enum rtw_btc_btf_reg_type { 1844 REG_MAC = 0x0, 1845 REG_BB = 0x1, 1846 REG_RF = 0x2, 1847 REG_BT_RF = 0x3, 1848 REG_BT_MODEM = 0x4, 1849 REG_BT_BLUEWIZE = 0x5, 1850 REG_BT_VENDOR = 0x6, 1851 REG_BT_LE = 0x7, 1852 REG_MAX_TYPE, 1853 }; 1854 1855 struct rtw89_btc_rpt_cmn_info { 1856 u32 rx_cnt; 1857 u32 rx_len; 1858 u32 req_len; /* expected rsp len */ 1859 u8 req_fver; /* expected rsp fver */ 1860 u8 rsp_fver; /* fver from fw */ 1861 u8 valid; 1862 } __packed; 1863 1864 struct rtw89_btc_report_ctrl_state { 1865 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1866 union { 1867 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw for 52A*/ 1868 struct rtw89_btc_fbtc_rpt_ctrl_v1 finfo_v1; /* info from fw for 52C*/ 1869 }; 1870 }; 1871 1872 struct rtw89_btc_rpt_fbtc_tdma { 1873 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1874 union { 1875 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1876 struct rtw89_btc_fbtc_tdma_v1 finfo_v1; /* info from fw for 52C*/ 1877 }; 1878 }; 1879 1880 struct rtw89_btc_rpt_fbtc_slots { 1881 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1882 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1883 }; 1884 1885 struct rtw89_btc_rpt_fbtc_cysta { 1886 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1887 union { 1888 struct rtw89_btc_fbtc_cysta finfo; /* info from fw for 52A*/ 1889 struct rtw89_btc_fbtc_cysta_v1 finfo_v1; /* info from fw for 52C*/ 1890 }; 1891 }; 1892 1893 struct rtw89_btc_rpt_fbtc_step { 1894 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1895 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1896 }; 1897 1898 struct rtw89_btc_rpt_fbtc_nullsta { 1899 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1900 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1901 }; 1902 1903 struct rtw89_btc_rpt_fbtc_mreg { 1904 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1905 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1906 }; 1907 1908 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1909 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1910 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1911 }; 1912 1913 struct rtw89_btc_rpt_fbtc_btver { 1914 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1915 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1916 }; 1917 1918 struct rtw89_btc_rpt_fbtc_btscan { 1919 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1920 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1921 }; 1922 1923 struct rtw89_btc_rpt_fbtc_btafh { 1924 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1925 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1926 }; 1927 1928 struct rtw89_btc_rpt_fbtc_btdev { 1929 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1930 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1931 }; 1932 1933 enum rtw89_btc_btfre_type { 1934 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1935 BTFRE_UNDEF_TYPE, 1936 BTFRE_EXCEPTION, 1937 BTFRE_MAX, 1938 }; 1939 1940 struct rtw89_btc_btf_fwinfo { 1941 u32 cnt_c2h; 1942 u32 cnt_h2c; 1943 u32 cnt_h2c_fail; 1944 u32 event[BTF_EVNT_MAX]; 1945 1946 u32 err[BTFRE_MAX]; 1947 u32 len_mismch; 1948 u32 fver_mismch; 1949 u32 rpt_en_map; 1950 1951 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1952 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1953 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1954 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1955 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1956 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1957 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1958 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1959 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1960 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1961 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1962 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1963 }; 1964 1965 #define RTW89_BTC_POLICY_MAXLEN 512 1966 1967 struct rtw89_btc { 1968 struct rtw89_btc_cx cx; 1969 struct rtw89_btc_dm dm; 1970 struct rtw89_btc_ctrl ctrl; 1971 struct rtw89_btc_module mdinfo; 1972 struct rtw89_btc_btf_fwinfo fwinfo; 1973 struct rtw89_btc_dbg dbg; 1974 1975 struct work_struct eapol_notify_work; 1976 struct work_struct arp_notify_work; 1977 struct work_struct dhcp_notify_work; 1978 struct work_struct icmp_notify_work; 1979 1980 u32 bt_req_len; 1981 1982 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 1983 u16 policy_len; 1984 u16 policy_type; 1985 bool bt_req_en; 1986 bool update_policy_force; 1987 bool lps; 1988 }; 1989 1990 enum rtw89_ra_mode { 1991 RTW89_RA_MODE_CCK = BIT(0), 1992 RTW89_RA_MODE_OFDM = BIT(1), 1993 RTW89_RA_MODE_HT = BIT(2), 1994 RTW89_RA_MODE_VHT = BIT(3), 1995 RTW89_RA_MODE_HE = BIT(4), 1996 }; 1997 1998 enum rtw89_ra_report_mode { 1999 RTW89_RA_RPT_MODE_LEGACY, 2000 RTW89_RA_RPT_MODE_HT, 2001 RTW89_RA_RPT_MODE_VHT, 2002 RTW89_RA_RPT_MODE_HE, 2003 }; 2004 2005 enum rtw89_dig_noisy_level { 2006 RTW89_DIG_NOISY_LEVEL0 = -1, 2007 RTW89_DIG_NOISY_LEVEL1 = 0, 2008 RTW89_DIG_NOISY_LEVEL2 = 1, 2009 RTW89_DIG_NOISY_LEVEL3 = 2, 2010 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2011 }; 2012 2013 enum rtw89_gi_ltf { 2014 RTW89_GILTF_LGI_4XHE32 = 0, 2015 RTW89_GILTF_SGI_4XHE08 = 1, 2016 RTW89_GILTF_2XHE16 = 2, 2017 RTW89_GILTF_2XHE08 = 3, 2018 RTW89_GILTF_1XHE16 = 4, 2019 RTW89_GILTF_1XHE08 = 5, 2020 RTW89_GILTF_MAX 2021 }; 2022 2023 enum rtw89_rx_frame_type { 2024 RTW89_RX_TYPE_MGNT = 0, 2025 RTW89_RX_TYPE_CTRL = 1, 2026 RTW89_RX_TYPE_DATA = 2, 2027 RTW89_RX_TYPE_RSVD = 3, 2028 }; 2029 2030 struct rtw89_ra_info { 2031 u8 is_dis_ra:1; 2032 /* Bit0 : CCK 2033 * Bit1 : OFDM 2034 * Bit2 : HT 2035 * Bit3 : VHT 2036 * Bit4 : HE 2037 */ 2038 u8 mode_ctrl:5; 2039 u8 bw_cap:2; 2040 u8 macid; 2041 u8 dcm_cap:1; 2042 u8 er_cap:1; 2043 u8 init_rate_lv:2; 2044 u8 upd_all:1; 2045 u8 en_sgi:1; 2046 u8 ldpc_cap:1; 2047 u8 stbc_cap:1; 2048 u8 ss_num:3; 2049 u8 giltf:3; 2050 u8 upd_bw_nss_mask:1; 2051 u8 upd_mask:1; 2052 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2053 /* BFee CSI */ 2054 u8 band_num; 2055 u8 ra_csi_rate_en:1; 2056 u8 fixed_csi_rate_en:1; 2057 u8 cr_tbl_sel:1; 2058 u8 rsvd2:5; 2059 u8 csi_mcs_ss_idx; 2060 u8 csi_mode:2; 2061 u8 csi_gi_ltf:3; 2062 u8 csi_bw:3; 2063 }; 2064 2065 #define RTW89_PPDU_MAX_USR 4 2066 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2067 #define RTW89_PPDU_MAC_INFO_SIZE 8 2068 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2069 2070 #define RTW89_MAX_RX_AGG_NUM 64 2071 #define RTW89_MAX_TX_AGG_NUM 128 2072 2073 struct rtw89_ampdu_params { 2074 u16 agg_num; 2075 bool amsdu; 2076 }; 2077 2078 struct rtw89_ra_report { 2079 struct rate_info txrate; 2080 u32 bit_rate; 2081 u16 hw_rate; 2082 bool might_fallback_legacy; 2083 }; 2084 2085 DECLARE_EWMA(rssi, 10, 16); 2086 2087 struct rtw89_ba_cam_entry { 2088 struct list_head list; 2089 u8 tid; 2090 }; 2091 2092 #define RTW89_MAX_ADDR_CAM_NUM 128 2093 #define RTW89_MAX_BSSID_CAM_NUM 20 2094 #define RTW89_MAX_SEC_CAM_NUM 128 2095 #define RTW89_MAX_BA_CAM_NUM 8 2096 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2097 2098 struct rtw89_addr_cam_entry { 2099 u8 addr_cam_idx; 2100 u8 offset; 2101 u8 len; 2102 u8 valid : 1; 2103 u8 addr_mask : 6; 2104 u8 wapi : 1; 2105 u8 mask_sel : 2; 2106 u8 bssid_cam_idx: 6; 2107 2108 u8 sec_ent_mode; 2109 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2110 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2111 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2112 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2113 }; 2114 2115 struct rtw89_bssid_cam_entry { 2116 u8 bssid[ETH_ALEN]; 2117 u8 phy_idx; 2118 u8 bssid_cam_idx; 2119 u8 offset; 2120 u8 len; 2121 u8 valid : 1; 2122 u8 num; 2123 }; 2124 2125 struct rtw89_sec_cam_entry { 2126 u8 sec_cam_idx; 2127 u8 offset; 2128 u8 len; 2129 u8 type : 4; 2130 u8 ext_key : 1; 2131 u8 spp_mode : 1; 2132 /* 256 bits */ 2133 u8 key[32]; 2134 }; 2135 2136 struct rtw89_sta { 2137 u8 mac_id; 2138 bool disassoc; 2139 struct rtw89_vif *rtwvif; 2140 struct rtw89_ra_info ra; 2141 struct rtw89_ra_report ra_report; 2142 int max_agg_wait; 2143 u8 prev_rssi; 2144 struct ewma_rssi avg_rssi; 2145 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2146 struct ieee80211_rx_status rx_status; 2147 u16 rx_hw_rate; 2148 __le32 htc_template; 2149 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2150 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2151 struct list_head ba_cam_list; 2152 2153 bool use_cfg_mask; 2154 struct cfg80211_bitrate_mask mask; 2155 2156 bool cctl_tx_time; 2157 u32 ampdu_max_time:4; 2158 bool cctl_tx_retry_limit; 2159 u32 data_tx_cnt_lmt:6; 2160 }; 2161 2162 struct rtw89_efuse { 2163 bool valid; 2164 u8 xtal_cap; 2165 u8 addr[ETH_ALEN]; 2166 u8 rfe_type; 2167 char country_code[2]; 2168 }; 2169 2170 struct rtw89_phy_rate_pattern { 2171 u64 ra_mask; 2172 u16 rate; 2173 u8 ra_mode; 2174 bool enable; 2175 }; 2176 2177 struct rtw89_vif { 2178 struct list_head list; 2179 struct rtw89_dev *rtwdev; 2180 u8 mac_id; 2181 u8 port; 2182 u8 mac_addr[ETH_ALEN]; 2183 u8 bssid[ETH_ALEN]; 2184 u8 phy_idx; 2185 u8 mac_idx; 2186 u8 net_type; 2187 u8 wifi_role; 2188 u8 self_role; 2189 u8 wmm; 2190 u8 bcn_hit_cond; 2191 u8 hit_rule; 2192 bool trigger; 2193 bool lsig_txop; 2194 u8 tgt_ind; 2195 u8 frm_tgt_ind; 2196 bool wowlan_pattern; 2197 bool wowlan_uc; 2198 bool wowlan_magic; 2199 bool is_hesta; 2200 bool last_a_ctrl; 2201 struct work_struct update_beacon_work; 2202 struct rtw89_addr_cam_entry addr_cam; 2203 struct rtw89_bssid_cam_entry bssid_cam; 2204 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2205 struct rtw89_traffic_stats stats; 2206 struct rtw89_phy_rate_pattern rate_pattern; 2207 struct cfg80211_scan_request *scan_req; 2208 struct ieee80211_scan_ies *scan_ies; 2209 }; 2210 2211 enum rtw89_lv1_rcvy_step { 2212 RTW89_LV1_RCVY_STEP_1, 2213 RTW89_LV1_RCVY_STEP_2, 2214 }; 2215 2216 struct rtw89_hci_ops { 2217 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2218 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2219 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2220 void (*reset)(struct rtw89_dev *rtwdev); 2221 int (*start)(struct rtw89_dev *rtwdev); 2222 void (*stop)(struct rtw89_dev *rtwdev); 2223 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2224 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2225 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2226 2227 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2228 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2229 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2230 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2231 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2232 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2233 2234 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2235 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2236 int (*deinit)(struct rtw89_dev *rtwdev); 2237 2238 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2239 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2240 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2241 int (*napi_poll)(struct napi_struct *napi, int budget); 2242 2243 /* Deal with locks inside recovery_start and recovery_complete callbacks 2244 * by hci instance, and handle things which need to consider under SER. 2245 * e.g. turn on/off interrupts except for the one for halt notification. 2246 */ 2247 void (*recovery_start)(struct rtw89_dev *rtwdev); 2248 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2249 }; 2250 2251 struct rtw89_hci_info { 2252 const struct rtw89_hci_ops *ops; 2253 enum rtw89_hci_type type; 2254 u32 rpwm_addr; 2255 u32 cpwm_addr; 2256 bool paused; 2257 }; 2258 2259 struct rtw89_chip_ops { 2260 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2261 void (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2262 void (*bb_reset)(struct rtw89_dev *rtwdev, 2263 enum rtw89_phy_idx phy_idx); 2264 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2265 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2266 u32 addr, u32 mask); 2267 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2268 u32 addr, u32 mask, u32 data); 2269 void (*set_channel)(struct rtw89_dev *rtwdev, 2270 const struct rtw89_chan *chan, 2271 enum rtw89_mac_idx mac_idx, 2272 enum rtw89_phy_idx phy_idx); 2273 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2274 struct rtw89_channel_help_params *p, 2275 const struct rtw89_chan *chan, 2276 enum rtw89_mac_idx mac_idx, 2277 enum rtw89_phy_idx phy_idx); 2278 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2279 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2280 void (*fem_setup)(struct rtw89_dev *rtwdev); 2281 void (*rfk_init)(struct rtw89_dev *rtwdev); 2282 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2283 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2284 enum rtw89_phy_idx phy_idx); 2285 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2286 void (*rfk_track)(struct rtw89_dev *rtwdev); 2287 void (*power_trim)(struct rtw89_dev *rtwdev); 2288 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2289 const struct rtw89_chan *chan, 2290 enum rtw89_phy_idx phy_idx); 2291 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2292 enum rtw89_phy_idx phy_idx); 2293 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2294 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2295 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2296 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2297 struct rtw89_rx_phy_ppdu *phy_ppdu, 2298 struct ieee80211_rx_status *status); 2299 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2300 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2301 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2302 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2303 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2304 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2305 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2306 struct rtw89_tx_desc_info *desc_info, 2307 void *txdesc); 2308 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2309 struct rtw89_tx_desc_info *desc_info, 2310 void *txdesc); 2311 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2312 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2313 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2314 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2315 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2316 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2317 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2318 struct rtw89_vif *rtwvif, 2319 struct rtw89_sta *rtwsta); 2320 2321 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2322 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2323 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2324 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2325 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2326 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2327 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2328 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2329 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2330 }; 2331 2332 enum rtw89_dma_ch { 2333 RTW89_DMA_ACH0 = 0, 2334 RTW89_DMA_ACH1 = 1, 2335 RTW89_DMA_ACH2 = 2, 2336 RTW89_DMA_ACH3 = 3, 2337 RTW89_DMA_ACH4 = 4, 2338 RTW89_DMA_ACH5 = 5, 2339 RTW89_DMA_ACH6 = 6, 2340 RTW89_DMA_ACH7 = 7, 2341 RTW89_DMA_B0MG = 8, 2342 RTW89_DMA_B0HI = 9, 2343 RTW89_DMA_B1MG = 10, 2344 RTW89_DMA_B1HI = 11, 2345 RTW89_DMA_H2C = 12, 2346 RTW89_DMA_CH_NUM = 13 2347 }; 2348 2349 enum rtw89_qta_mode { 2350 RTW89_QTA_SCC, 2351 RTW89_QTA_DLFW, 2352 2353 /* keep last */ 2354 RTW89_QTA_INVALID, 2355 }; 2356 2357 struct rtw89_hfc_ch_cfg { 2358 u16 min; 2359 u16 max; 2360 #define grp_0 0 2361 #define grp_1 1 2362 #define grp_num 2 2363 u8 grp; 2364 }; 2365 2366 struct rtw89_hfc_ch_info { 2367 u16 aval; 2368 u16 used; 2369 }; 2370 2371 struct rtw89_hfc_pub_cfg { 2372 u16 grp0; 2373 u16 grp1; 2374 u16 pub_max; 2375 u16 wp_thrd; 2376 }; 2377 2378 struct rtw89_hfc_pub_info { 2379 u16 g0_used; 2380 u16 g1_used; 2381 u16 g0_aval; 2382 u16 g1_aval; 2383 u16 pub_aval; 2384 u16 wp_aval; 2385 }; 2386 2387 struct rtw89_hfc_prec_cfg { 2388 u16 ch011_prec; 2389 u16 h2c_prec; 2390 u16 wp_ch07_prec; 2391 u16 wp_ch811_prec; 2392 u8 ch011_full_cond; 2393 u8 h2c_full_cond; 2394 u8 wp_ch07_full_cond; 2395 u8 wp_ch811_full_cond; 2396 }; 2397 2398 struct rtw89_hfc_param { 2399 bool en; 2400 bool h2c_en; 2401 u8 mode; 2402 const struct rtw89_hfc_ch_cfg *ch_cfg; 2403 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2404 struct rtw89_hfc_pub_cfg pub_cfg; 2405 struct rtw89_hfc_pub_info pub_info; 2406 struct rtw89_hfc_prec_cfg prec_cfg; 2407 }; 2408 2409 struct rtw89_hfc_param_ini { 2410 const struct rtw89_hfc_ch_cfg *ch_cfg; 2411 const struct rtw89_hfc_pub_cfg *pub_cfg; 2412 const struct rtw89_hfc_prec_cfg *prec_cfg; 2413 u8 mode; 2414 }; 2415 2416 struct rtw89_dle_size { 2417 u16 pge_size; 2418 u16 lnk_pge_num; 2419 u16 unlnk_pge_num; 2420 }; 2421 2422 struct rtw89_wde_quota { 2423 u16 hif; 2424 u16 wcpu; 2425 u16 pkt_in; 2426 u16 cpu_io; 2427 }; 2428 2429 struct rtw89_ple_quota { 2430 u16 cma0_tx; 2431 u16 cma1_tx; 2432 u16 c2h; 2433 u16 h2c; 2434 u16 wcpu; 2435 u16 mpdu_proc; 2436 u16 cma0_dma; 2437 u16 cma1_dma; 2438 u16 bb_rpt; 2439 u16 wd_rel; 2440 u16 cpu_io; 2441 u16 tx_rpt; 2442 }; 2443 2444 struct rtw89_dle_mem { 2445 enum rtw89_qta_mode mode; 2446 const struct rtw89_dle_size *wde_size; 2447 const struct rtw89_dle_size *ple_size; 2448 const struct rtw89_wde_quota *wde_min_qt; 2449 const struct rtw89_wde_quota *wde_max_qt; 2450 const struct rtw89_ple_quota *ple_min_qt; 2451 const struct rtw89_ple_quota *ple_max_qt; 2452 }; 2453 2454 struct rtw89_reg_def { 2455 u32 addr; 2456 u32 mask; 2457 }; 2458 2459 struct rtw89_reg2_def { 2460 u32 addr; 2461 u32 data; 2462 }; 2463 2464 struct rtw89_reg3_def { 2465 u32 addr; 2466 u32 mask; 2467 u32 data; 2468 }; 2469 2470 struct rtw89_reg5_def { 2471 u8 flag; /* recognized by parsers */ 2472 u8 path; 2473 u32 addr; 2474 u32 mask; 2475 u32 data; 2476 }; 2477 2478 struct rtw89_phy_table { 2479 const struct rtw89_reg2_def *regs; 2480 u32 n_regs; 2481 enum rtw89_rf_path rf_path; 2482 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2483 enum rtw89_rf_path rf_path, void *data); 2484 }; 2485 2486 struct rtw89_txpwr_table { 2487 const void *data; 2488 u32 size; 2489 void (*load)(struct rtw89_dev *rtwdev, 2490 const struct rtw89_txpwr_table *tbl); 2491 }; 2492 2493 struct rtw89_page_regs { 2494 u32 hci_fc_ctrl; 2495 u32 ch_page_ctrl; 2496 u32 ach_page_ctrl; 2497 u32 ach_page_info; 2498 u32 pub_page_info3; 2499 u32 pub_page_ctrl1; 2500 u32 pub_page_ctrl2; 2501 u32 pub_page_info1; 2502 u32 pub_page_info2; 2503 u32 wp_page_ctrl1; 2504 u32 wp_page_ctrl2; 2505 u32 wp_page_info1; 2506 }; 2507 2508 struct rtw89_imr_info { 2509 u32 wdrls_imr_set; 2510 u32 wsec_imr_reg; 2511 u32 wsec_imr_set; 2512 u32 mpdu_tx_imr_set; 2513 u32 mpdu_rx_imr_set; 2514 u32 sta_sch_imr_set; 2515 u32 txpktctl_imr_b0_reg; 2516 u32 txpktctl_imr_b0_clr; 2517 u32 txpktctl_imr_b0_set; 2518 u32 txpktctl_imr_b1_reg; 2519 u32 txpktctl_imr_b1_clr; 2520 u32 txpktctl_imr_b1_set; 2521 u32 wde_imr_clr; 2522 u32 wde_imr_set; 2523 u32 ple_imr_clr; 2524 u32 ple_imr_set; 2525 u32 host_disp_imr_clr; 2526 u32 host_disp_imr_set; 2527 u32 cpu_disp_imr_clr; 2528 u32 cpu_disp_imr_set; 2529 u32 other_disp_imr_clr; 2530 u32 other_disp_imr_set; 2531 u32 bbrpt_chinfo_err_imr_reg; 2532 u32 bbrpt_err_imr_set; 2533 u32 bbrpt_dfs_err_imr_reg; 2534 u32 ptcl_imr_clr; 2535 u32 ptcl_imr_set; 2536 u32 cdma_imr_0_reg; 2537 u32 cdma_imr_0_clr; 2538 u32 cdma_imr_0_set; 2539 u32 cdma_imr_1_reg; 2540 u32 cdma_imr_1_clr; 2541 u32 cdma_imr_1_set; 2542 u32 phy_intf_imr_reg; 2543 u32 phy_intf_imr_clr; 2544 u32 phy_intf_imr_set; 2545 u32 rmac_imr_reg; 2546 u32 rmac_imr_clr; 2547 u32 rmac_imr_set; 2548 u32 tmac_imr_reg; 2549 u32 tmac_imr_clr; 2550 u32 tmac_imr_set; 2551 }; 2552 2553 struct rtw89_chip_info { 2554 enum rtw89_core_chip_id chip_id; 2555 const struct rtw89_chip_ops *ops; 2556 const char *fw_name; 2557 u32 fifo_size; 2558 u16 max_amsdu_limit; 2559 bool dis_2g_40m_ul_ofdma; 2560 u32 rsvd_ple_ofst; 2561 const struct rtw89_hfc_param_ini *hfc_param_ini; 2562 const struct rtw89_dle_mem *dle_mem; 2563 u32 rf_base_addr[2]; 2564 u8 support_chanctx_num; 2565 u8 support_bands; 2566 bool support_bw160; 2567 bool hw_sec_hdr; 2568 u8 rf_path_num; 2569 u8 tx_nss; 2570 u8 rx_nss; 2571 u8 acam_num; 2572 u8 bcam_num; 2573 u8 scam_num; 2574 u8 bacam_num; 2575 u8 bacam_dynamic_num; 2576 bool bacam_v1; 2577 2578 u8 sec_ctrl_efuse_size; 2579 u32 physical_efuse_size; 2580 u32 logical_efuse_size; 2581 u32 limit_efuse_size; 2582 u32 dav_phy_efuse_size; 2583 u32 dav_log_efuse_size; 2584 u32 phycap_addr; 2585 u32 phycap_size; 2586 2587 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2588 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2589 const struct rtw89_phy_table *bb_table; 2590 const struct rtw89_phy_table *bb_gain_table; 2591 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2592 const struct rtw89_phy_table *nctl_table; 2593 const struct rtw89_txpwr_table *byr_table; 2594 const struct rtw89_phy_dig_gain_table *dig_table; 2595 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2596 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2597 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2598 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2599 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2600 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2601 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2602 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2603 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2604 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2605 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2606 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2607 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2608 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2609 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2610 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2611 2612 u8 txpwr_factor_rf; 2613 u8 txpwr_factor_mac; 2614 2615 u32 para_ver; 2616 u32 wlcx_desired; 2617 u8 btcx_desired; 2618 u8 scbd; 2619 u8 mailbox; 2620 2621 u8 fcxbtcrpt_ver; 2622 u8 fcxtdma_ver; 2623 u8 fcxslots_ver; 2624 u8 fcxcysta_ver; 2625 u8 fcxstep_ver; 2626 u8 fcxnullsta_ver; 2627 u8 fcxmreg_ver; 2628 u8 fcxgpiodbg_ver; 2629 u8 fcxbtver_ver; 2630 u8 fcxbtscan_ver; 2631 u8 fcxbtafh_ver; 2632 u8 fcxbtdevinfo_ver; 2633 2634 u8 afh_guard_ch; 2635 const u8 *wl_rssi_thres; 2636 const u8 *bt_rssi_thres; 2637 u8 rssi_tol; 2638 2639 u8 mon_reg_num; 2640 const struct rtw89_btc_fbtc_mreg *mon_reg; 2641 u8 rf_para_ulink_num; 2642 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2643 u8 rf_para_dlink_num; 2644 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2645 u8 ps_mode_supported; 2646 u8 low_power_hci_modes; 2647 2648 u32 h2c_cctl_func_id; 2649 u32 hci_func_en_addr; 2650 u32 h2c_desc_size; 2651 u32 txwd_body_size; 2652 u32 h2c_ctrl_reg; 2653 const u32 *h2c_regs; 2654 u32 c2h_ctrl_reg; 2655 const u32 *c2h_regs; 2656 const struct rtw89_page_regs *page_regs; 2657 const struct rtw89_reg_def *dcfo_comp; 2658 u8 dcfo_comp_sft; 2659 const struct rtw89_imr_info *imr_info; 2660 }; 2661 2662 union rtw89_bus_info { 2663 const struct rtw89_pci_info *pci; 2664 }; 2665 2666 struct rtw89_driver_info { 2667 const struct rtw89_chip_info *chip; 2668 union rtw89_bus_info bus; 2669 }; 2670 2671 enum rtw89_hcifc_mode { 2672 RTW89_HCIFC_POH = 0, 2673 RTW89_HCIFC_STF = 1, 2674 RTW89_HCIFC_SDIO = 2, 2675 2676 /* keep last */ 2677 RTW89_HCIFC_MODE_INVALID, 2678 }; 2679 2680 struct rtw89_dle_info { 2681 enum rtw89_qta_mode qta_mode; 2682 u16 wde_pg_size; 2683 u16 ple_pg_size; 2684 u16 c0_rx_qta; 2685 u16 c1_rx_qta; 2686 }; 2687 2688 enum rtw89_host_rpr_mode { 2689 RTW89_RPR_MODE_POH = 0, 2690 RTW89_RPR_MODE_STF 2691 }; 2692 2693 struct rtw89_mac_info { 2694 struct rtw89_dle_info dle_info; 2695 struct rtw89_hfc_param hfc_param; 2696 enum rtw89_qta_mode qta_mode; 2697 u8 rpwm_seq_num; 2698 u8 cpwm_seq_num; 2699 }; 2700 2701 enum rtw89_fw_type { 2702 RTW89_FW_NORMAL = 1, 2703 RTW89_FW_WOWLAN = 3, 2704 }; 2705 2706 enum rtw89_fw_feature { 2707 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 2708 RTW89_FW_FEATURE_SCAN_OFFLOAD, 2709 RTW89_FW_FEATURE_TX_WAKE, 2710 RTW89_FW_FEATURE_CRASH_TRIGGER, 2711 }; 2712 2713 struct rtw89_fw_suit { 2714 const u8 *data; 2715 u32 size; 2716 u8 major_ver; 2717 u8 minor_ver; 2718 u8 sub_ver; 2719 u8 sub_idex; 2720 u16 build_year; 2721 u16 build_mon; 2722 u16 build_date; 2723 u16 build_hour; 2724 u16 build_min; 2725 u8 cmd_ver; 2726 }; 2727 2728 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2729 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2730 #define RTW89_FW_SUIT_VER_CODE(s) \ 2731 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2732 2733 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 2734 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 2735 (mfw_hdr)->ver.minor, \ 2736 (mfw_hdr)->ver.sub, \ 2737 (mfw_hdr)->ver.idx) 2738 2739 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 2740 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 2741 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 2742 GET_FW_HDR_SUBVERSION(fw_hdr), \ 2743 GET_FW_HDR_SUBINDEX(fw_hdr)) 2744 2745 struct rtw89_fw_info { 2746 const struct firmware *firmware; 2747 struct rtw89_dev *rtwdev; 2748 struct completion completion; 2749 u8 h2c_seq; 2750 u8 rec_seq; 2751 struct rtw89_fw_suit normal; 2752 struct rtw89_fw_suit wowlan; 2753 bool fw_log_enable; 2754 u32 feature_map; 2755 }; 2756 2757 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 2758 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 2759 2760 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 2761 ((_fw)->feature_map |= BIT(_fw_feature)) 2762 2763 struct rtw89_cam_info { 2764 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2765 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2766 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2767 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 2768 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 2769 }; 2770 2771 enum rtw89_sar_sources { 2772 RTW89_SAR_SOURCE_NONE, 2773 RTW89_SAR_SOURCE_COMMON, 2774 2775 RTW89_SAR_SOURCE_NR, 2776 }; 2777 2778 enum rtw89_sar_subband { 2779 RTW89_SAR_2GHZ_SUBBAND, 2780 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 2781 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 2782 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 2783 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 2784 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 2785 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 2786 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 2787 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 2788 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 2789 2790 RTW89_SAR_SUBBAND_NR, 2791 }; 2792 2793 struct rtw89_sar_cfg_common { 2794 bool set[RTW89_SAR_SUBBAND_NR]; 2795 s32 cfg[RTW89_SAR_SUBBAND_NR]; 2796 }; 2797 2798 struct rtw89_sar_info { 2799 /* used to decide how to acces SAR cfg union */ 2800 enum rtw89_sar_sources src; 2801 2802 /* reserved for different knids of SAR cfg struct. 2803 * supposed that a single cfg struct cannot handle various SAR sources. 2804 */ 2805 union { 2806 struct rtw89_sar_cfg_common cfg_common; 2807 }; 2808 }; 2809 2810 struct rtw89_chanctx_cfg { 2811 enum rtw89_sub_entity_idx idx; 2812 }; 2813 2814 enum rtw89_entity_mode { 2815 RTW89_ENTITY_MODE_SCC, 2816 }; 2817 2818 struct rtw89_hal { 2819 u32 rx_fltr; 2820 u8 cv; 2821 u32 sw_amsdu_max_size; 2822 u32 antenna_tx; 2823 u32 antenna_rx; 2824 u8 tx_nss; 2825 u8 rx_nss; 2826 bool support_cckpd; 2827 bool support_igi; 2828 2829 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 2830 struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY]; 2831 2832 bool entity_active; 2833 enum rtw89_entity_mode entity_mode; 2834 2835 struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY]; 2836 struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY]; 2837 }; 2838 2839 #define RTW89_MAX_MAC_ID_NUM 128 2840 #define RTW89_MAX_PKT_OFLD_NUM 255 2841 2842 enum rtw89_flags { 2843 RTW89_FLAG_POWERON, 2844 RTW89_FLAG_FW_RDY, 2845 RTW89_FLAG_RUNNING, 2846 RTW89_FLAG_BFEE_MON, 2847 RTW89_FLAG_BFEE_EN, 2848 RTW89_FLAG_NAPI_RUNNING, 2849 RTW89_FLAG_LEISURE_PS, 2850 RTW89_FLAG_LOW_POWER_MODE, 2851 RTW89_FLAG_INACTIVE_PS, 2852 RTW89_FLAG_RESTART_TRIGGER, 2853 2854 NUM_OF_RTW89_FLAGS, 2855 }; 2856 2857 struct rtw89_pkt_stat { 2858 u16 beacon_nr; 2859 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2860 }; 2861 2862 DECLARE_EWMA(thermal, 4, 4); 2863 2864 struct rtw89_phy_stat { 2865 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2866 struct rtw89_pkt_stat cur_pkt_stat; 2867 struct rtw89_pkt_stat last_pkt_stat; 2868 }; 2869 2870 #define RTW89_DACK_PATH_NR 2 2871 #define RTW89_DACK_IDX_NR 2 2872 #define RTW89_DACK_MSBK_NR 16 2873 struct rtw89_dack_info { 2874 bool dack_done; 2875 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2876 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2877 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2878 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2879 u32 dack_cnt; 2880 bool addck_timeout[RTW89_DACK_PATH_NR]; 2881 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2882 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2883 }; 2884 2885 #define RTW89_IQK_CHS_NR 2 2886 #define RTW89_IQK_PATH_NR 4 2887 2888 struct rtw89_mcc_info { 2889 u8 ch[RTW89_IQK_CHS_NR]; 2890 u8 band[RTW89_IQK_CHS_NR]; 2891 u8 table_idx; 2892 }; 2893 2894 struct rtw89_lck_info { 2895 u8 thermal[RF_PATH_MAX]; 2896 }; 2897 2898 struct rtw89_rx_dck_info { 2899 u8 thermal[RF_PATH_MAX]; 2900 }; 2901 2902 struct rtw89_iqk_info { 2903 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2904 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2905 bool lok_fail[RTW89_IQK_PATH_NR]; 2906 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2907 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2908 u32 iqk_fail_cnt; 2909 bool is_iqk_init; 2910 u32 iqk_channel[RTW89_IQK_CHS_NR]; 2911 u8 iqk_band[RTW89_IQK_PATH_NR]; 2912 u8 iqk_ch[RTW89_IQK_PATH_NR]; 2913 u8 iqk_bw[RTW89_IQK_PATH_NR]; 2914 u8 kcount; 2915 u8 iqk_times; 2916 u8 version; 2917 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 2918 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 2919 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 2920 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 2921 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 2922 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 2923 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 2924 bool is_nbiqk; 2925 bool iqk_fft_en; 2926 bool iqk_xym_en; 2927 bool iqk_sram_en; 2928 bool iqk_cfir_en; 2929 u8 thermal[RTW89_IQK_PATH_NR]; 2930 bool thermal_rek_en; 2931 u32 syn1to2; 2932 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2933 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 2934 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2935 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2936 }; 2937 2938 #define RTW89_DPK_RF_PATH 2 2939 #define RTW89_DPK_AVG_THERMAL_NUM 8 2940 #define RTW89_DPK_BKUP_NUM 2 2941 struct rtw89_dpk_bkup_para { 2942 enum rtw89_band band; 2943 enum rtw89_bandwidth bw; 2944 u8 ch; 2945 bool path_ok; 2946 u8 mdpd_en; 2947 u8 txagc_dpk; 2948 u8 ther_dpk; 2949 u8 gs; 2950 u16 pwsf; 2951 }; 2952 2953 struct rtw89_dpk_info { 2954 bool is_dpk_enable; 2955 bool is_dpk_reload_en; 2956 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2957 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2958 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2959 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2960 u8 cur_idx[RTW89_DPK_RF_PATH]; 2961 u8 cur_k_set; 2962 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2963 }; 2964 2965 struct rtw89_fem_info { 2966 bool elna_2g; 2967 bool elna_5g; 2968 bool epa_2g; 2969 bool epa_5g; 2970 bool epa_6g; 2971 }; 2972 2973 struct rtw89_phy_ch_info { 2974 u8 rssi_min; 2975 u16 rssi_min_macid; 2976 u8 pre_rssi_min; 2977 u8 rssi_max; 2978 u16 rssi_max_macid; 2979 u8 rxsc_160; 2980 u8 rxsc_80; 2981 u8 rxsc_40; 2982 u8 rxsc_20; 2983 u8 rxsc_l; 2984 u8 is_noisy; 2985 }; 2986 2987 struct rtw89_agc_gaincode_set { 2988 u8 lna_idx; 2989 u8 tia_idx; 2990 u8 rxb_idx; 2991 }; 2992 2993 #define IGI_RSSI_TH_NUM 5 2994 #define FA_TH_NUM 4 2995 #define LNA_GAIN_NUM 7 2996 #define TIA_GAIN_NUM 2 2997 struct rtw89_dig_info { 2998 struct rtw89_agc_gaincode_set cur_gaincode; 2999 bool force_gaincode_idx_en; 3000 struct rtw89_agc_gaincode_set force_gaincode; 3001 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3002 u16 fa_th[FA_TH_NUM]; 3003 u8 igi_rssi; 3004 u8 igi_fa_rssi; 3005 u8 fa_rssi_ofst; 3006 u8 dyn_igi_max; 3007 u8 dyn_igi_min; 3008 bool dyn_pd_th_en; 3009 u8 dyn_pd_th_max; 3010 u8 pd_low_th_ofst; 3011 u8 ib_pbk; 3012 s8 ib_pkpwr; 3013 s8 lna_gain_a[LNA_GAIN_NUM]; 3014 s8 lna_gain_g[LNA_GAIN_NUM]; 3015 s8 *lna_gain; 3016 s8 tia_gain_a[TIA_GAIN_NUM]; 3017 s8 tia_gain_g[TIA_GAIN_NUM]; 3018 s8 *tia_gain; 3019 bool is_linked_pre; 3020 bool bypass_dig; 3021 }; 3022 3023 enum rtw89_multi_cfo_mode { 3024 RTW89_PKT_BASED_AVG_MODE = 0, 3025 RTW89_ENTRY_BASED_AVG_MODE = 1, 3026 RTW89_TP_BASED_AVG_MODE = 2, 3027 }; 3028 3029 enum rtw89_phy_cfo_status { 3030 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3031 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3032 RTW89_PHY_DCFO_STATE_HOLD = 2, 3033 RTW89_PHY_DCFO_STATE_MAX 3034 }; 3035 3036 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3037 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3038 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3039 }; 3040 3041 struct rtw89_cfo_tracking_info { 3042 u16 cfo_timer_ms; 3043 bool cfo_trig_by_timer_en; 3044 enum rtw89_phy_cfo_status phy_cfo_status; 3045 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3046 u8 phy_cfo_trk_cnt; 3047 bool is_adjust; 3048 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3049 bool apply_compensation; 3050 u8 crystal_cap; 3051 u8 crystal_cap_default; 3052 u8 def_x_cap; 3053 s8 x_cap_ofst; 3054 u32 sta_cfo_tolerance; 3055 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3056 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3057 s32 cfo_avg_pre; 3058 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3059 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3060 u32 packet_count; 3061 u32 packet_count_pre; 3062 s32 residual_cfo_acc; 3063 u8 phy_cfotrk_state; 3064 u8 phy_cfotrk_cnt; 3065 bool divergence_lock_en; 3066 u8 x_cap_lb; 3067 u8 x_cap_ub; 3068 u8 lock_cnt; 3069 }; 3070 3071 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3072 #define TSSI_TRIM_CH_GROUP_NUM 8 3073 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3074 3075 #define TSSI_CCK_CH_GROUP_NUM 6 3076 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3077 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3078 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3079 #define TSSI_MCS_CH_GROUP_NUM \ 3080 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3081 3082 struct rtw89_tssi_info { 3083 u8 thermal[RF_PATH_MAX]; 3084 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3085 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3086 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3087 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3088 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3089 s8 extra_ofst[RF_PATH_MAX]; 3090 bool tssi_tracking_check[RF_PATH_MAX]; 3091 u8 default_txagc_offset[RF_PATH_MAX]; 3092 u32 base_thermal[RF_PATH_MAX]; 3093 }; 3094 3095 struct rtw89_power_trim_info { 3096 bool pg_thermal_trim; 3097 bool pg_pa_bias_trim; 3098 u8 thermal_trim[RF_PATH_MAX]; 3099 u8 pa_bias_trim[RF_PATH_MAX]; 3100 }; 3101 3102 struct rtw89_regulatory { 3103 char alpha2[3]; 3104 u8 txpwr_regd[RTW89_BAND_MAX]; 3105 }; 3106 3107 enum rtw89_ifs_clm_application { 3108 RTW89_IFS_CLM_INIT = 0, 3109 RTW89_IFS_CLM_BACKGROUND = 1, 3110 RTW89_IFS_CLM_ACS = 2, 3111 RTW89_IFS_CLM_DIG = 3, 3112 RTW89_IFS_CLM_TDMA_DIG = 4, 3113 RTW89_IFS_CLM_DBG = 5, 3114 RTW89_IFS_CLM_DBG_MANUAL = 6 3115 }; 3116 3117 enum rtw89_env_racing_lv { 3118 RTW89_RAC_RELEASE = 0, 3119 RTW89_RAC_LV_1 = 1, 3120 RTW89_RAC_LV_2 = 2, 3121 RTW89_RAC_LV_3 = 3, 3122 RTW89_RAC_LV_4 = 4, 3123 RTW89_RAC_MAX_NUM = 5 3124 }; 3125 3126 struct rtw89_ccx_para_info { 3127 enum rtw89_env_racing_lv rac_lv; 3128 u16 mntr_time; 3129 u8 nhm_manual_th_ofst; 3130 u8 nhm_manual_th0; 3131 enum rtw89_ifs_clm_application ifs_clm_app; 3132 u32 ifs_clm_manual_th_times; 3133 u32 ifs_clm_manual_th0; 3134 u8 fahm_manual_th_ofst; 3135 u8 fahm_manual_th0; 3136 u8 fahm_numer_opt; 3137 u8 fahm_denom_opt; 3138 }; 3139 3140 enum rtw89_ccx_edcca_opt_sc_idx { 3141 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3142 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3143 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3144 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3145 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3146 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3147 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3148 RTW89_CCX_EDCCA_SEG1_S3 = 7 3149 }; 3150 3151 enum rtw89_ccx_edcca_opt_bw_idx { 3152 RTW89_CCX_EDCCA_BW20_0 = 0, 3153 RTW89_CCX_EDCCA_BW20_1 = 1, 3154 RTW89_CCX_EDCCA_BW20_2 = 2, 3155 RTW89_CCX_EDCCA_BW20_3 = 3, 3156 RTW89_CCX_EDCCA_BW20_4 = 4, 3157 RTW89_CCX_EDCCA_BW20_5 = 5, 3158 RTW89_CCX_EDCCA_BW20_6 = 6, 3159 RTW89_CCX_EDCCA_BW20_7 = 7 3160 }; 3161 3162 #define RTW89_NHM_TH_NUM 11 3163 #define RTW89_FAHM_TH_NUM 11 3164 #define RTW89_NHM_RPT_NUM 12 3165 #define RTW89_FAHM_RPT_NUM 12 3166 #define RTW89_IFS_CLM_NUM 4 3167 struct rtw89_env_monitor_info { 3168 u32 ccx_trigger_time; 3169 u64 start_time; 3170 u8 ccx_rpt_stamp; 3171 u8 ccx_watchdog_result; 3172 bool ccx_ongoing; 3173 u8 ccx_rac_lv; 3174 bool ccx_manual_ctrl; 3175 u8 ccx_pre_rssi; 3176 u16 clm_mntr_time; 3177 u16 nhm_mntr_time; 3178 u16 ifs_clm_mntr_time; 3179 enum rtw89_ifs_clm_application ifs_clm_app; 3180 u16 fahm_mntr_time; 3181 u16 edcca_clm_mntr_time; 3182 u16 ccx_period; 3183 u8 ccx_unit_idx; 3184 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3185 u8 nhm_th[RTW89_NHM_TH_NUM]; 3186 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3187 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3188 u8 fahm_numer_opt; 3189 u8 fahm_denom_opt; 3190 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3191 u16 clm_result; 3192 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3193 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3194 u16 nhm_tx_cnt; 3195 u16 nhm_cca_cnt; 3196 u16 nhm_idle_cnt; 3197 u16 ifs_clm_tx; 3198 u16 ifs_clm_edcca_excl_cca; 3199 u16 ifs_clm_ofdmfa; 3200 u16 ifs_clm_ofdmcca_excl_fa; 3201 u16 ifs_clm_cckfa; 3202 u16 ifs_clm_cckcca_excl_fa; 3203 u16 ifs_clm_total_ifs; 3204 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3205 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3206 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3207 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3208 u16 fahm_denom_result; 3209 u16 edcca_clm_result; 3210 u8 clm_ratio; 3211 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3212 u8 nhm_tx_ratio; 3213 u8 nhm_cca_ratio; 3214 u8 nhm_idle_ratio; 3215 u8 nhm_ratio; 3216 u16 nhm_result_sum; 3217 u8 nhm_pwr; 3218 u8 ifs_clm_tx_ratio; 3219 u8 ifs_clm_edcca_excl_cca_ratio; 3220 u8 ifs_clm_cck_fa_ratio; 3221 u8 ifs_clm_ofdm_fa_ratio; 3222 u8 ifs_clm_cck_cca_excl_fa_ratio; 3223 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3224 u16 ifs_clm_cck_fa_permil; 3225 u16 ifs_clm_ofdm_fa_permil; 3226 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3227 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3228 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3229 u16 fahm_result_sum; 3230 u8 fahm_ratio; 3231 u8 fahm_denom_ratio; 3232 u8 fahm_pwr; 3233 u8 edcca_clm_ratio; 3234 }; 3235 3236 enum rtw89_ser_rcvy_step { 3237 RTW89_SER_DRV_STOP_TX, 3238 RTW89_SER_DRV_STOP_RX, 3239 RTW89_SER_DRV_STOP_RUN, 3240 RTW89_SER_HAL_STOP_DMA, 3241 RTW89_NUM_OF_SER_FLAGS 3242 }; 3243 3244 struct rtw89_ser { 3245 u8 state; 3246 u8 alarm_event; 3247 3248 struct work_struct ser_hdl_work; 3249 struct delayed_work ser_alarm_work; 3250 const struct state_ent *st_tbl; 3251 const struct event_ent *ev_tbl; 3252 struct list_head msg_q; 3253 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3254 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3255 }; 3256 3257 enum rtw89_mac_ax_ps_mode { 3258 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3259 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3260 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3261 RTW89_MAC_AX_PS_MODE_MAX = 3, 3262 }; 3263 3264 enum rtw89_last_rpwm_mode { 3265 RTW89_LAST_RPWM_PS = 0x0, 3266 RTW89_LAST_RPWM_ACTIVE = 0x6, 3267 }; 3268 3269 struct rtw89_lps_parm { 3270 u8 macid; 3271 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3272 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3273 }; 3274 3275 struct rtw89_ppdu_sts_info { 3276 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3277 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3278 }; 3279 3280 struct rtw89_early_h2c { 3281 struct list_head list; 3282 u8 *h2c; 3283 u16 h2c_len; 3284 }; 3285 3286 struct rtw89_hw_scan_info { 3287 struct ieee80211_vif *scanning_vif; 3288 struct list_head pkt_list[NUM_NL80211_BANDS]; 3289 u8 op_pri_ch; 3290 u8 op_chan; 3291 u8 op_bw; 3292 u8 op_band; 3293 }; 3294 3295 enum rtw89_phy_bb_gain_band { 3296 RTW89_BB_GAIN_BAND_2G = 0, 3297 RTW89_BB_GAIN_BAND_5G_L = 1, 3298 RTW89_BB_GAIN_BAND_5G_M = 2, 3299 RTW89_BB_GAIN_BAND_5G_H = 3, 3300 RTW89_BB_GAIN_BAND_6G_L = 4, 3301 RTW89_BB_GAIN_BAND_6G_M = 5, 3302 RTW89_BB_GAIN_BAND_6G_H = 6, 3303 RTW89_BB_GAIN_BAND_6G_UH = 7, 3304 3305 RTW89_BB_GAIN_BAND_NR, 3306 }; 3307 3308 enum rtw89_phy_bb_rxsc_num { 3309 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3310 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3311 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3312 }; 3313 3314 struct rtw89_phy_bb_gain_info { 3315 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3316 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3317 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3318 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3319 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3320 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3321 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3322 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3323 [RTW89_BB_RXSC_NUM_40]; 3324 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3325 [RTW89_BB_RXSC_NUM_80]; 3326 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3327 [RTW89_BB_RXSC_NUM_160]; 3328 }; 3329 3330 struct rtw89_phy_efuse_gain { 3331 bool offset_valid; 3332 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3333 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3334 }; 3335 3336 struct rtw89_dev { 3337 struct ieee80211_hw *hw; 3338 struct device *dev; 3339 const struct ieee80211_ops *ops; 3340 3341 bool dbcc_en; 3342 struct rtw89_hw_scan_info scan_info; 3343 const struct rtw89_chip_info *chip; 3344 const struct rtw89_pci_info *pci_info; 3345 struct rtw89_hal hal; 3346 struct rtw89_mac_info mac; 3347 struct rtw89_fw_info fw; 3348 struct rtw89_hci_info hci; 3349 struct rtw89_efuse efuse; 3350 struct rtw89_traffic_stats stats; 3351 3352 /* ensures exclusive access from mac80211 callbacks */ 3353 struct mutex mutex; 3354 struct list_head rtwvifs_list; 3355 /* used to protect rf read write */ 3356 struct mutex rf_mutex; 3357 struct workqueue_struct *txq_wq; 3358 struct work_struct txq_work; 3359 struct delayed_work txq_reinvoke_work; 3360 /* used to protect ba_list and forbid_ba_list */ 3361 spinlock_t ba_lock; 3362 /* txqs to setup ba session */ 3363 struct list_head ba_list; 3364 /* txqs to forbid ba session */ 3365 struct list_head forbid_ba_list; 3366 struct work_struct ba_work; 3367 /* used to protect rpwm */ 3368 spinlock_t rpwm_lock; 3369 3370 struct rtw89_cam_info cam_info; 3371 3372 struct sk_buff_head c2h_queue; 3373 struct work_struct c2h_work; 3374 struct work_struct ips_work; 3375 3376 struct list_head early_h2c_list; 3377 3378 struct rtw89_ser ser; 3379 3380 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3381 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3382 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3383 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3384 3385 struct rtw89_phy_stat phystat; 3386 struct rtw89_dack_info dack; 3387 struct rtw89_iqk_info iqk; 3388 struct rtw89_dpk_info dpk; 3389 struct rtw89_mcc_info mcc; 3390 struct rtw89_lck_info lck; 3391 struct rtw89_rx_dck_info rx_dck; 3392 bool is_tssi_mode[RF_PATH_MAX]; 3393 bool is_bt_iqk_timeout; 3394 3395 struct rtw89_fem_info fem; 3396 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3397 struct rtw89_tssi_info tssi; 3398 struct rtw89_power_trim_info pwr_trim; 3399 3400 struct rtw89_cfo_tracking_info cfo_tracking; 3401 struct rtw89_env_monitor_info env_monitor; 3402 struct rtw89_dig_info dig; 3403 struct rtw89_phy_ch_info ch_info; 3404 struct rtw89_phy_bb_gain_info bb_gain; 3405 struct rtw89_phy_efuse_gain efuse_gain; 3406 3407 struct delayed_work track_work; 3408 struct delayed_work coex_act1_work; 3409 struct delayed_work coex_bt_devinfo_work; 3410 struct delayed_work coex_rfk_chk_work; 3411 struct delayed_work cfo_track_work; 3412 struct delayed_work forbid_ba_work; 3413 struct rtw89_ppdu_sts_info ppdu_sts; 3414 u8 total_sta_assoc; 3415 bool scanning; 3416 3417 const struct rtw89_regulatory *regd; 3418 struct rtw89_sar_info sar; 3419 3420 struct rtw89_btc btc; 3421 enum rtw89_ps_mode ps_mode; 3422 bool lps_enabled; 3423 3424 /* napi structure */ 3425 struct net_device netdev; 3426 struct napi_struct napi; 3427 int napi_budget_countdown; 3428 3429 /* HCI related data, keep last */ 3430 u8 priv[] __aligned(sizeof(void *)); 3431 }; 3432 3433 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3434 struct rtw89_core_tx_request *tx_req) 3435 { 3436 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3437 } 3438 3439 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3440 { 3441 rtwdev->hci.ops->reset(rtwdev); 3442 } 3443 3444 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3445 { 3446 return rtwdev->hci.ops->start(rtwdev); 3447 } 3448 3449 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3450 { 3451 rtwdev->hci.ops->stop(rtwdev); 3452 } 3453 3454 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3455 { 3456 return rtwdev->hci.ops->deinit(rtwdev); 3457 } 3458 3459 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3460 { 3461 rtwdev->hci.ops->pause(rtwdev, pause); 3462 } 3463 3464 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3465 { 3466 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3467 } 3468 3469 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3470 { 3471 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3472 } 3473 3474 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3475 { 3476 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3477 } 3478 3479 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3480 { 3481 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3482 } 3483 3484 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3485 bool drop) 3486 { 3487 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3488 return; 3489 3490 if (rtwdev->hci.ops->flush_queues) 3491 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3492 } 3493 3494 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3495 { 3496 if (rtwdev->hci.ops->recovery_start) 3497 rtwdev->hci.ops->recovery_start(rtwdev); 3498 } 3499 3500 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3501 { 3502 if (rtwdev->hci.ops->recovery_complete) 3503 rtwdev->hci.ops->recovery_complete(rtwdev); 3504 } 3505 3506 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3507 { 3508 return rtwdev->hci.ops->read8(rtwdev, addr); 3509 } 3510 3511 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3512 { 3513 return rtwdev->hci.ops->read16(rtwdev, addr); 3514 } 3515 3516 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3517 { 3518 return rtwdev->hci.ops->read32(rtwdev, addr); 3519 } 3520 3521 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3522 { 3523 rtwdev->hci.ops->write8(rtwdev, addr, data); 3524 } 3525 3526 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3527 { 3528 rtwdev->hci.ops->write16(rtwdev, addr, data); 3529 } 3530 3531 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3532 { 3533 rtwdev->hci.ops->write32(rtwdev, addr, data); 3534 } 3535 3536 static inline void 3537 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3538 { 3539 u8 val; 3540 3541 val = rtw89_read8(rtwdev, addr); 3542 rtw89_write8(rtwdev, addr, val | bit); 3543 } 3544 3545 static inline void 3546 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3547 { 3548 u16 val; 3549 3550 val = rtw89_read16(rtwdev, addr); 3551 rtw89_write16(rtwdev, addr, val | bit); 3552 } 3553 3554 static inline void 3555 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3556 { 3557 u32 val; 3558 3559 val = rtw89_read32(rtwdev, addr); 3560 rtw89_write32(rtwdev, addr, val | bit); 3561 } 3562 3563 static inline void 3564 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3565 { 3566 u8 val; 3567 3568 val = rtw89_read8(rtwdev, addr); 3569 rtw89_write8(rtwdev, addr, val & ~bit); 3570 } 3571 3572 static inline void 3573 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3574 { 3575 u16 val; 3576 3577 val = rtw89_read16(rtwdev, addr); 3578 rtw89_write16(rtwdev, addr, val & ~bit); 3579 } 3580 3581 static inline void 3582 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3583 { 3584 u32 val; 3585 3586 val = rtw89_read32(rtwdev, addr); 3587 rtw89_write32(rtwdev, addr, val & ~bit); 3588 } 3589 3590 static inline u32 3591 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3592 { 3593 u32 shift = __ffs(mask); 3594 u32 orig; 3595 u32 ret; 3596 3597 orig = rtw89_read32(rtwdev, addr); 3598 ret = (orig & mask) >> shift; 3599 3600 return ret; 3601 } 3602 3603 static inline u16 3604 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3605 { 3606 u32 shift = __ffs(mask); 3607 u32 orig; 3608 u32 ret; 3609 3610 orig = rtw89_read16(rtwdev, addr); 3611 ret = (orig & mask) >> shift; 3612 3613 return ret; 3614 } 3615 3616 static inline u8 3617 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3618 { 3619 u32 shift = __ffs(mask); 3620 u32 orig; 3621 u32 ret; 3622 3623 orig = rtw89_read8(rtwdev, addr); 3624 ret = (orig & mask) >> shift; 3625 3626 return ret; 3627 } 3628 3629 static inline void 3630 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3631 { 3632 u32 shift = __ffs(mask); 3633 u32 orig; 3634 u32 set; 3635 3636 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3637 3638 orig = rtw89_read32(rtwdev, addr); 3639 set = (orig & ~mask) | ((data << shift) & mask); 3640 rtw89_write32(rtwdev, addr, set); 3641 } 3642 3643 static inline void 3644 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3645 { 3646 u32 shift; 3647 u16 orig, set; 3648 3649 mask &= 0xffff; 3650 shift = __ffs(mask); 3651 3652 orig = rtw89_read16(rtwdev, addr); 3653 set = (orig & ~mask) | ((data << shift) & mask); 3654 rtw89_write16(rtwdev, addr, set); 3655 } 3656 3657 static inline void 3658 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3659 { 3660 u32 shift; 3661 u8 orig, set; 3662 3663 mask &= 0xff; 3664 shift = __ffs(mask); 3665 3666 orig = rtw89_read8(rtwdev, addr); 3667 set = (orig & ~mask) | ((data << shift) & mask); 3668 rtw89_write8(rtwdev, addr, set); 3669 } 3670 3671 static inline u32 3672 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3673 u32 addr, u32 mask) 3674 { 3675 u32 val; 3676 3677 mutex_lock(&rtwdev->rf_mutex); 3678 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3679 mutex_unlock(&rtwdev->rf_mutex); 3680 3681 return val; 3682 } 3683 3684 static inline void 3685 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3686 u32 addr, u32 mask, u32 data) 3687 { 3688 mutex_lock(&rtwdev->rf_mutex); 3689 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3690 mutex_unlock(&rtwdev->rf_mutex); 3691 } 3692 3693 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3694 { 3695 void *p = rtwtxq; 3696 3697 return container_of(p, struct ieee80211_txq, drv_priv); 3698 } 3699 3700 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3701 struct ieee80211_txq *txq) 3702 { 3703 struct rtw89_txq *rtwtxq; 3704 3705 if (!txq) 3706 return; 3707 3708 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3709 INIT_LIST_HEAD(&rtwtxq->list); 3710 } 3711 3712 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3713 { 3714 void *p = rtwvif; 3715 3716 return container_of(p, struct ieee80211_vif, drv_priv); 3717 } 3718 3719 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3720 { 3721 void *p = rtwsta; 3722 3723 return container_of(p, struct ieee80211_sta, drv_priv); 3724 } 3725 3726 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3727 { 3728 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3729 } 3730 3731 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3732 { 3733 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3734 } 3735 3736 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3737 { 3738 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3739 return RATE_INFO_BW_160; 3740 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3741 return RATE_INFO_BW_80; 3742 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3743 return RATE_INFO_BW_40; 3744 else 3745 return RATE_INFO_BW_20; 3746 } 3747 3748 static inline 3749 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 3750 { 3751 switch (hw_band) { 3752 default: 3753 case RTW89_BAND_2G: 3754 return NL80211_BAND_2GHZ; 3755 case RTW89_BAND_5G: 3756 return NL80211_BAND_5GHZ; 3757 case RTW89_BAND_6G: 3758 return NL80211_BAND_6GHZ; 3759 } 3760 } 3761 3762 static inline 3763 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 3764 { 3765 switch (width) { 3766 default: 3767 WARN(1, "Not support bandwidth %d\n", width); 3768 fallthrough; 3769 case NL80211_CHAN_WIDTH_20_NOHT: 3770 case NL80211_CHAN_WIDTH_20: 3771 return RTW89_CHANNEL_WIDTH_20; 3772 case NL80211_CHAN_WIDTH_40: 3773 return RTW89_CHANNEL_WIDTH_40; 3774 case NL80211_CHAN_WIDTH_80: 3775 return RTW89_CHANNEL_WIDTH_80; 3776 case NL80211_CHAN_WIDTH_160: 3777 return RTW89_CHANNEL_WIDTH_160; 3778 } 3779 } 3780 3781 static inline 3782 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3783 struct rtw89_sta *rtwsta) 3784 { 3785 if (rtwsta) { 3786 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3787 3788 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 3789 return &rtwsta->addr_cam; 3790 } 3791 return &rtwvif->addr_cam; 3792 } 3793 3794 static inline 3795 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 3796 struct rtw89_sta *rtwsta) 3797 { 3798 if (rtwsta) { 3799 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3800 3801 if (sta->tdls) 3802 return &rtwsta->bssid_cam; 3803 } 3804 return &rtwvif->bssid_cam; 3805 } 3806 3807 static inline 3808 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3809 struct rtw89_channel_help_params *p, 3810 const struct rtw89_chan *chan, 3811 enum rtw89_mac_idx mac_idx, 3812 enum rtw89_phy_idx phy_idx) 3813 { 3814 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 3815 mac_idx, phy_idx); 3816 } 3817 3818 static inline 3819 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3820 struct rtw89_channel_help_params *p, 3821 const struct rtw89_chan *chan, 3822 enum rtw89_mac_idx mac_idx, 3823 enum rtw89_phy_idx phy_idx) 3824 { 3825 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 3826 mac_idx, phy_idx); 3827 } 3828 3829 static inline 3830 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 3831 enum rtw89_sub_entity_idx idx) 3832 { 3833 struct rtw89_hal *hal = &rtwdev->hal; 3834 3835 return &hal->chandef[idx]; 3836 } 3837 3838 static inline 3839 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 3840 enum rtw89_sub_entity_idx idx) 3841 { 3842 struct rtw89_hal *hal = &rtwdev->hal; 3843 3844 return &hal->chan[idx]; 3845 } 3846 3847 static inline 3848 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 3849 enum rtw89_sub_entity_idx idx) 3850 { 3851 struct rtw89_hal *hal = &rtwdev->hal; 3852 3853 return &hal->chan_rcd[idx]; 3854 } 3855 3856 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3857 { 3858 const struct rtw89_chip_info *chip = rtwdev->chip; 3859 3860 if (chip->ops->fem_setup) 3861 chip->ops->fem_setup(rtwdev); 3862 } 3863 3864 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3865 { 3866 const struct rtw89_chip_info *chip = rtwdev->chip; 3867 3868 if (chip->ops->bb_sethw) 3869 chip->ops->bb_sethw(rtwdev); 3870 } 3871 3872 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3873 { 3874 const struct rtw89_chip_info *chip = rtwdev->chip; 3875 3876 if (chip->ops->rfk_init) 3877 chip->ops->rfk_init(rtwdev); 3878 } 3879 3880 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 3881 { 3882 const struct rtw89_chip_info *chip = rtwdev->chip; 3883 3884 if (chip->ops->rfk_channel) 3885 chip->ops->rfk_channel(rtwdev); 3886 } 3887 3888 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 3889 enum rtw89_phy_idx phy_idx) 3890 { 3891 const struct rtw89_chip_info *chip = rtwdev->chip; 3892 3893 if (chip->ops->rfk_band_changed) 3894 chip->ops->rfk_band_changed(rtwdev, phy_idx); 3895 } 3896 3897 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 3898 { 3899 const struct rtw89_chip_info *chip = rtwdev->chip; 3900 3901 if (chip->ops->rfk_scan) 3902 chip->ops->rfk_scan(rtwdev, start); 3903 } 3904 3905 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 3906 { 3907 const struct rtw89_chip_info *chip = rtwdev->chip; 3908 3909 if (chip->ops->rfk_track) 3910 chip->ops->rfk_track(rtwdev); 3911 } 3912 3913 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 3914 { 3915 const struct rtw89_chip_info *chip = rtwdev->chip; 3916 3917 if (chip->ops->set_txpwr_ctrl) 3918 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 3919 } 3920 3921 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 3922 { 3923 const struct rtw89_chip_info *chip = rtwdev->chip; 3924 3925 if (chip->ops->power_trim) 3926 chip->ops->power_trim(rtwdev); 3927 } 3928 3929 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 3930 enum rtw89_phy_idx phy_idx) 3931 { 3932 const struct rtw89_chip_info *chip = rtwdev->chip; 3933 3934 if (chip->ops->init_txpwr_unit) 3935 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 3936 } 3937 3938 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 3939 enum rtw89_rf_path rf_path) 3940 { 3941 const struct rtw89_chip_info *chip = rtwdev->chip; 3942 3943 if (!chip->ops->get_thermal) 3944 return 0x10; 3945 3946 return chip->ops->get_thermal(rtwdev, rf_path); 3947 } 3948 3949 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 3950 struct rtw89_rx_phy_ppdu *phy_ppdu, 3951 struct ieee80211_rx_status *status) 3952 { 3953 const struct rtw89_chip_info *chip = rtwdev->chip; 3954 3955 if (chip->ops->query_ppdu) 3956 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 3957 } 3958 3959 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 3960 bool bt_en) 3961 { 3962 const struct rtw89_chip_info *chip = rtwdev->chip; 3963 3964 if (chip->ops->bb_ctrl_btc_preagc) 3965 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 3966 } 3967 3968 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 3969 { 3970 const struct rtw89_chip_info *chip = rtwdev->chip; 3971 3972 if (chip->ops->cfg_txrx_path) 3973 chip->ops->cfg_txrx_path(rtwdev); 3974 } 3975 3976 static inline 3977 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 3978 struct ieee80211_vif *vif) 3979 { 3980 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3981 const struct rtw89_chip_info *chip = rtwdev->chip; 3982 3983 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3984 return; 3985 3986 if (chip->ops->set_txpwr_ul_tb_offset) 3987 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 3988 } 3989 3990 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 3991 const struct rtw89_txpwr_table *tbl) 3992 { 3993 tbl->load(rtwdev, tbl); 3994 } 3995 3996 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 3997 { 3998 return rtwdev->regd->txpwr_regd[band]; 3999 } 4000 4001 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4002 { 4003 const struct rtw89_chip_info *chip = rtwdev->chip; 4004 4005 if (chip->ops->ctrl_btg) 4006 chip->ops->ctrl_btg(rtwdev, btg); 4007 } 4008 4009 static inline 4010 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4011 struct rtw89_tx_desc_info *desc_info, 4012 void *txdesc) 4013 { 4014 const struct rtw89_chip_info *chip = rtwdev->chip; 4015 4016 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4017 } 4018 4019 static inline 4020 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4021 struct rtw89_tx_desc_info *desc_info, 4022 void *txdesc) 4023 { 4024 const struct rtw89_chip_info *chip = rtwdev->chip; 4025 4026 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4027 } 4028 4029 static inline 4030 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4031 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4032 { 4033 const struct rtw89_chip_info *chip = rtwdev->chip; 4034 4035 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4036 } 4037 4038 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4039 { 4040 const struct rtw89_chip_info *chip = rtwdev->chip; 4041 4042 chip->ops->cfg_ctrl_path(rtwdev, wl); 4043 } 4044 4045 static inline 4046 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4047 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4048 { 4049 const struct rtw89_chip_info *chip = rtwdev->chip; 4050 4051 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4052 } 4053 4054 static inline 4055 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4056 { 4057 const struct rtw89_chip_info *chip = rtwdev->chip; 4058 4059 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4060 } 4061 4062 static inline 4063 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4064 struct rtw89_vif *rtwvif, 4065 struct rtw89_sta *rtwsta) 4066 { 4067 const struct rtw89_chip_info *chip = rtwdev->chip; 4068 4069 if (!chip->ops->h2c_dctl_sec_cam) 4070 return 0; 4071 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4072 } 4073 4074 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4075 { 4076 __le16 fc = hdr->frame_control; 4077 4078 if (ieee80211_has_tods(fc)) 4079 return hdr->addr1; 4080 else if (ieee80211_has_fromds(fc)) 4081 return hdr->addr2; 4082 else 4083 return hdr->addr3; 4084 } 4085 4086 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4087 { 4088 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4089 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4090 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4091 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4092 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4093 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4094 return true; 4095 return false; 4096 } 4097 4098 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4099 enum rtw89_fw_type type) 4100 { 4101 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4102 4103 if (type == RTW89_FW_WOWLAN) 4104 return &fw_info->wowlan; 4105 return &fw_info->normal; 4106 } 4107 4108 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4109 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4110 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4111 struct sk_buff *skb, bool fwdl); 4112 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4113 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4114 struct rtw89_tx_desc_info *desc_info, 4115 void *txdesc); 4116 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4117 struct rtw89_tx_desc_info *desc_info, 4118 void *txdesc); 4119 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4120 struct rtw89_tx_desc_info *desc_info, 4121 void *txdesc); 4122 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4123 struct rtw89_rx_desc_info *desc_info, 4124 struct sk_buff *skb); 4125 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4126 struct rtw89_rx_desc_info *desc_info, 4127 u8 *data, u32 data_offset); 4128 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4129 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4130 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4131 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4132 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4133 struct ieee80211_vif *vif, 4134 struct ieee80211_sta *sta); 4135 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4136 struct ieee80211_vif *vif, 4137 struct ieee80211_sta *sta); 4138 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4139 struct ieee80211_vif *vif, 4140 struct ieee80211_sta *sta); 4141 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4142 struct ieee80211_vif *vif, 4143 struct ieee80211_sta *sta); 4144 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4145 struct ieee80211_vif *vif, 4146 struct ieee80211_sta *sta); 4147 int rtw89_core_init(struct rtw89_dev *rtwdev); 4148 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4149 int rtw89_core_register(struct rtw89_dev *rtwdev); 4150 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4151 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4152 u32 bus_data_size, 4153 const struct rtw89_chip_info *chip); 4154 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4155 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4156 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4157 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4158 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4159 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4160 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4161 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4162 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4163 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4164 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4165 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4166 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4167 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4168 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4169 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4170 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4171 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4172 struct rtw89_traffic_stats *stats); 4173 int rtw89_core_start(struct rtw89_dev *rtwdev); 4174 void rtw89_core_stop(struct rtw89_dev *rtwdev); 4175 void rtw89_core_update_beacon_work(struct work_struct *work); 4176 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4177 const u8 *mac_addr, bool hw_scan); 4178 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4179 struct ieee80211_vif *vif, bool hw_scan); 4180 4181 #endif 4182