1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "coex.h" 9 #include "core.h" 10 #include "efuse.h" 11 #include "fw.h" 12 #include "mac.h" 13 #include "phy.h" 14 #include "ps.h" 15 #include "reg.h" 16 #include "sar.h" 17 #include "ser.h" 18 #include "txrx.h" 19 #include "util.h" 20 21 static bool rtw89_disable_ps_mode; 22 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 23 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 24 25 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 26 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 27 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 28 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 29 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 31 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 35 36 static struct ieee80211_channel rtw89_channels_2ghz[] = { 37 RTW89_DEF_CHAN_2G(2412, 1), 38 RTW89_DEF_CHAN_2G(2417, 2), 39 RTW89_DEF_CHAN_2G(2422, 3), 40 RTW89_DEF_CHAN_2G(2427, 4), 41 RTW89_DEF_CHAN_2G(2432, 5), 42 RTW89_DEF_CHAN_2G(2437, 6), 43 RTW89_DEF_CHAN_2G(2442, 7), 44 RTW89_DEF_CHAN_2G(2447, 8), 45 RTW89_DEF_CHAN_2G(2452, 9), 46 RTW89_DEF_CHAN_2G(2457, 10), 47 RTW89_DEF_CHAN_2G(2462, 11), 48 RTW89_DEF_CHAN_2G(2467, 12), 49 RTW89_DEF_CHAN_2G(2472, 13), 50 RTW89_DEF_CHAN_2G(2484, 14), 51 }; 52 53 static struct ieee80211_channel rtw89_channels_5ghz[] = { 54 RTW89_DEF_CHAN_5G(5180, 36), 55 RTW89_DEF_CHAN_5G(5200, 40), 56 RTW89_DEF_CHAN_5G(5220, 44), 57 RTW89_DEF_CHAN_5G(5240, 48), 58 RTW89_DEF_CHAN_5G(5260, 52), 59 RTW89_DEF_CHAN_5G(5280, 56), 60 RTW89_DEF_CHAN_5G(5300, 60), 61 RTW89_DEF_CHAN_5G(5320, 64), 62 RTW89_DEF_CHAN_5G(5500, 100), 63 RTW89_DEF_CHAN_5G(5520, 104), 64 RTW89_DEF_CHAN_5G(5540, 108), 65 RTW89_DEF_CHAN_5G(5560, 112), 66 RTW89_DEF_CHAN_5G(5580, 116), 67 RTW89_DEF_CHAN_5G(5600, 120), 68 RTW89_DEF_CHAN_5G(5620, 124), 69 RTW89_DEF_CHAN_5G(5640, 128), 70 RTW89_DEF_CHAN_5G(5660, 132), 71 RTW89_DEF_CHAN_5G(5680, 136), 72 RTW89_DEF_CHAN_5G(5700, 140), 73 RTW89_DEF_CHAN_5G(5720, 144), 74 RTW89_DEF_CHAN_5G(5745, 149), 75 RTW89_DEF_CHAN_5G(5765, 153), 76 RTW89_DEF_CHAN_5G(5785, 157), 77 RTW89_DEF_CHAN_5G(5805, 161), 78 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 79 }; 80 81 static struct ieee80211_channel rtw89_channels_6ghz[] = { 82 RTW89_DEF_CHAN_6G(5955, 1), 83 RTW89_DEF_CHAN_6G(5975, 5), 84 RTW89_DEF_CHAN_6G(5995, 9), 85 RTW89_DEF_CHAN_6G(6015, 13), 86 RTW89_DEF_CHAN_6G(6035, 17), 87 RTW89_DEF_CHAN_6G(6055, 21), 88 RTW89_DEF_CHAN_6G(6075, 25), 89 RTW89_DEF_CHAN_6G(6095, 29), 90 RTW89_DEF_CHAN_6G(6115, 33), 91 RTW89_DEF_CHAN_6G(6135, 37), 92 RTW89_DEF_CHAN_6G(6155, 41), 93 RTW89_DEF_CHAN_6G(6175, 45), 94 RTW89_DEF_CHAN_6G(6195, 49), 95 RTW89_DEF_CHAN_6G(6215, 53), 96 RTW89_DEF_CHAN_6G(6235, 57), 97 RTW89_DEF_CHAN_6G(6255, 61), 98 RTW89_DEF_CHAN_6G(6275, 65), 99 RTW89_DEF_CHAN_6G(6295, 69), 100 RTW89_DEF_CHAN_6G(6315, 73), 101 RTW89_DEF_CHAN_6G(6335, 77), 102 RTW89_DEF_CHAN_6G(6355, 81), 103 RTW89_DEF_CHAN_6G(6375, 85), 104 RTW89_DEF_CHAN_6G(6395, 89), 105 RTW89_DEF_CHAN_6G(6415, 93), 106 RTW89_DEF_CHAN_6G(6435, 97), 107 RTW89_DEF_CHAN_6G(6455, 101), 108 RTW89_DEF_CHAN_6G(6475, 105), 109 RTW89_DEF_CHAN_6G(6495, 109), 110 RTW89_DEF_CHAN_6G(6515, 113), 111 RTW89_DEF_CHAN_6G(6535, 117), 112 RTW89_DEF_CHAN_6G(6555, 121), 113 RTW89_DEF_CHAN_6G(6575, 125), 114 RTW89_DEF_CHAN_6G(6595, 129), 115 RTW89_DEF_CHAN_6G(6615, 133), 116 RTW89_DEF_CHAN_6G(6635, 137), 117 RTW89_DEF_CHAN_6G(6655, 141), 118 RTW89_DEF_CHAN_6G(6675, 145), 119 RTW89_DEF_CHAN_6G(6695, 149), 120 RTW89_DEF_CHAN_6G(6715, 153), 121 RTW89_DEF_CHAN_6G(6735, 157), 122 RTW89_DEF_CHAN_6G(6755, 161), 123 RTW89_DEF_CHAN_6G(6775, 165), 124 RTW89_DEF_CHAN_6G(6795, 169), 125 RTW89_DEF_CHAN_6G(6815, 173), 126 RTW89_DEF_CHAN_6G(6835, 177), 127 RTW89_DEF_CHAN_6G(6855, 181), 128 RTW89_DEF_CHAN_6G(6875, 185), 129 RTW89_DEF_CHAN_6G(6895, 189), 130 RTW89_DEF_CHAN_6G(6915, 193), 131 RTW89_DEF_CHAN_6G(6935, 197), 132 RTW89_DEF_CHAN_6G(6955, 201), 133 RTW89_DEF_CHAN_6G(6975, 205), 134 RTW89_DEF_CHAN_6G(6995, 209), 135 RTW89_DEF_CHAN_6G(7015, 213), 136 RTW89_DEF_CHAN_6G(7035, 217), 137 RTW89_DEF_CHAN_6G(7055, 221), 138 RTW89_DEF_CHAN_6G(7075, 225), 139 RTW89_DEF_CHAN_6G(7095, 229), 140 RTW89_DEF_CHAN_6G(7115, 233), 141 }; 142 143 static struct ieee80211_rate rtw89_bitrates[] = { 144 { .bitrate = 10, .hw_value = 0x00, }, 145 { .bitrate = 20, .hw_value = 0x01, }, 146 { .bitrate = 55, .hw_value = 0x02, }, 147 { .bitrate = 110, .hw_value = 0x03, }, 148 { .bitrate = 60, .hw_value = 0x04, }, 149 { .bitrate = 90, .hw_value = 0x05, }, 150 { .bitrate = 120, .hw_value = 0x06, }, 151 { .bitrate = 180, .hw_value = 0x07, }, 152 { .bitrate = 240, .hw_value = 0x08, }, 153 { .bitrate = 360, .hw_value = 0x09, }, 154 { .bitrate = 480, .hw_value = 0x0a, }, 155 { .bitrate = 540, .hw_value = 0x0b, }, 156 }; 157 158 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 159 { 160 struct ieee80211_rate rate; 161 162 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 163 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 164 return false; 165 } 166 167 rate = rtw89_bitrates[rpt_rate]; 168 *bitrate = rate.bitrate; 169 170 return true; 171 } 172 173 static struct ieee80211_supported_band rtw89_sband_2ghz = { 174 .band = NL80211_BAND_2GHZ, 175 .channels = rtw89_channels_2ghz, 176 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 177 .bitrates = rtw89_bitrates, 178 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 179 .ht_cap = {0}, 180 .vht_cap = {0}, 181 }; 182 183 static struct ieee80211_supported_band rtw89_sband_5ghz = { 184 .band = NL80211_BAND_5GHZ, 185 .channels = rtw89_channels_5ghz, 186 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 187 188 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 189 .bitrates = rtw89_bitrates + 4, 190 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 191 .ht_cap = {0}, 192 .vht_cap = {0}, 193 }; 194 195 static struct ieee80211_supported_band rtw89_sband_6ghz = { 196 .band = NL80211_BAND_6GHZ, 197 .channels = rtw89_channels_6ghz, 198 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 199 200 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 201 .bitrates = rtw89_bitrates + 4, 202 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 203 }; 204 205 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 206 struct rtw89_traffic_stats *stats, 207 struct sk_buff *skb, bool tx) 208 { 209 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 210 211 if (!ieee80211_is_data(hdr->frame_control)) 212 return; 213 214 if (is_broadcast_ether_addr(hdr->addr1) || 215 is_multicast_ether_addr(hdr->addr1)) 216 return; 217 218 if (tx) { 219 stats->tx_cnt++; 220 stats->tx_unicast += skb->len; 221 } else { 222 stats->rx_cnt++; 223 stats->rx_unicast += skb->len; 224 } 225 } 226 227 static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef, 228 struct rtw89_channel_params *chan_param) 229 { 230 struct ieee80211_channel *channel = chandef->chan; 231 enum nl80211_chan_width width = chandef->width; 232 u32 primary_freq, center_freq; 233 u8 center_chan; 234 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 235 u8 primary_chan_idx = 0; 236 u32 offset; 237 u8 band; 238 u8 subband; 239 240 center_chan = channel->hw_value; 241 primary_freq = channel->center_freq; 242 center_freq = chandef->center_freq1; 243 244 switch (width) { 245 case NL80211_CHAN_WIDTH_20_NOHT: 246 case NL80211_CHAN_WIDTH_20: 247 bandwidth = RTW89_CHANNEL_WIDTH_20; 248 primary_chan_idx = RTW89_SC_DONT_CARE; 249 break; 250 case NL80211_CHAN_WIDTH_40: 251 bandwidth = RTW89_CHANNEL_WIDTH_40; 252 if (primary_freq > center_freq) { 253 primary_chan_idx = RTW89_SC_20_UPPER; 254 center_chan -= 2; 255 } else { 256 primary_chan_idx = RTW89_SC_20_LOWER; 257 center_chan += 2; 258 } 259 break; 260 case NL80211_CHAN_WIDTH_80: 261 case NL80211_CHAN_WIDTH_160: 262 bandwidth = nl_to_rtw89_bandwidth(width); 263 if (primary_freq > center_freq) { 264 offset = (primary_freq - center_freq - 10) / 20; 265 primary_chan_idx = RTW89_SC_20_UPPER + offset * 2; 266 center_chan -= 2 + offset * 4; 267 } else { 268 offset = (center_freq - primary_freq - 10) / 20; 269 primary_chan_idx = RTW89_SC_20_LOWER + offset * 2; 270 center_chan += 2 + offset * 4; 271 } 272 break; 273 default: 274 center_chan = 0; 275 break; 276 } 277 278 switch (channel->band) { 279 default: 280 case NL80211_BAND_2GHZ: 281 band = RTW89_BAND_2G; 282 break; 283 case NL80211_BAND_5GHZ: 284 band = RTW89_BAND_5G; 285 break; 286 case NL80211_BAND_6GHZ: 287 band = RTW89_BAND_6G; 288 break; 289 } 290 291 switch (band) { 292 default: 293 case RTW89_BAND_2G: 294 switch (center_chan) { 295 default: 296 case 1 ... 14: 297 subband = RTW89_CH_2G; 298 break; 299 } 300 break; 301 case RTW89_BAND_5G: 302 switch (center_chan) { 303 default: 304 case 36 ... 64: 305 subband = RTW89_CH_5G_BAND_1; 306 break; 307 case 100 ... 144: 308 subband = RTW89_CH_5G_BAND_3; 309 break; 310 case 149 ... 177: 311 subband = RTW89_CH_5G_BAND_4; 312 break; 313 } 314 break; 315 case RTW89_BAND_6G: 316 switch (center_chan) { 317 default: 318 case 1 ... 29: 319 subband = RTW89_CH_6G_BAND_IDX0; 320 break; 321 case 33 ... 61: 322 subband = RTW89_CH_6G_BAND_IDX1; 323 break; 324 case 65 ... 93: 325 subband = RTW89_CH_6G_BAND_IDX2; 326 break; 327 case 97 ... 125: 328 subband = RTW89_CH_6G_BAND_IDX3; 329 break; 330 case 129 ... 157: 331 subband = RTW89_CH_6G_BAND_IDX4; 332 break; 333 case 161 ... 189: 334 subband = RTW89_CH_6G_BAND_IDX5; 335 break; 336 case 193 ... 221: 337 subband = RTW89_CH_6G_BAND_IDX6; 338 break; 339 case 225 ... 253: 340 subband = RTW89_CH_6G_BAND_IDX7; 341 break; 342 } 343 break; 344 } 345 346 chan_param->center_chan = center_chan; 347 chan_param->center_freq = center_freq; 348 chan_param->primary_chan = channel->hw_value; 349 chan_param->bandwidth = bandwidth; 350 chan_param->pri_ch_idx = primary_chan_idx; 351 chan_param->band_type = band; 352 chan_param->subband_type = subband; 353 } 354 355 void rtw89_set_channel(struct rtw89_dev *rtwdev) 356 { 357 struct ieee80211_hw *hw = rtwdev->hw; 358 const struct rtw89_chip_info *chip = rtwdev->chip; 359 struct rtw89_hal *hal = &rtwdev->hal; 360 struct rtw89_channel_params ch_param; 361 struct rtw89_channel_help_params bak; 362 u8 center_chan, bandwidth; 363 bool band_changed; 364 365 rtw89_get_channel_params(&hw->conf.chandef, &ch_param); 366 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 367 return; 368 369 center_chan = ch_param.center_chan; 370 bandwidth = ch_param.bandwidth; 371 band_changed = hal->current_band_type != ch_param.band_type || 372 hal->current_channel == 0; 373 374 hal->current_band_width = bandwidth; 375 hal->current_channel = center_chan; 376 hal->current_freq = ch_param.center_freq; 377 hal->prev_primary_channel = hal->current_primary_channel; 378 hal->prev_band_type = hal->current_band_type; 379 hal->current_primary_channel = ch_param.primary_chan; 380 hal->current_band_type = ch_param.band_type; 381 hal->current_subband = ch_param.subband_type; 382 383 rtw89_chip_set_channel_prepare(rtwdev, &bak); 384 385 chip->ops->set_channel(rtwdev, &ch_param); 386 387 rtw89_chip_set_txpwr(rtwdev); 388 389 rtw89_chip_set_channel_done(rtwdev, &bak); 390 391 if (band_changed) { 392 rtw89_btc_ntfy_switch_band(rtwdev, RTW89_PHY_0, hal->current_band_type); 393 rtw89_chip_rfk_band_changed(rtwdev); 394 } 395 } 396 397 static enum rtw89_core_tx_type 398 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 399 struct sk_buff *skb) 400 { 401 struct ieee80211_hdr *hdr = (void *)skb->data; 402 __le16 fc = hdr->frame_control; 403 404 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 405 return RTW89_CORE_TX_TYPE_MGMT; 406 407 return RTW89_CORE_TX_TYPE_DATA; 408 } 409 410 static void 411 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 412 struct rtw89_core_tx_request *tx_req, 413 enum btc_pkt_type pkt_type) 414 { 415 struct ieee80211_sta *sta = tx_req->sta; 416 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 417 struct sk_buff *skb = tx_req->skb; 418 struct rtw89_sta *rtwsta; 419 u8 ampdu_num; 420 u8 tid; 421 422 if (pkt_type == PACKET_EAPOL) { 423 desc_info->bk = true; 424 return; 425 } 426 427 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 428 return; 429 430 if (!sta) { 431 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 432 return; 433 } 434 435 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 436 rtwsta = (struct rtw89_sta *)sta->drv_priv; 437 438 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 439 rtwsta->ampdu_params[tid].agg_num : 440 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 441 442 desc_info->agg_en = true; 443 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 444 desc_info->ampdu_num = ampdu_num; 445 } 446 447 static void 448 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 449 struct rtw89_core_tx_request *tx_req) 450 { 451 const struct rtw89_chip_info *chip = rtwdev->chip; 452 struct ieee80211_vif *vif = tx_req->vif; 453 struct ieee80211_sta *sta = tx_req->sta; 454 struct ieee80211_tx_info *info; 455 struct ieee80211_key_conf *key; 456 struct rtw89_vif *rtwvif; 457 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 458 struct rtw89_addr_cam_entry *addr_cam; 459 struct rtw89_sec_cam_entry *sec_cam; 460 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 461 struct sk_buff *skb = tx_req->skb; 462 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 463 u64 pn64; 464 465 if (!vif) { 466 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 467 return; 468 } 469 470 rtwvif = (struct rtw89_vif *)vif->drv_priv; 471 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 472 473 info = IEEE80211_SKB_CB(skb); 474 key = info->control.hw_key; 475 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 476 if (!sec_cam) { 477 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 478 return; 479 } 480 481 switch (key->cipher) { 482 case WLAN_CIPHER_SUITE_WEP40: 483 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 484 break; 485 case WLAN_CIPHER_SUITE_WEP104: 486 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 487 break; 488 case WLAN_CIPHER_SUITE_TKIP: 489 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 490 break; 491 case WLAN_CIPHER_SUITE_CCMP: 492 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 493 break; 494 case WLAN_CIPHER_SUITE_CCMP_256: 495 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 496 break; 497 case WLAN_CIPHER_SUITE_GCMP: 498 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 499 break; 500 case WLAN_CIPHER_SUITE_GCMP_256: 501 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 502 break; 503 default: 504 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 505 return; 506 } 507 508 desc_info->sec_en = true; 509 desc_info->sec_keyid = key->keyidx; 510 desc_info->sec_type = sec_type; 511 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 512 513 if (!chip->hw_sec_hdr) 514 return; 515 516 pn64 = atomic64_inc_return(&key->tx_pn); 517 desc_info->sec_seq[0] = pn64; 518 desc_info->sec_seq[1] = pn64 >> 8; 519 desc_info->sec_seq[2] = pn64 >> 16; 520 desc_info->sec_seq[3] = pn64 >> 24; 521 desc_info->sec_seq[4] = pn64 >> 32; 522 desc_info->sec_seq[5] = pn64 >> 40; 523 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 524 } 525 526 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 527 struct rtw89_core_tx_request *tx_req) 528 { 529 struct sk_buff *skb = tx_req->skb; 530 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 531 struct ieee80211_vif *vif = tx_info->control.vif; 532 struct rtw89_hal *hal = &rtwdev->hal; 533 u16 lowest_rate = hal->current_band_type == RTW89_BAND_2G ? 534 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6; 535 536 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 537 return lowest_rate; 538 539 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 540 } 541 542 static void 543 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 544 struct rtw89_core_tx_request *tx_req) 545 { 546 struct ieee80211_vif *vif = tx_req->vif; 547 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 548 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 549 u8 qsel, ch_dma; 550 551 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 552 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 553 554 desc_info->qsel = qsel; 555 desc_info->ch_dma = ch_dma; 556 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 557 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 558 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 559 560 /* fixed data rate for mgmt frames */ 561 desc_info->en_wd_info = true; 562 desc_info->use_rate = true; 563 desc_info->dis_data_fb = true; 564 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); 565 566 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 567 "tx mgmt frame with rate 0x%x on channel %d (bw %d)\n", 568 desc_info->data_rate, rtwdev->hal.current_channel, 569 rtwdev->hal.current_band_width); 570 } 571 572 static void 573 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 574 struct rtw89_core_tx_request *tx_req) 575 { 576 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 577 578 desc_info->is_bmc = false; 579 desc_info->wd_page = false; 580 desc_info->ch_dma = RTW89_DMA_H2C; 581 } 582 583 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) 584 { 585 static const u8 rtw89_bandwidth_to_om[] = { 586 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 587 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 588 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 589 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 590 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 591 }; 592 const struct rtw89_chip_info *chip = rtwdev->chip; 593 struct rtw89_hal *hal = &rtwdev->hal; 594 u8 om_bandwidth; 595 596 if (!chip->dis_2g_40m_ul_ofdma || 597 hal->current_band_type != RTW89_BAND_2G || 598 hal->current_band_width != RTW89_CHANNEL_WIDTH_40) 599 return; 600 601 om_bandwidth = hal->current_band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 602 rtw89_bandwidth_to_om[hal->current_band_width] : 0; 603 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 604 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 605 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 606 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 607 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 608 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 609 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 610 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 611 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 612 } 613 614 static bool 615 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 616 struct rtw89_core_tx_request *tx_req, 617 enum btc_pkt_type pkt_type) 618 { 619 struct ieee80211_sta *sta = tx_req->sta; 620 struct sk_buff *skb = tx_req->skb; 621 struct ieee80211_hdr *hdr = (void *)skb->data; 622 __le16 fc = hdr->frame_control; 623 624 /* AP IOT issue with EAPoL, ARP and DHCP */ 625 if (pkt_type < PACKET_MAX) 626 return false; 627 628 if (!sta || !sta->deflink.he_cap.has_he) 629 return false; 630 631 if (!ieee80211_is_data_qos(fc)) 632 return false; 633 634 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 635 return false; 636 637 return true; 638 } 639 640 static void 641 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 642 struct rtw89_core_tx_request *tx_req) 643 { 644 struct ieee80211_sta *sta = tx_req->sta; 645 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 646 struct sk_buff *skb = tx_req->skb; 647 struct ieee80211_hdr *hdr = (void *)skb->data; 648 __le16 fc = hdr->frame_control; 649 void *data; 650 __le32 *htc; 651 u8 *qc; 652 int hdr_len; 653 654 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 655 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 656 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 657 658 hdr = data; 659 htc = data + hdr_len; 660 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 661 *htc = rtwsta->htc_template ? rtwsta->htc_template : 662 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 663 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 664 665 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 666 qc[0] |= IEEE80211_QOS_CTL_EOSP; 667 } 668 669 static void 670 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 671 struct rtw89_core_tx_request *tx_req, 672 enum btc_pkt_type pkt_type) 673 { 674 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 675 struct ieee80211_vif *vif = tx_req->vif; 676 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 677 678 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 679 goto desc_bk; 680 681 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 682 683 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 684 desc_info->a_ctrl_bsr = true; 685 686 desc_bk: 687 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 688 return; 689 690 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 691 desc_info->bk = true; 692 } 693 694 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 695 struct rtw89_core_tx_request *tx_req) 696 { 697 struct ieee80211_vif *vif = tx_req->vif; 698 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 699 struct ieee80211_sta *sta = tx_req->sta; 700 struct rtw89_sta *rtwsta; 701 702 if (!sta) 703 return rtwvif->mac_id; 704 705 rtwsta = (struct rtw89_sta *)sta->drv_priv; 706 return rtwsta->mac_id; 707 } 708 709 static void 710 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 711 struct rtw89_core_tx_request *tx_req) 712 { 713 struct ieee80211_vif *vif = tx_req->vif; 714 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 715 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 716 struct rtw89_hal *hal = &rtwdev->hal; 717 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 718 struct sk_buff *skb = tx_req->skb; 719 u8 tid, tid_indicate; 720 u8 qsel, ch_dma; 721 722 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 723 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 724 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 725 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 726 727 desc_info->ch_dma = ch_dma; 728 desc_info->tid_indicate = tid_indicate; 729 desc_info->qsel = qsel; 730 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 731 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 732 733 /* enable wd_info for AMPDU */ 734 desc_info->en_wd_info = true; 735 736 if (IEEE80211_SKB_CB(skb)->control.hw_key) 737 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 738 739 if (rate_pattern->enable) 740 desc_info->data_retry_lowest_rate = rate_pattern->rate; 741 else if (hal->current_band_type == RTW89_BAND_2G) 742 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_CCK1; 743 else 744 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 745 } 746 747 static enum btc_pkt_type 748 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 749 struct rtw89_core_tx_request *tx_req) 750 { 751 struct sk_buff *skb = tx_req->skb; 752 struct udphdr *udphdr; 753 754 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 755 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 756 return PACKET_EAPOL; 757 } 758 759 if (skb->protocol == htons(ETH_P_ARP)) { 760 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 761 return PACKET_ARP; 762 } 763 764 if (skb->protocol == htons(ETH_P_IP) && 765 ip_hdr(skb)->protocol == IPPROTO_UDP) { 766 udphdr = udp_hdr(skb); 767 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 768 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 769 skb->len > 282) { 770 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 771 return PACKET_DHCP; 772 } 773 } 774 775 if (skb->protocol == htons(ETH_P_IP) && 776 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 777 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 778 return PACKET_ICMP; 779 } 780 781 return PACKET_MAX; 782 } 783 784 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 785 struct rtw89_tx_desc_info *desc_info, 786 struct sk_buff *skb) 787 { 788 struct ieee80211_hdr *hdr = (void *)skb->data; 789 __le16 fc = hdr->frame_control; 790 791 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 792 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 793 } 794 795 static void 796 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 797 struct rtw89_core_tx_request *tx_req) 798 { 799 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 800 return; 801 802 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 803 return; 804 805 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 806 return; 807 808 rtw89_mac_notify_wake(rtwdev); 809 } 810 811 static void 812 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 813 struct rtw89_core_tx_request *tx_req) 814 { 815 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 816 struct sk_buff *skb = tx_req->skb; 817 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 818 struct ieee80211_hdr *hdr = (void *)skb->data; 819 enum rtw89_core_tx_type tx_type; 820 enum btc_pkt_type pkt_type; 821 bool is_bmc; 822 u16 seq; 823 824 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 825 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 826 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 827 tx_req->tx_type = tx_type; 828 } 829 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 830 is_multicast_ether_addr(hdr->addr1)); 831 832 desc_info->seq = seq; 833 desc_info->pkt_size = skb->len; 834 desc_info->is_bmc = is_bmc; 835 desc_info->wd_page = true; 836 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 837 838 switch (tx_req->tx_type) { 839 case RTW89_CORE_TX_TYPE_MGMT: 840 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 841 break; 842 case RTW89_CORE_TX_TYPE_DATA: 843 rtw89_core_tx_update_data_info(rtwdev, tx_req); 844 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 845 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 846 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 847 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 848 break; 849 case RTW89_CORE_TX_TYPE_FWCMD: 850 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 851 break; 852 } 853 } 854 855 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 856 { 857 u8 ch_dma; 858 859 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 860 861 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 862 } 863 864 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 865 struct sk_buff *skb, bool fwdl) 866 { 867 struct rtw89_core_tx_request tx_req = {0}; 868 u32 cnt; 869 int ret; 870 871 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 872 rtw89_debug(rtwdev, RTW89_DBG_FW, 873 "ignore h2c due to power is off with firmware state=%d\n", 874 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 875 return 0; 876 } 877 878 tx_req.skb = skb; 879 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 880 if (fwdl) 881 tx_req.desc_info.fw_dl = true; 882 883 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 884 885 if (!fwdl) 886 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 887 888 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 889 if (cnt == 0) { 890 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 891 return -ENOSPC; 892 } 893 894 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 895 if (ret) { 896 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 897 return ret; 898 } 899 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 900 901 return 0; 902 } 903 904 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 905 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 906 { 907 struct rtw89_core_tx_request tx_req = {0}; 908 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 909 int ret; 910 911 tx_req.skb = skb; 912 tx_req.sta = sta; 913 tx_req.vif = vif; 914 915 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 916 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 917 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 918 rtw89_core_tx_wake(rtwdev, &tx_req); 919 920 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 921 if (ret) { 922 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 923 return ret; 924 } 925 926 if (qsel) 927 *qsel = tx_req.desc_info.qsel; 928 929 return 0; 930 } 931 932 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 933 { 934 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 935 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 936 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 937 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 938 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 939 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 940 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 941 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 942 943 return cpu_to_le32(dword); 944 } 945 946 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 947 { 948 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 949 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 950 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 951 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 952 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 953 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 954 955 return cpu_to_le32(dword); 956 } 957 958 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 959 { 960 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 961 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 962 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 963 964 return cpu_to_le32(dword); 965 } 966 967 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 968 { 969 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 970 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 971 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 972 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 973 974 return cpu_to_le32(dword); 975 } 976 977 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 978 { 979 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 980 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 981 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 982 983 return cpu_to_le32(dword); 984 } 985 986 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 987 { 988 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 989 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 990 991 return cpu_to_le32(dword); 992 } 993 994 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 995 { 996 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 997 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 998 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 999 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1000 1001 return cpu_to_le32(dword); 1002 } 1003 1004 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1005 { 1006 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1007 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1008 1009 return cpu_to_le32(dword); 1010 } 1011 1012 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1013 { 1014 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1015 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1016 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1017 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1018 1019 return cpu_to_le32(dword); 1020 } 1021 1022 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1023 { 1024 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb); 1025 1026 return cpu_to_le32(dword); 1027 } 1028 1029 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1030 { 1031 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1032 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1033 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1034 desc_info->data_retry_lowest_rate); 1035 1036 return cpu_to_le32(dword); 1037 } 1038 1039 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1040 { 1041 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1042 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1043 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1044 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1045 1046 return cpu_to_le32(dword); 1047 } 1048 1049 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1050 { 1051 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1052 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1053 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1054 1055 return cpu_to_le32(dword); 1056 } 1057 1058 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1059 { 1060 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1061 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1062 1063 return cpu_to_le32(dword); 1064 } 1065 1066 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1067 struct rtw89_tx_desc_info *desc_info, 1068 void *txdesc) 1069 { 1070 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1071 struct rtw89_txwd_info *txwd_info; 1072 1073 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1074 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1075 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1076 1077 if (!desc_info->en_wd_info) 1078 return; 1079 1080 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1081 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1082 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1083 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1084 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1085 1086 } 1087 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1088 1089 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1090 struct rtw89_tx_desc_info *desc_info, 1091 void *txdesc) 1092 { 1093 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1094 struct rtw89_txwd_info *txwd_info; 1095 1096 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1097 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1098 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1099 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1100 if (desc_info->sec_en) { 1101 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1102 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1103 } 1104 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1105 1106 if (!desc_info->en_wd_info) 1107 return; 1108 1109 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1110 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1111 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1112 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1113 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1114 } 1115 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1116 1117 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1118 { 1119 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1120 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1121 RTW89_CORE_RX_TYPE_FWDL : 1122 RTW89_CORE_RX_TYPE_H2C); 1123 1124 return cpu_to_le32(dword); 1125 } 1126 1127 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1128 struct rtw89_tx_desc_info *desc_info, 1129 void *txdesc) 1130 { 1131 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1132 1133 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1134 } 1135 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1136 1137 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1138 struct sk_buff *skb, 1139 struct rtw89_rx_phy_ppdu *phy_ppdu) 1140 { 1141 bool rx_cnt_valid = false; 1142 u8 plcp_size = 0; 1143 u8 usr_num = 0; 1144 u8 *phy_sts; 1145 1146 rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); 1147 plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; 1148 usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); 1149 if (usr_num > RTW89_PPDU_MAX_USR) { 1150 rtw89_warn(rtwdev, "Invalid user number in mac info\n"); 1151 return -EINVAL; 1152 } 1153 1154 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1155 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1156 /* 8-byte alignment */ 1157 if (usr_num & BIT(0)) 1158 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1159 if (rx_cnt_valid) 1160 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; 1161 phy_sts += plcp_size; 1162 1163 phy_ppdu->buf = phy_sts; 1164 phy_ppdu->len = skb->data + skb->len - phy_sts; 1165 1166 return 0; 1167 } 1168 1169 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1170 struct ieee80211_sta *sta) 1171 { 1172 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1173 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1174 1175 if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) 1176 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1177 } 1178 1179 #define VAR_LEN 0xff 1180 #define VAR_LEN_UNIT 8 1181 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) 1182 { 1183 static const u8 physts_ie_len_tab[32] = { 1184 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1185 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1186 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1187 }; 1188 u16 ie_len; 1189 u8 ie; 1190 1191 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1192 if (physts_ie_len_tab[ie] != VAR_LEN) 1193 ie_len = physts_ie_len_tab[ie]; 1194 else 1195 ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; 1196 1197 return ie_len; 1198 } 1199 1200 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, 1201 struct rtw89_rx_phy_ppdu *phy_ppdu) 1202 { 1203 s16 cfo; 1204 1205 phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr); 1206 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1207 return; 1208 /* sign conversion for S(12,2) */ 1209 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_CFO(addr), 11); 1210 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1211 } 1212 1213 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, 1214 struct rtw89_rx_phy_ppdu *phy_ppdu) 1215 { 1216 u8 ie; 1217 1218 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1219 switch (ie) { 1220 case RTW89_PHYSTS_IE01_CMN_OFDM: 1221 rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); 1222 break; 1223 default: 1224 break; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1231 { 1232 s8 *rssi = phy_ppdu->rssi; 1233 u8 *buf = phy_ppdu->buf; 1234 1235 phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf); 1236 phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); 1237 rssi[RF_PATH_A] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_A(buf)); 1238 rssi[RF_PATH_B] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_B(buf)); 1239 rssi[RF_PATH_C] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_C(buf)); 1240 rssi[RF_PATH_D] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_D(buf)); 1241 } 1242 1243 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1244 struct rtw89_rx_phy_ppdu *phy_ppdu) 1245 { 1246 if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { 1247 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1248 return -EINVAL; 1249 } 1250 rtw89_core_update_phy_ppdu(phy_ppdu); 1251 ieee80211_iterate_stations_atomic(rtwdev->hw, 1252 rtw89_core_rx_process_phy_ppdu_iter, 1253 phy_ppdu); 1254 1255 return 0; 1256 } 1257 1258 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1259 struct rtw89_rx_phy_ppdu *phy_ppdu) 1260 { 1261 u16 ie_len; 1262 u8 *pos, *end; 1263 1264 /* mark invalid reports and bypass them */ 1265 if (phy_ppdu->ie < RTW89_CCK_PKT) 1266 return -EINVAL; 1267 1268 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1269 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1270 while (pos < end) { 1271 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); 1272 rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); 1273 pos += ie_len; 1274 if (pos > end || ie_len == 0) { 1275 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1276 "phy status parse failed\n"); 1277 return -EINVAL; 1278 } 1279 } 1280 1281 return 0; 1282 } 1283 1284 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1285 struct rtw89_rx_phy_ppdu *phy_ppdu) 1286 { 1287 int ret; 1288 1289 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1290 if (ret) 1291 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1292 else 1293 phy_ppdu->valid = true; 1294 } 1295 1296 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1297 const struct rtw89_rx_desc_info *desc_info, 1298 bool rx_status) 1299 { 1300 switch (desc_info->gi_ltf) { 1301 case RTW89_GILTF_SGI_4XHE08: 1302 case RTW89_GILTF_2XHE08: 1303 case RTW89_GILTF_1XHE08: 1304 return NL80211_RATE_INFO_HE_GI_0_8; 1305 case RTW89_GILTF_2XHE16: 1306 case RTW89_GILTF_1XHE16: 1307 return NL80211_RATE_INFO_HE_GI_1_6; 1308 case RTW89_GILTF_LGI_4XHE32: 1309 return NL80211_RATE_INFO_HE_GI_3_2; 1310 default: 1311 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); 1312 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; 1313 } 1314 } 1315 1316 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1317 struct rtw89_rx_desc_info *desc_info, 1318 struct ieee80211_rx_status *status) 1319 { 1320 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1321 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1322 u16 data_rate; 1323 bool ret; 1324 1325 data_rate = desc_info->data_rate; 1326 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1327 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1328 rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1329 /* rate_idx is still hardware value here */ 1330 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1331 rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1332 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1333 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1334 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1335 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1336 } else { 1337 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1338 } 1339 1340 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1341 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); 1342 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1343 status->rate_idx == rate_idx && 1344 status->he_gi == gi_ltf && 1345 status->bw == bw; 1346 1347 return ret; 1348 } 1349 1350 struct rtw89_vif_rx_stats_iter_data { 1351 struct rtw89_dev *rtwdev; 1352 struct rtw89_rx_phy_ppdu *phy_ppdu; 1353 struct rtw89_rx_desc_info *desc_info; 1354 struct sk_buff *skb; 1355 const u8 *bssid; 1356 }; 1357 1358 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1359 struct ieee80211_vif *vif, 1360 struct sk_buff *skb) 1361 { 1362 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1363 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1364 u8 *pos, *end, type; 1365 u16 aid; 1366 1367 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1368 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1369 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1370 return; 1371 1372 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1373 if (type != IEEE80211_TRIGGER_TYPE_BASIC) 1374 return; 1375 1376 end = (u8 *)tf + skb->len; 1377 pos = tf->variable; 1378 1379 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1380 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1381 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1382 "[TF] aid: %d, ul_mcs: %d, rua: %d\n", 1383 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1384 RTW89_GET_TF_USER_INFO_RUA(pos)); 1385 1386 if (aid == RTW89_TF_PAD) 1387 break; 1388 1389 if (aid == vif->cfg.aid) { 1390 rtwvif->stats.rx_tf_acc++; 1391 rtwdev->stats.rx_tf_acc++; 1392 break; 1393 } 1394 1395 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1396 } 1397 } 1398 1399 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1400 struct ieee80211_vif *vif) 1401 { 1402 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1403 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1404 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1405 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1406 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1407 struct sk_buff *skb = iter_data->skb; 1408 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1409 const u8 *bssid = iter_data->bssid; 1410 1411 if (ieee80211_is_trigger(hdr->frame_control)) { 1412 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1413 return; 1414 } 1415 1416 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1417 return; 1418 1419 if (ieee80211_is_beacon(hdr->frame_control)) 1420 pkt_stat->beacon_nr++; 1421 1422 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1423 return; 1424 1425 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1426 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1427 1428 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1429 } 1430 1431 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1432 struct rtw89_rx_phy_ppdu *phy_ppdu, 1433 struct rtw89_rx_desc_info *desc_info, 1434 struct sk_buff *skb) 1435 { 1436 struct rtw89_vif_rx_stats_iter_data iter_data; 1437 1438 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1439 1440 iter_data.rtwdev = rtwdev; 1441 iter_data.phy_ppdu = phy_ppdu; 1442 iter_data.desc_info = desc_info; 1443 iter_data.skb = skb; 1444 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1445 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1446 } 1447 1448 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1449 struct ieee80211_rx_status *status) 1450 { 1451 u16 chan = rtwdev->hal.prev_primary_channel; 1452 u8 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1453 1454 if (status->band != NL80211_BAND_2GHZ && 1455 status->encoding == RX_ENC_LEGACY && 1456 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1457 status->freq = ieee80211_channel_to_frequency(chan, band); 1458 status->band = band; 1459 } 1460 } 1461 1462 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1463 { 1464 if (rx_status->band == NL80211_BAND_2GHZ || 1465 rx_status->encoding != RX_ENC_LEGACY) 1466 return; 1467 1468 /* Some control frames' freq(ACKs in this case) are reported wrong due 1469 * to FW notify timing, set to lowest rate to prevent overflow. 1470 */ 1471 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1472 rx_status->rate_idx = 0; 1473 return; 1474 } 1475 1476 /* No 4 CCK rates for non-2G */ 1477 rx_status->rate_idx -= 4; 1478 } 1479 1480 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 1481 struct rtw89_rx_phy_ppdu *phy_ppdu, 1482 struct rtw89_rx_desc_info *desc_info, 1483 struct sk_buff *skb_ppdu, 1484 struct ieee80211_rx_status *rx_status) 1485 { 1486 struct napi_struct *napi = &rtwdev->napi; 1487 1488 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 1489 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state))) 1490 napi = NULL; 1491 1492 rtw89_core_hw_to_sband_rate(rx_status); 1493 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 1494 /* In low power mode, it does RX in thread context. */ 1495 local_bh_disable(); 1496 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 1497 local_bh_enable(); 1498 rtwdev->napi_budget_countdown--; 1499 } 1500 1501 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 1502 struct rtw89_rx_phy_ppdu *phy_ppdu, 1503 struct rtw89_rx_desc_info *desc_info, 1504 struct sk_buff *skb) 1505 { 1506 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1507 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 1508 struct sk_buff *skb_ppdu = NULL, *tmp; 1509 struct ieee80211_rx_status *rx_status; 1510 1511 if (curr > RTW89_MAX_PPDU_CNT) 1512 return; 1513 1514 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 1515 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 1516 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1517 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 1518 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 1519 rtw89_correct_cck_chan(rtwdev, rx_status); 1520 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 1521 } 1522 } 1523 1524 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 1525 struct rtw89_rx_desc_info *desc_info, 1526 struct sk_buff *skb) 1527 { 1528 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 1529 .len = skb->len, 1530 .to_self = desc_info->addr1_match, 1531 .rate = desc_info->data_rate, 1532 .mac_id = desc_info->mac_id}; 1533 int ret; 1534 1535 if (desc_info->mac_info_valid) 1536 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 1537 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 1538 if (ret) 1539 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); 1540 1541 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 1542 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 1543 dev_kfree_skb_any(skb); 1544 } 1545 1546 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 1547 struct rtw89_rx_desc_info *desc_info, 1548 struct sk_buff *skb) 1549 { 1550 switch (desc_info->pkt_type) { 1551 case RTW89_CORE_RX_TYPE_C2H: 1552 rtw89_fw_c2h_irqsafe(rtwdev, skb); 1553 break; 1554 case RTW89_CORE_RX_TYPE_PPDU_STAT: 1555 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 1556 break; 1557 default: 1558 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 1559 desc_info->pkt_type); 1560 dev_kfree_skb_any(skb); 1561 break; 1562 } 1563 } 1564 1565 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 1566 struct rtw89_rx_desc_info *desc_info, 1567 u8 *data, u32 data_offset) 1568 { 1569 const struct rtw89_chip_info *chip = rtwdev->chip; 1570 struct rtw89_rxdesc_short *rxd_s; 1571 struct rtw89_rxdesc_long *rxd_l; 1572 u8 shift_len, drv_info_len; 1573 1574 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 1575 desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); 1576 desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); 1577 desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); 1578 desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); 1579 desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); 1580 if (chip->chip_id == RTL8852C) 1581 desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s); 1582 else 1583 desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); 1584 desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); 1585 desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); 1586 desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); 1587 desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); 1588 desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); 1589 desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); 1590 desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); 1591 desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); 1592 desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); 1593 desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); 1594 desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); 1595 desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); 1596 1597 shift_len = desc_info->shift << 1; /* 2-byte unit */ 1598 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 1599 desc_info->offset = data_offset + shift_len + drv_info_len; 1600 desc_info->ready = true; 1601 1602 if (!desc_info->long_rxdesc) 1603 return; 1604 1605 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 1606 desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); 1607 desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); 1608 desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); 1609 desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); 1610 desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); 1611 desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); 1612 } 1613 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 1614 1615 struct rtw89_core_iter_rx_status { 1616 struct rtw89_dev *rtwdev; 1617 struct ieee80211_rx_status *rx_status; 1618 struct rtw89_rx_desc_info *desc_info; 1619 u8 mac_id; 1620 }; 1621 1622 static 1623 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 1624 { 1625 struct rtw89_core_iter_rx_status *iter_data = 1626 (struct rtw89_core_iter_rx_status *)data; 1627 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 1628 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1629 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1630 u8 mac_id = iter_data->mac_id; 1631 1632 if (mac_id != rtwsta->mac_id) 1633 return; 1634 1635 rtwsta->rx_status = *rx_status; 1636 rtwsta->rx_hw_rate = desc_info->data_rate; 1637 } 1638 1639 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 1640 struct rtw89_rx_desc_info *desc_info, 1641 struct ieee80211_rx_status *rx_status) 1642 { 1643 struct rtw89_core_iter_rx_status iter_data; 1644 1645 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 1646 return; 1647 1648 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 1649 return; 1650 1651 iter_data.rtwdev = rtwdev; 1652 iter_data.rx_status = rx_status; 1653 iter_data.desc_info = desc_info; 1654 iter_data.mac_id = desc_info->mac_id; 1655 ieee80211_iterate_stations_atomic(rtwdev->hw, 1656 rtw89_core_stats_sta_rx_status_iter, 1657 &iter_data); 1658 } 1659 1660 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 1661 struct rtw89_rx_desc_info *desc_info, 1662 struct ieee80211_rx_status *rx_status) 1663 { 1664 struct ieee80211_hw *hw = rtwdev->hw; 1665 struct rtw89_hal *hal = &rtwdev->hal; 1666 u16 data_rate; 1667 u8 data_rate_mode; 1668 1669 /* currently using single PHY */ 1670 rx_status->freq = hw->conf.chandef.chan->center_freq; 1671 rx_status->band = hw->conf.chandef.chan->band; 1672 1673 if (rtwdev->scanning && 1674 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 1675 u8 chan = hal->current_primary_channel; 1676 u8 band = hal->current_band_type; 1677 enum nl80211_band nl_band; 1678 1679 nl_band = rtw89_hw_to_nl80211_band(band); 1680 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 1681 rx_status->band = nl_band; 1682 } 1683 1684 if (desc_info->icv_err || desc_info->crc32_err) 1685 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 1686 1687 if (desc_info->hw_dec && 1688 !(desc_info->sw_dec || desc_info->icv_err)) 1689 rx_status->flag |= RX_FLAG_DECRYPTED; 1690 1691 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1692 1693 data_rate = desc_info->data_rate; 1694 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1695 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1696 rx_status->encoding = RX_ENC_LEGACY; 1697 rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1698 /* convert rate_idx after we get the correct band */ 1699 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1700 rx_status->encoding = RX_ENC_HT; 1701 rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1702 if (desc_info->gi_ltf) 1703 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1704 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1705 rx_status->encoding = RX_ENC_VHT; 1706 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1707 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1708 if (desc_info->gi_ltf) 1709 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1710 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1711 rx_status->encoding = RX_ENC_HE; 1712 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1713 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1714 } else { 1715 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1716 } 1717 1718 /* he_gi is used to match ppdu, so we always fill it. */ 1719 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); 1720 rx_status->flag |= RX_FLAG_MACTIME_START; 1721 rx_status->mactime = desc_info->free_run_cnt; 1722 1723 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 1724 } 1725 1726 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 1727 { 1728 const struct rtw89_chip_info *chip = rtwdev->chip; 1729 1730 if (rtw89_disable_ps_mode || !chip->ps_mode_supported) 1731 return RTW89_PS_MODE_NONE; 1732 1733 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) 1734 return RTW89_PS_MODE_PWR_GATED; 1735 1736 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 1737 return RTW89_PS_MODE_CLK_GATED; 1738 1739 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 1740 return RTW89_PS_MODE_RFOFF; 1741 1742 return RTW89_PS_MODE_NONE; 1743 } 1744 1745 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 1746 struct rtw89_rx_desc_info *desc_info) 1747 { 1748 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1749 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1750 struct ieee80211_rx_status *rx_status; 1751 struct sk_buff *skb_ppdu, *tmp; 1752 1753 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 1754 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 1755 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1756 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 1757 } 1758 } 1759 1760 void rtw89_core_rx(struct rtw89_dev *rtwdev, 1761 struct rtw89_rx_desc_info *desc_info, 1762 struct sk_buff *skb) 1763 { 1764 struct ieee80211_rx_status *rx_status; 1765 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1766 u8 ppdu_cnt = desc_info->ppdu_cnt; 1767 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1768 1769 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 1770 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 1771 return; 1772 } 1773 1774 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 1775 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 1776 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 1777 } 1778 1779 rx_status = IEEE80211_SKB_RXCB(skb); 1780 memset(rx_status, 0, sizeof(*rx_status)); 1781 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 1782 if (desc_info->long_rxdesc && 1783 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 1784 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 1785 else 1786 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 1787 } 1788 EXPORT_SYMBOL(rtw89_core_rx); 1789 1790 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 1791 { 1792 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1793 return; 1794 1795 napi_enable(&rtwdev->napi); 1796 } 1797 EXPORT_SYMBOL(rtw89_core_napi_start); 1798 1799 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 1800 { 1801 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1802 return; 1803 1804 napi_synchronize(&rtwdev->napi); 1805 napi_disable(&rtwdev->napi); 1806 } 1807 EXPORT_SYMBOL(rtw89_core_napi_stop); 1808 1809 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 1810 { 1811 init_dummy_netdev(&rtwdev->netdev); 1812 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 1813 rtwdev->hci.ops->napi_poll, NAPI_POLL_WEIGHT); 1814 } 1815 EXPORT_SYMBOL(rtw89_core_napi_init); 1816 1817 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 1818 { 1819 rtw89_core_napi_stop(rtwdev); 1820 netif_napi_del(&rtwdev->napi); 1821 } 1822 EXPORT_SYMBOL(rtw89_core_napi_deinit); 1823 1824 static void rtw89_core_ba_work(struct work_struct *work) 1825 { 1826 struct rtw89_dev *rtwdev = 1827 container_of(work, struct rtw89_dev, ba_work); 1828 struct rtw89_txq *rtwtxq, *tmp; 1829 int ret; 1830 1831 spin_lock_bh(&rtwdev->ba_lock); 1832 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1833 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1834 struct ieee80211_sta *sta = txq->sta; 1835 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1836 u8 tid = txq->tid; 1837 1838 if (!sta) { 1839 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 1840 goto skip_ba_work; 1841 } 1842 1843 if (rtwsta->disassoc) { 1844 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1845 "cannot start BA with disassoc sta\n"); 1846 goto skip_ba_work; 1847 } 1848 1849 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 1850 if (ret) { 1851 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1852 "failed to setup BA session for %pM:%2d: %d\n", 1853 sta->addr, tid, ret); 1854 if (ret == -EINVAL) 1855 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 1856 } 1857 skip_ba_work: 1858 list_del_init(&rtwtxq->list); 1859 } 1860 spin_unlock_bh(&rtwdev->ba_lock); 1861 } 1862 1863 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 1864 struct ieee80211_sta *sta) 1865 { 1866 struct rtw89_txq *rtwtxq, *tmp; 1867 1868 spin_lock_bh(&rtwdev->ba_lock); 1869 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1870 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1871 1872 if (sta == txq->sta) 1873 list_del_init(&rtwtxq->list); 1874 } 1875 spin_unlock_bh(&rtwdev->ba_lock); 1876 } 1877 1878 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 1879 struct ieee80211_sta *sta) 1880 { 1881 struct rtw89_txq *rtwtxq, *tmp; 1882 1883 spin_lock_bh(&rtwdev->ba_lock); 1884 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 1885 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1886 1887 if (sta == txq->sta) { 1888 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 1889 list_del_init(&rtwtxq->list); 1890 } 1891 } 1892 spin_unlock_bh(&rtwdev->ba_lock); 1893 } 1894 1895 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 1896 struct rtw89_txq *rtwtxq) 1897 { 1898 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1899 struct ieee80211_sta *sta = txq->sta; 1900 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1901 1902 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 1903 return; 1904 1905 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 1906 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1907 return; 1908 1909 spin_lock_bh(&rtwdev->ba_lock); 1910 if (!list_empty(&rtwtxq->list)) { 1911 list_del_init(&rtwtxq->list); 1912 goto out; 1913 } 1914 1915 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 1916 1917 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 1918 ieee80211_stop_tx_ba_session(sta, txq->tid); 1919 cancel_delayed_work(&rtwdev->forbid_ba_work); 1920 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 1921 RTW89_FORBID_BA_TIMER); 1922 1923 out: 1924 spin_unlock_bh(&rtwdev->ba_lock); 1925 } 1926 1927 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 1928 struct rtw89_txq *rtwtxq, 1929 struct sk_buff *skb) 1930 { 1931 struct ieee80211_hw *hw = rtwdev->hw; 1932 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1933 struct ieee80211_sta *sta = txq->sta; 1934 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1935 1936 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 1937 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 1938 return; 1939 } 1940 1941 if (unlikely(!sta)) 1942 return; 1943 1944 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1945 return; 1946 1947 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 1948 return; 1949 1950 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 1951 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 1952 return; 1953 } 1954 1955 spin_lock_bh(&rtwdev->ba_lock); 1956 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 1957 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 1958 ieee80211_queue_work(hw, &rtwdev->ba_work); 1959 } 1960 spin_unlock_bh(&rtwdev->ba_lock); 1961 } 1962 1963 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 1964 struct rtw89_txq *rtwtxq, 1965 unsigned long frame_cnt, 1966 unsigned long byte_cnt) 1967 { 1968 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1969 struct ieee80211_vif *vif = txq->vif; 1970 struct ieee80211_sta *sta = txq->sta; 1971 struct sk_buff *skb; 1972 unsigned long i; 1973 int ret; 1974 1975 rcu_read_lock(); 1976 for (i = 0; i < frame_cnt; i++) { 1977 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 1978 if (!skb) { 1979 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 1980 goto out; 1981 } 1982 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 1983 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 1984 if (ret) { 1985 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 1986 ieee80211_free_txskb(rtwdev->hw, skb); 1987 break; 1988 } 1989 } 1990 out: 1991 rcu_read_unlock(); 1992 } 1993 1994 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 1995 { 1996 u8 qsel, ch_dma; 1997 1998 qsel = rtw89_core_get_qsel(rtwdev, tid); 1999 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2000 2001 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2002 } 2003 2004 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2005 struct ieee80211_txq *txq, 2006 unsigned long *frame_cnt, 2007 bool *sched_txq, bool *reinvoke) 2008 { 2009 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2010 struct ieee80211_sta *sta = txq->sta; 2011 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2012 2013 if (!sta || rtwsta->max_agg_wait <= 0) 2014 return false; 2015 2016 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2017 return false; 2018 2019 if (*frame_cnt > 1) { 2020 *frame_cnt -= 1; 2021 *sched_txq = true; 2022 *reinvoke = true; 2023 rtwtxq->wait_cnt = 1; 2024 return false; 2025 } 2026 2027 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2028 *reinvoke = true; 2029 rtwtxq->wait_cnt++; 2030 return true; 2031 } 2032 2033 rtwtxq->wait_cnt = 0; 2034 return false; 2035 } 2036 2037 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2038 { 2039 struct ieee80211_hw *hw = rtwdev->hw; 2040 struct ieee80211_txq *txq; 2041 struct rtw89_txq *rtwtxq; 2042 unsigned long frame_cnt; 2043 unsigned long byte_cnt; 2044 u32 tx_resource; 2045 bool sched_txq; 2046 2047 ieee80211_txq_schedule_start(hw, ac); 2048 while ((txq = ieee80211_next_txq(hw, ac))) { 2049 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2050 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2051 sched_txq = false; 2052 2053 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2054 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2055 ieee80211_return_txq(hw, txq, true); 2056 continue; 2057 } 2058 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2059 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2060 ieee80211_return_txq(hw, txq, sched_txq); 2061 if (frame_cnt != 0) 2062 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2063 2064 /* bound of tx_resource could get stuck due to burst traffic */ 2065 if (frame_cnt == tx_resource) 2066 *reinvoke = true; 2067 } 2068 ieee80211_txq_schedule_end(hw, ac); 2069 } 2070 2071 static void rtw89_ips_work(struct work_struct *work) 2072 { 2073 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2074 ips_work); 2075 mutex_lock(&rtwdev->mutex); 2076 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 2077 rtw89_enter_ips(rtwdev); 2078 mutex_unlock(&rtwdev->mutex); 2079 } 2080 2081 static void rtw89_core_txq_work(struct work_struct *w) 2082 { 2083 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2084 bool reinvoke = false; 2085 u8 ac; 2086 2087 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2088 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2089 2090 if (reinvoke) { 2091 /* reinvoke to process the last frame */ 2092 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2093 } 2094 } 2095 2096 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2097 { 2098 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2099 txq_reinvoke_work.work); 2100 2101 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2102 } 2103 2104 static void rtw89_forbid_ba_work(struct work_struct *w) 2105 { 2106 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2107 forbid_ba_work.work); 2108 struct rtw89_txq *rtwtxq, *tmp; 2109 2110 spin_lock_bh(&rtwdev->ba_lock); 2111 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2112 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2113 list_del_init(&rtwtxq->list); 2114 } 2115 spin_unlock_bh(&rtwdev->ba_lock); 2116 } 2117 2118 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2119 u32 throughput, u64 cnt) 2120 { 2121 if (cnt < 100) 2122 return RTW89_TFC_IDLE; 2123 if (throughput > 50) 2124 return RTW89_TFC_HIGH; 2125 if (throughput > 10) 2126 return RTW89_TFC_MID; 2127 if (throughput > 2) 2128 return RTW89_TFC_LOW; 2129 return RTW89_TFC_ULTRA_LOW; 2130 } 2131 2132 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2133 struct rtw89_traffic_stats *stats) 2134 { 2135 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2136 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2137 2138 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2139 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2140 2141 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 2142 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 2143 2144 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 2145 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 2146 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 2147 stats->tx_cnt); 2148 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 2149 stats->rx_cnt); 2150 stats->tx_avg_len = stats->tx_cnt ? 2151 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 2152 stats->rx_avg_len = stats->rx_cnt ? 2153 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 2154 2155 stats->tx_unicast = 0; 2156 stats->rx_unicast = 0; 2157 stats->tx_cnt = 0; 2158 stats->rx_cnt = 0; 2159 stats->rx_tf_periodic = stats->rx_tf_acc; 2160 stats->rx_tf_acc = 0; 2161 2162 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 2163 return true; 2164 2165 return false; 2166 } 2167 2168 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 2169 { 2170 struct rtw89_vif *rtwvif; 2171 bool tfc_changed; 2172 2173 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 2174 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2175 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 2176 2177 return tfc_changed; 2178 } 2179 2180 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2181 { 2182 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2183 return; 2184 2185 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 2186 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 2187 rtw89_enter_lps(rtwdev, rtwvif->mac_id); 2188 } 2189 2190 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 2191 { 2192 struct rtw89_vif *rtwvif; 2193 2194 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2195 rtw89_vif_enter_lps(rtwdev, rtwvif); 2196 } 2197 2198 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 2199 struct rtw89_traffic_stats *stats) 2200 { 2201 stats->tx_unicast = 0; 2202 stats->rx_unicast = 0; 2203 stats->tx_cnt = 0; 2204 stats->rx_cnt = 0; 2205 ewma_tp_init(&stats->tx_ewma_tp); 2206 ewma_tp_init(&stats->rx_ewma_tp); 2207 } 2208 2209 static void rtw89_track_work(struct work_struct *work) 2210 { 2211 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2212 track_work.work); 2213 bool tfc_changed; 2214 2215 mutex_lock(&rtwdev->mutex); 2216 2217 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2218 goto out; 2219 2220 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2221 RTW89_TRACK_WORK_PERIOD); 2222 2223 tfc_changed = rtw89_traffic_stats_track(rtwdev); 2224 if (rtwdev->scanning) 2225 goto out; 2226 2227 rtw89_leave_lps(rtwdev); 2228 2229 if (tfc_changed) { 2230 rtw89_hci_recalc_int_mit(rtwdev); 2231 rtw89_btc_ntfy_wl_sta(rtwdev); 2232 } 2233 rtw89_mac_bf_monitor_track(rtwdev); 2234 rtw89_phy_stat_track(rtwdev); 2235 rtw89_phy_env_monitor_track(rtwdev); 2236 rtw89_phy_dig(rtwdev); 2237 rtw89_chip_rfk_track(rtwdev); 2238 rtw89_phy_ra_update(rtwdev); 2239 rtw89_phy_cfo_track(rtwdev); 2240 2241 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 2242 rtw89_enter_lps_track(rtwdev); 2243 2244 out: 2245 mutex_unlock(&rtwdev->mutex); 2246 } 2247 2248 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 2249 { 2250 unsigned long bit; 2251 2252 bit = find_first_zero_bit(addr, size); 2253 if (bit < size) 2254 set_bit(bit, addr); 2255 2256 return bit; 2257 } 2258 2259 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 2260 { 2261 clear_bit(bit, addr); 2262 } 2263 2264 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 2265 { 2266 bitmap_zero(addr, nbits); 2267 } 2268 2269 int rtw89_core_acquire_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2270 { 2271 struct rtw89_ba_cam_entry *entry; 2272 u8 idx; 2273 2274 idx = rtw89_core_acquire_bit_map(rtwsta->ba_cam_map, RTW89_BA_CAM_NUM); 2275 if (idx == RTW89_BA_CAM_NUM) { 2276 /* allocate a static BA CAM to tid=0, so replace the existing 2277 * one if BA CAM is full. Hardware will process the original tid 2278 * automatically. 2279 */ 2280 if (tid != 0) 2281 return -ENOSPC; 2282 2283 idx = 0; 2284 } 2285 2286 entry = &rtwsta->ba_cam_entry[idx]; 2287 entry->tid = tid; 2288 *cam_idx = idx; 2289 2290 return 0; 2291 } 2292 2293 int rtw89_core_release_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2294 { 2295 struct rtw89_ba_cam_entry *entry; 2296 int i; 2297 2298 for (i = 0; i < RTW89_BA_CAM_NUM; i++) { 2299 if (!test_bit(i, rtwsta->ba_cam_map)) 2300 continue; 2301 2302 entry = &rtwsta->ba_cam_entry[i]; 2303 if (entry->tid != tid) 2304 continue; 2305 2306 rtw89_core_release_bit_map(rtwsta->ba_cam_map, i); 2307 *cam_idx = i; 2308 return 0; 2309 } 2310 2311 return -ENOENT; 2312 } 2313 2314 #define RTW89_TYPE_MAPPING(_type) \ 2315 case NL80211_IFTYPE_ ## _type: \ 2316 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 2317 break 2318 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 2319 { 2320 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2321 2322 switch (vif->type) { 2323 RTW89_TYPE_MAPPING(ADHOC); 2324 RTW89_TYPE_MAPPING(STATION); 2325 RTW89_TYPE_MAPPING(AP); 2326 RTW89_TYPE_MAPPING(MONITOR); 2327 RTW89_TYPE_MAPPING(MESH_POINT); 2328 default: 2329 WARN_ON(1); 2330 break; 2331 } 2332 2333 switch (vif->type) { 2334 case NL80211_IFTYPE_AP: 2335 case NL80211_IFTYPE_MESH_POINT: 2336 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 2337 rtwvif->self_role = RTW89_SELF_ROLE_AP; 2338 break; 2339 case NL80211_IFTYPE_ADHOC: 2340 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 2341 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2342 break; 2343 case NL80211_IFTYPE_STATION: 2344 if (assoc) { 2345 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 2346 rtwvif->trigger = vif->bss_conf.he_support; 2347 } else { 2348 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 2349 rtwvif->trigger = false; 2350 } 2351 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2352 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 2353 break; 2354 default: 2355 WARN_ON(1); 2356 break; 2357 } 2358 } 2359 2360 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 2361 struct ieee80211_vif *vif, 2362 struct ieee80211_sta *sta) 2363 { 2364 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2365 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2366 int i; 2367 2368 rtwsta->rtwvif = rtwvif; 2369 rtwsta->prev_rssi = 0; 2370 2371 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 2372 rtw89_core_txq_init(rtwdev, sta->txq[i]); 2373 2374 ewma_rssi_init(&rtwsta->avg_rssi); 2375 2376 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2377 /* for station mode, assign the mac_id from itself */ 2378 rtwsta->mac_id = rtwvif->mac_id; 2379 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2380 BTC_ROLE_MSTS_STA_CONN_START); 2381 rtw89_chip_rfk_channel(rtwdev); 2382 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2383 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 2384 RTW89_MAX_MAC_ID_NUM); 2385 } 2386 2387 return 0; 2388 } 2389 2390 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 2391 struct ieee80211_vif *vif, 2392 struct ieee80211_sta *sta) 2393 { 2394 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2395 2396 rtwdev->total_sta_assoc--; 2397 rtwsta->disassoc = true; 2398 2399 return 0; 2400 } 2401 2402 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 2403 struct ieee80211_vif *vif, 2404 struct ieee80211_sta *sta) 2405 { 2406 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2407 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2408 int ret; 2409 2410 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 2411 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 2412 rtw89_core_free_sta_pending_ba(rtwdev, sta); 2413 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 2414 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2415 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 2416 if (sta->tdls) 2417 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 2418 2419 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2420 rtw89_vif_type_mapping(vif, false); 2421 2422 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2423 if (ret) { 2424 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2425 return ret; 2426 } 2427 2428 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 2429 if (ret) { 2430 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2431 return ret; 2432 } 2433 2434 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2435 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_REMOVE); 2436 if (ret) { 2437 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2438 return ret; 2439 } 2440 } 2441 2442 /* update cam aid mac_id net_type */ 2443 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2444 if (ret) { 2445 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2446 return ret; 2447 } 2448 2449 return ret; 2450 } 2451 2452 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 2453 struct ieee80211_vif *vif, 2454 struct ieee80211_sta *sta) 2455 { 2456 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2457 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2458 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 2459 int ret; 2460 2461 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2462 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 2463 if (ret) { 2464 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 2465 return ret; 2466 } 2467 2468 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_CREATE); 2469 if (ret) { 2470 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2471 return ret; 2472 } 2473 2474 if (sta->tdls) { 2475 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 2476 if (ret) { 2477 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 2478 return ret; 2479 } 2480 } 2481 2482 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 2483 if (ret) { 2484 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 2485 return ret; 2486 } 2487 } 2488 2489 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2490 if (ret) { 2491 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2492 return ret; 2493 } 2494 2495 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 2496 if (ret) { 2497 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2498 return ret; 2499 } 2500 2501 /* update cam aid mac_id net_type */ 2502 rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2503 if (ret) { 2504 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2505 return ret; 2506 } 2507 2508 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwsta->mac_id); 2509 if (ret) { 2510 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 2511 return ret; 2512 } 2513 2514 rtwdev->total_sta_assoc++; 2515 rtw89_phy_ra_assoc(rtwdev, sta); 2516 rtw89_mac_bf_assoc(rtwdev, vif, sta); 2517 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 2518 2519 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2520 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2521 BTC_ROLE_MSTS_STA_CONN_END); 2522 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); 2523 } 2524 2525 return ret; 2526 } 2527 2528 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 2529 struct ieee80211_vif *vif, 2530 struct ieee80211_sta *sta) 2531 { 2532 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2533 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2534 2535 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2536 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2537 BTC_ROLE_MSTS_STA_DIS_CONN); 2538 else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2539 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2540 2541 return 0; 2542 } 2543 2544 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 2545 struct ieee80211_sta_ht_cap *ht_cap) 2546 { 2547 static const __le16 highest[RF_PATH_MAX] = { 2548 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 2549 }; 2550 struct rtw89_hal *hal = &rtwdev->hal; 2551 u8 nss = hal->rx_nss; 2552 int i; 2553 2554 ht_cap->ht_supported = true; 2555 ht_cap->cap = 0; 2556 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 2557 IEEE80211_HT_CAP_MAX_AMSDU | 2558 IEEE80211_HT_CAP_TX_STBC | 2559 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 2560 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 2561 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 2562 IEEE80211_HT_CAP_DSSSCCK40 | 2563 IEEE80211_HT_CAP_SGI_40; 2564 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 2565 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 2566 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 2567 for (i = 0; i < nss; i++) 2568 ht_cap->mcs.rx_mask[i] = 0xFF; 2569 ht_cap->mcs.rx_mask[4] = 0x01; 2570 ht_cap->mcs.rx_highest = highest[nss - 1]; 2571 } 2572 2573 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 2574 struct ieee80211_sta_vht_cap *vht_cap) 2575 { 2576 static const __le16 highest_bw80[RF_PATH_MAX] = { 2577 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 2578 }; 2579 static const __le16 highest_bw160[RF_PATH_MAX] = { 2580 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 2581 }; 2582 const struct rtw89_chip_info *chip = rtwdev->chip; 2583 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 2584 struct rtw89_hal *hal = &rtwdev->hal; 2585 u16 tx_mcs_map = 0, rx_mcs_map = 0; 2586 u8 sts_cap = 3; 2587 int i; 2588 2589 for (i = 0; i < 8; i++) { 2590 if (i < hal->tx_nss) 2591 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2592 else 2593 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2594 if (i < hal->rx_nss) 2595 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2596 else 2597 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2598 } 2599 2600 vht_cap->vht_supported = true; 2601 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 2602 IEEE80211_VHT_CAP_SHORT_GI_80 | 2603 IEEE80211_VHT_CAP_RXSTBC_1 | 2604 IEEE80211_VHT_CAP_HTC_VHT | 2605 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 2606 0; 2607 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 2608 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 2609 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 2610 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 2611 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 2612 if (chip->support_bw160) 2613 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 2614 IEEE80211_VHT_CAP_SHORT_GI_160; 2615 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 2616 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 2617 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 2618 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 2619 } 2620 2621 #define RTW89_SBAND_IFTYPES_NR 2 2622 2623 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 2624 enum nl80211_band band, 2625 struct ieee80211_supported_band *sband) 2626 { 2627 const struct rtw89_chip_info *chip = rtwdev->chip; 2628 struct rtw89_hal *hal = &rtwdev->hal; 2629 struct ieee80211_sband_iftype_data *iftype_data; 2630 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 2631 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 2632 u16 mcs_map = 0; 2633 int i; 2634 int nss = hal->rx_nss; 2635 int idx = 0; 2636 2637 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 2638 if (!iftype_data) 2639 return; 2640 2641 for (i = 0; i < 8; i++) { 2642 if (i < nss) 2643 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 2644 else 2645 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 2646 } 2647 2648 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 2649 struct ieee80211_sta_he_cap *he_cap; 2650 u8 *mac_cap_info; 2651 u8 *phy_cap_info; 2652 2653 switch (i) { 2654 case NL80211_IFTYPE_STATION: 2655 case NL80211_IFTYPE_AP: 2656 break; 2657 default: 2658 continue; 2659 } 2660 2661 if (idx >= RTW89_SBAND_IFTYPES_NR) { 2662 rtw89_warn(rtwdev, "run out of iftype_data\n"); 2663 break; 2664 } 2665 2666 iftype_data[idx].types_mask = BIT(i); 2667 he_cap = &iftype_data[idx].he_cap; 2668 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 2669 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 2670 2671 he_cap->has_he = true; 2672 if (i == NL80211_IFTYPE_AP) 2673 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 2674 if (i == NL80211_IFTYPE_STATION) 2675 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 2676 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 2677 IEEE80211_HE_MAC_CAP2_BSR; 2678 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 2679 if (i == NL80211_IFTYPE_AP) 2680 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 2681 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 2682 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 2683 if (i == NL80211_IFTYPE_STATION) 2684 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 2685 if (band == NL80211_BAND_2GHZ) { 2686 phy_cap_info[0] = 2687 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 2688 } else { 2689 phy_cap_info[0] = 2690 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 2691 if (chip->support_bw160) 2692 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 2693 } 2694 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 2695 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 2696 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 2697 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 2698 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 2699 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 2700 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 2701 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 2702 if (i == NL80211_IFTYPE_STATION) 2703 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 2704 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 2705 if (i == NL80211_IFTYPE_AP) 2706 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 2707 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 2708 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 2709 phy_cap_info[5] = no_ng16 ? 0 : 2710 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 2711 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 2712 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 2713 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 2714 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 2715 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 2716 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 2717 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 2718 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 2719 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 2720 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 2721 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 2722 if (chip->support_bw160) 2723 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 2724 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 2725 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 2726 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 2727 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 2728 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 2729 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 2730 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 2731 if (i == NL80211_IFTYPE_STATION) 2732 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 2733 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 2734 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 2735 if (chip->support_bw160) { 2736 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 2737 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 2738 } 2739 2740 if (band == NL80211_BAND_6GHZ) { 2741 __le16 capa; 2742 2743 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 2744 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 2745 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 2746 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 2747 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 2748 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 2749 iftype_data[idx].he_6ghz_capa.capa = capa; 2750 } 2751 2752 idx++; 2753 } 2754 2755 sband->iftype_data = iftype_data; 2756 sband->n_iftype_data = idx; 2757 } 2758 2759 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 2760 { 2761 struct ieee80211_hw *hw = rtwdev->hw; 2762 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 2763 struct ieee80211_supported_band *sband_6ghz = NULL; 2764 u32 size = sizeof(struct ieee80211_supported_band); 2765 u8 support_bands = rtwdev->chip->support_bands; 2766 2767 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 2768 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 2769 if (!sband_2ghz) 2770 goto err; 2771 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 2772 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 2773 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 2774 } 2775 2776 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 2777 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 2778 if (!sband_5ghz) 2779 goto err; 2780 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 2781 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 2782 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 2783 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 2784 } 2785 2786 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 2787 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 2788 if (!sband_6ghz) 2789 goto err; 2790 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 2791 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 2792 } 2793 2794 return 0; 2795 2796 err: 2797 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2798 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2799 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2800 if (sband_2ghz) 2801 kfree(sband_2ghz->iftype_data); 2802 if (sband_5ghz) 2803 kfree(sband_5ghz->iftype_data); 2804 if (sband_6ghz) 2805 kfree(sband_6ghz->iftype_data); 2806 kfree(sband_2ghz); 2807 kfree(sband_5ghz); 2808 kfree(sband_6ghz); 2809 return -ENOMEM; 2810 } 2811 2812 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 2813 { 2814 struct ieee80211_hw *hw = rtwdev->hw; 2815 2816 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 2817 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 2818 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 2819 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 2820 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 2821 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 2822 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 2823 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2824 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2825 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2826 } 2827 2828 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 2829 { 2830 int i; 2831 2832 for (i = 0; i < RTW89_PHY_MAX; i++) 2833 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 2834 for (i = 0; i < RTW89_PHY_MAX; i++) 2835 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 2836 } 2837 2838 void rtw89_core_update_beacon_work(struct work_struct *work) 2839 { 2840 struct rtw89_dev *rtwdev; 2841 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2842 update_beacon_work); 2843 2844 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 2845 return; 2846 2847 rtwdev = rtwvif->rtwdev; 2848 mutex_lock(&rtwdev->mutex); 2849 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 2850 mutex_unlock(&rtwdev->mutex); 2851 } 2852 2853 int rtw89_core_start(struct rtw89_dev *rtwdev) 2854 { 2855 int ret; 2856 2857 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 2858 ret = rtw89_mac_init(rtwdev); 2859 if (ret) { 2860 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 2861 return ret; 2862 } 2863 2864 rtw89_btc_ntfy_poweron(rtwdev); 2865 2866 /* efuse process */ 2867 2868 /* pre-config BB/RF, BB reset/RFC reset */ 2869 rtw89_chip_disable_bb_rf(rtwdev); 2870 ret = rtw89_chip_enable_bb_rf(rtwdev); 2871 if (ret) 2872 return ret; 2873 2874 rtw89_phy_init_bb_reg(rtwdev); 2875 rtw89_phy_init_rf_reg(rtwdev); 2876 2877 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 2878 2879 rtw89_phy_dm_init(rtwdev); 2880 2881 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 2882 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 2883 2884 ret = rtw89_hci_start(rtwdev); 2885 if (ret) { 2886 rtw89_err(rtwdev, "failed to start hci\n"); 2887 return ret; 2888 } 2889 2890 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2891 RTW89_TRACK_WORK_PERIOD); 2892 2893 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 2894 2895 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 2896 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); 2897 2898 return 0; 2899 } 2900 2901 void rtw89_core_stop(struct rtw89_dev *rtwdev) 2902 { 2903 struct rtw89_btc *btc = &rtwdev->btc; 2904 2905 /* Prvent to stop twice; enter_ips and ops_stop */ 2906 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2907 return; 2908 2909 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 2910 2911 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 2912 2913 mutex_unlock(&rtwdev->mutex); 2914 2915 cancel_work_sync(&rtwdev->c2h_work); 2916 cancel_work_sync(&btc->eapol_notify_work); 2917 cancel_work_sync(&btc->arp_notify_work); 2918 cancel_work_sync(&btc->dhcp_notify_work); 2919 cancel_work_sync(&btc->icmp_notify_work); 2920 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 2921 cancel_delayed_work_sync(&rtwdev->track_work); 2922 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 2923 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 2924 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 2925 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 2926 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 2927 2928 mutex_lock(&rtwdev->mutex); 2929 2930 rtw89_btc_ntfy_poweroff(rtwdev); 2931 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 2932 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 2933 rtw89_hci_stop(rtwdev); 2934 rtw89_hci_deinit(rtwdev); 2935 rtw89_mac_pwr_off(rtwdev); 2936 rtw89_hci_reset(rtwdev); 2937 } 2938 2939 int rtw89_core_init(struct rtw89_dev *rtwdev) 2940 { 2941 struct rtw89_btc *btc = &rtwdev->btc; 2942 int ret; 2943 u8 band; 2944 2945 INIT_LIST_HEAD(&rtwdev->ba_list); 2946 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 2947 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 2948 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 2949 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 2950 if (!(rtwdev->chip->support_bands & BIT(band))) 2951 continue; 2952 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 2953 } 2954 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 2955 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 2956 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 2957 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 2958 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 2959 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 2960 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 2961 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 2962 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 2963 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2964 spin_lock_init(&rtwdev->ba_lock); 2965 spin_lock_init(&rtwdev->rpwm_lock); 2966 mutex_init(&rtwdev->mutex); 2967 mutex_init(&rtwdev->rf_mutex); 2968 rtwdev->total_sta_assoc = 0; 2969 2970 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 2971 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 2972 skb_queue_head_init(&rtwdev->c2h_queue); 2973 rtw89_core_ppdu_sts_init(rtwdev); 2974 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 2975 2976 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 2977 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 2978 2979 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 2980 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 2981 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 2982 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 2983 2984 ret = rtw89_load_firmware(rtwdev); 2985 if (ret) { 2986 rtw89_warn(rtwdev, "no firmware loaded\n"); 2987 return ret; 2988 } 2989 rtw89_ser_init(rtwdev); 2990 2991 return 0; 2992 } 2993 EXPORT_SYMBOL(rtw89_core_init); 2994 2995 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 2996 { 2997 rtw89_ser_deinit(rtwdev); 2998 rtw89_unload_firmware(rtwdev); 2999 rtw89_fw_free_all_early_h2c(rtwdev); 3000 3001 destroy_workqueue(rtwdev->txq_wq); 3002 mutex_destroy(&rtwdev->rf_mutex); 3003 mutex_destroy(&rtwdev->mutex); 3004 } 3005 EXPORT_SYMBOL(rtw89_core_deinit); 3006 3007 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3008 const u8 *mac_addr, bool hw_scan) 3009 { 3010 struct rtw89_hal *hal = &rtwdev->hal; 3011 3012 rtwdev->scanning = true; 3013 rtw89_leave_lps(rtwdev); 3014 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3015 rtw89_leave_ips(rtwdev); 3016 3017 ether_addr_copy(rtwvif->mac_addr, mac_addr); 3018 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, hal->current_band_type); 3019 rtw89_chip_rfk_scan(rtwdev, true); 3020 rtw89_hci_recalc_int_mit(rtwdev); 3021 3022 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 3023 } 3024 3025 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3026 struct ieee80211_vif *vif, bool hw_scan) 3027 { 3028 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3029 3030 if (!rtwvif) 3031 return; 3032 3033 ether_addr_copy(rtwvif->mac_addr, vif->addr); 3034 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3035 3036 rtw89_chip_rfk_scan(rtwdev, false); 3037 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 3038 3039 rtwdev->scanning = false; 3040 rtwdev->dig.bypass_dig = true; 3041 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3042 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 3043 } 3044 3045 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 3046 { 3047 const struct rtw89_chip_info *chip = rtwdev->chip; 3048 u8 cv; 3049 3050 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 3051 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 3052 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 3053 cv = CHIP_CAV; 3054 else 3055 cv = CHIP_CBV; 3056 } 3057 3058 rtwdev->hal.cv = cv; 3059 } 3060 3061 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 3062 { 3063 rtwdev->hal.support_cckpd = 3064 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 3065 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 3066 rtwdev->hal.support_igi = 3067 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 3068 } 3069 3070 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 3071 { 3072 int ret; 3073 3074 ret = rtw89_mac_partial_init(rtwdev); 3075 if (ret) 3076 return ret; 3077 3078 ret = rtw89_parse_efuse_map(rtwdev); 3079 if (ret) 3080 return ret; 3081 3082 ret = rtw89_parse_phycap_map(rtwdev); 3083 if (ret) 3084 return ret; 3085 3086 ret = rtw89_mac_setup_phycap(rtwdev); 3087 if (ret) 3088 return ret; 3089 3090 rtw89_core_setup_phycap(rtwdev); 3091 3092 rtw89_mac_pwr_off(rtwdev); 3093 3094 return 0; 3095 } 3096 3097 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 3098 { 3099 rtw89_chip_fem_setup(rtwdev); 3100 3101 return 0; 3102 } 3103 3104 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 3105 { 3106 int ret; 3107 3108 rtw89_read_chip_ver(rtwdev); 3109 3110 ret = rtw89_wait_firmware_completion(rtwdev); 3111 if (ret) { 3112 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 3113 return ret; 3114 } 3115 3116 ret = rtw89_fw_recognize(rtwdev); 3117 if (ret) { 3118 rtw89_err(rtwdev, "failed to recognize firmware\n"); 3119 return ret; 3120 } 3121 3122 ret = rtw89_chip_efuse_info_setup(rtwdev); 3123 if (ret) 3124 return ret; 3125 3126 ret = rtw89_chip_board_info_setup(rtwdev); 3127 if (ret) 3128 return ret; 3129 3130 return 0; 3131 } 3132 EXPORT_SYMBOL(rtw89_chip_info_setup); 3133 3134 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 3135 { 3136 struct ieee80211_hw *hw = rtwdev->hw; 3137 struct rtw89_efuse *efuse = &rtwdev->efuse; 3138 int ret; 3139 int tx_headroom = IEEE80211_HT_CTL_LEN; 3140 3141 hw->vif_data_size = sizeof(struct rtw89_vif); 3142 hw->sta_data_size = sizeof(struct rtw89_sta); 3143 hw->txq_data_size = sizeof(struct rtw89_txq); 3144 3145 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 3146 3147 hw->extra_tx_headroom = tx_headroom; 3148 hw->queues = IEEE80211_NUM_ACS; 3149 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 3150 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 3151 3152 ieee80211_hw_set(hw, SIGNAL_DBM); 3153 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 3154 ieee80211_hw_set(hw, MFP_CAPABLE); 3155 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 3156 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 3157 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 3158 ieee80211_hw_set(hw, TX_AMSDU); 3159 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 3160 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 3161 ieee80211_hw_set(hw, SUPPORTS_PS); 3162 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 3163 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 3164 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 3165 3166 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 3167 BIT(NL80211_IFTYPE_AP); 3168 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 3169 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 3170 3171 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 3172 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 3173 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 3174 3175 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 3176 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 3177 3178 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 3179 3180 ret = rtw89_core_set_supported_band(rtwdev); 3181 if (ret) { 3182 rtw89_err(rtwdev, "failed to set supported band\n"); 3183 return ret; 3184 } 3185 3186 hw->wiphy->reg_notifier = rtw89_regd_notifier; 3187 hw->wiphy->sar_capa = &rtw89_sar_capa; 3188 3189 ret = ieee80211_register_hw(hw); 3190 if (ret) { 3191 rtw89_err(rtwdev, "failed to register hw\n"); 3192 goto err; 3193 } 3194 3195 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 3196 if (ret) { 3197 rtw89_err(rtwdev, "failed to init regd\n"); 3198 goto err; 3199 } 3200 3201 return 0; 3202 3203 err: 3204 return ret; 3205 } 3206 3207 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 3208 { 3209 struct ieee80211_hw *hw = rtwdev->hw; 3210 3211 ieee80211_unregister_hw(hw); 3212 rtw89_core_clr_supported_band(rtwdev); 3213 } 3214 3215 int rtw89_core_register(struct rtw89_dev *rtwdev) 3216 { 3217 int ret; 3218 3219 ret = rtw89_core_register_hw(rtwdev); 3220 if (ret) { 3221 rtw89_err(rtwdev, "failed to register core hw\n"); 3222 return ret; 3223 } 3224 3225 rtw89_debugfs_init(rtwdev); 3226 3227 return 0; 3228 } 3229 EXPORT_SYMBOL(rtw89_core_register); 3230 3231 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 3232 { 3233 rtw89_core_unregister_hw(rtwdev); 3234 } 3235 EXPORT_SYMBOL(rtw89_core_unregister); 3236 3237 MODULE_AUTHOR("Realtek Corporation"); 3238 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 3239 MODULE_LICENSE("Dual BSD/GPL"); 3240