1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 }; 81 82 static struct ieee80211_channel rtw89_channels_6ghz[] = { 83 RTW89_DEF_CHAN_6G(5955, 1), 84 RTW89_DEF_CHAN_6G(5975, 5), 85 RTW89_DEF_CHAN_6G(5995, 9), 86 RTW89_DEF_CHAN_6G(6015, 13), 87 RTW89_DEF_CHAN_6G(6035, 17), 88 RTW89_DEF_CHAN_6G(6055, 21), 89 RTW89_DEF_CHAN_6G(6075, 25), 90 RTW89_DEF_CHAN_6G(6095, 29), 91 RTW89_DEF_CHAN_6G(6115, 33), 92 RTW89_DEF_CHAN_6G(6135, 37), 93 RTW89_DEF_CHAN_6G(6155, 41), 94 RTW89_DEF_CHAN_6G(6175, 45), 95 RTW89_DEF_CHAN_6G(6195, 49), 96 RTW89_DEF_CHAN_6G(6215, 53), 97 RTW89_DEF_CHAN_6G(6235, 57), 98 RTW89_DEF_CHAN_6G(6255, 61), 99 RTW89_DEF_CHAN_6G(6275, 65), 100 RTW89_DEF_CHAN_6G(6295, 69), 101 RTW89_DEF_CHAN_6G(6315, 73), 102 RTW89_DEF_CHAN_6G(6335, 77), 103 RTW89_DEF_CHAN_6G(6355, 81), 104 RTW89_DEF_CHAN_6G(6375, 85), 105 RTW89_DEF_CHAN_6G(6395, 89), 106 RTW89_DEF_CHAN_6G(6415, 93), 107 RTW89_DEF_CHAN_6G(6435, 97), 108 RTW89_DEF_CHAN_6G(6455, 101), 109 RTW89_DEF_CHAN_6G(6475, 105), 110 RTW89_DEF_CHAN_6G(6495, 109), 111 RTW89_DEF_CHAN_6G(6515, 113), 112 RTW89_DEF_CHAN_6G(6535, 117), 113 RTW89_DEF_CHAN_6G(6555, 121), 114 RTW89_DEF_CHAN_6G(6575, 125), 115 RTW89_DEF_CHAN_6G(6595, 129), 116 RTW89_DEF_CHAN_6G(6615, 133), 117 RTW89_DEF_CHAN_6G(6635, 137), 118 RTW89_DEF_CHAN_6G(6655, 141), 119 RTW89_DEF_CHAN_6G(6675, 145), 120 RTW89_DEF_CHAN_6G(6695, 149), 121 RTW89_DEF_CHAN_6G(6715, 153), 122 RTW89_DEF_CHAN_6G(6735, 157), 123 RTW89_DEF_CHAN_6G(6755, 161), 124 RTW89_DEF_CHAN_6G(6775, 165), 125 RTW89_DEF_CHAN_6G(6795, 169), 126 RTW89_DEF_CHAN_6G(6815, 173), 127 RTW89_DEF_CHAN_6G(6835, 177), 128 RTW89_DEF_CHAN_6G(6855, 181), 129 RTW89_DEF_CHAN_6G(6875, 185), 130 RTW89_DEF_CHAN_6G(6895, 189), 131 RTW89_DEF_CHAN_6G(6915, 193), 132 RTW89_DEF_CHAN_6G(6935, 197), 133 RTW89_DEF_CHAN_6G(6955, 201), 134 RTW89_DEF_CHAN_6G(6975, 205), 135 RTW89_DEF_CHAN_6G(6995, 209), 136 RTW89_DEF_CHAN_6G(7015, 213), 137 RTW89_DEF_CHAN_6G(7035, 217), 138 RTW89_DEF_CHAN_6G(7055, 221), 139 RTW89_DEF_CHAN_6G(7075, 225), 140 RTW89_DEF_CHAN_6G(7095, 229), 141 RTW89_DEF_CHAN_6G(7115, 233), 142 }; 143 144 static struct ieee80211_rate rtw89_bitrates[] = { 145 { .bitrate = 10, .hw_value = 0x00, }, 146 { .bitrate = 20, .hw_value = 0x01, }, 147 { .bitrate = 55, .hw_value = 0x02, }, 148 { .bitrate = 110, .hw_value = 0x03, }, 149 { .bitrate = 60, .hw_value = 0x04, }, 150 { .bitrate = 90, .hw_value = 0x05, }, 151 { .bitrate = 120, .hw_value = 0x06, }, 152 { .bitrate = 180, .hw_value = 0x07, }, 153 { .bitrate = 240, .hw_value = 0x08, }, 154 { .bitrate = 360, .hw_value = 0x09, }, 155 { .bitrate = 480, .hw_value = 0x0a, }, 156 { .bitrate = 540, .hw_value = 0x0b, }, 157 }; 158 159 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 160 { 161 struct ieee80211_rate rate; 162 163 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 164 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 165 return false; 166 } 167 168 rate = rtw89_bitrates[rpt_rate]; 169 *bitrate = rate.bitrate; 170 171 return true; 172 } 173 174 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 175 .band = NL80211_BAND_2GHZ, 176 .channels = rtw89_channels_2ghz, 177 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 178 .bitrates = rtw89_bitrates, 179 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 180 .ht_cap = {0}, 181 .vht_cap = {0}, 182 }; 183 184 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 185 .band = NL80211_BAND_5GHZ, 186 .channels = rtw89_channels_5ghz, 187 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 188 189 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 190 .bitrates = rtw89_bitrates + 4, 191 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 192 .ht_cap = {0}, 193 .vht_cap = {0}, 194 }; 195 196 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 197 .band = NL80211_BAND_6GHZ, 198 .channels = rtw89_channels_6ghz, 199 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 200 201 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 202 .bitrates = rtw89_bitrates + 4, 203 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 204 }; 205 206 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 207 struct rtw89_traffic_stats *stats, 208 struct sk_buff *skb, bool tx) 209 { 210 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 211 212 if (!ieee80211_is_data(hdr->frame_control)) 213 return; 214 215 if (is_broadcast_ether_addr(hdr->addr1) || 216 is_multicast_ether_addr(hdr->addr1)) 217 return; 218 219 if (tx) { 220 stats->tx_cnt++; 221 stats->tx_unicast += skb->len; 222 } else { 223 stats->rx_cnt++; 224 stats->rx_unicast += skb->len; 225 } 226 } 227 228 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 229 { 230 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 231 NL80211_CHAN_NO_HT); 232 } 233 234 static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 235 struct rtw89_chan *chan) 236 { 237 struct ieee80211_channel *channel = chandef->chan; 238 enum nl80211_chan_width width = chandef->width; 239 u32 primary_freq, center_freq; 240 u8 center_chan; 241 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 242 u32 offset; 243 u8 band; 244 245 center_chan = channel->hw_value; 246 primary_freq = channel->center_freq; 247 center_freq = chandef->center_freq1; 248 249 switch (width) { 250 case NL80211_CHAN_WIDTH_20_NOHT: 251 case NL80211_CHAN_WIDTH_20: 252 bandwidth = RTW89_CHANNEL_WIDTH_20; 253 break; 254 case NL80211_CHAN_WIDTH_40: 255 bandwidth = RTW89_CHANNEL_WIDTH_40; 256 if (primary_freq > center_freq) { 257 center_chan -= 2; 258 } else { 259 center_chan += 2; 260 } 261 break; 262 case NL80211_CHAN_WIDTH_80: 263 case NL80211_CHAN_WIDTH_160: 264 bandwidth = nl_to_rtw89_bandwidth(width); 265 if (primary_freq > center_freq) { 266 offset = (primary_freq - center_freq - 10) / 20; 267 center_chan -= 2 + offset * 4; 268 } else { 269 offset = (center_freq - primary_freq - 10) / 20; 270 center_chan += 2 + offset * 4; 271 } 272 break; 273 default: 274 center_chan = 0; 275 break; 276 } 277 278 switch (channel->band) { 279 default: 280 case NL80211_BAND_2GHZ: 281 band = RTW89_BAND_2G; 282 break; 283 case NL80211_BAND_5GHZ: 284 band = RTW89_BAND_5G; 285 break; 286 case NL80211_BAND_6GHZ: 287 band = RTW89_BAND_6G; 288 break; 289 } 290 291 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 292 } 293 294 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 295 { 296 const struct rtw89_chip_info *chip = rtwdev->chip; 297 const struct rtw89_chan *chan; 298 enum rtw89_sub_entity_idx sub_entity_idx; 299 enum rtw89_phy_idx phy_idx; 300 enum rtw89_entity_mode mode; 301 bool entity_active; 302 303 entity_active = rtw89_get_entity_state(rtwdev); 304 if (!entity_active) 305 return; 306 307 mode = rtw89_get_entity_mode(rtwdev); 308 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 309 return; 310 311 sub_entity_idx = RTW89_SUB_ENTITY_0; 312 phy_idx = RTW89_PHY_0; 313 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 314 if (chip->ops->set_txpwr) 315 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 316 } 317 318 void rtw89_set_channel(struct rtw89_dev *rtwdev) 319 { 320 const struct rtw89_chip_info *chip = rtwdev->chip; 321 const struct cfg80211_chan_def *chandef; 322 enum rtw89_sub_entity_idx sub_entity_idx; 323 enum rtw89_mac_idx mac_idx; 324 enum rtw89_phy_idx phy_idx; 325 struct rtw89_chan chan; 326 struct rtw89_channel_help_params bak; 327 enum rtw89_entity_mode mode; 328 bool band_changed; 329 bool entity_active; 330 331 entity_active = rtw89_get_entity_state(rtwdev); 332 333 mode = rtw89_entity_recalc(rtwdev); 334 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 335 return; 336 337 sub_entity_idx = RTW89_SUB_ENTITY_0; 338 mac_idx = RTW89_MAC_0; 339 phy_idx = RTW89_PHY_0; 340 chandef = rtw89_chandef_get(rtwdev, sub_entity_idx); 341 rtw89_get_channel_params(chandef, &chan); 342 if (WARN(chan.channel == 0, "Invalid channel\n")) 343 return; 344 345 band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan); 346 347 rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx); 348 349 chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx); 350 351 rtw89_core_set_chip_txpwr(rtwdev); 352 353 rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx); 354 355 if (!entity_active || band_changed) { 356 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type); 357 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 358 } 359 360 rtw89_set_entity_state(rtwdev, true); 361 } 362 363 static enum rtw89_core_tx_type 364 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 365 struct sk_buff *skb) 366 { 367 struct ieee80211_hdr *hdr = (void *)skb->data; 368 __le16 fc = hdr->frame_control; 369 370 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 371 return RTW89_CORE_TX_TYPE_MGMT; 372 373 return RTW89_CORE_TX_TYPE_DATA; 374 } 375 376 static void 377 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 378 struct rtw89_core_tx_request *tx_req, 379 enum btc_pkt_type pkt_type) 380 { 381 struct ieee80211_sta *sta = tx_req->sta; 382 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 383 struct sk_buff *skb = tx_req->skb; 384 struct rtw89_sta *rtwsta; 385 u8 ampdu_num; 386 u8 tid; 387 388 if (pkt_type == PACKET_EAPOL) { 389 desc_info->bk = true; 390 return; 391 } 392 393 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 394 return; 395 396 if (!sta) { 397 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 398 return; 399 } 400 401 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 402 rtwsta = (struct rtw89_sta *)sta->drv_priv; 403 404 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 405 rtwsta->ampdu_params[tid].agg_num : 406 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 407 408 desc_info->agg_en = true; 409 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 410 desc_info->ampdu_num = ampdu_num; 411 } 412 413 static void 414 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 415 struct rtw89_core_tx_request *tx_req) 416 { 417 const struct rtw89_chip_info *chip = rtwdev->chip; 418 struct ieee80211_vif *vif = tx_req->vif; 419 struct ieee80211_sta *sta = tx_req->sta; 420 struct ieee80211_tx_info *info; 421 struct ieee80211_key_conf *key; 422 struct rtw89_vif *rtwvif; 423 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 424 struct rtw89_addr_cam_entry *addr_cam; 425 struct rtw89_sec_cam_entry *sec_cam; 426 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 427 struct sk_buff *skb = tx_req->skb; 428 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 429 u64 pn64; 430 431 if (!vif) { 432 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 433 return; 434 } 435 436 rtwvif = (struct rtw89_vif *)vif->drv_priv; 437 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 438 439 info = IEEE80211_SKB_CB(skb); 440 key = info->control.hw_key; 441 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 442 if (!sec_cam) { 443 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 444 return; 445 } 446 447 switch (key->cipher) { 448 case WLAN_CIPHER_SUITE_WEP40: 449 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 450 break; 451 case WLAN_CIPHER_SUITE_WEP104: 452 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 453 break; 454 case WLAN_CIPHER_SUITE_TKIP: 455 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 456 break; 457 case WLAN_CIPHER_SUITE_CCMP: 458 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 459 break; 460 case WLAN_CIPHER_SUITE_CCMP_256: 461 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 462 break; 463 case WLAN_CIPHER_SUITE_GCMP: 464 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 465 break; 466 case WLAN_CIPHER_SUITE_GCMP_256: 467 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 468 break; 469 default: 470 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 471 return; 472 } 473 474 desc_info->sec_en = true; 475 desc_info->sec_keyid = key->keyidx; 476 desc_info->sec_type = sec_type; 477 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 478 479 if (!chip->hw_sec_hdr) 480 return; 481 482 pn64 = atomic64_inc_return(&key->tx_pn); 483 desc_info->sec_seq[0] = pn64; 484 desc_info->sec_seq[1] = pn64 >> 8; 485 desc_info->sec_seq[2] = pn64 >> 16; 486 desc_info->sec_seq[3] = pn64 >> 24; 487 desc_info->sec_seq[4] = pn64 >> 32; 488 desc_info->sec_seq[5] = pn64 >> 40; 489 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 490 } 491 492 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 493 struct rtw89_core_tx_request *tx_req) 494 { 495 struct sk_buff *skb = tx_req->skb; 496 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 497 struct ieee80211_vif *vif = tx_info->control.vif; 498 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 499 u16 lowest_rate; 500 501 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || vif->p2p) 502 lowest_rate = RTW89_HW_RATE_OFDM6; 503 else if (chan->band_type == RTW89_BAND_2G) 504 lowest_rate = RTW89_HW_RATE_CCK1; 505 else 506 lowest_rate = RTW89_HW_RATE_OFDM6; 507 508 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 509 return lowest_rate; 510 511 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 512 } 513 514 static void 515 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 516 struct rtw89_core_tx_request *tx_req) 517 { 518 struct ieee80211_vif *vif = tx_req->vif; 519 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 520 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 521 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 522 u8 qsel, ch_dma; 523 524 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 525 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 526 527 desc_info->qsel = qsel; 528 desc_info->ch_dma = ch_dma; 529 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 530 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 531 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 532 533 /* fixed data rate for mgmt frames */ 534 desc_info->en_wd_info = true; 535 desc_info->use_rate = true; 536 desc_info->dis_data_fb = true; 537 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); 538 539 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 540 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 541 desc_info->data_rate, chan->channel, chan->band_type, 542 chan->band_width); 543 } 544 545 static void 546 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 547 struct rtw89_core_tx_request *tx_req) 548 { 549 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 550 551 desc_info->is_bmc = false; 552 desc_info->wd_page = false; 553 desc_info->ch_dma = RTW89_DMA_H2C; 554 } 555 556 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) 557 { 558 static const u8 rtw89_bandwidth_to_om[] = { 559 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 560 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 561 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 562 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 563 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 564 }; 565 const struct rtw89_chip_info *chip = rtwdev->chip; 566 struct rtw89_hal *hal = &rtwdev->hal; 567 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 568 u8 om_bandwidth; 569 570 if (!chip->dis_2g_40m_ul_ofdma || 571 chan->band_type != RTW89_BAND_2G || 572 chan->band_width != RTW89_CHANNEL_WIDTH_40) 573 return; 574 575 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 576 rtw89_bandwidth_to_om[chan->band_width] : 0; 577 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 578 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 579 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 580 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 581 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 582 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 583 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 584 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 585 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 586 } 587 588 static bool 589 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 590 struct rtw89_core_tx_request *tx_req, 591 enum btc_pkt_type pkt_type) 592 { 593 struct ieee80211_sta *sta = tx_req->sta; 594 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 595 struct sk_buff *skb = tx_req->skb; 596 struct ieee80211_hdr *hdr = (void *)skb->data; 597 __le16 fc = hdr->frame_control; 598 599 /* AP IOT issue with EAPoL, ARP and DHCP */ 600 if (pkt_type < PACKET_MAX) 601 return false; 602 603 if (!sta || !sta->deflink.he_cap.has_he) 604 return false; 605 606 if (!ieee80211_is_data_qos(fc)) 607 return false; 608 609 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 610 return false; 611 612 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 613 return false; 614 615 return true; 616 } 617 618 static void 619 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 620 struct rtw89_core_tx_request *tx_req) 621 { 622 struct ieee80211_sta *sta = tx_req->sta; 623 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 624 struct sk_buff *skb = tx_req->skb; 625 struct ieee80211_hdr *hdr = (void *)skb->data; 626 __le16 fc = hdr->frame_control; 627 void *data; 628 __le32 *htc; 629 u8 *qc; 630 int hdr_len; 631 632 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 633 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 634 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 635 636 hdr = data; 637 htc = data + hdr_len; 638 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 639 *htc = rtwsta->htc_template ? rtwsta->htc_template : 640 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 641 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 642 643 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 644 qc[0] |= IEEE80211_QOS_CTL_EOSP; 645 } 646 647 static void 648 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 649 struct rtw89_core_tx_request *tx_req, 650 enum btc_pkt_type pkt_type) 651 { 652 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 653 struct ieee80211_vif *vif = tx_req->vif; 654 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 655 656 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 657 goto desc_bk; 658 659 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 660 661 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 662 desc_info->a_ctrl_bsr = true; 663 664 desc_bk: 665 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 666 return; 667 668 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 669 desc_info->bk = true; 670 } 671 672 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 673 struct rtw89_core_tx_request *tx_req) 674 { 675 struct ieee80211_vif *vif = tx_req->vif; 676 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 677 struct ieee80211_sta *sta = tx_req->sta; 678 struct rtw89_sta *rtwsta; 679 680 if (!sta) 681 return rtwvif->mac_id; 682 683 rtwsta = (struct rtw89_sta *)sta->drv_priv; 684 return rtwsta->mac_id; 685 } 686 687 static void 688 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 689 struct rtw89_core_tx_request *tx_req) 690 { 691 struct ieee80211_vif *vif = tx_req->vif; 692 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 693 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 694 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 695 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 696 struct sk_buff *skb = tx_req->skb; 697 u8 tid, tid_indicate; 698 u8 qsel, ch_dma; 699 700 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 701 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 702 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 703 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 704 705 desc_info->ch_dma = ch_dma; 706 desc_info->tid_indicate = tid_indicate; 707 desc_info->qsel = qsel; 708 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 709 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 710 711 /* enable wd_info for AMPDU */ 712 desc_info->en_wd_info = true; 713 714 if (IEEE80211_SKB_CB(skb)->control.hw_key) 715 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 716 717 if (vif->p2p) 718 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 719 else if (rate_pattern->enable) 720 desc_info->data_retry_lowest_rate = rate_pattern->rate; 721 else if (chan->band_type == RTW89_BAND_2G) 722 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_CCK1; 723 else 724 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 725 } 726 727 static enum btc_pkt_type 728 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 729 struct rtw89_core_tx_request *tx_req) 730 { 731 struct sk_buff *skb = tx_req->skb; 732 struct udphdr *udphdr; 733 734 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 735 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 736 return PACKET_EAPOL; 737 } 738 739 if (skb->protocol == htons(ETH_P_ARP)) { 740 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 741 return PACKET_ARP; 742 } 743 744 if (skb->protocol == htons(ETH_P_IP) && 745 ip_hdr(skb)->protocol == IPPROTO_UDP) { 746 udphdr = udp_hdr(skb); 747 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 748 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 749 skb->len > 282) { 750 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 751 return PACKET_DHCP; 752 } 753 } 754 755 if (skb->protocol == htons(ETH_P_IP) && 756 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 757 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 758 return PACKET_ICMP; 759 } 760 761 return PACKET_MAX; 762 } 763 764 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 765 struct rtw89_tx_desc_info *desc_info, 766 struct sk_buff *skb) 767 { 768 struct ieee80211_hdr *hdr = (void *)skb->data; 769 __le16 fc = hdr->frame_control; 770 771 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 772 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 773 } 774 775 static void 776 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 777 struct rtw89_core_tx_request *tx_req) 778 { 779 const struct rtw89_chip_info *chip = rtwdev->chip; 780 781 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 782 return; 783 784 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 785 return; 786 787 if (chip->chip_id != RTL8852C && 788 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 789 return; 790 791 rtw89_mac_notify_wake(rtwdev); 792 } 793 794 static void 795 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 796 struct rtw89_core_tx_request *tx_req) 797 { 798 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 799 struct sk_buff *skb = tx_req->skb; 800 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 801 struct ieee80211_hdr *hdr = (void *)skb->data; 802 enum rtw89_core_tx_type tx_type; 803 enum btc_pkt_type pkt_type; 804 bool is_bmc; 805 u16 seq; 806 807 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 808 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 809 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 810 tx_req->tx_type = tx_type; 811 } 812 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 813 is_multicast_ether_addr(hdr->addr1)); 814 815 desc_info->seq = seq; 816 desc_info->pkt_size = skb->len; 817 desc_info->is_bmc = is_bmc; 818 desc_info->wd_page = true; 819 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 820 821 switch (tx_req->tx_type) { 822 case RTW89_CORE_TX_TYPE_MGMT: 823 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 824 break; 825 case RTW89_CORE_TX_TYPE_DATA: 826 rtw89_core_tx_update_data_info(rtwdev, tx_req); 827 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 828 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 829 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 830 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 831 break; 832 case RTW89_CORE_TX_TYPE_FWCMD: 833 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 834 break; 835 } 836 } 837 838 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 839 { 840 u8 ch_dma; 841 842 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 843 844 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 845 } 846 847 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 848 struct sk_buff *skb, bool fwdl) 849 { 850 struct rtw89_core_tx_request tx_req = {0}; 851 u32 cnt; 852 int ret; 853 854 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 855 rtw89_debug(rtwdev, RTW89_DBG_FW, 856 "ignore h2c due to power is off with firmware state=%d\n", 857 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 858 dev_kfree_skb(skb); 859 return 0; 860 } 861 862 tx_req.skb = skb; 863 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 864 if (fwdl) 865 tx_req.desc_info.fw_dl = true; 866 867 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 868 869 if (!fwdl) 870 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 871 872 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 873 if (cnt == 0) { 874 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 875 return -ENOSPC; 876 } 877 878 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 879 if (ret) { 880 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 881 return ret; 882 } 883 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 884 885 return 0; 886 } 887 888 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 889 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 890 { 891 struct rtw89_core_tx_request tx_req = {0}; 892 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 893 int ret; 894 895 tx_req.skb = skb; 896 tx_req.sta = sta; 897 tx_req.vif = vif; 898 899 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 900 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 901 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 902 rtw89_core_tx_wake(rtwdev, &tx_req); 903 904 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 905 if (ret) { 906 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 907 return ret; 908 } 909 910 if (qsel) 911 *qsel = tx_req.desc_info.qsel; 912 913 return 0; 914 } 915 916 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 917 { 918 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 919 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 920 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 921 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 922 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 923 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 924 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 925 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 926 927 return cpu_to_le32(dword); 928 } 929 930 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 931 { 932 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 933 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 934 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 935 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 936 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 937 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 938 939 return cpu_to_le32(dword); 940 } 941 942 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 943 { 944 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 945 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 946 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 947 948 return cpu_to_le32(dword); 949 } 950 951 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 952 { 953 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 954 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 955 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 956 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 957 958 return cpu_to_le32(dword); 959 } 960 961 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 962 { 963 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 964 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 965 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 966 967 return cpu_to_le32(dword); 968 } 969 970 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 971 { 972 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 973 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 974 975 return cpu_to_le32(dword); 976 } 977 978 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 979 { 980 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 981 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 982 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 983 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 984 985 return cpu_to_le32(dword); 986 } 987 988 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 989 { 990 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 991 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 992 993 return cpu_to_le32(dword); 994 } 995 996 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 997 { 998 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 999 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1000 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1001 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1002 1003 return cpu_to_le32(dword); 1004 } 1005 1006 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1007 { 1008 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1009 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1010 1011 return cpu_to_le32(dword); 1012 } 1013 1014 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1015 { 1016 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1017 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1018 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1019 desc_info->data_retry_lowest_rate); 1020 1021 return cpu_to_le32(dword); 1022 } 1023 1024 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1025 { 1026 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1027 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1028 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1029 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1030 1031 return cpu_to_le32(dword); 1032 } 1033 1034 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1035 { 1036 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1037 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1038 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1039 1040 return cpu_to_le32(dword); 1041 } 1042 1043 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1044 { 1045 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1046 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1047 1048 return cpu_to_le32(dword); 1049 } 1050 1051 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1052 struct rtw89_tx_desc_info *desc_info, 1053 void *txdesc) 1054 { 1055 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1056 struct rtw89_txwd_info *txwd_info; 1057 1058 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1059 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1060 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1061 1062 if (!desc_info->en_wd_info) 1063 return; 1064 1065 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1066 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1067 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1068 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1069 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1070 1071 } 1072 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1073 1074 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1075 struct rtw89_tx_desc_info *desc_info, 1076 void *txdesc) 1077 { 1078 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1079 struct rtw89_txwd_info *txwd_info; 1080 1081 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1082 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1083 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1084 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1085 if (desc_info->sec_en) { 1086 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1087 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1088 } 1089 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1090 1091 if (!desc_info->en_wd_info) 1092 return; 1093 1094 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1095 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1096 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1097 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1098 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1099 } 1100 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1101 1102 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1103 { 1104 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1105 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1106 RTW89_CORE_RX_TYPE_FWDL : 1107 RTW89_CORE_RX_TYPE_H2C); 1108 1109 return cpu_to_le32(dword); 1110 } 1111 1112 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1113 struct rtw89_tx_desc_info *desc_info, 1114 void *txdesc) 1115 { 1116 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1117 1118 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1119 } 1120 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1121 1122 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1123 struct sk_buff *skb, 1124 struct rtw89_rx_phy_ppdu *phy_ppdu) 1125 { 1126 bool rx_cnt_valid = false; 1127 u8 plcp_size = 0; 1128 u8 usr_num = 0; 1129 u8 *phy_sts; 1130 1131 rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); 1132 plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; 1133 usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); 1134 if (usr_num > RTW89_PPDU_MAX_USR) { 1135 rtw89_warn(rtwdev, "Invalid user number in mac info\n"); 1136 return -EINVAL; 1137 } 1138 1139 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1140 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1141 /* 8-byte alignment */ 1142 if (usr_num & BIT(0)) 1143 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1144 if (rx_cnt_valid) 1145 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; 1146 phy_sts += plcp_size; 1147 1148 phy_ppdu->buf = phy_sts; 1149 phy_ppdu->len = skb->data + skb->len - phy_sts; 1150 1151 return 0; 1152 } 1153 1154 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1155 struct ieee80211_sta *sta) 1156 { 1157 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1158 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1159 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1160 int i; 1161 1162 if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) { 1163 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1164 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1165 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1166 } 1167 } 1168 1169 #define VAR_LEN 0xff 1170 #define VAR_LEN_UNIT 8 1171 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) 1172 { 1173 static const u8 physts_ie_len_tab[32] = { 1174 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1175 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1176 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1177 }; 1178 u16 ie_len; 1179 u8 ie; 1180 1181 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1182 if (physts_ie_len_tab[ie] != VAR_LEN) 1183 ie_len = physts_ie_len_tab[ie]; 1184 else 1185 ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; 1186 1187 return ie_len; 1188 } 1189 1190 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, 1191 struct rtw89_rx_phy_ppdu *phy_ppdu) 1192 { 1193 s16 cfo; 1194 1195 phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr); 1196 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1197 return; 1198 /* sign conversion for S(12,2) */ 1199 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_CFO(addr), 11); 1200 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1201 } 1202 1203 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, 1204 struct rtw89_rx_phy_ppdu *phy_ppdu) 1205 { 1206 u8 ie; 1207 1208 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1209 switch (ie) { 1210 case RTW89_PHYSTS_IE01_CMN_OFDM: 1211 rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); 1212 break; 1213 default: 1214 break; 1215 } 1216 1217 return 0; 1218 } 1219 1220 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1221 { 1222 u8 *rssi = phy_ppdu->rssi; 1223 u8 *buf = phy_ppdu->buf; 1224 1225 phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf); 1226 phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); 1227 rssi[RF_PATH_A] = RTW89_GET_PHY_STS_RSSI_A(buf); 1228 rssi[RF_PATH_B] = RTW89_GET_PHY_STS_RSSI_B(buf); 1229 rssi[RF_PATH_C] = RTW89_GET_PHY_STS_RSSI_C(buf); 1230 rssi[RF_PATH_D] = RTW89_GET_PHY_STS_RSSI_D(buf); 1231 } 1232 1233 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1234 struct rtw89_rx_phy_ppdu *phy_ppdu) 1235 { 1236 if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { 1237 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1238 return -EINVAL; 1239 } 1240 rtw89_core_update_phy_ppdu(phy_ppdu); 1241 ieee80211_iterate_stations_atomic(rtwdev->hw, 1242 rtw89_core_rx_process_phy_ppdu_iter, 1243 phy_ppdu); 1244 1245 return 0; 1246 } 1247 1248 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1249 struct rtw89_rx_phy_ppdu *phy_ppdu) 1250 { 1251 u16 ie_len; 1252 u8 *pos, *end; 1253 1254 /* mark invalid reports and bypass them */ 1255 if (phy_ppdu->ie < RTW89_CCK_PKT) 1256 return -EINVAL; 1257 1258 if (!phy_ppdu->to_self) 1259 return 0; 1260 1261 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1262 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1263 while (pos < end) { 1264 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); 1265 rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); 1266 pos += ie_len; 1267 if (pos > end || ie_len == 0) { 1268 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1269 "phy status parse failed\n"); 1270 return -EINVAL; 1271 } 1272 } 1273 1274 return 0; 1275 } 1276 1277 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1278 struct rtw89_rx_phy_ppdu *phy_ppdu) 1279 { 1280 int ret; 1281 1282 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1283 if (ret) 1284 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1285 else 1286 phy_ppdu->valid = true; 1287 } 1288 1289 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1290 const struct rtw89_rx_desc_info *desc_info, 1291 bool rx_status) 1292 { 1293 switch (desc_info->gi_ltf) { 1294 case RTW89_GILTF_SGI_4XHE08: 1295 case RTW89_GILTF_2XHE08: 1296 case RTW89_GILTF_1XHE08: 1297 return NL80211_RATE_INFO_HE_GI_0_8; 1298 case RTW89_GILTF_2XHE16: 1299 case RTW89_GILTF_1XHE16: 1300 return NL80211_RATE_INFO_HE_GI_1_6; 1301 case RTW89_GILTF_LGI_4XHE32: 1302 return NL80211_RATE_INFO_HE_GI_3_2; 1303 default: 1304 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); 1305 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; 1306 } 1307 } 1308 1309 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1310 struct rtw89_rx_desc_info *desc_info, 1311 struct ieee80211_rx_status *status) 1312 { 1313 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1314 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1315 u16 data_rate; 1316 bool ret; 1317 1318 data_rate = desc_info->data_rate; 1319 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1320 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1321 rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1322 /* rate_idx is still hardware value here */ 1323 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1324 rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1325 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1326 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1327 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1328 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1329 } else { 1330 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1331 } 1332 1333 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1334 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); 1335 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1336 status->rate_idx == rate_idx && 1337 status->he_gi == gi_ltf && 1338 status->bw == bw; 1339 1340 return ret; 1341 } 1342 1343 struct rtw89_vif_rx_stats_iter_data { 1344 struct rtw89_dev *rtwdev; 1345 struct rtw89_rx_phy_ppdu *phy_ppdu; 1346 struct rtw89_rx_desc_info *desc_info; 1347 struct sk_buff *skb; 1348 const u8 *bssid; 1349 }; 1350 1351 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1352 struct ieee80211_vif *vif, 1353 struct sk_buff *skb) 1354 { 1355 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1356 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1357 u8 *pos, *end, type; 1358 u16 aid; 1359 1360 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1361 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1362 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1363 return; 1364 1365 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1366 if (type != IEEE80211_TRIGGER_TYPE_BASIC) 1367 return; 1368 1369 end = (u8 *)tf + skb->len; 1370 pos = tf->variable; 1371 1372 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1373 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1374 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1375 "[TF] aid: %d, ul_mcs: %d, rua: %d\n", 1376 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1377 RTW89_GET_TF_USER_INFO_RUA(pos)); 1378 1379 if (aid == RTW89_TF_PAD) 1380 break; 1381 1382 if (aid == vif->cfg.aid) { 1383 rtwvif->stats.rx_tf_acc++; 1384 rtwdev->stats.rx_tf_acc++; 1385 break; 1386 } 1387 1388 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1389 } 1390 } 1391 1392 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1393 struct ieee80211_vif *vif) 1394 { 1395 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1396 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1397 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1398 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1399 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1400 struct sk_buff *skb = iter_data->skb; 1401 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1402 const u8 *bssid = iter_data->bssid; 1403 1404 if (ieee80211_is_trigger(hdr->frame_control)) { 1405 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1406 return; 1407 } 1408 1409 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1410 return; 1411 1412 if (ieee80211_is_beacon(hdr->frame_control)) 1413 pkt_stat->beacon_nr++; 1414 1415 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1416 return; 1417 1418 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1419 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1420 1421 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1422 } 1423 1424 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1425 struct rtw89_rx_phy_ppdu *phy_ppdu, 1426 struct rtw89_rx_desc_info *desc_info, 1427 struct sk_buff *skb) 1428 { 1429 struct rtw89_vif_rx_stats_iter_data iter_data; 1430 1431 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1432 1433 iter_data.rtwdev = rtwdev; 1434 iter_data.phy_ppdu = phy_ppdu; 1435 iter_data.desc_info = desc_info; 1436 iter_data.skb = skb; 1437 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1438 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1439 } 1440 1441 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1442 struct ieee80211_rx_status *status) 1443 { 1444 const struct rtw89_chan_rcd *rcd = 1445 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1446 u16 chan = rcd->prev_primary_channel; 1447 u8 band = rcd->prev_band_type == RTW89_BAND_2G ? 1448 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1449 1450 if (status->band != NL80211_BAND_2GHZ && 1451 status->encoding == RX_ENC_LEGACY && 1452 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1453 status->freq = ieee80211_channel_to_frequency(chan, band); 1454 status->band = band; 1455 } 1456 } 1457 1458 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1459 { 1460 if (rx_status->band == NL80211_BAND_2GHZ || 1461 rx_status->encoding != RX_ENC_LEGACY) 1462 return; 1463 1464 /* Some control frames' freq(ACKs in this case) are reported wrong due 1465 * to FW notify timing, set to lowest rate to prevent overflow. 1466 */ 1467 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1468 rx_status->rate_idx = 0; 1469 return; 1470 } 1471 1472 /* No 4 CCK rates for non-2G */ 1473 rx_status->rate_idx -= 4; 1474 } 1475 1476 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 1477 struct rtw89_rx_phy_ppdu *phy_ppdu, 1478 struct rtw89_rx_desc_info *desc_info, 1479 struct sk_buff *skb_ppdu, 1480 struct ieee80211_rx_status *rx_status) 1481 { 1482 struct napi_struct *napi = &rtwdev->napi; 1483 1484 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 1485 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state))) 1486 napi = NULL; 1487 1488 rtw89_core_hw_to_sband_rate(rx_status); 1489 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 1490 /* In low power mode, it does RX in thread context. */ 1491 local_bh_disable(); 1492 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 1493 local_bh_enable(); 1494 rtwdev->napi_budget_countdown--; 1495 } 1496 1497 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 1498 struct rtw89_rx_phy_ppdu *phy_ppdu, 1499 struct rtw89_rx_desc_info *desc_info, 1500 struct sk_buff *skb) 1501 { 1502 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1503 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 1504 struct sk_buff *skb_ppdu = NULL, *tmp; 1505 struct ieee80211_rx_status *rx_status; 1506 1507 if (curr > RTW89_MAX_PPDU_CNT) 1508 return; 1509 1510 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 1511 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 1512 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1513 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 1514 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 1515 rtw89_correct_cck_chan(rtwdev, rx_status); 1516 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 1517 } 1518 } 1519 1520 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 1521 struct rtw89_rx_desc_info *desc_info, 1522 struct sk_buff *skb) 1523 { 1524 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 1525 .len = skb->len, 1526 .to_self = desc_info->addr1_match, 1527 .rate = desc_info->data_rate, 1528 .mac_id = desc_info->mac_id}; 1529 int ret; 1530 1531 if (desc_info->mac_info_valid) 1532 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 1533 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 1534 if (ret) 1535 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); 1536 1537 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 1538 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 1539 dev_kfree_skb_any(skb); 1540 } 1541 1542 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 1543 struct rtw89_rx_desc_info *desc_info, 1544 struct sk_buff *skb) 1545 { 1546 switch (desc_info->pkt_type) { 1547 case RTW89_CORE_RX_TYPE_C2H: 1548 rtw89_fw_c2h_irqsafe(rtwdev, skb); 1549 break; 1550 case RTW89_CORE_RX_TYPE_PPDU_STAT: 1551 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 1552 break; 1553 default: 1554 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 1555 desc_info->pkt_type); 1556 dev_kfree_skb_any(skb); 1557 break; 1558 } 1559 } 1560 1561 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 1562 struct rtw89_rx_desc_info *desc_info, 1563 u8 *data, u32 data_offset) 1564 { 1565 const struct rtw89_chip_info *chip = rtwdev->chip; 1566 struct rtw89_rxdesc_short *rxd_s; 1567 struct rtw89_rxdesc_long *rxd_l; 1568 u8 shift_len, drv_info_len; 1569 1570 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 1571 desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); 1572 desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); 1573 desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); 1574 desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); 1575 desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); 1576 if (chip->chip_id == RTL8852C) 1577 desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s); 1578 else 1579 desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); 1580 desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); 1581 desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); 1582 desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); 1583 desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); 1584 desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); 1585 desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); 1586 desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); 1587 desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); 1588 desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); 1589 desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); 1590 desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); 1591 desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); 1592 1593 shift_len = desc_info->shift << 1; /* 2-byte unit */ 1594 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 1595 desc_info->offset = data_offset + shift_len + drv_info_len; 1596 desc_info->ready = true; 1597 1598 if (!desc_info->long_rxdesc) 1599 return; 1600 1601 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 1602 desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); 1603 desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); 1604 desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); 1605 desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); 1606 desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); 1607 desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); 1608 } 1609 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 1610 1611 struct rtw89_core_iter_rx_status { 1612 struct rtw89_dev *rtwdev; 1613 struct ieee80211_rx_status *rx_status; 1614 struct rtw89_rx_desc_info *desc_info; 1615 u8 mac_id; 1616 }; 1617 1618 static 1619 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 1620 { 1621 struct rtw89_core_iter_rx_status *iter_data = 1622 (struct rtw89_core_iter_rx_status *)data; 1623 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 1624 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1625 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1626 u8 mac_id = iter_data->mac_id; 1627 1628 if (mac_id != rtwsta->mac_id) 1629 return; 1630 1631 rtwsta->rx_status = *rx_status; 1632 rtwsta->rx_hw_rate = desc_info->data_rate; 1633 } 1634 1635 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 1636 struct rtw89_rx_desc_info *desc_info, 1637 struct ieee80211_rx_status *rx_status) 1638 { 1639 struct rtw89_core_iter_rx_status iter_data; 1640 1641 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 1642 return; 1643 1644 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 1645 return; 1646 1647 iter_data.rtwdev = rtwdev; 1648 iter_data.rx_status = rx_status; 1649 iter_data.desc_info = desc_info; 1650 iter_data.mac_id = desc_info->mac_id; 1651 ieee80211_iterate_stations_atomic(rtwdev->hw, 1652 rtw89_core_stats_sta_rx_status_iter, 1653 &iter_data); 1654 } 1655 1656 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 1657 struct rtw89_rx_desc_info *desc_info, 1658 struct ieee80211_rx_status *rx_status) 1659 { 1660 const struct cfg80211_chan_def *chandef = 1661 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 1662 const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1663 u16 data_rate; 1664 u8 data_rate_mode; 1665 1666 /* currently using single PHY */ 1667 rx_status->freq = chandef->chan->center_freq; 1668 rx_status->band = chandef->chan->band; 1669 1670 if (rtwdev->scanning && 1671 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 1672 u8 chan = cur->primary_channel; 1673 u8 band = cur->band_type; 1674 enum nl80211_band nl_band; 1675 1676 nl_band = rtw89_hw_to_nl80211_band(band); 1677 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 1678 rx_status->band = nl_band; 1679 } 1680 1681 if (desc_info->icv_err || desc_info->crc32_err) 1682 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 1683 1684 if (desc_info->hw_dec && 1685 !(desc_info->sw_dec || desc_info->icv_err)) 1686 rx_status->flag |= RX_FLAG_DECRYPTED; 1687 1688 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1689 1690 data_rate = desc_info->data_rate; 1691 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1692 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1693 rx_status->encoding = RX_ENC_LEGACY; 1694 rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1695 /* convert rate_idx after we get the correct band */ 1696 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1697 rx_status->encoding = RX_ENC_HT; 1698 rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1699 if (desc_info->gi_ltf) 1700 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1701 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1702 rx_status->encoding = RX_ENC_VHT; 1703 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1704 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1705 if (desc_info->gi_ltf) 1706 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1707 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1708 rx_status->encoding = RX_ENC_HE; 1709 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1710 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1711 } else { 1712 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1713 } 1714 1715 /* he_gi is used to match ppdu, so we always fill it. */ 1716 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); 1717 rx_status->flag |= RX_FLAG_MACTIME_START; 1718 rx_status->mactime = desc_info->free_run_cnt; 1719 1720 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 1721 } 1722 1723 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 1724 { 1725 const struct rtw89_chip_info *chip = rtwdev->chip; 1726 1727 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 1728 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 1729 return RTW89_PS_MODE_NONE; 1730 1731 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) 1732 return RTW89_PS_MODE_PWR_GATED; 1733 1734 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 1735 return RTW89_PS_MODE_CLK_GATED; 1736 1737 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 1738 return RTW89_PS_MODE_RFOFF; 1739 1740 return RTW89_PS_MODE_NONE; 1741 } 1742 1743 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 1744 struct rtw89_rx_desc_info *desc_info) 1745 { 1746 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1747 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1748 struct ieee80211_rx_status *rx_status; 1749 struct sk_buff *skb_ppdu, *tmp; 1750 1751 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 1752 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 1753 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1754 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 1755 } 1756 } 1757 1758 void rtw89_core_rx(struct rtw89_dev *rtwdev, 1759 struct rtw89_rx_desc_info *desc_info, 1760 struct sk_buff *skb) 1761 { 1762 struct ieee80211_rx_status *rx_status; 1763 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1764 u8 ppdu_cnt = desc_info->ppdu_cnt; 1765 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1766 1767 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 1768 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 1769 return; 1770 } 1771 1772 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 1773 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 1774 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 1775 } 1776 1777 rx_status = IEEE80211_SKB_RXCB(skb); 1778 memset(rx_status, 0, sizeof(*rx_status)); 1779 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 1780 if (desc_info->long_rxdesc && 1781 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 1782 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 1783 else 1784 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 1785 } 1786 EXPORT_SYMBOL(rtw89_core_rx); 1787 1788 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 1789 { 1790 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1791 return; 1792 1793 napi_enable(&rtwdev->napi); 1794 } 1795 EXPORT_SYMBOL(rtw89_core_napi_start); 1796 1797 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 1798 { 1799 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1800 return; 1801 1802 napi_synchronize(&rtwdev->napi); 1803 napi_disable(&rtwdev->napi); 1804 } 1805 EXPORT_SYMBOL(rtw89_core_napi_stop); 1806 1807 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 1808 { 1809 init_dummy_netdev(&rtwdev->netdev); 1810 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 1811 rtwdev->hci.ops->napi_poll); 1812 } 1813 EXPORT_SYMBOL(rtw89_core_napi_init); 1814 1815 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 1816 { 1817 rtw89_core_napi_stop(rtwdev); 1818 netif_napi_del(&rtwdev->napi); 1819 } 1820 EXPORT_SYMBOL(rtw89_core_napi_deinit); 1821 1822 static void rtw89_core_ba_work(struct work_struct *work) 1823 { 1824 struct rtw89_dev *rtwdev = 1825 container_of(work, struct rtw89_dev, ba_work); 1826 struct rtw89_txq *rtwtxq, *tmp; 1827 int ret; 1828 1829 spin_lock_bh(&rtwdev->ba_lock); 1830 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1831 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1832 struct ieee80211_sta *sta = txq->sta; 1833 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1834 u8 tid = txq->tid; 1835 1836 if (!sta) { 1837 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 1838 goto skip_ba_work; 1839 } 1840 1841 if (rtwsta->disassoc) { 1842 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1843 "cannot start BA with disassoc sta\n"); 1844 goto skip_ba_work; 1845 } 1846 1847 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 1848 if (ret) { 1849 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1850 "failed to setup BA session for %pM:%2d: %d\n", 1851 sta->addr, tid, ret); 1852 if (ret == -EINVAL) 1853 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 1854 } 1855 skip_ba_work: 1856 list_del_init(&rtwtxq->list); 1857 } 1858 spin_unlock_bh(&rtwdev->ba_lock); 1859 } 1860 1861 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 1862 struct ieee80211_sta *sta) 1863 { 1864 struct rtw89_txq *rtwtxq, *tmp; 1865 1866 spin_lock_bh(&rtwdev->ba_lock); 1867 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1868 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1869 1870 if (sta == txq->sta) 1871 list_del_init(&rtwtxq->list); 1872 } 1873 spin_unlock_bh(&rtwdev->ba_lock); 1874 } 1875 1876 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 1877 struct ieee80211_sta *sta) 1878 { 1879 struct rtw89_txq *rtwtxq, *tmp; 1880 1881 spin_lock_bh(&rtwdev->ba_lock); 1882 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 1883 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1884 1885 if (sta == txq->sta) { 1886 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 1887 list_del_init(&rtwtxq->list); 1888 } 1889 } 1890 spin_unlock_bh(&rtwdev->ba_lock); 1891 } 1892 1893 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 1894 struct rtw89_txq *rtwtxq) 1895 { 1896 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1897 struct ieee80211_sta *sta = txq->sta; 1898 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1899 1900 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 1901 return; 1902 1903 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 1904 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1905 return; 1906 1907 spin_lock_bh(&rtwdev->ba_lock); 1908 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1909 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 1910 spin_unlock_bh(&rtwdev->ba_lock); 1911 1912 ieee80211_stop_tx_ba_session(sta, txq->tid); 1913 cancel_delayed_work(&rtwdev->forbid_ba_work); 1914 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 1915 RTW89_FORBID_BA_TIMER); 1916 } 1917 1918 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 1919 struct rtw89_txq *rtwtxq, 1920 struct sk_buff *skb) 1921 { 1922 struct ieee80211_hw *hw = rtwdev->hw; 1923 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1924 struct ieee80211_sta *sta = txq->sta; 1925 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1926 1927 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1928 return; 1929 1930 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 1931 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 1932 return; 1933 } 1934 1935 if (unlikely(!sta)) 1936 return; 1937 1938 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 1939 return; 1940 1941 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 1942 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 1943 return; 1944 } 1945 1946 spin_lock_bh(&rtwdev->ba_lock); 1947 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 1948 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 1949 ieee80211_queue_work(hw, &rtwdev->ba_work); 1950 } 1951 spin_unlock_bh(&rtwdev->ba_lock); 1952 } 1953 1954 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 1955 struct rtw89_txq *rtwtxq, 1956 unsigned long frame_cnt, 1957 unsigned long byte_cnt) 1958 { 1959 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1960 struct ieee80211_vif *vif = txq->vif; 1961 struct ieee80211_sta *sta = txq->sta; 1962 struct sk_buff *skb; 1963 unsigned long i; 1964 int ret; 1965 1966 rcu_read_lock(); 1967 for (i = 0; i < frame_cnt; i++) { 1968 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 1969 if (!skb) { 1970 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 1971 goto out; 1972 } 1973 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 1974 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 1975 if (ret) { 1976 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 1977 ieee80211_free_txskb(rtwdev->hw, skb); 1978 break; 1979 } 1980 } 1981 out: 1982 rcu_read_unlock(); 1983 } 1984 1985 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 1986 { 1987 u8 qsel, ch_dma; 1988 1989 qsel = rtw89_core_get_qsel(rtwdev, tid); 1990 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1991 1992 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 1993 } 1994 1995 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 1996 struct ieee80211_txq *txq, 1997 unsigned long *frame_cnt, 1998 bool *sched_txq, bool *reinvoke) 1999 { 2000 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2001 struct ieee80211_sta *sta = txq->sta; 2002 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2003 2004 if (!sta || rtwsta->max_agg_wait <= 0) 2005 return false; 2006 2007 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2008 return false; 2009 2010 if (*frame_cnt > 1) { 2011 *frame_cnt -= 1; 2012 *sched_txq = true; 2013 *reinvoke = true; 2014 rtwtxq->wait_cnt = 1; 2015 return false; 2016 } 2017 2018 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2019 *reinvoke = true; 2020 rtwtxq->wait_cnt++; 2021 return true; 2022 } 2023 2024 rtwtxq->wait_cnt = 0; 2025 return false; 2026 } 2027 2028 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2029 { 2030 struct ieee80211_hw *hw = rtwdev->hw; 2031 struct ieee80211_txq *txq; 2032 struct rtw89_txq *rtwtxq; 2033 unsigned long frame_cnt; 2034 unsigned long byte_cnt; 2035 u32 tx_resource; 2036 bool sched_txq; 2037 2038 ieee80211_txq_schedule_start(hw, ac); 2039 while ((txq = ieee80211_next_txq(hw, ac))) { 2040 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2041 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2042 sched_txq = false; 2043 2044 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2045 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2046 ieee80211_return_txq(hw, txq, true); 2047 continue; 2048 } 2049 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2050 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2051 ieee80211_return_txq(hw, txq, sched_txq); 2052 if (frame_cnt != 0) 2053 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2054 2055 /* bound of tx_resource could get stuck due to burst traffic */ 2056 if (frame_cnt == tx_resource) 2057 *reinvoke = true; 2058 } 2059 ieee80211_txq_schedule_end(hw, ac); 2060 } 2061 2062 static void rtw89_ips_work(struct work_struct *work) 2063 { 2064 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2065 ips_work); 2066 mutex_lock(&rtwdev->mutex); 2067 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 2068 rtw89_enter_ips(rtwdev); 2069 mutex_unlock(&rtwdev->mutex); 2070 } 2071 2072 static void rtw89_core_txq_work(struct work_struct *w) 2073 { 2074 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2075 bool reinvoke = false; 2076 u8 ac; 2077 2078 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2079 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2080 2081 if (reinvoke) { 2082 /* reinvoke to process the last frame */ 2083 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2084 } 2085 } 2086 2087 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2088 { 2089 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2090 txq_reinvoke_work.work); 2091 2092 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2093 } 2094 2095 static void rtw89_forbid_ba_work(struct work_struct *w) 2096 { 2097 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2098 forbid_ba_work.work); 2099 struct rtw89_txq *rtwtxq, *tmp; 2100 2101 spin_lock_bh(&rtwdev->ba_lock); 2102 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2103 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2104 list_del_init(&rtwtxq->list); 2105 } 2106 spin_unlock_bh(&rtwdev->ba_lock); 2107 } 2108 2109 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2110 u32 throughput, u64 cnt) 2111 { 2112 if (cnt < 100) 2113 return RTW89_TFC_IDLE; 2114 if (throughput > 50) 2115 return RTW89_TFC_HIGH; 2116 if (throughput > 10) 2117 return RTW89_TFC_MID; 2118 if (throughput > 2) 2119 return RTW89_TFC_LOW; 2120 return RTW89_TFC_ULTRA_LOW; 2121 } 2122 2123 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2124 struct rtw89_traffic_stats *stats) 2125 { 2126 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2127 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2128 2129 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2130 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2131 2132 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 2133 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 2134 2135 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 2136 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 2137 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 2138 stats->tx_cnt); 2139 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 2140 stats->rx_cnt); 2141 stats->tx_avg_len = stats->tx_cnt ? 2142 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 2143 stats->rx_avg_len = stats->rx_cnt ? 2144 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 2145 2146 stats->tx_unicast = 0; 2147 stats->rx_unicast = 0; 2148 stats->tx_cnt = 0; 2149 stats->rx_cnt = 0; 2150 stats->rx_tf_periodic = stats->rx_tf_acc; 2151 stats->rx_tf_acc = 0; 2152 2153 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 2154 return true; 2155 2156 return false; 2157 } 2158 2159 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 2160 { 2161 struct rtw89_vif *rtwvif; 2162 bool tfc_changed; 2163 2164 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 2165 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2166 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 2167 2168 return tfc_changed; 2169 } 2170 2171 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2172 { 2173 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 2174 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) 2175 return; 2176 2177 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 2178 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 2179 rtw89_enter_lps(rtwdev, rtwvif); 2180 } 2181 2182 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 2183 { 2184 struct rtw89_vif *rtwvif; 2185 2186 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2187 rtw89_vif_enter_lps(rtwdev, rtwvif); 2188 } 2189 2190 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 2191 struct rtw89_traffic_stats *stats) 2192 { 2193 stats->tx_unicast = 0; 2194 stats->rx_unicast = 0; 2195 stats->tx_cnt = 0; 2196 stats->rx_cnt = 0; 2197 ewma_tp_init(&stats->tx_ewma_tp); 2198 ewma_tp_init(&stats->rx_ewma_tp); 2199 } 2200 2201 static void rtw89_track_work(struct work_struct *work) 2202 { 2203 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2204 track_work.work); 2205 bool tfc_changed; 2206 2207 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 2208 return; 2209 2210 mutex_lock(&rtwdev->mutex); 2211 2212 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2213 goto out; 2214 2215 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2216 RTW89_TRACK_WORK_PERIOD); 2217 2218 tfc_changed = rtw89_traffic_stats_track(rtwdev); 2219 if (rtwdev->scanning) 2220 goto out; 2221 2222 rtw89_leave_lps(rtwdev); 2223 2224 if (tfc_changed) { 2225 rtw89_hci_recalc_int_mit(rtwdev); 2226 rtw89_btc_ntfy_wl_sta(rtwdev); 2227 } 2228 rtw89_mac_bf_monitor_track(rtwdev); 2229 rtw89_phy_stat_track(rtwdev); 2230 rtw89_phy_env_monitor_track(rtwdev); 2231 rtw89_phy_dig(rtwdev); 2232 rtw89_chip_rfk_track(rtwdev); 2233 rtw89_phy_ra_update(rtwdev); 2234 rtw89_phy_cfo_track(rtwdev); 2235 rtw89_phy_tx_path_div_track(rtwdev); 2236 2237 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 2238 rtw89_enter_lps_track(rtwdev); 2239 2240 out: 2241 mutex_unlock(&rtwdev->mutex); 2242 } 2243 2244 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 2245 { 2246 unsigned long bit; 2247 2248 bit = find_first_zero_bit(addr, size); 2249 if (bit < size) 2250 set_bit(bit, addr); 2251 2252 return bit; 2253 } 2254 2255 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 2256 { 2257 clear_bit(bit, addr); 2258 } 2259 2260 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 2261 { 2262 bitmap_zero(addr, nbits); 2263 } 2264 2265 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 2266 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2267 { 2268 const struct rtw89_chip_info *chip = rtwdev->chip; 2269 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2270 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2271 u8 idx; 2272 int i; 2273 2274 lockdep_assert_held(&rtwdev->mutex); 2275 2276 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 2277 if (idx == chip->bacam_num) { 2278 /* allocate a static BA CAM to tid=0/5, so replace the existing 2279 * one if BA CAM is full. Hardware will process the original tid 2280 * automatically. 2281 */ 2282 if (tid != 0 && tid != 5) 2283 return -ENOSPC; 2284 2285 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 2286 tmp = &cam_info->ba_cam_entry[i]; 2287 if (tmp->tid == 0 || tmp->tid == 5) 2288 continue; 2289 2290 idx = i; 2291 entry = tmp; 2292 list_del(&entry->list); 2293 break; 2294 } 2295 2296 if (!entry) 2297 return -ENOSPC; 2298 } else { 2299 entry = &cam_info->ba_cam_entry[idx]; 2300 } 2301 2302 entry->tid = tid; 2303 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 2304 2305 *cam_idx = idx; 2306 2307 return 0; 2308 } 2309 2310 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 2311 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2312 { 2313 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2314 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2315 u8 idx; 2316 2317 lockdep_assert_held(&rtwdev->mutex); 2318 2319 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 2320 if (entry->tid != tid) 2321 continue; 2322 2323 idx = entry - cam_info->ba_cam_entry; 2324 list_del(&entry->list); 2325 2326 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 2327 *cam_idx = idx; 2328 return 0; 2329 } 2330 2331 return -ENOENT; 2332 } 2333 2334 #define RTW89_TYPE_MAPPING(_type) \ 2335 case NL80211_IFTYPE_ ## _type: \ 2336 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 2337 break 2338 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 2339 { 2340 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2341 2342 switch (vif->type) { 2343 case NL80211_IFTYPE_STATION: 2344 if (vif->p2p) 2345 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 2346 else 2347 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 2348 break; 2349 case NL80211_IFTYPE_AP: 2350 if (vif->p2p) 2351 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 2352 else 2353 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 2354 break; 2355 RTW89_TYPE_MAPPING(ADHOC); 2356 RTW89_TYPE_MAPPING(MONITOR); 2357 RTW89_TYPE_MAPPING(MESH_POINT); 2358 default: 2359 WARN_ON(1); 2360 break; 2361 } 2362 2363 switch (vif->type) { 2364 case NL80211_IFTYPE_AP: 2365 case NL80211_IFTYPE_MESH_POINT: 2366 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 2367 rtwvif->self_role = RTW89_SELF_ROLE_AP; 2368 break; 2369 case NL80211_IFTYPE_ADHOC: 2370 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 2371 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2372 break; 2373 case NL80211_IFTYPE_STATION: 2374 if (assoc) { 2375 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 2376 rtwvif->trigger = vif->bss_conf.he_support; 2377 } else { 2378 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 2379 rtwvif->trigger = false; 2380 } 2381 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2382 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 2383 break; 2384 default: 2385 WARN_ON(1); 2386 break; 2387 } 2388 } 2389 2390 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 2391 struct ieee80211_vif *vif, 2392 struct ieee80211_sta *sta) 2393 { 2394 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2395 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2396 int i; 2397 2398 rtwsta->rtwdev = rtwdev; 2399 rtwsta->rtwvif = rtwvif; 2400 rtwsta->prev_rssi = 0; 2401 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 2402 2403 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 2404 rtw89_core_txq_init(rtwdev, sta->txq[i]); 2405 2406 ewma_rssi_init(&rtwsta->avg_rssi); 2407 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2408 ewma_rssi_init(&rtwsta->rssi[i]); 2409 2410 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2411 /* for station mode, assign the mac_id from itself */ 2412 rtwsta->mac_id = rtwvif->mac_id; 2413 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2414 BTC_ROLE_MSTS_STA_CONN_START); 2415 rtw89_chip_rfk_channel(rtwdev); 2416 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2417 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 2418 RTW89_MAX_MAC_ID_NUM); 2419 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 2420 return -ENOSPC; 2421 } 2422 2423 return 0; 2424 } 2425 2426 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 2427 struct ieee80211_vif *vif, 2428 struct ieee80211_sta *sta) 2429 { 2430 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2431 2432 rtwdev->total_sta_assoc--; 2433 rtwsta->disassoc = true; 2434 2435 return 0; 2436 } 2437 2438 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 2439 struct ieee80211_vif *vif, 2440 struct ieee80211_sta *sta) 2441 { 2442 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2443 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2444 int ret; 2445 2446 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 2447 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 2448 rtw89_core_free_sta_pending_ba(rtwdev, sta); 2449 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 2450 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2451 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 2452 if (sta->tdls) 2453 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 2454 2455 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2456 rtw89_vif_type_mapping(vif, false); 2457 2458 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2459 if (ret) { 2460 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2461 return ret; 2462 } 2463 2464 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 2465 if (ret) { 2466 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2467 return ret; 2468 } 2469 2470 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2471 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_REMOVE); 2472 if (ret) { 2473 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2474 return ret; 2475 } 2476 } 2477 2478 /* update cam aid mac_id net_type */ 2479 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2480 if (ret) { 2481 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2482 return ret; 2483 } 2484 2485 return ret; 2486 } 2487 2488 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 2489 struct ieee80211_vif *vif, 2490 struct ieee80211_sta *sta) 2491 { 2492 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2493 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2494 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 2495 int ret; 2496 2497 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2498 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 2499 if (ret) { 2500 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 2501 return ret; 2502 } 2503 2504 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_CREATE); 2505 if (ret) { 2506 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2507 return ret; 2508 } 2509 2510 if (sta->tdls) { 2511 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 2512 if (ret) { 2513 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 2514 return ret; 2515 } 2516 } 2517 2518 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 2519 if (ret) { 2520 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 2521 return ret; 2522 } 2523 } 2524 2525 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2526 if (ret) { 2527 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2528 return ret; 2529 } 2530 2531 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 2532 if (ret) { 2533 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2534 return ret; 2535 } 2536 2537 /* update cam aid mac_id net_type */ 2538 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2539 if (ret) { 2540 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2541 return ret; 2542 } 2543 2544 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwsta->mac_id); 2545 if (ret) { 2546 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 2547 return ret; 2548 } 2549 2550 rtwdev->total_sta_assoc++; 2551 rtw89_phy_ra_assoc(rtwdev, sta); 2552 rtw89_mac_bf_assoc(rtwdev, vif, sta); 2553 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 2554 2555 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2556 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2557 BTC_ROLE_MSTS_STA_CONN_END); 2558 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); 2559 } 2560 2561 return ret; 2562 } 2563 2564 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 2565 struct ieee80211_vif *vif, 2566 struct ieee80211_sta *sta) 2567 { 2568 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2569 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2570 2571 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2572 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2573 BTC_ROLE_MSTS_STA_DIS_CONN); 2574 else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2575 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2576 2577 return 0; 2578 } 2579 2580 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 2581 struct ieee80211_sta *sta, 2582 struct cfg80211_tid_cfg *tid_conf) 2583 { 2584 struct ieee80211_txq *txq; 2585 struct rtw89_txq *rtwtxq; 2586 u32 mask = tid_conf->mask; 2587 u8 tids = tid_conf->tids; 2588 int tids_nbit = BITS_PER_BYTE; 2589 int i; 2590 2591 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 2592 if (!tids) 2593 break; 2594 2595 if (!(tids & BIT(0))) 2596 continue; 2597 2598 txq = sta->txq[i]; 2599 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2600 2601 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 2602 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 2603 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2604 } else { 2605 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 2606 ieee80211_stop_tx_ba_session(sta, txq->tid); 2607 spin_lock_bh(&rtwdev->ba_lock); 2608 list_del_init(&rtwtxq->list); 2609 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2610 spin_unlock_bh(&rtwdev->ba_lock); 2611 } 2612 } 2613 2614 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 2615 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 2616 sta->max_amsdu_subframes = 0; 2617 else 2618 sta->max_amsdu_subframes = 1; 2619 } 2620 } 2621 } 2622 2623 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 2624 struct ieee80211_sta *sta, 2625 struct cfg80211_tid_config *tid_config) 2626 { 2627 int i; 2628 2629 for (i = 0; i < tid_config->n_tid_conf; i++) 2630 _rtw89_core_set_tid_config(rtwdev, sta, 2631 &tid_config->tid_conf[i]); 2632 } 2633 2634 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 2635 struct ieee80211_sta_ht_cap *ht_cap) 2636 { 2637 static const __le16 highest[RF_PATH_MAX] = { 2638 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 2639 }; 2640 struct rtw89_hal *hal = &rtwdev->hal; 2641 u8 nss = hal->rx_nss; 2642 int i; 2643 2644 ht_cap->ht_supported = true; 2645 ht_cap->cap = 0; 2646 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 2647 IEEE80211_HT_CAP_MAX_AMSDU | 2648 IEEE80211_HT_CAP_TX_STBC | 2649 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 2650 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 2651 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 2652 IEEE80211_HT_CAP_DSSSCCK40 | 2653 IEEE80211_HT_CAP_SGI_40; 2654 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 2655 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 2656 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 2657 for (i = 0; i < nss; i++) 2658 ht_cap->mcs.rx_mask[i] = 0xFF; 2659 ht_cap->mcs.rx_mask[4] = 0x01; 2660 ht_cap->mcs.rx_highest = highest[nss - 1]; 2661 } 2662 2663 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 2664 struct ieee80211_sta_vht_cap *vht_cap) 2665 { 2666 static const __le16 highest_bw80[RF_PATH_MAX] = { 2667 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 2668 }; 2669 static const __le16 highest_bw160[RF_PATH_MAX] = { 2670 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 2671 }; 2672 const struct rtw89_chip_info *chip = rtwdev->chip; 2673 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 2674 struct rtw89_hal *hal = &rtwdev->hal; 2675 u16 tx_mcs_map = 0, rx_mcs_map = 0; 2676 u8 sts_cap = 3; 2677 int i; 2678 2679 for (i = 0; i < 8; i++) { 2680 if (i < hal->tx_nss) 2681 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2682 else 2683 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2684 if (i < hal->rx_nss) 2685 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2686 else 2687 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2688 } 2689 2690 vht_cap->vht_supported = true; 2691 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 2692 IEEE80211_VHT_CAP_SHORT_GI_80 | 2693 IEEE80211_VHT_CAP_RXSTBC_1 | 2694 IEEE80211_VHT_CAP_HTC_VHT | 2695 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 2696 0; 2697 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 2698 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 2699 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 2700 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 2701 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 2702 if (chip->support_bw160) 2703 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 2704 IEEE80211_VHT_CAP_SHORT_GI_160; 2705 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 2706 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 2707 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 2708 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 2709 } 2710 2711 #define RTW89_SBAND_IFTYPES_NR 2 2712 2713 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 2714 enum nl80211_band band, 2715 struct ieee80211_supported_band *sband) 2716 { 2717 const struct rtw89_chip_info *chip = rtwdev->chip; 2718 struct rtw89_hal *hal = &rtwdev->hal; 2719 struct ieee80211_sband_iftype_data *iftype_data; 2720 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 2721 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 2722 u16 mcs_map = 0; 2723 int i; 2724 int nss = hal->rx_nss; 2725 int idx = 0; 2726 2727 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 2728 if (!iftype_data) 2729 return; 2730 2731 for (i = 0; i < 8; i++) { 2732 if (i < nss) 2733 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 2734 else 2735 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 2736 } 2737 2738 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 2739 struct ieee80211_sta_he_cap *he_cap; 2740 u8 *mac_cap_info; 2741 u8 *phy_cap_info; 2742 2743 switch (i) { 2744 case NL80211_IFTYPE_STATION: 2745 case NL80211_IFTYPE_AP: 2746 break; 2747 default: 2748 continue; 2749 } 2750 2751 if (idx >= RTW89_SBAND_IFTYPES_NR) { 2752 rtw89_warn(rtwdev, "run out of iftype_data\n"); 2753 break; 2754 } 2755 2756 iftype_data[idx].types_mask = BIT(i); 2757 he_cap = &iftype_data[idx].he_cap; 2758 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 2759 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 2760 2761 he_cap->has_he = true; 2762 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 2763 if (i == NL80211_IFTYPE_STATION) 2764 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 2765 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 2766 IEEE80211_HE_MAC_CAP2_BSR; 2767 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 2768 if (i == NL80211_IFTYPE_AP) 2769 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 2770 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 2771 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 2772 if (i == NL80211_IFTYPE_STATION) 2773 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 2774 if (band == NL80211_BAND_2GHZ) { 2775 phy_cap_info[0] = 2776 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 2777 } else { 2778 phy_cap_info[0] = 2779 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 2780 if (chip->support_bw160) 2781 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 2782 } 2783 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 2784 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 2785 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 2786 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 2787 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 2788 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 2789 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 2790 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 2791 if (i == NL80211_IFTYPE_STATION) 2792 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 2793 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 2794 if (i == NL80211_IFTYPE_AP) 2795 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 2796 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 2797 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 2798 if (chip->support_bw160) 2799 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 2800 phy_cap_info[5] = no_ng16 ? 0 : 2801 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 2802 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 2803 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 2804 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 2805 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 2806 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 2807 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 2808 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 2809 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 2810 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 2811 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 2812 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 2813 if (chip->support_bw160) 2814 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 2815 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 2816 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 2817 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 2818 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 2819 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 2820 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 2821 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 2822 if (i == NL80211_IFTYPE_STATION) 2823 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 2824 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 2825 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 2826 if (chip->support_bw160) { 2827 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 2828 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 2829 } 2830 2831 if (band == NL80211_BAND_6GHZ) { 2832 __le16 capa; 2833 2834 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 2835 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 2836 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 2837 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 2838 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 2839 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 2840 iftype_data[idx].he_6ghz_capa.capa = capa; 2841 } 2842 2843 idx++; 2844 } 2845 2846 sband->iftype_data = iftype_data; 2847 sband->n_iftype_data = idx; 2848 } 2849 2850 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 2851 { 2852 struct ieee80211_hw *hw = rtwdev->hw; 2853 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 2854 struct ieee80211_supported_band *sband_6ghz = NULL; 2855 u32 size = sizeof(struct ieee80211_supported_band); 2856 u8 support_bands = rtwdev->chip->support_bands; 2857 2858 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 2859 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 2860 if (!sband_2ghz) 2861 goto err; 2862 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 2863 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 2864 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 2865 } 2866 2867 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 2868 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 2869 if (!sband_5ghz) 2870 goto err; 2871 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 2872 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 2873 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 2874 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 2875 } 2876 2877 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 2878 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 2879 if (!sband_6ghz) 2880 goto err; 2881 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 2882 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 2883 } 2884 2885 return 0; 2886 2887 err: 2888 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2889 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2890 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2891 if (sband_2ghz) 2892 kfree(sband_2ghz->iftype_data); 2893 if (sband_5ghz) 2894 kfree(sband_5ghz->iftype_data); 2895 if (sband_6ghz) 2896 kfree(sband_6ghz->iftype_data); 2897 kfree(sband_2ghz); 2898 kfree(sband_5ghz); 2899 kfree(sband_6ghz); 2900 return -ENOMEM; 2901 } 2902 2903 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 2904 { 2905 struct ieee80211_hw *hw = rtwdev->hw; 2906 2907 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 2908 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 2909 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 2910 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 2911 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 2912 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 2913 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 2914 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2915 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2916 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2917 } 2918 2919 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 2920 { 2921 int i; 2922 2923 for (i = 0; i < RTW89_PHY_MAX; i++) 2924 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 2925 for (i = 0; i < RTW89_PHY_MAX; i++) 2926 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 2927 } 2928 2929 void rtw89_core_update_beacon_work(struct work_struct *work) 2930 { 2931 struct rtw89_dev *rtwdev; 2932 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2933 update_beacon_work); 2934 2935 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 2936 return; 2937 2938 rtwdev = rtwvif->rtwdev; 2939 mutex_lock(&rtwdev->mutex); 2940 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 2941 mutex_unlock(&rtwdev->mutex); 2942 } 2943 2944 int rtw89_core_start(struct rtw89_dev *rtwdev) 2945 { 2946 int ret; 2947 2948 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 2949 ret = rtw89_mac_init(rtwdev); 2950 if (ret) { 2951 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 2952 return ret; 2953 } 2954 2955 rtw89_btc_ntfy_poweron(rtwdev); 2956 2957 /* efuse process */ 2958 2959 /* pre-config BB/RF, BB reset/RFC reset */ 2960 ret = rtw89_chip_disable_bb_rf(rtwdev); 2961 if (ret) 2962 return ret; 2963 ret = rtw89_chip_enable_bb_rf(rtwdev); 2964 if (ret) 2965 return ret; 2966 2967 rtw89_phy_init_bb_reg(rtwdev); 2968 rtw89_phy_init_rf_reg(rtwdev, false); 2969 2970 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 2971 2972 rtw89_phy_dm_init(rtwdev); 2973 2974 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 2975 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 2976 2977 ret = rtw89_hci_start(rtwdev); 2978 if (ret) { 2979 rtw89_err(rtwdev, "failed to start hci\n"); 2980 return ret; 2981 } 2982 2983 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2984 RTW89_TRACK_WORK_PERIOD); 2985 2986 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 2987 2988 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 2989 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); 2990 rtw89_fw_h2c_init_ba_cam(rtwdev); 2991 2992 return 0; 2993 } 2994 2995 void rtw89_core_stop(struct rtw89_dev *rtwdev) 2996 { 2997 struct rtw89_btc *btc = &rtwdev->btc; 2998 2999 /* Prvent to stop twice; enter_ips and ops_stop */ 3000 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3001 return; 3002 3003 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 3004 3005 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3006 3007 mutex_unlock(&rtwdev->mutex); 3008 3009 cancel_work_sync(&rtwdev->c2h_work); 3010 cancel_work_sync(&btc->eapol_notify_work); 3011 cancel_work_sync(&btc->arp_notify_work); 3012 cancel_work_sync(&btc->dhcp_notify_work); 3013 cancel_work_sync(&btc->icmp_notify_work); 3014 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 3015 cancel_delayed_work_sync(&rtwdev->track_work); 3016 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 3017 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 3018 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 3019 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 3020 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 3021 3022 mutex_lock(&rtwdev->mutex); 3023 3024 rtw89_btc_ntfy_poweroff(rtwdev); 3025 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3026 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3027 rtw89_hci_stop(rtwdev); 3028 rtw89_hci_deinit(rtwdev); 3029 rtw89_mac_pwr_off(rtwdev); 3030 rtw89_hci_reset(rtwdev); 3031 } 3032 3033 int rtw89_core_init(struct rtw89_dev *rtwdev) 3034 { 3035 struct rtw89_btc *btc = &rtwdev->btc; 3036 int ret; 3037 u8 band; 3038 3039 INIT_LIST_HEAD(&rtwdev->ba_list); 3040 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 3041 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 3042 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 3043 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 3044 if (!(rtwdev->chip->support_bands & BIT(band))) 3045 continue; 3046 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 3047 } 3048 INIT_LIST_HEAD(&rtwdev->wow.pkt_list); 3049 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 3050 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 3051 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 3052 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 3053 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 3054 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 3055 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 3056 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 3057 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 3058 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 3059 spin_lock_init(&rtwdev->ba_lock); 3060 spin_lock_init(&rtwdev->rpwm_lock); 3061 mutex_init(&rtwdev->mutex); 3062 mutex_init(&rtwdev->rf_mutex); 3063 rtwdev->total_sta_assoc = 0; 3064 3065 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 3066 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 3067 skb_queue_head_init(&rtwdev->c2h_queue); 3068 rtw89_core_ppdu_sts_init(rtwdev); 3069 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 3070 3071 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 3072 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 3073 3074 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 3075 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 3076 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 3077 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 3078 3079 ret = rtw89_load_firmware(rtwdev); 3080 if (ret) { 3081 rtw89_warn(rtwdev, "no firmware loaded\n"); 3082 return ret; 3083 } 3084 rtw89_ser_init(rtwdev); 3085 rtw89_entity_init(rtwdev); 3086 3087 return 0; 3088 } 3089 EXPORT_SYMBOL(rtw89_core_init); 3090 3091 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 3092 { 3093 rtw89_ser_deinit(rtwdev); 3094 rtw89_unload_firmware(rtwdev); 3095 rtw89_fw_free_all_early_h2c(rtwdev); 3096 3097 destroy_workqueue(rtwdev->txq_wq); 3098 mutex_destroy(&rtwdev->rf_mutex); 3099 mutex_destroy(&rtwdev->mutex); 3100 } 3101 EXPORT_SYMBOL(rtw89_core_deinit); 3102 3103 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3104 const u8 *mac_addr, bool hw_scan) 3105 { 3106 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3107 3108 rtwdev->scanning = true; 3109 rtw89_leave_lps(rtwdev); 3110 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3111 rtw89_leave_ips(rtwdev); 3112 3113 ether_addr_copy(rtwvif->mac_addr, mac_addr); 3114 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 3115 rtw89_chip_rfk_scan(rtwdev, true); 3116 rtw89_hci_recalc_int_mit(rtwdev); 3117 3118 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 3119 } 3120 3121 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3122 struct ieee80211_vif *vif, bool hw_scan) 3123 { 3124 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3125 3126 if (!rtwvif) 3127 return; 3128 3129 ether_addr_copy(rtwvif->mac_addr, vif->addr); 3130 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3131 3132 rtw89_chip_rfk_scan(rtwdev, false); 3133 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 3134 3135 rtwdev->scanning = false; 3136 rtwdev->dig.bypass_dig = true; 3137 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3138 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 3139 } 3140 3141 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 3142 { 3143 const struct rtw89_chip_info *chip = rtwdev->chip; 3144 u8 cv; 3145 3146 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 3147 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 3148 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 3149 cv = CHIP_CAV; 3150 else 3151 cv = CHIP_CBV; 3152 } 3153 3154 rtwdev->hal.cv = cv; 3155 } 3156 3157 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 3158 { 3159 rtwdev->hal.support_cckpd = 3160 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 3161 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 3162 rtwdev->hal.support_igi = 3163 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 3164 } 3165 3166 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 3167 { 3168 int ret; 3169 3170 ret = rtw89_mac_partial_init(rtwdev); 3171 if (ret) 3172 return ret; 3173 3174 ret = rtw89_parse_efuse_map(rtwdev); 3175 if (ret) 3176 return ret; 3177 3178 ret = rtw89_parse_phycap_map(rtwdev); 3179 if (ret) 3180 return ret; 3181 3182 ret = rtw89_mac_setup_phycap(rtwdev); 3183 if (ret) 3184 return ret; 3185 3186 rtw89_core_setup_phycap(rtwdev); 3187 3188 rtw89_mac_pwr_off(rtwdev); 3189 3190 return 0; 3191 } 3192 3193 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 3194 { 3195 rtw89_chip_fem_setup(rtwdev); 3196 3197 return 0; 3198 } 3199 3200 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 3201 { 3202 int ret; 3203 3204 rtw89_read_chip_ver(rtwdev); 3205 3206 ret = rtw89_wait_firmware_completion(rtwdev); 3207 if (ret) { 3208 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 3209 return ret; 3210 } 3211 3212 ret = rtw89_fw_recognize(rtwdev); 3213 if (ret) { 3214 rtw89_err(rtwdev, "failed to recognize firmware\n"); 3215 return ret; 3216 } 3217 3218 ret = rtw89_chip_efuse_info_setup(rtwdev); 3219 if (ret) 3220 return ret; 3221 3222 ret = rtw89_chip_board_info_setup(rtwdev); 3223 if (ret) 3224 return ret; 3225 3226 return 0; 3227 } 3228 EXPORT_SYMBOL(rtw89_chip_info_setup); 3229 3230 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 3231 { 3232 struct ieee80211_hw *hw = rtwdev->hw; 3233 struct rtw89_efuse *efuse = &rtwdev->efuse; 3234 int ret; 3235 int tx_headroom = IEEE80211_HT_CTL_LEN; 3236 3237 hw->vif_data_size = sizeof(struct rtw89_vif); 3238 hw->sta_data_size = sizeof(struct rtw89_sta); 3239 hw->txq_data_size = sizeof(struct rtw89_txq); 3240 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 3241 3242 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 3243 3244 hw->extra_tx_headroom = tx_headroom; 3245 hw->queues = IEEE80211_NUM_ACS; 3246 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 3247 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 3248 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 3249 3250 ieee80211_hw_set(hw, SIGNAL_DBM); 3251 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 3252 ieee80211_hw_set(hw, MFP_CAPABLE); 3253 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 3254 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 3255 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 3256 ieee80211_hw_set(hw, TX_AMSDU); 3257 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 3258 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 3259 ieee80211_hw_set(hw, SUPPORTS_PS); 3260 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 3261 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 3262 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 3263 3264 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 3265 BIT(NL80211_IFTYPE_AP) | 3266 BIT(NL80211_IFTYPE_P2P_CLIENT) | 3267 BIT(NL80211_IFTYPE_P2P_GO); 3268 3269 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 3270 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 3271 3272 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 3273 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 3274 WIPHY_FLAG_AP_UAPSD; 3275 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 3276 3277 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 3278 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 3279 3280 #ifdef CONFIG_PM 3281 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 3282 #endif 3283 3284 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3285 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3286 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3287 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3288 3289 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 3290 3291 ret = rtw89_core_set_supported_band(rtwdev); 3292 if (ret) { 3293 rtw89_err(rtwdev, "failed to set supported band\n"); 3294 return ret; 3295 } 3296 3297 hw->wiphy->reg_notifier = rtw89_regd_notifier; 3298 hw->wiphy->sar_capa = &rtw89_sar_capa; 3299 3300 ret = ieee80211_register_hw(hw); 3301 if (ret) { 3302 rtw89_err(rtwdev, "failed to register hw\n"); 3303 goto err; 3304 } 3305 3306 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 3307 if (ret) { 3308 rtw89_err(rtwdev, "failed to init regd\n"); 3309 goto err; 3310 } 3311 3312 return 0; 3313 3314 err: 3315 return ret; 3316 } 3317 3318 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 3319 { 3320 struct ieee80211_hw *hw = rtwdev->hw; 3321 3322 ieee80211_unregister_hw(hw); 3323 rtw89_core_clr_supported_band(rtwdev); 3324 } 3325 3326 int rtw89_core_register(struct rtw89_dev *rtwdev) 3327 { 3328 int ret; 3329 3330 ret = rtw89_core_register_hw(rtwdev); 3331 if (ret) { 3332 rtw89_err(rtwdev, "failed to register core hw\n"); 3333 return ret; 3334 } 3335 3336 rtw89_debugfs_init(rtwdev); 3337 3338 return 0; 3339 } 3340 EXPORT_SYMBOL(rtw89_core_register); 3341 3342 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 3343 { 3344 rtw89_core_unregister_hw(rtwdev); 3345 } 3346 EXPORT_SYMBOL(rtw89_core_unregister); 3347 3348 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 3349 u32 bus_data_size, 3350 const struct rtw89_chip_info *chip) 3351 { 3352 struct ieee80211_hw *hw; 3353 struct rtw89_dev *rtwdev; 3354 struct ieee80211_ops *ops; 3355 u32 driver_data_size; 3356 u32 early_feat_map = 0; 3357 bool no_chanctx; 3358 3359 rtw89_early_fw_feature_recognize(device, chip, &early_feat_map); 3360 3361 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 3362 if (!ops) 3363 goto err; 3364 3365 no_chanctx = chip->support_chanctx_num == 0 || 3366 !(early_feat_map & BIT(RTW89_FW_FEATURE_SCAN_OFFLOAD)); 3367 3368 if (no_chanctx) { 3369 ops->add_chanctx = NULL; 3370 ops->remove_chanctx = NULL; 3371 ops->change_chanctx = NULL; 3372 ops->assign_vif_chanctx = NULL; 3373 ops->unassign_vif_chanctx = NULL; 3374 } 3375 3376 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 3377 hw = ieee80211_alloc_hw(driver_data_size, ops); 3378 if (!hw) 3379 goto err; 3380 3381 rtwdev = hw->priv; 3382 rtwdev->hw = hw; 3383 rtwdev->dev = device; 3384 rtwdev->ops = ops; 3385 rtwdev->chip = chip; 3386 3387 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 3388 no_chanctx ? "without" : "with"); 3389 3390 return rtwdev; 3391 3392 err: 3393 kfree(ops); 3394 return NULL; 3395 } 3396 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 3397 3398 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 3399 { 3400 kfree(rtwdev->ops); 3401 ieee80211_free_hw(rtwdev->hw); 3402 } 3403 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 3404 3405 MODULE_AUTHOR("Realtek Corporation"); 3406 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 3407 MODULE_LICENSE("Dual BSD/GPL"); 3408