1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 }; 81 82 static struct ieee80211_channel rtw89_channels_6ghz[] = { 83 RTW89_DEF_CHAN_6G(5955, 1), 84 RTW89_DEF_CHAN_6G(5975, 5), 85 RTW89_DEF_CHAN_6G(5995, 9), 86 RTW89_DEF_CHAN_6G(6015, 13), 87 RTW89_DEF_CHAN_6G(6035, 17), 88 RTW89_DEF_CHAN_6G(6055, 21), 89 RTW89_DEF_CHAN_6G(6075, 25), 90 RTW89_DEF_CHAN_6G(6095, 29), 91 RTW89_DEF_CHAN_6G(6115, 33), 92 RTW89_DEF_CHAN_6G(6135, 37), 93 RTW89_DEF_CHAN_6G(6155, 41), 94 RTW89_DEF_CHAN_6G(6175, 45), 95 RTW89_DEF_CHAN_6G(6195, 49), 96 RTW89_DEF_CHAN_6G(6215, 53), 97 RTW89_DEF_CHAN_6G(6235, 57), 98 RTW89_DEF_CHAN_6G(6255, 61), 99 RTW89_DEF_CHAN_6G(6275, 65), 100 RTW89_DEF_CHAN_6G(6295, 69), 101 RTW89_DEF_CHAN_6G(6315, 73), 102 RTW89_DEF_CHAN_6G(6335, 77), 103 RTW89_DEF_CHAN_6G(6355, 81), 104 RTW89_DEF_CHAN_6G(6375, 85), 105 RTW89_DEF_CHAN_6G(6395, 89), 106 RTW89_DEF_CHAN_6G(6415, 93), 107 RTW89_DEF_CHAN_6G(6435, 97), 108 RTW89_DEF_CHAN_6G(6455, 101), 109 RTW89_DEF_CHAN_6G(6475, 105), 110 RTW89_DEF_CHAN_6G(6495, 109), 111 RTW89_DEF_CHAN_6G(6515, 113), 112 RTW89_DEF_CHAN_6G(6535, 117), 113 RTW89_DEF_CHAN_6G(6555, 121), 114 RTW89_DEF_CHAN_6G(6575, 125), 115 RTW89_DEF_CHAN_6G(6595, 129), 116 RTW89_DEF_CHAN_6G(6615, 133), 117 RTW89_DEF_CHAN_6G(6635, 137), 118 RTW89_DEF_CHAN_6G(6655, 141), 119 RTW89_DEF_CHAN_6G(6675, 145), 120 RTW89_DEF_CHAN_6G(6695, 149), 121 RTW89_DEF_CHAN_6G(6715, 153), 122 RTW89_DEF_CHAN_6G(6735, 157), 123 RTW89_DEF_CHAN_6G(6755, 161), 124 RTW89_DEF_CHAN_6G(6775, 165), 125 RTW89_DEF_CHAN_6G(6795, 169), 126 RTW89_DEF_CHAN_6G(6815, 173), 127 RTW89_DEF_CHAN_6G(6835, 177), 128 RTW89_DEF_CHAN_6G(6855, 181), 129 RTW89_DEF_CHAN_6G(6875, 185), 130 RTW89_DEF_CHAN_6G(6895, 189), 131 RTW89_DEF_CHAN_6G(6915, 193), 132 RTW89_DEF_CHAN_6G(6935, 197), 133 RTW89_DEF_CHAN_6G(6955, 201), 134 RTW89_DEF_CHAN_6G(6975, 205), 135 RTW89_DEF_CHAN_6G(6995, 209), 136 RTW89_DEF_CHAN_6G(7015, 213), 137 RTW89_DEF_CHAN_6G(7035, 217), 138 RTW89_DEF_CHAN_6G(7055, 221), 139 RTW89_DEF_CHAN_6G(7075, 225), 140 RTW89_DEF_CHAN_6G(7095, 229), 141 RTW89_DEF_CHAN_6G(7115, 233), 142 }; 143 144 static struct ieee80211_rate rtw89_bitrates[] = { 145 { .bitrate = 10, .hw_value = 0x00, }, 146 { .bitrate = 20, .hw_value = 0x01, }, 147 { .bitrate = 55, .hw_value = 0x02, }, 148 { .bitrate = 110, .hw_value = 0x03, }, 149 { .bitrate = 60, .hw_value = 0x04, }, 150 { .bitrate = 90, .hw_value = 0x05, }, 151 { .bitrate = 120, .hw_value = 0x06, }, 152 { .bitrate = 180, .hw_value = 0x07, }, 153 { .bitrate = 240, .hw_value = 0x08, }, 154 { .bitrate = 360, .hw_value = 0x09, }, 155 { .bitrate = 480, .hw_value = 0x0a, }, 156 { .bitrate = 540, .hw_value = 0x0b, }, 157 }; 158 159 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 160 { 161 struct ieee80211_rate rate; 162 163 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 164 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 165 return false; 166 } 167 168 rate = rtw89_bitrates[rpt_rate]; 169 *bitrate = rate.bitrate; 170 171 return true; 172 } 173 174 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 175 .band = NL80211_BAND_2GHZ, 176 .channels = rtw89_channels_2ghz, 177 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 178 .bitrates = rtw89_bitrates, 179 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 180 .ht_cap = {0}, 181 .vht_cap = {0}, 182 }; 183 184 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 185 .band = NL80211_BAND_5GHZ, 186 .channels = rtw89_channels_5ghz, 187 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 188 189 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 190 .bitrates = rtw89_bitrates + 4, 191 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 192 .ht_cap = {0}, 193 .vht_cap = {0}, 194 }; 195 196 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 197 .band = NL80211_BAND_6GHZ, 198 .channels = rtw89_channels_6ghz, 199 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 200 201 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 202 .bitrates = rtw89_bitrates + 4, 203 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 204 }; 205 206 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 207 struct rtw89_traffic_stats *stats, 208 struct sk_buff *skb, bool tx) 209 { 210 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 211 212 if (!ieee80211_is_data(hdr->frame_control)) 213 return; 214 215 if (is_broadcast_ether_addr(hdr->addr1) || 216 is_multicast_ether_addr(hdr->addr1)) 217 return; 218 219 if (tx) { 220 stats->tx_cnt++; 221 stats->tx_unicast += skb->len; 222 } else { 223 stats->rx_cnt++; 224 stats->rx_unicast += skb->len; 225 } 226 } 227 228 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 229 { 230 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 231 NL80211_CHAN_NO_HT); 232 } 233 234 static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 235 struct rtw89_chan *chan) 236 { 237 struct ieee80211_channel *channel = chandef->chan; 238 enum nl80211_chan_width width = chandef->width; 239 u32 primary_freq, center_freq; 240 u8 center_chan; 241 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 242 u32 offset; 243 u8 band; 244 245 center_chan = channel->hw_value; 246 primary_freq = channel->center_freq; 247 center_freq = chandef->center_freq1; 248 249 switch (width) { 250 case NL80211_CHAN_WIDTH_20_NOHT: 251 case NL80211_CHAN_WIDTH_20: 252 bandwidth = RTW89_CHANNEL_WIDTH_20; 253 break; 254 case NL80211_CHAN_WIDTH_40: 255 bandwidth = RTW89_CHANNEL_WIDTH_40; 256 if (primary_freq > center_freq) { 257 center_chan -= 2; 258 } else { 259 center_chan += 2; 260 } 261 break; 262 case NL80211_CHAN_WIDTH_80: 263 case NL80211_CHAN_WIDTH_160: 264 bandwidth = nl_to_rtw89_bandwidth(width); 265 if (primary_freq > center_freq) { 266 offset = (primary_freq - center_freq - 10) / 20; 267 center_chan -= 2 + offset * 4; 268 } else { 269 offset = (center_freq - primary_freq - 10) / 20; 270 center_chan += 2 + offset * 4; 271 } 272 break; 273 default: 274 center_chan = 0; 275 break; 276 } 277 278 switch (channel->band) { 279 default: 280 case NL80211_BAND_2GHZ: 281 band = RTW89_BAND_2G; 282 break; 283 case NL80211_BAND_5GHZ: 284 band = RTW89_BAND_5G; 285 break; 286 case NL80211_BAND_6GHZ: 287 band = RTW89_BAND_6G; 288 break; 289 } 290 291 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 292 } 293 294 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 295 { 296 const struct rtw89_chip_info *chip = rtwdev->chip; 297 const struct rtw89_chan *chan; 298 enum rtw89_sub_entity_idx sub_entity_idx; 299 enum rtw89_phy_idx phy_idx; 300 enum rtw89_entity_mode mode; 301 bool entity_active; 302 303 entity_active = rtw89_get_entity_state(rtwdev); 304 if (!entity_active) 305 return; 306 307 mode = rtw89_get_entity_mode(rtwdev); 308 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 309 return; 310 311 sub_entity_idx = RTW89_SUB_ENTITY_0; 312 phy_idx = RTW89_PHY_0; 313 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 314 if (chip->ops->set_txpwr) 315 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 316 } 317 318 void rtw89_set_channel(struct rtw89_dev *rtwdev) 319 { 320 const struct rtw89_chip_info *chip = rtwdev->chip; 321 const struct cfg80211_chan_def *chandef; 322 enum rtw89_sub_entity_idx sub_entity_idx; 323 enum rtw89_mac_idx mac_idx; 324 enum rtw89_phy_idx phy_idx; 325 struct rtw89_chan chan; 326 struct rtw89_channel_help_params bak; 327 enum rtw89_entity_mode mode; 328 bool band_changed; 329 bool entity_active; 330 331 entity_active = rtw89_get_entity_state(rtwdev); 332 333 mode = rtw89_entity_recalc(rtwdev); 334 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 335 return; 336 337 sub_entity_idx = RTW89_SUB_ENTITY_0; 338 mac_idx = RTW89_MAC_0; 339 phy_idx = RTW89_PHY_0; 340 chandef = rtw89_chandef_get(rtwdev, sub_entity_idx); 341 rtw89_get_channel_params(chandef, &chan); 342 if (WARN(chan.channel == 0, "Invalid channel\n")) 343 return; 344 345 band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan); 346 347 rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx); 348 349 chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx); 350 351 rtw89_core_set_chip_txpwr(rtwdev); 352 353 rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx); 354 355 if (!entity_active || band_changed) { 356 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type); 357 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 358 } 359 360 rtw89_set_entity_state(rtwdev, true); 361 } 362 363 static enum rtw89_core_tx_type 364 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 365 struct sk_buff *skb) 366 { 367 struct ieee80211_hdr *hdr = (void *)skb->data; 368 __le16 fc = hdr->frame_control; 369 370 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 371 return RTW89_CORE_TX_TYPE_MGMT; 372 373 return RTW89_CORE_TX_TYPE_DATA; 374 } 375 376 static void 377 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 378 struct rtw89_core_tx_request *tx_req, 379 enum btc_pkt_type pkt_type) 380 { 381 struct ieee80211_sta *sta = tx_req->sta; 382 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 383 struct sk_buff *skb = tx_req->skb; 384 struct rtw89_sta *rtwsta; 385 u8 ampdu_num; 386 u8 tid; 387 388 if (pkt_type == PACKET_EAPOL) { 389 desc_info->bk = true; 390 return; 391 } 392 393 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 394 return; 395 396 if (!sta) { 397 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 398 return; 399 } 400 401 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 402 rtwsta = (struct rtw89_sta *)sta->drv_priv; 403 404 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 405 rtwsta->ampdu_params[tid].agg_num : 406 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 407 408 desc_info->agg_en = true; 409 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 410 desc_info->ampdu_num = ampdu_num; 411 } 412 413 static void 414 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 415 struct rtw89_core_tx_request *tx_req) 416 { 417 const struct rtw89_chip_info *chip = rtwdev->chip; 418 struct ieee80211_vif *vif = tx_req->vif; 419 struct ieee80211_sta *sta = tx_req->sta; 420 struct ieee80211_tx_info *info; 421 struct ieee80211_key_conf *key; 422 struct rtw89_vif *rtwvif; 423 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 424 struct rtw89_addr_cam_entry *addr_cam; 425 struct rtw89_sec_cam_entry *sec_cam; 426 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 427 struct sk_buff *skb = tx_req->skb; 428 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 429 u64 pn64; 430 431 if (!vif) { 432 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 433 return; 434 } 435 436 rtwvif = (struct rtw89_vif *)vif->drv_priv; 437 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 438 439 info = IEEE80211_SKB_CB(skb); 440 key = info->control.hw_key; 441 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 442 if (!sec_cam) { 443 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 444 return; 445 } 446 447 switch (key->cipher) { 448 case WLAN_CIPHER_SUITE_WEP40: 449 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 450 break; 451 case WLAN_CIPHER_SUITE_WEP104: 452 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 453 break; 454 case WLAN_CIPHER_SUITE_TKIP: 455 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 456 break; 457 case WLAN_CIPHER_SUITE_CCMP: 458 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 459 break; 460 case WLAN_CIPHER_SUITE_CCMP_256: 461 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 462 break; 463 case WLAN_CIPHER_SUITE_GCMP: 464 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 465 break; 466 case WLAN_CIPHER_SUITE_GCMP_256: 467 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 468 break; 469 default: 470 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 471 return; 472 } 473 474 desc_info->sec_en = true; 475 desc_info->sec_keyid = key->keyidx; 476 desc_info->sec_type = sec_type; 477 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 478 479 if (!chip->hw_sec_hdr) 480 return; 481 482 pn64 = atomic64_inc_return(&key->tx_pn); 483 desc_info->sec_seq[0] = pn64; 484 desc_info->sec_seq[1] = pn64 >> 8; 485 desc_info->sec_seq[2] = pn64 >> 16; 486 desc_info->sec_seq[3] = pn64 >> 24; 487 desc_info->sec_seq[4] = pn64 >> 32; 488 desc_info->sec_seq[5] = pn64 >> 40; 489 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 490 } 491 492 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 493 struct rtw89_core_tx_request *tx_req) 494 { 495 struct sk_buff *skb = tx_req->skb; 496 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 497 struct ieee80211_vif *vif = tx_info->control.vif; 498 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 499 u16 lowest_rate; 500 501 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || vif->p2p) 502 lowest_rate = RTW89_HW_RATE_OFDM6; 503 else if (chan->band_type == RTW89_BAND_2G) 504 lowest_rate = RTW89_HW_RATE_CCK1; 505 else 506 lowest_rate = RTW89_HW_RATE_OFDM6; 507 508 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 509 return lowest_rate; 510 511 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 512 } 513 514 static void 515 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 516 struct rtw89_core_tx_request *tx_req) 517 { 518 struct ieee80211_vif *vif = tx_req->vif; 519 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 520 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 521 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 522 u8 qsel, ch_dma; 523 524 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 525 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 526 527 desc_info->qsel = qsel; 528 desc_info->ch_dma = ch_dma; 529 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 530 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 531 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 532 533 /* fixed data rate for mgmt frames */ 534 desc_info->en_wd_info = true; 535 desc_info->use_rate = true; 536 desc_info->dis_data_fb = true; 537 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); 538 539 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 540 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 541 desc_info->data_rate, chan->channel, chan->band_type, 542 chan->band_width); 543 } 544 545 static void 546 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 547 struct rtw89_core_tx_request *tx_req) 548 { 549 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 550 551 desc_info->is_bmc = false; 552 desc_info->wd_page = false; 553 desc_info->ch_dma = RTW89_DMA_H2C; 554 } 555 556 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) 557 { 558 static const u8 rtw89_bandwidth_to_om[] = { 559 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 560 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 561 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 562 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 563 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 564 }; 565 const struct rtw89_chip_info *chip = rtwdev->chip; 566 struct rtw89_hal *hal = &rtwdev->hal; 567 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 568 u8 om_bandwidth; 569 570 if (!chip->dis_2g_40m_ul_ofdma || 571 chan->band_type != RTW89_BAND_2G || 572 chan->band_width != RTW89_CHANNEL_WIDTH_40) 573 return; 574 575 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 576 rtw89_bandwidth_to_om[chan->band_width] : 0; 577 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 578 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 579 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 580 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 581 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 582 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 583 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 584 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 585 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 586 } 587 588 static bool 589 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 590 struct rtw89_core_tx_request *tx_req, 591 enum btc_pkt_type pkt_type) 592 { 593 struct ieee80211_sta *sta = tx_req->sta; 594 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 595 struct sk_buff *skb = tx_req->skb; 596 struct ieee80211_hdr *hdr = (void *)skb->data; 597 __le16 fc = hdr->frame_control; 598 599 /* AP IOT issue with EAPoL, ARP and DHCP */ 600 if (pkt_type < PACKET_MAX) 601 return false; 602 603 if (!sta || !sta->deflink.he_cap.has_he) 604 return false; 605 606 if (!ieee80211_is_data_qos(fc)) 607 return false; 608 609 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 610 return false; 611 612 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 613 return false; 614 615 return true; 616 } 617 618 static void 619 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 620 struct rtw89_core_tx_request *tx_req) 621 { 622 struct ieee80211_sta *sta = tx_req->sta; 623 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 624 struct sk_buff *skb = tx_req->skb; 625 struct ieee80211_hdr *hdr = (void *)skb->data; 626 __le16 fc = hdr->frame_control; 627 void *data; 628 __le32 *htc; 629 u8 *qc; 630 int hdr_len; 631 632 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 633 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 634 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 635 636 hdr = data; 637 htc = data + hdr_len; 638 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 639 *htc = rtwsta->htc_template ? rtwsta->htc_template : 640 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 641 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 642 643 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 644 qc[0] |= IEEE80211_QOS_CTL_EOSP; 645 } 646 647 static void 648 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 649 struct rtw89_core_tx_request *tx_req, 650 enum btc_pkt_type pkt_type) 651 { 652 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 653 struct ieee80211_vif *vif = tx_req->vif; 654 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 655 656 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 657 goto desc_bk; 658 659 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 660 661 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 662 desc_info->a_ctrl_bsr = true; 663 664 desc_bk: 665 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 666 return; 667 668 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 669 desc_info->bk = true; 670 } 671 672 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 673 struct rtw89_core_tx_request *tx_req) 674 { 675 struct ieee80211_vif *vif = tx_req->vif; 676 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 677 struct ieee80211_sta *sta = tx_req->sta; 678 struct rtw89_sta *rtwsta; 679 680 if (!sta) 681 return rtwvif->mac_id; 682 683 rtwsta = (struct rtw89_sta *)sta->drv_priv; 684 return rtwsta->mac_id; 685 } 686 687 static void 688 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 689 struct rtw89_core_tx_request *tx_req) 690 { 691 struct ieee80211_vif *vif = tx_req->vif; 692 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 693 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 694 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 695 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 696 struct sk_buff *skb = tx_req->skb; 697 u8 tid, tid_indicate; 698 u8 qsel, ch_dma; 699 700 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 701 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 702 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 703 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 704 705 desc_info->ch_dma = ch_dma; 706 desc_info->tid_indicate = tid_indicate; 707 desc_info->qsel = qsel; 708 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 709 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 710 711 /* enable wd_info for AMPDU */ 712 desc_info->en_wd_info = true; 713 714 if (IEEE80211_SKB_CB(skb)->control.hw_key) 715 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 716 717 if (vif->p2p) 718 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 719 else if (rate_pattern->enable) 720 desc_info->data_retry_lowest_rate = rate_pattern->rate; 721 else if (chan->band_type == RTW89_BAND_2G) 722 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_CCK1; 723 else 724 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 725 } 726 727 static enum btc_pkt_type 728 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 729 struct rtw89_core_tx_request *tx_req) 730 { 731 struct sk_buff *skb = tx_req->skb; 732 struct udphdr *udphdr; 733 734 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 735 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 736 return PACKET_EAPOL; 737 } 738 739 if (skb->protocol == htons(ETH_P_ARP)) { 740 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 741 return PACKET_ARP; 742 } 743 744 if (skb->protocol == htons(ETH_P_IP) && 745 ip_hdr(skb)->protocol == IPPROTO_UDP) { 746 udphdr = udp_hdr(skb); 747 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 748 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 749 skb->len > 282) { 750 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 751 return PACKET_DHCP; 752 } 753 } 754 755 if (skb->protocol == htons(ETH_P_IP) && 756 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 757 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 758 return PACKET_ICMP; 759 } 760 761 return PACKET_MAX; 762 } 763 764 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 765 struct rtw89_tx_desc_info *desc_info, 766 struct sk_buff *skb) 767 { 768 struct ieee80211_hdr *hdr = (void *)skb->data; 769 __le16 fc = hdr->frame_control; 770 771 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 772 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 773 } 774 775 static void 776 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 777 struct rtw89_core_tx_request *tx_req) 778 { 779 const struct rtw89_chip_info *chip = rtwdev->chip; 780 781 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 782 return; 783 784 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 785 return; 786 787 if (chip->chip_id != RTL8852C && 788 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 789 return; 790 791 rtw89_mac_notify_wake(rtwdev); 792 } 793 794 static void 795 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 796 struct rtw89_core_tx_request *tx_req) 797 { 798 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 799 struct sk_buff *skb = tx_req->skb; 800 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 801 struct ieee80211_hdr *hdr = (void *)skb->data; 802 enum rtw89_core_tx_type tx_type; 803 enum btc_pkt_type pkt_type; 804 bool is_bmc; 805 u16 seq; 806 807 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 808 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 809 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 810 tx_req->tx_type = tx_type; 811 } 812 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 813 is_multicast_ether_addr(hdr->addr1)); 814 815 desc_info->seq = seq; 816 desc_info->pkt_size = skb->len; 817 desc_info->is_bmc = is_bmc; 818 desc_info->wd_page = true; 819 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 820 821 switch (tx_req->tx_type) { 822 case RTW89_CORE_TX_TYPE_MGMT: 823 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 824 break; 825 case RTW89_CORE_TX_TYPE_DATA: 826 rtw89_core_tx_update_data_info(rtwdev, tx_req); 827 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 828 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 829 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 830 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 831 break; 832 case RTW89_CORE_TX_TYPE_FWCMD: 833 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 834 break; 835 } 836 } 837 838 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 839 { 840 u8 ch_dma; 841 842 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 843 844 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 845 } 846 847 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 848 struct sk_buff *skb, bool fwdl) 849 { 850 struct rtw89_core_tx_request tx_req = {0}; 851 u32 cnt; 852 int ret; 853 854 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 855 rtw89_debug(rtwdev, RTW89_DBG_FW, 856 "ignore h2c due to power is off with firmware state=%d\n", 857 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 858 dev_kfree_skb(skb); 859 return 0; 860 } 861 862 tx_req.skb = skb; 863 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 864 if (fwdl) 865 tx_req.desc_info.fw_dl = true; 866 867 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 868 869 if (!fwdl) 870 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 871 872 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 873 if (cnt == 0) { 874 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 875 return -ENOSPC; 876 } 877 878 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 879 if (ret) { 880 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 881 return ret; 882 } 883 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 884 885 return 0; 886 } 887 888 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 889 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 890 { 891 struct rtw89_core_tx_request tx_req = {0}; 892 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 893 int ret; 894 895 tx_req.skb = skb; 896 tx_req.sta = sta; 897 tx_req.vif = vif; 898 899 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 900 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 901 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 902 rtw89_core_tx_wake(rtwdev, &tx_req); 903 904 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 905 if (ret) { 906 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 907 return ret; 908 } 909 910 if (qsel) 911 *qsel = tx_req.desc_info.qsel; 912 913 return 0; 914 } 915 916 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 917 { 918 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 919 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 920 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 921 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 922 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 923 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 924 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 925 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 926 927 return cpu_to_le32(dword); 928 } 929 930 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 931 { 932 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 933 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 934 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 935 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 936 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 937 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 938 939 return cpu_to_le32(dword); 940 } 941 942 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 943 { 944 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 945 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 946 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 947 948 return cpu_to_le32(dword); 949 } 950 951 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 952 { 953 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 954 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 955 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 956 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 957 958 return cpu_to_le32(dword); 959 } 960 961 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 962 { 963 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 964 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 965 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 966 967 return cpu_to_le32(dword); 968 } 969 970 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 971 { 972 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 973 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 974 975 return cpu_to_le32(dword); 976 } 977 978 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 979 { 980 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 981 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 982 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 983 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 984 985 return cpu_to_le32(dword); 986 } 987 988 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 989 { 990 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 991 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 992 993 return cpu_to_le32(dword); 994 } 995 996 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 997 { 998 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 999 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1000 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1001 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1002 1003 return cpu_to_le32(dword); 1004 } 1005 1006 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1007 { 1008 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1009 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1010 1011 return cpu_to_le32(dword); 1012 } 1013 1014 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1015 { 1016 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1017 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1018 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1019 desc_info->data_retry_lowest_rate); 1020 1021 return cpu_to_le32(dword); 1022 } 1023 1024 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1025 { 1026 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1027 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1028 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1029 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1030 1031 return cpu_to_le32(dword); 1032 } 1033 1034 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1035 { 1036 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1037 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1038 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1039 1040 return cpu_to_le32(dword); 1041 } 1042 1043 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1044 { 1045 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1046 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1047 1048 return cpu_to_le32(dword); 1049 } 1050 1051 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1052 struct rtw89_tx_desc_info *desc_info, 1053 void *txdesc) 1054 { 1055 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1056 struct rtw89_txwd_info *txwd_info; 1057 1058 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1059 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1060 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1061 1062 if (!desc_info->en_wd_info) 1063 return; 1064 1065 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1066 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1067 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1068 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1069 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1070 1071 } 1072 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1073 1074 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1075 struct rtw89_tx_desc_info *desc_info, 1076 void *txdesc) 1077 { 1078 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1079 struct rtw89_txwd_info *txwd_info; 1080 1081 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1082 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1083 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1084 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1085 if (desc_info->sec_en) { 1086 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1087 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1088 } 1089 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1090 1091 if (!desc_info->en_wd_info) 1092 return; 1093 1094 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1095 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1096 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1097 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1098 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1099 } 1100 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1101 1102 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1103 { 1104 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1105 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1106 RTW89_CORE_RX_TYPE_FWDL : 1107 RTW89_CORE_RX_TYPE_H2C); 1108 1109 return cpu_to_le32(dword); 1110 } 1111 1112 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1113 struct rtw89_tx_desc_info *desc_info, 1114 void *txdesc) 1115 { 1116 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1117 1118 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1119 } 1120 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1121 1122 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1123 struct sk_buff *skb, 1124 struct rtw89_rx_phy_ppdu *phy_ppdu) 1125 { 1126 bool rx_cnt_valid = false; 1127 u8 plcp_size = 0; 1128 u8 usr_num = 0; 1129 u8 *phy_sts; 1130 1131 rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); 1132 plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; 1133 usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); 1134 if (usr_num > RTW89_PPDU_MAX_USR) { 1135 rtw89_warn(rtwdev, "Invalid user number in mac info\n"); 1136 return -EINVAL; 1137 } 1138 1139 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1140 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1141 /* 8-byte alignment */ 1142 if (usr_num & BIT(0)) 1143 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1144 if (rx_cnt_valid) 1145 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; 1146 phy_sts += plcp_size; 1147 1148 phy_ppdu->buf = phy_sts; 1149 phy_ppdu->len = skb->data + skb->len - phy_sts; 1150 1151 return 0; 1152 } 1153 1154 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1155 struct ieee80211_sta *sta) 1156 { 1157 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1158 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1159 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1160 int i; 1161 1162 if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) { 1163 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1164 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1165 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1166 } 1167 } 1168 1169 #define VAR_LEN 0xff 1170 #define VAR_LEN_UNIT 8 1171 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) 1172 { 1173 static const u8 physts_ie_len_tab[32] = { 1174 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1175 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1176 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1177 }; 1178 u16 ie_len; 1179 u8 ie; 1180 1181 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1182 if (physts_ie_len_tab[ie] != VAR_LEN) 1183 ie_len = physts_ie_len_tab[ie]; 1184 else 1185 ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; 1186 1187 return ie_len; 1188 } 1189 1190 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, 1191 struct rtw89_rx_phy_ppdu *phy_ppdu) 1192 { 1193 s16 cfo; 1194 1195 phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr); 1196 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1197 return; 1198 /* sign conversion for S(12,2) */ 1199 if (rtwdev->chip->cfo_src_fd) 1200 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_FD_CFO(addr), 11); 1201 else 1202 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_PREMB_CFO(addr), 11); 1203 1204 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1205 } 1206 1207 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, 1208 struct rtw89_rx_phy_ppdu *phy_ppdu) 1209 { 1210 u8 ie; 1211 1212 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1213 switch (ie) { 1214 case RTW89_PHYSTS_IE01_CMN_OFDM: 1215 rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); 1216 break; 1217 default: 1218 break; 1219 } 1220 1221 return 0; 1222 } 1223 1224 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1225 { 1226 u8 *rssi = phy_ppdu->rssi; 1227 u8 *buf = phy_ppdu->buf; 1228 1229 phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf); 1230 phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); 1231 rssi[RF_PATH_A] = RTW89_GET_PHY_STS_RSSI_A(buf); 1232 rssi[RF_PATH_B] = RTW89_GET_PHY_STS_RSSI_B(buf); 1233 rssi[RF_PATH_C] = RTW89_GET_PHY_STS_RSSI_C(buf); 1234 rssi[RF_PATH_D] = RTW89_GET_PHY_STS_RSSI_D(buf); 1235 } 1236 1237 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1238 struct rtw89_rx_phy_ppdu *phy_ppdu) 1239 { 1240 if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { 1241 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1242 return -EINVAL; 1243 } 1244 rtw89_core_update_phy_ppdu(phy_ppdu); 1245 ieee80211_iterate_stations_atomic(rtwdev->hw, 1246 rtw89_core_rx_process_phy_ppdu_iter, 1247 phy_ppdu); 1248 1249 return 0; 1250 } 1251 1252 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1253 struct rtw89_rx_phy_ppdu *phy_ppdu) 1254 { 1255 u16 ie_len; 1256 u8 *pos, *end; 1257 1258 /* mark invalid reports and bypass them */ 1259 if (phy_ppdu->ie < RTW89_CCK_PKT) 1260 return -EINVAL; 1261 1262 if (!phy_ppdu->to_self) 1263 return 0; 1264 1265 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1266 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1267 while (pos < end) { 1268 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); 1269 rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); 1270 pos += ie_len; 1271 if (pos > end || ie_len == 0) { 1272 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1273 "phy status parse failed\n"); 1274 return -EINVAL; 1275 } 1276 } 1277 1278 return 0; 1279 } 1280 1281 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1282 struct rtw89_rx_phy_ppdu *phy_ppdu) 1283 { 1284 int ret; 1285 1286 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1287 if (ret) 1288 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1289 else 1290 phy_ppdu->valid = true; 1291 } 1292 1293 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1294 const struct rtw89_rx_desc_info *desc_info, 1295 bool rx_status) 1296 { 1297 switch (desc_info->gi_ltf) { 1298 case RTW89_GILTF_SGI_4XHE08: 1299 case RTW89_GILTF_2XHE08: 1300 case RTW89_GILTF_1XHE08: 1301 return NL80211_RATE_INFO_HE_GI_0_8; 1302 case RTW89_GILTF_2XHE16: 1303 case RTW89_GILTF_1XHE16: 1304 return NL80211_RATE_INFO_HE_GI_1_6; 1305 case RTW89_GILTF_LGI_4XHE32: 1306 return NL80211_RATE_INFO_HE_GI_3_2; 1307 default: 1308 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); 1309 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; 1310 } 1311 } 1312 1313 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1314 struct rtw89_rx_desc_info *desc_info, 1315 struct ieee80211_rx_status *status) 1316 { 1317 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1318 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1319 u16 data_rate; 1320 bool ret; 1321 1322 data_rate = desc_info->data_rate; 1323 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1324 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1325 rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1326 /* rate_idx is still hardware value here */ 1327 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1328 rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1329 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1330 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1331 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1332 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1333 } else { 1334 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1335 } 1336 1337 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1338 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); 1339 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1340 status->rate_idx == rate_idx && 1341 status->he_gi == gi_ltf && 1342 status->bw == bw; 1343 1344 return ret; 1345 } 1346 1347 struct rtw89_vif_rx_stats_iter_data { 1348 struct rtw89_dev *rtwdev; 1349 struct rtw89_rx_phy_ppdu *phy_ppdu; 1350 struct rtw89_rx_desc_info *desc_info; 1351 struct sk_buff *skb; 1352 const u8 *bssid; 1353 }; 1354 1355 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1356 struct ieee80211_vif *vif, 1357 struct sk_buff *skb) 1358 { 1359 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1360 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1361 u8 *pos, *end, type; 1362 u16 aid; 1363 1364 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1365 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1366 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1367 return; 1368 1369 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1370 if (type != IEEE80211_TRIGGER_TYPE_BASIC) 1371 return; 1372 1373 end = (u8 *)tf + skb->len; 1374 pos = tf->variable; 1375 1376 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1377 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1378 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1379 "[TF] aid: %d, ul_mcs: %d, rua: %d\n", 1380 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1381 RTW89_GET_TF_USER_INFO_RUA(pos)); 1382 1383 if (aid == RTW89_TF_PAD) 1384 break; 1385 1386 if (aid == vif->cfg.aid) { 1387 rtwvif->stats.rx_tf_acc++; 1388 rtwdev->stats.rx_tf_acc++; 1389 break; 1390 } 1391 1392 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1393 } 1394 } 1395 1396 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1397 struct ieee80211_vif *vif) 1398 { 1399 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1400 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1401 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1402 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1403 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1404 struct sk_buff *skb = iter_data->skb; 1405 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1406 const u8 *bssid = iter_data->bssid; 1407 1408 if (!vif->bss_conf.bssid) 1409 return; 1410 1411 if (ieee80211_is_trigger(hdr->frame_control)) { 1412 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1413 return; 1414 } 1415 1416 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1417 return; 1418 1419 if (ieee80211_is_beacon(hdr->frame_control)) 1420 pkt_stat->beacon_nr++; 1421 1422 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1423 return; 1424 1425 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1426 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1427 1428 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1429 } 1430 1431 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1432 struct rtw89_rx_phy_ppdu *phy_ppdu, 1433 struct rtw89_rx_desc_info *desc_info, 1434 struct sk_buff *skb) 1435 { 1436 struct rtw89_vif_rx_stats_iter_data iter_data; 1437 1438 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1439 1440 iter_data.rtwdev = rtwdev; 1441 iter_data.phy_ppdu = phy_ppdu; 1442 iter_data.desc_info = desc_info; 1443 iter_data.skb = skb; 1444 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1445 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1446 } 1447 1448 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1449 struct ieee80211_rx_status *status) 1450 { 1451 const struct rtw89_chan_rcd *rcd = 1452 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1453 u16 chan = rcd->prev_primary_channel; 1454 u8 band = rcd->prev_band_type == RTW89_BAND_2G ? 1455 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1456 1457 if (status->band != NL80211_BAND_2GHZ && 1458 status->encoding == RX_ENC_LEGACY && 1459 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1460 status->freq = ieee80211_channel_to_frequency(chan, band); 1461 status->band = band; 1462 } 1463 } 1464 1465 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1466 { 1467 if (rx_status->band == NL80211_BAND_2GHZ || 1468 rx_status->encoding != RX_ENC_LEGACY) 1469 return; 1470 1471 /* Some control frames' freq(ACKs in this case) are reported wrong due 1472 * to FW notify timing, set to lowest rate to prevent overflow. 1473 */ 1474 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1475 rx_status->rate_idx = 0; 1476 return; 1477 } 1478 1479 /* No 4 CCK rates for non-2G */ 1480 rx_status->rate_idx -= 4; 1481 } 1482 1483 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 1484 struct sk_buff *skb, 1485 struct ieee80211_rx_status *rx_status) 1486 { 1487 static const struct ieee80211_radiotap_he known_he = { 1488 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1489 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 1490 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 1491 }; 1492 struct ieee80211_radiotap_he *he; 1493 1494 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 1495 return; 1496 1497 if (rx_status->encoding == RX_ENC_HE) { 1498 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 1499 he = skb_push(skb, sizeof(*he)); 1500 *he = known_he; 1501 } 1502 } 1503 1504 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 1505 struct rtw89_rx_phy_ppdu *phy_ppdu, 1506 struct rtw89_rx_desc_info *desc_info, 1507 struct sk_buff *skb_ppdu, 1508 struct ieee80211_rx_status *rx_status) 1509 { 1510 struct napi_struct *napi = &rtwdev->napi; 1511 1512 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 1513 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state))) 1514 napi = NULL; 1515 1516 rtw89_core_hw_to_sband_rate(rx_status); 1517 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 1518 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 1519 /* In low power mode, it does RX in thread context. */ 1520 local_bh_disable(); 1521 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 1522 local_bh_enable(); 1523 rtwdev->napi_budget_countdown--; 1524 } 1525 1526 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 1527 struct rtw89_rx_phy_ppdu *phy_ppdu, 1528 struct rtw89_rx_desc_info *desc_info, 1529 struct sk_buff *skb) 1530 { 1531 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1532 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 1533 struct sk_buff *skb_ppdu = NULL, *tmp; 1534 struct ieee80211_rx_status *rx_status; 1535 1536 if (curr > RTW89_MAX_PPDU_CNT) 1537 return; 1538 1539 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 1540 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 1541 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1542 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 1543 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 1544 rtw89_correct_cck_chan(rtwdev, rx_status); 1545 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 1546 } 1547 } 1548 1549 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 1550 struct rtw89_rx_desc_info *desc_info, 1551 struct sk_buff *skb) 1552 { 1553 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 1554 .len = skb->len, 1555 .to_self = desc_info->addr1_match, 1556 .rate = desc_info->data_rate, 1557 .mac_id = desc_info->mac_id}; 1558 int ret; 1559 1560 if (desc_info->mac_info_valid) 1561 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 1562 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 1563 if (ret) 1564 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); 1565 1566 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 1567 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 1568 dev_kfree_skb_any(skb); 1569 } 1570 1571 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 1572 struct rtw89_rx_desc_info *desc_info, 1573 struct sk_buff *skb) 1574 { 1575 switch (desc_info->pkt_type) { 1576 case RTW89_CORE_RX_TYPE_C2H: 1577 rtw89_fw_c2h_irqsafe(rtwdev, skb); 1578 break; 1579 case RTW89_CORE_RX_TYPE_PPDU_STAT: 1580 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 1581 break; 1582 default: 1583 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 1584 desc_info->pkt_type); 1585 dev_kfree_skb_any(skb); 1586 break; 1587 } 1588 } 1589 1590 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 1591 struct rtw89_rx_desc_info *desc_info, 1592 u8 *data, u32 data_offset) 1593 { 1594 const struct rtw89_chip_info *chip = rtwdev->chip; 1595 struct rtw89_rxdesc_short *rxd_s; 1596 struct rtw89_rxdesc_long *rxd_l; 1597 u8 shift_len, drv_info_len; 1598 1599 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 1600 desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); 1601 desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); 1602 desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); 1603 desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); 1604 desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); 1605 if (chip->chip_id == RTL8852C) 1606 desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s); 1607 else 1608 desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); 1609 desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); 1610 desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); 1611 desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); 1612 desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); 1613 desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); 1614 desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); 1615 desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); 1616 desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); 1617 desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); 1618 desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); 1619 desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); 1620 desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); 1621 1622 shift_len = desc_info->shift << 1; /* 2-byte unit */ 1623 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 1624 desc_info->offset = data_offset + shift_len + drv_info_len; 1625 desc_info->ready = true; 1626 1627 if (!desc_info->long_rxdesc) 1628 return; 1629 1630 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 1631 desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); 1632 desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); 1633 desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); 1634 desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); 1635 desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); 1636 desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); 1637 } 1638 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 1639 1640 struct rtw89_core_iter_rx_status { 1641 struct rtw89_dev *rtwdev; 1642 struct ieee80211_rx_status *rx_status; 1643 struct rtw89_rx_desc_info *desc_info; 1644 u8 mac_id; 1645 }; 1646 1647 static 1648 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 1649 { 1650 struct rtw89_core_iter_rx_status *iter_data = 1651 (struct rtw89_core_iter_rx_status *)data; 1652 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 1653 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1654 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1655 u8 mac_id = iter_data->mac_id; 1656 1657 if (mac_id != rtwsta->mac_id) 1658 return; 1659 1660 rtwsta->rx_status = *rx_status; 1661 rtwsta->rx_hw_rate = desc_info->data_rate; 1662 } 1663 1664 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 1665 struct rtw89_rx_desc_info *desc_info, 1666 struct ieee80211_rx_status *rx_status) 1667 { 1668 struct rtw89_core_iter_rx_status iter_data; 1669 1670 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 1671 return; 1672 1673 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 1674 return; 1675 1676 iter_data.rtwdev = rtwdev; 1677 iter_data.rx_status = rx_status; 1678 iter_data.desc_info = desc_info; 1679 iter_data.mac_id = desc_info->mac_id; 1680 ieee80211_iterate_stations_atomic(rtwdev->hw, 1681 rtw89_core_stats_sta_rx_status_iter, 1682 &iter_data); 1683 } 1684 1685 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 1686 struct rtw89_rx_desc_info *desc_info, 1687 struct ieee80211_rx_status *rx_status) 1688 { 1689 const struct cfg80211_chan_def *chandef = 1690 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 1691 const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1692 u16 data_rate; 1693 u8 data_rate_mode; 1694 1695 /* currently using single PHY */ 1696 rx_status->freq = chandef->chan->center_freq; 1697 rx_status->band = chandef->chan->band; 1698 1699 if (rtwdev->scanning && 1700 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 1701 u8 chan = cur->primary_channel; 1702 u8 band = cur->band_type; 1703 enum nl80211_band nl_band; 1704 1705 nl_band = rtw89_hw_to_nl80211_band(band); 1706 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 1707 rx_status->band = nl_band; 1708 } 1709 1710 if (desc_info->icv_err || desc_info->crc32_err) 1711 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 1712 1713 if (desc_info->hw_dec && 1714 !(desc_info->sw_dec || desc_info->icv_err)) 1715 rx_status->flag |= RX_FLAG_DECRYPTED; 1716 1717 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1718 1719 data_rate = desc_info->data_rate; 1720 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1721 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1722 rx_status->encoding = RX_ENC_LEGACY; 1723 rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1724 /* convert rate_idx after we get the correct band */ 1725 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1726 rx_status->encoding = RX_ENC_HT; 1727 rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1728 if (desc_info->gi_ltf) 1729 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1730 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1731 rx_status->encoding = RX_ENC_VHT; 1732 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1733 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1734 if (desc_info->gi_ltf) 1735 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1736 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1737 rx_status->encoding = RX_ENC_HE; 1738 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1739 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1740 } else { 1741 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1742 } 1743 1744 /* he_gi is used to match ppdu, so we always fill it. */ 1745 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); 1746 rx_status->flag |= RX_FLAG_MACTIME_START; 1747 rx_status->mactime = desc_info->free_run_cnt; 1748 1749 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 1750 } 1751 1752 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 1753 { 1754 const struct rtw89_chip_info *chip = rtwdev->chip; 1755 1756 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 1757 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 1758 return RTW89_PS_MODE_NONE; 1759 1760 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) 1761 return RTW89_PS_MODE_PWR_GATED; 1762 1763 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 1764 return RTW89_PS_MODE_CLK_GATED; 1765 1766 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 1767 return RTW89_PS_MODE_RFOFF; 1768 1769 return RTW89_PS_MODE_NONE; 1770 } 1771 1772 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 1773 struct rtw89_rx_desc_info *desc_info) 1774 { 1775 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1776 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1777 struct ieee80211_rx_status *rx_status; 1778 struct sk_buff *skb_ppdu, *tmp; 1779 1780 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 1781 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 1782 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1783 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 1784 } 1785 } 1786 1787 void rtw89_core_rx(struct rtw89_dev *rtwdev, 1788 struct rtw89_rx_desc_info *desc_info, 1789 struct sk_buff *skb) 1790 { 1791 struct ieee80211_rx_status *rx_status; 1792 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1793 u8 ppdu_cnt = desc_info->ppdu_cnt; 1794 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1795 1796 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 1797 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 1798 return; 1799 } 1800 1801 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 1802 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 1803 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 1804 } 1805 1806 rx_status = IEEE80211_SKB_RXCB(skb); 1807 memset(rx_status, 0, sizeof(*rx_status)); 1808 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 1809 if (desc_info->long_rxdesc && 1810 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 1811 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 1812 else 1813 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 1814 } 1815 EXPORT_SYMBOL(rtw89_core_rx); 1816 1817 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 1818 { 1819 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1820 return; 1821 1822 napi_enable(&rtwdev->napi); 1823 } 1824 EXPORT_SYMBOL(rtw89_core_napi_start); 1825 1826 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 1827 { 1828 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1829 return; 1830 1831 napi_synchronize(&rtwdev->napi); 1832 napi_disable(&rtwdev->napi); 1833 } 1834 EXPORT_SYMBOL(rtw89_core_napi_stop); 1835 1836 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 1837 { 1838 init_dummy_netdev(&rtwdev->netdev); 1839 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 1840 rtwdev->hci.ops->napi_poll); 1841 } 1842 EXPORT_SYMBOL(rtw89_core_napi_init); 1843 1844 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 1845 { 1846 rtw89_core_napi_stop(rtwdev); 1847 netif_napi_del(&rtwdev->napi); 1848 } 1849 EXPORT_SYMBOL(rtw89_core_napi_deinit); 1850 1851 static void rtw89_core_ba_work(struct work_struct *work) 1852 { 1853 struct rtw89_dev *rtwdev = 1854 container_of(work, struct rtw89_dev, ba_work); 1855 struct rtw89_txq *rtwtxq, *tmp; 1856 int ret; 1857 1858 spin_lock_bh(&rtwdev->ba_lock); 1859 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1860 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1861 struct ieee80211_sta *sta = txq->sta; 1862 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1863 u8 tid = txq->tid; 1864 1865 if (!sta) { 1866 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 1867 goto skip_ba_work; 1868 } 1869 1870 if (rtwsta->disassoc) { 1871 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1872 "cannot start BA with disassoc sta\n"); 1873 goto skip_ba_work; 1874 } 1875 1876 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 1877 if (ret) { 1878 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1879 "failed to setup BA session for %pM:%2d: %d\n", 1880 sta->addr, tid, ret); 1881 if (ret == -EINVAL) 1882 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 1883 } 1884 skip_ba_work: 1885 list_del_init(&rtwtxq->list); 1886 } 1887 spin_unlock_bh(&rtwdev->ba_lock); 1888 } 1889 1890 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 1891 struct ieee80211_sta *sta) 1892 { 1893 struct rtw89_txq *rtwtxq, *tmp; 1894 1895 spin_lock_bh(&rtwdev->ba_lock); 1896 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1897 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1898 1899 if (sta == txq->sta) 1900 list_del_init(&rtwtxq->list); 1901 } 1902 spin_unlock_bh(&rtwdev->ba_lock); 1903 } 1904 1905 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 1906 struct ieee80211_sta *sta) 1907 { 1908 struct rtw89_txq *rtwtxq, *tmp; 1909 1910 spin_lock_bh(&rtwdev->ba_lock); 1911 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 1912 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1913 1914 if (sta == txq->sta) { 1915 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 1916 list_del_init(&rtwtxq->list); 1917 } 1918 } 1919 spin_unlock_bh(&rtwdev->ba_lock); 1920 } 1921 1922 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 1923 struct rtw89_txq *rtwtxq) 1924 { 1925 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1926 struct ieee80211_sta *sta = txq->sta; 1927 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1928 1929 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 1930 return; 1931 1932 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 1933 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1934 return; 1935 1936 spin_lock_bh(&rtwdev->ba_lock); 1937 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1938 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 1939 spin_unlock_bh(&rtwdev->ba_lock); 1940 1941 ieee80211_stop_tx_ba_session(sta, txq->tid); 1942 cancel_delayed_work(&rtwdev->forbid_ba_work); 1943 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 1944 RTW89_FORBID_BA_TIMER); 1945 } 1946 1947 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 1948 struct rtw89_txq *rtwtxq, 1949 struct sk_buff *skb) 1950 { 1951 struct ieee80211_hw *hw = rtwdev->hw; 1952 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1953 struct ieee80211_sta *sta = txq->sta; 1954 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1955 1956 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1957 return; 1958 1959 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 1960 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 1961 return; 1962 } 1963 1964 if (unlikely(!sta)) 1965 return; 1966 1967 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 1968 return; 1969 1970 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 1971 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 1972 return; 1973 } 1974 1975 spin_lock_bh(&rtwdev->ba_lock); 1976 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 1977 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 1978 ieee80211_queue_work(hw, &rtwdev->ba_work); 1979 } 1980 spin_unlock_bh(&rtwdev->ba_lock); 1981 } 1982 1983 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 1984 struct rtw89_txq *rtwtxq, 1985 unsigned long frame_cnt, 1986 unsigned long byte_cnt) 1987 { 1988 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1989 struct ieee80211_vif *vif = txq->vif; 1990 struct ieee80211_sta *sta = txq->sta; 1991 struct sk_buff *skb; 1992 unsigned long i; 1993 int ret; 1994 1995 rcu_read_lock(); 1996 for (i = 0; i < frame_cnt; i++) { 1997 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 1998 if (!skb) { 1999 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2000 goto out; 2001 } 2002 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2003 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2004 if (ret) { 2005 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2006 ieee80211_free_txskb(rtwdev->hw, skb); 2007 break; 2008 } 2009 } 2010 out: 2011 rcu_read_unlock(); 2012 } 2013 2014 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2015 { 2016 u8 qsel, ch_dma; 2017 2018 qsel = rtw89_core_get_qsel(rtwdev, tid); 2019 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2020 2021 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2022 } 2023 2024 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2025 struct ieee80211_txq *txq, 2026 unsigned long *frame_cnt, 2027 bool *sched_txq, bool *reinvoke) 2028 { 2029 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2030 struct ieee80211_sta *sta = txq->sta; 2031 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2032 2033 if (!sta || rtwsta->max_agg_wait <= 0) 2034 return false; 2035 2036 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2037 return false; 2038 2039 if (*frame_cnt > 1) { 2040 *frame_cnt -= 1; 2041 *sched_txq = true; 2042 *reinvoke = true; 2043 rtwtxq->wait_cnt = 1; 2044 return false; 2045 } 2046 2047 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2048 *reinvoke = true; 2049 rtwtxq->wait_cnt++; 2050 return true; 2051 } 2052 2053 rtwtxq->wait_cnt = 0; 2054 return false; 2055 } 2056 2057 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2058 { 2059 struct ieee80211_hw *hw = rtwdev->hw; 2060 struct ieee80211_txq *txq; 2061 struct rtw89_txq *rtwtxq; 2062 unsigned long frame_cnt; 2063 unsigned long byte_cnt; 2064 u32 tx_resource; 2065 bool sched_txq; 2066 2067 ieee80211_txq_schedule_start(hw, ac); 2068 while ((txq = ieee80211_next_txq(hw, ac))) { 2069 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2070 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2071 sched_txq = false; 2072 2073 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2074 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2075 ieee80211_return_txq(hw, txq, true); 2076 continue; 2077 } 2078 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2079 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2080 ieee80211_return_txq(hw, txq, sched_txq); 2081 if (frame_cnt != 0) 2082 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2083 2084 /* bound of tx_resource could get stuck due to burst traffic */ 2085 if (frame_cnt == tx_resource) 2086 *reinvoke = true; 2087 } 2088 ieee80211_txq_schedule_end(hw, ac); 2089 } 2090 2091 static void rtw89_ips_work(struct work_struct *work) 2092 { 2093 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2094 ips_work); 2095 mutex_lock(&rtwdev->mutex); 2096 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 2097 rtw89_enter_ips(rtwdev); 2098 mutex_unlock(&rtwdev->mutex); 2099 } 2100 2101 static void rtw89_core_txq_work(struct work_struct *w) 2102 { 2103 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2104 bool reinvoke = false; 2105 u8 ac; 2106 2107 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2108 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2109 2110 if (reinvoke) { 2111 /* reinvoke to process the last frame */ 2112 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2113 } 2114 } 2115 2116 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2117 { 2118 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2119 txq_reinvoke_work.work); 2120 2121 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2122 } 2123 2124 static void rtw89_forbid_ba_work(struct work_struct *w) 2125 { 2126 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2127 forbid_ba_work.work); 2128 struct rtw89_txq *rtwtxq, *tmp; 2129 2130 spin_lock_bh(&rtwdev->ba_lock); 2131 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2132 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2133 list_del_init(&rtwtxq->list); 2134 } 2135 spin_unlock_bh(&rtwdev->ba_lock); 2136 } 2137 2138 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2139 u32 throughput, u64 cnt) 2140 { 2141 if (cnt < 100) 2142 return RTW89_TFC_IDLE; 2143 if (throughput > 50) 2144 return RTW89_TFC_HIGH; 2145 if (throughput > 10) 2146 return RTW89_TFC_MID; 2147 if (throughput > 2) 2148 return RTW89_TFC_LOW; 2149 return RTW89_TFC_ULTRA_LOW; 2150 } 2151 2152 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2153 struct rtw89_traffic_stats *stats) 2154 { 2155 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2156 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2157 2158 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2159 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2160 2161 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 2162 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 2163 2164 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 2165 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 2166 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 2167 stats->tx_cnt); 2168 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 2169 stats->rx_cnt); 2170 stats->tx_avg_len = stats->tx_cnt ? 2171 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 2172 stats->rx_avg_len = stats->rx_cnt ? 2173 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 2174 2175 stats->tx_unicast = 0; 2176 stats->rx_unicast = 0; 2177 stats->tx_cnt = 0; 2178 stats->rx_cnt = 0; 2179 stats->rx_tf_periodic = stats->rx_tf_acc; 2180 stats->rx_tf_acc = 0; 2181 2182 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 2183 return true; 2184 2185 return false; 2186 } 2187 2188 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 2189 { 2190 struct rtw89_vif *rtwvif; 2191 bool tfc_changed; 2192 2193 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 2194 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2195 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 2196 2197 return tfc_changed; 2198 } 2199 2200 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2201 { 2202 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 2203 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) 2204 return; 2205 2206 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 2207 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 2208 rtw89_enter_lps(rtwdev, rtwvif); 2209 } 2210 2211 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 2212 { 2213 struct rtw89_vif *rtwvif; 2214 2215 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2216 rtw89_vif_enter_lps(rtwdev, rtwvif); 2217 } 2218 2219 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 2220 struct rtw89_traffic_stats *stats) 2221 { 2222 stats->tx_unicast = 0; 2223 stats->rx_unicast = 0; 2224 stats->tx_cnt = 0; 2225 stats->rx_cnt = 0; 2226 ewma_tp_init(&stats->tx_ewma_tp); 2227 ewma_tp_init(&stats->rx_ewma_tp); 2228 } 2229 2230 static void rtw89_track_work(struct work_struct *work) 2231 { 2232 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2233 track_work.work); 2234 bool tfc_changed; 2235 2236 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 2237 return; 2238 2239 mutex_lock(&rtwdev->mutex); 2240 2241 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2242 goto out; 2243 2244 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2245 RTW89_TRACK_WORK_PERIOD); 2246 2247 tfc_changed = rtw89_traffic_stats_track(rtwdev); 2248 if (rtwdev->scanning) 2249 goto out; 2250 2251 rtw89_leave_lps(rtwdev); 2252 2253 if (tfc_changed) { 2254 rtw89_hci_recalc_int_mit(rtwdev); 2255 rtw89_btc_ntfy_wl_sta(rtwdev); 2256 } 2257 rtw89_mac_bf_monitor_track(rtwdev); 2258 rtw89_phy_stat_track(rtwdev); 2259 rtw89_phy_env_monitor_track(rtwdev); 2260 rtw89_phy_dig(rtwdev); 2261 rtw89_chip_rfk_track(rtwdev); 2262 rtw89_phy_ra_update(rtwdev); 2263 rtw89_phy_cfo_track(rtwdev); 2264 rtw89_phy_tx_path_div_track(rtwdev); 2265 rtw89_phy_ul_tb_ctrl_track(rtwdev); 2266 2267 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 2268 rtw89_enter_lps_track(rtwdev); 2269 2270 out: 2271 mutex_unlock(&rtwdev->mutex); 2272 } 2273 2274 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 2275 { 2276 unsigned long bit; 2277 2278 bit = find_first_zero_bit(addr, size); 2279 if (bit < size) 2280 set_bit(bit, addr); 2281 2282 return bit; 2283 } 2284 2285 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 2286 { 2287 clear_bit(bit, addr); 2288 } 2289 2290 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 2291 { 2292 bitmap_zero(addr, nbits); 2293 } 2294 2295 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 2296 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2297 { 2298 const struct rtw89_chip_info *chip = rtwdev->chip; 2299 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2300 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2301 u8 idx; 2302 int i; 2303 2304 lockdep_assert_held(&rtwdev->mutex); 2305 2306 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 2307 if (idx == chip->bacam_num) { 2308 /* allocate a static BA CAM to tid=0/5, so replace the existing 2309 * one if BA CAM is full. Hardware will process the original tid 2310 * automatically. 2311 */ 2312 if (tid != 0 && tid != 5) 2313 return -ENOSPC; 2314 2315 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 2316 tmp = &cam_info->ba_cam_entry[i]; 2317 if (tmp->tid == 0 || tmp->tid == 5) 2318 continue; 2319 2320 idx = i; 2321 entry = tmp; 2322 list_del(&entry->list); 2323 break; 2324 } 2325 2326 if (!entry) 2327 return -ENOSPC; 2328 } else { 2329 entry = &cam_info->ba_cam_entry[idx]; 2330 } 2331 2332 entry->tid = tid; 2333 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 2334 2335 *cam_idx = idx; 2336 2337 return 0; 2338 } 2339 2340 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 2341 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2342 { 2343 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2344 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2345 u8 idx; 2346 2347 lockdep_assert_held(&rtwdev->mutex); 2348 2349 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 2350 if (entry->tid != tid) 2351 continue; 2352 2353 idx = entry - cam_info->ba_cam_entry; 2354 list_del(&entry->list); 2355 2356 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 2357 *cam_idx = idx; 2358 return 0; 2359 } 2360 2361 return -ENOENT; 2362 } 2363 2364 #define RTW89_TYPE_MAPPING(_type) \ 2365 case NL80211_IFTYPE_ ## _type: \ 2366 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 2367 break 2368 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 2369 { 2370 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2371 2372 switch (vif->type) { 2373 case NL80211_IFTYPE_STATION: 2374 if (vif->p2p) 2375 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 2376 else 2377 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 2378 break; 2379 case NL80211_IFTYPE_AP: 2380 if (vif->p2p) 2381 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 2382 else 2383 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 2384 break; 2385 RTW89_TYPE_MAPPING(ADHOC); 2386 RTW89_TYPE_MAPPING(MONITOR); 2387 RTW89_TYPE_MAPPING(MESH_POINT); 2388 default: 2389 WARN_ON(1); 2390 break; 2391 } 2392 2393 switch (vif->type) { 2394 case NL80211_IFTYPE_AP: 2395 case NL80211_IFTYPE_MESH_POINT: 2396 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 2397 rtwvif->self_role = RTW89_SELF_ROLE_AP; 2398 break; 2399 case NL80211_IFTYPE_ADHOC: 2400 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 2401 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2402 break; 2403 case NL80211_IFTYPE_STATION: 2404 if (assoc) { 2405 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 2406 rtwvif->trigger = vif->bss_conf.he_support; 2407 } else { 2408 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 2409 rtwvif->trigger = false; 2410 } 2411 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2412 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 2413 break; 2414 case NL80211_IFTYPE_MONITOR: 2415 break; 2416 default: 2417 WARN_ON(1); 2418 break; 2419 } 2420 } 2421 2422 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 2423 struct ieee80211_vif *vif, 2424 struct ieee80211_sta *sta) 2425 { 2426 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2427 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2428 int i; 2429 2430 rtwsta->rtwdev = rtwdev; 2431 rtwsta->rtwvif = rtwvif; 2432 rtwsta->prev_rssi = 0; 2433 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 2434 2435 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 2436 rtw89_core_txq_init(rtwdev, sta->txq[i]); 2437 2438 ewma_rssi_init(&rtwsta->avg_rssi); 2439 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2440 ewma_rssi_init(&rtwsta->rssi[i]); 2441 2442 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2443 /* for station mode, assign the mac_id from itself */ 2444 rtwsta->mac_id = rtwvif->mac_id; 2445 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2446 BTC_ROLE_MSTS_STA_CONN_START); 2447 rtw89_chip_rfk_channel(rtwdev); 2448 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2449 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 2450 RTW89_MAX_MAC_ID_NUM); 2451 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 2452 return -ENOSPC; 2453 } 2454 2455 return 0; 2456 } 2457 2458 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 2459 struct ieee80211_vif *vif, 2460 struct ieee80211_sta *sta) 2461 { 2462 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2463 2464 rtwdev->total_sta_assoc--; 2465 rtwsta->disassoc = true; 2466 2467 return 0; 2468 } 2469 2470 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 2471 struct ieee80211_vif *vif, 2472 struct ieee80211_sta *sta) 2473 { 2474 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2475 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2476 int ret; 2477 2478 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 2479 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 2480 rtw89_core_free_sta_pending_ba(rtwdev, sta); 2481 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 2482 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2483 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 2484 if (sta->tdls) 2485 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 2486 2487 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2488 rtw89_vif_type_mapping(vif, false); 2489 2490 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2491 if (ret) { 2492 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2493 return ret; 2494 } 2495 2496 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 2497 if (ret) { 2498 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2499 return ret; 2500 } 2501 2502 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2503 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_REMOVE); 2504 if (ret) { 2505 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2506 return ret; 2507 } 2508 } 2509 2510 /* update cam aid mac_id net_type */ 2511 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2512 if (ret) { 2513 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2514 return ret; 2515 } 2516 2517 return ret; 2518 } 2519 2520 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 2521 struct ieee80211_vif *vif, 2522 struct ieee80211_sta *sta) 2523 { 2524 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2525 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2526 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 2527 int ret; 2528 2529 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2530 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 2531 if (ret) { 2532 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 2533 return ret; 2534 } 2535 2536 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_CREATE); 2537 if (ret) { 2538 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2539 return ret; 2540 } 2541 2542 if (sta->tdls) { 2543 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 2544 if (ret) { 2545 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 2546 return ret; 2547 } 2548 } 2549 2550 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 2551 if (ret) { 2552 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 2553 return ret; 2554 } 2555 } 2556 2557 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2558 if (ret) { 2559 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2560 return ret; 2561 } 2562 2563 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 2564 if (ret) { 2565 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2566 return ret; 2567 } 2568 2569 /* update cam aid mac_id net_type */ 2570 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2571 if (ret) { 2572 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2573 return ret; 2574 } 2575 2576 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwsta->mac_id); 2577 if (ret) { 2578 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 2579 return ret; 2580 } 2581 2582 rtwdev->total_sta_assoc++; 2583 rtw89_phy_ra_assoc(rtwdev, sta); 2584 rtw89_mac_bf_assoc(rtwdev, vif, sta); 2585 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 2586 2587 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2588 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2589 BTC_ROLE_MSTS_STA_CONN_END); 2590 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); 2591 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 2592 } 2593 2594 return ret; 2595 } 2596 2597 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 2598 struct ieee80211_vif *vif, 2599 struct ieee80211_sta *sta) 2600 { 2601 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2602 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2603 2604 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2605 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2606 BTC_ROLE_MSTS_STA_DIS_CONN); 2607 else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2608 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2609 2610 return 0; 2611 } 2612 2613 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 2614 struct ieee80211_sta *sta, 2615 struct cfg80211_tid_cfg *tid_conf) 2616 { 2617 struct ieee80211_txq *txq; 2618 struct rtw89_txq *rtwtxq; 2619 u32 mask = tid_conf->mask; 2620 u8 tids = tid_conf->tids; 2621 int tids_nbit = BITS_PER_BYTE; 2622 int i; 2623 2624 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 2625 if (!tids) 2626 break; 2627 2628 if (!(tids & BIT(0))) 2629 continue; 2630 2631 txq = sta->txq[i]; 2632 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2633 2634 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 2635 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 2636 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2637 } else { 2638 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 2639 ieee80211_stop_tx_ba_session(sta, txq->tid); 2640 spin_lock_bh(&rtwdev->ba_lock); 2641 list_del_init(&rtwtxq->list); 2642 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2643 spin_unlock_bh(&rtwdev->ba_lock); 2644 } 2645 } 2646 2647 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 2648 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 2649 sta->max_amsdu_subframes = 0; 2650 else 2651 sta->max_amsdu_subframes = 1; 2652 } 2653 } 2654 } 2655 2656 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 2657 struct ieee80211_sta *sta, 2658 struct cfg80211_tid_config *tid_config) 2659 { 2660 int i; 2661 2662 for (i = 0; i < tid_config->n_tid_conf; i++) 2663 _rtw89_core_set_tid_config(rtwdev, sta, 2664 &tid_config->tid_conf[i]); 2665 } 2666 2667 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 2668 struct ieee80211_sta_ht_cap *ht_cap) 2669 { 2670 static const __le16 highest[RF_PATH_MAX] = { 2671 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 2672 }; 2673 struct rtw89_hal *hal = &rtwdev->hal; 2674 u8 nss = hal->rx_nss; 2675 int i; 2676 2677 ht_cap->ht_supported = true; 2678 ht_cap->cap = 0; 2679 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 2680 IEEE80211_HT_CAP_MAX_AMSDU | 2681 IEEE80211_HT_CAP_TX_STBC | 2682 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 2683 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 2684 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 2685 IEEE80211_HT_CAP_DSSSCCK40 | 2686 IEEE80211_HT_CAP_SGI_40; 2687 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 2688 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 2689 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 2690 for (i = 0; i < nss; i++) 2691 ht_cap->mcs.rx_mask[i] = 0xFF; 2692 ht_cap->mcs.rx_mask[4] = 0x01; 2693 ht_cap->mcs.rx_highest = highest[nss - 1]; 2694 } 2695 2696 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 2697 struct ieee80211_sta_vht_cap *vht_cap) 2698 { 2699 static const __le16 highest_bw80[RF_PATH_MAX] = { 2700 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 2701 }; 2702 static const __le16 highest_bw160[RF_PATH_MAX] = { 2703 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 2704 }; 2705 const struct rtw89_chip_info *chip = rtwdev->chip; 2706 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 2707 struct rtw89_hal *hal = &rtwdev->hal; 2708 u16 tx_mcs_map = 0, rx_mcs_map = 0; 2709 u8 sts_cap = 3; 2710 int i; 2711 2712 for (i = 0; i < 8; i++) { 2713 if (i < hal->tx_nss) 2714 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2715 else 2716 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2717 if (i < hal->rx_nss) 2718 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2719 else 2720 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2721 } 2722 2723 vht_cap->vht_supported = true; 2724 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 2725 IEEE80211_VHT_CAP_SHORT_GI_80 | 2726 IEEE80211_VHT_CAP_RXSTBC_1 | 2727 IEEE80211_VHT_CAP_HTC_VHT | 2728 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 2729 0; 2730 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 2731 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 2732 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 2733 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 2734 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 2735 if (chip->support_bw160) 2736 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 2737 IEEE80211_VHT_CAP_SHORT_GI_160; 2738 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 2739 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 2740 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 2741 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 2742 } 2743 2744 #define RTW89_SBAND_IFTYPES_NR 2 2745 2746 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 2747 enum nl80211_band band, 2748 struct ieee80211_supported_band *sband) 2749 { 2750 const struct rtw89_chip_info *chip = rtwdev->chip; 2751 struct rtw89_hal *hal = &rtwdev->hal; 2752 struct ieee80211_sband_iftype_data *iftype_data; 2753 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 2754 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 2755 u16 mcs_map = 0; 2756 int i; 2757 int nss = hal->rx_nss; 2758 int idx = 0; 2759 2760 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 2761 if (!iftype_data) 2762 return; 2763 2764 for (i = 0; i < 8; i++) { 2765 if (i < nss) 2766 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 2767 else 2768 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 2769 } 2770 2771 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 2772 struct ieee80211_sta_he_cap *he_cap; 2773 u8 *mac_cap_info; 2774 u8 *phy_cap_info; 2775 2776 switch (i) { 2777 case NL80211_IFTYPE_STATION: 2778 case NL80211_IFTYPE_AP: 2779 break; 2780 default: 2781 continue; 2782 } 2783 2784 if (idx >= RTW89_SBAND_IFTYPES_NR) { 2785 rtw89_warn(rtwdev, "run out of iftype_data\n"); 2786 break; 2787 } 2788 2789 iftype_data[idx].types_mask = BIT(i); 2790 he_cap = &iftype_data[idx].he_cap; 2791 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 2792 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 2793 2794 he_cap->has_he = true; 2795 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 2796 if (i == NL80211_IFTYPE_STATION) 2797 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 2798 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 2799 IEEE80211_HE_MAC_CAP2_BSR; 2800 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 2801 if (i == NL80211_IFTYPE_AP) 2802 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 2803 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 2804 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 2805 if (i == NL80211_IFTYPE_STATION) 2806 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 2807 if (band == NL80211_BAND_2GHZ) { 2808 phy_cap_info[0] = 2809 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 2810 } else { 2811 phy_cap_info[0] = 2812 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 2813 if (chip->support_bw160) 2814 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 2815 } 2816 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 2817 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 2818 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 2819 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 2820 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 2821 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 2822 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 2823 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 2824 if (i == NL80211_IFTYPE_STATION) 2825 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 2826 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 2827 if (i == NL80211_IFTYPE_AP) 2828 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 2829 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 2830 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 2831 if (chip->support_bw160) 2832 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 2833 phy_cap_info[5] = no_ng16 ? 0 : 2834 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 2835 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 2836 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 2837 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 2838 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 2839 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 2840 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 2841 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 2842 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 2843 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 2844 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 2845 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 2846 if (chip->support_bw160) 2847 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 2848 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 2849 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 2850 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 2851 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 2852 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 2853 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 2854 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 2855 if (i == NL80211_IFTYPE_STATION) 2856 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 2857 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 2858 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 2859 if (chip->support_bw160) { 2860 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 2861 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 2862 } 2863 2864 if (band == NL80211_BAND_6GHZ) { 2865 __le16 capa; 2866 2867 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 2868 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 2869 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 2870 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 2871 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 2872 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 2873 iftype_data[idx].he_6ghz_capa.capa = capa; 2874 } 2875 2876 idx++; 2877 } 2878 2879 sband->iftype_data = iftype_data; 2880 sband->n_iftype_data = idx; 2881 } 2882 2883 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 2884 { 2885 struct ieee80211_hw *hw = rtwdev->hw; 2886 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 2887 struct ieee80211_supported_band *sband_6ghz = NULL; 2888 u32 size = sizeof(struct ieee80211_supported_band); 2889 u8 support_bands = rtwdev->chip->support_bands; 2890 2891 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 2892 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 2893 if (!sband_2ghz) 2894 goto err; 2895 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 2896 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 2897 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 2898 } 2899 2900 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 2901 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 2902 if (!sband_5ghz) 2903 goto err; 2904 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 2905 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 2906 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 2907 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 2908 } 2909 2910 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 2911 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 2912 if (!sband_6ghz) 2913 goto err; 2914 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 2915 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 2916 } 2917 2918 return 0; 2919 2920 err: 2921 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2922 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2923 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2924 if (sband_2ghz) 2925 kfree(sband_2ghz->iftype_data); 2926 if (sband_5ghz) 2927 kfree(sband_5ghz->iftype_data); 2928 if (sband_6ghz) 2929 kfree(sband_6ghz->iftype_data); 2930 kfree(sband_2ghz); 2931 kfree(sband_5ghz); 2932 kfree(sband_6ghz); 2933 return -ENOMEM; 2934 } 2935 2936 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 2937 { 2938 struct ieee80211_hw *hw = rtwdev->hw; 2939 2940 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 2941 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 2942 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 2943 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 2944 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 2945 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 2946 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 2947 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2948 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2949 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2950 } 2951 2952 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 2953 { 2954 int i; 2955 2956 for (i = 0; i < RTW89_PHY_MAX; i++) 2957 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 2958 for (i = 0; i < RTW89_PHY_MAX; i++) 2959 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 2960 } 2961 2962 void rtw89_core_update_beacon_work(struct work_struct *work) 2963 { 2964 struct rtw89_dev *rtwdev; 2965 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2966 update_beacon_work); 2967 2968 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 2969 return; 2970 2971 rtwdev = rtwvif->rtwdev; 2972 mutex_lock(&rtwdev->mutex); 2973 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 2974 mutex_unlock(&rtwdev->mutex); 2975 } 2976 2977 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 2978 { 2979 struct completion *cmpl = &wait->completion; 2980 unsigned long timeout; 2981 unsigned int cur; 2982 2983 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 2984 if (cur != RTW89_WAIT_COND_IDLE) 2985 return -EBUSY; 2986 2987 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 2988 if (timeout == 0) { 2989 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 2990 return -ETIMEDOUT; 2991 } 2992 2993 if (wait->data.err) 2994 return -EFAULT; 2995 2996 return 0; 2997 } 2998 2999 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 3000 const struct rtw89_completion_data *data) 3001 { 3002 unsigned int cur; 3003 3004 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 3005 if (cur != cond) 3006 return; 3007 3008 wait->data = *data; 3009 complete(&wait->completion); 3010 } 3011 3012 int rtw89_core_start(struct rtw89_dev *rtwdev) 3013 { 3014 int ret; 3015 3016 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 3017 ret = rtw89_mac_init(rtwdev); 3018 if (ret) { 3019 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 3020 return ret; 3021 } 3022 3023 rtw89_btc_ntfy_poweron(rtwdev); 3024 3025 /* efuse process */ 3026 3027 /* pre-config BB/RF, BB reset/RFC reset */ 3028 ret = rtw89_chip_disable_bb_rf(rtwdev); 3029 if (ret) 3030 return ret; 3031 ret = rtw89_chip_enable_bb_rf(rtwdev); 3032 if (ret) 3033 return ret; 3034 3035 rtw89_phy_init_bb_reg(rtwdev); 3036 rtw89_phy_init_rf_reg(rtwdev, false); 3037 3038 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 3039 3040 rtw89_phy_dm_init(rtwdev); 3041 3042 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 3043 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 3044 3045 ret = rtw89_hci_start(rtwdev); 3046 if (ret) { 3047 rtw89_err(rtwdev, "failed to start hci\n"); 3048 return ret; 3049 } 3050 3051 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3052 RTW89_TRACK_WORK_PERIOD); 3053 3054 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3055 3056 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 3057 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); 3058 rtw89_fw_h2c_init_ba_cam(rtwdev); 3059 3060 return 0; 3061 } 3062 3063 void rtw89_core_stop(struct rtw89_dev *rtwdev) 3064 { 3065 struct rtw89_btc *btc = &rtwdev->btc; 3066 3067 /* Prvent to stop twice; enter_ips and ops_stop */ 3068 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3069 return; 3070 3071 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 3072 3073 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3074 3075 mutex_unlock(&rtwdev->mutex); 3076 3077 cancel_work_sync(&rtwdev->c2h_work); 3078 cancel_work_sync(&btc->eapol_notify_work); 3079 cancel_work_sync(&btc->arp_notify_work); 3080 cancel_work_sync(&btc->dhcp_notify_work); 3081 cancel_work_sync(&btc->icmp_notify_work); 3082 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 3083 cancel_delayed_work_sync(&rtwdev->track_work); 3084 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 3085 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 3086 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 3087 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 3088 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 3089 3090 mutex_lock(&rtwdev->mutex); 3091 3092 rtw89_btc_ntfy_poweroff(rtwdev); 3093 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3094 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3095 rtw89_hci_stop(rtwdev); 3096 rtw89_hci_deinit(rtwdev); 3097 rtw89_mac_pwr_off(rtwdev); 3098 rtw89_hci_reset(rtwdev); 3099 } 3100 3101 int rtw89_core_init(struct rtw89_dev *rtwdev) 3102 { 3103 struct rtw89_btc *btc = &rtwdev->btc; 3104 int ret; 3105 u8 band; 3106 3107 INIT_LIST_HEAD(&rtwdev->ba_list); 3108 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 3109 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 3110 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 3111 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 3112 if (!(rtwdev->chip->support_bands & BIT(band))) 3113 continue; 3114 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 3115 } 3116 INIT_LIST_HEAD(&rtwdev->wow.pkt_list); 3117 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 3118 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 3119 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 3120 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 3121 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 3122 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 3123 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 3124 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 3125 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 3126 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 3127 spin_lock_init(&rtwdev->ba_lock); 3128 spin_lock_init(&rtwdev->rpwm_lock); 3129 mutex_init(&rtwdev->mutex); 3130 mutex_init(&rtwdev->rf_mutex); 3131 rtwdev->total_sta_assoc = 0; 3132 3133 rtw89_init_wait(&rtwdev->mcc.wait); 3134 3135 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 3136 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 3137 skb_queue_head_init(&rtwdev->c2h_queue); 3138 rtw89_core_ppdu_sts_init(rtwdev); 3139 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 3140 3141 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 3142 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 3143 3144 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 3145 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 3146 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 3147 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 3148 3149 ret = rtw89_load_firmware(rtwdev); 3150 if (ret) { 3151 rtw89_warn(rtwdev, "no firmware loaded\n"); 3152 return ret; 3153 } 3154 rtw89_ser_init(rtwdev); 3155 rtw89_entity_init(rtwdev); 3156 3157 return 0; 3158 } 3159 EXPORT_SYMBOL(rtw89_core_init); 3160 3161 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 3162 { 3163 rtw89_ser_deinit(rtwdev); 3164 rtw89_unload_firmware(rtwdev); 3165 rtw89_fw_free_all_early_h2c(rtwdev); 3166 3167 destroy_workqueue(rtwdev->txq_wq); 3168 mutex_destroy(&rtwdev->rf_mutex); 3169 mutex_destroy(&rtwdev->mutex); 3170 } 3171 EXPORT_SYMBOL(rtw89_core_deinit); 3172 3173 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3174 const u8 *mac_addr, bool hw_scan) 3175 { 3176 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3177 3178 rtwdev->scanning = true; 3179 rtw89_leave_lps(rtwdev); 3180 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3181 rtw89_leave_ips(rtwdev); 3182 3183 ether_addr_copy(rtwvif->mac_addr, mac_addr); 3184 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 3185 rtw89_chip_rfk_scan(rtwdev, true); 3186 rtw89_hci_recalc_int_mit(rtwdev); 3187 3188 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 3189 } 3190 3191 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3192 struct ieee80211_vif *vif, bool hw_scan) 3193 { 3194 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3195 3196 if (!rtwvif) 3197 return; 3198 3199 ether_addr_copy(rtwvif->mac_addr, vif->addr); 3200 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3201 3202 rtw89_chip_rfk_scan(rtwdev, false); 3203 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 3204 3205 rtwdev->scanning = false; 3206 rtwdev->dig.bypass_dig = true; 3207 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3208 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 3209 } 3210 3211 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 3212 { 3213 const struct rtw89_chip_info *chip = rtwdev->chip; 3214 u8 cv; 3215 3216 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 3217 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 3218 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 3219 cv = CHIP_CAV; 3220 else 3221 cv = CHIP_CBV; 3222 } 3223 3224 rtwdev->hal.cv = cv; 3225 } 3226 3227 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 3228 { 3229 rtwdev->hal.support_cckpd = 3230 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 3231 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 3232 rtwdev->hal.support_igi = 3233 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 3234 } 3235 3236 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 3237 { 3238 int ret; 3239 3240 ret = rtw89_mac_partial_init(rtwdev); 3241 if (ret) 3242 return ret; 3243 3244 ret = rtw89_parse_efuse_map(rtwdev); 3245 if (ret) 3246 return ret; 3247 3248 ret = rtw89_parse_phycap_map(rtwdev); 3249 if (ret) 3250 return ret; 3251 3252 ret = rtw89_mac_setup_phycap(rtwdev); 3253 if (ret) 3254 return ret; 3255 3256 rtw89_core_setup_phycap(rtwdev); 3257 3258 rtw89_mac_pwr_off(rtwdev); 3259 3260 return 0; 3261 } 3262 3263 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 3264 { 3265 rtw89_chip_fem_setup(rtwdev); 3266 3267 return 0; 3268 } 3269 3270 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 3271 { 3272 int ret; 3273 3274 rtw89_read_chip_ver(rtwdev); 3275 3276 ret = rtw89_wait_firmware_completion(rtwdev); 3277 if (ret) { 3278 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 3279 return ret; 3280 } 3281 3282 ret = rtw89_fw_recognize(rtwdev); 3283 if (ret) { 3284 rtw89_err(rtwdev, "failed to recognize firmware\n"); 3285 return ret; 3286 } 3287 3288 ret = rtw89_chip_efuse_info_setup(rtwdev); 3289 if (ret) 3290 return ret; 3291 3292 ret = rtw89_chip_board_info_setup(rtwdev); 3293 if (ret) 3294 return ret; 3295 3296 return 0; 3297 } 3298 EXPORT_SYMBOL(rtw89_chip_info_setup); 3299 3300 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 3301 { 3302 struct ieee80211_hw *hw = rtwdev->hw; 3303 struct rtw89_efuse *efuse = &rtwdev->efuse; 3304 int ret; 3305 int tx_headroom = IEEE80211_HT_CTL_LEN; 3306 3307 hw->vif_data_size = sizeof(struct rtw89_vif); 3308 hw->sta_data_size = sizeof(struct rtw89_sta); 3309 hw->txq_data_size = sizeof(struct rtw89_txq); 3310 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 3311 3312 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 3313 3314 hw->extra_tx_headroom = tx_headroom; 3315 hw->queues = IEEE80211_NUM_ACS; 3316 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 3317 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 3318 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 3319 3320 ieee80211_hw_set(hw, SIGNAL_DBM); 3321 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 3322 ieee80211_hw_set(hw, MFP_CAPABLE); 3323 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 3324 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 3325 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 3326 ieee80211_hw_set(hw, TX_AMSDU); 3327 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 3328 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 3329 ieee80211_hw_set(hw, SUPPORTS_PS); 3330 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 3331 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 3332 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 3333 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 3334 3335 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 3336 BIT(NL80211_IFTYPE_AP) | 3337 BIT(NL80211_IFTYPE_P2P_CLIENT) | 3338 BIT(NL80211_IFTYPE_P2P_GO); 3339 3340 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 3341 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 3342 3343 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 3344 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 3345 WIPHY_FLAG_AP_UAPSD; 3346 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 3347 3348 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 3349 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 3350 3351 #ifdef CONFIG_PM 3352 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 3353 #endif 3354 3355 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3356 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3357 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3358 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3359 3360 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 3361 3362 ret = rtw89_core_set_supported_band(rtwdev); 3363 if (ret) { 3364 rtw89_err(rtwdev, "failed to set supported band\n"); 3365 return ret; 3366 } 3367 3368 hw->wiphy->reg_notifier = rtw89_regd_notifier; 3369 hw->wiphy->sar_capa = &rtw89_sar_capa; 3370 3371 ret = ieee80211_register_hw(hw); 3372 if (ret) { 3373 rtw89_err(rtwdev, "failed to register hw\n"); 3374 goto err; 3375 } 3376 3377 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 3378 if (ret) { 3379 rtw89_err(rtwdev, "failed to init regd\n"); 3380 goto err; 3381 } 3382 3383 return 0; 3384 3385 err: 3386 return ret; 3387 } 3388 3389 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 3390 { 3391 struct ieee80211_hw *hw = rtwdev->hw; 3392 3393 ieee80211_unregister_hw(hw); 3394 rtw89_core_clr_supported_band(rtwdev); 3395 } 3396 3397 int rtw89_core_register(struct rtw89_dev *rtwdev) 3398 { 3399 int ret; 3400 3401 ret = rtw89_core_register_hw(rtwdev); 3402 if (ret) { 3403 rtw89_err(rtwdev, "failed to register core hw\n"); 3404 return ret; 3405 } 3406 3407 rtw89_debugfs_init(rtwdev); 3408 3409 return 0; 3410 } 3411 EXPORT_SYMBOL(rtw89_core_register); 3412 3413 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 3414 { 3415 rtw89_core_unregister_hw(rtwdev); 3416 } 3417 EXPORT_SYMBOL(rtw89_core_unregister); 3418 3419 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 3420 u32 bus_data_size, 3421 const struct rtw89_chip_info *chip) 3422 { 3423 const struct firmware *firmware; 3424 struct ieee80211_hw *hw; 3425 struct rtw89_dev *rtwdev; 3426 struct ieee80211_ops *ops; 3427 u32 driver_data_size; 3428 u32 early_feat_map = 0; 3429 bool no_chanctx; 3430 3431 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_feat_map); 3432 3433 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 3434 if (!ops) 3435 goto err; 3436 3437 no_chanctx = chip->support_chanctx_num == 0 || 3438 !(early_feat_map & BIT(RTW89_FW_FEATURE_SCAN_OFFLOAD)); 3439 3440 if (no_chanctx) { 3441 ops->add_chanctx = NULL; 3442 ops->remove_chanctx = NULL; 3443 ops->change_chanctx = NULL; 3444 ops->assign_vif_chanctx = NULL; 3445 ops->unassign_vif_chanctx = NULL; 3446 } 3447 3448 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 3449 hw = ieee80211_alloc_hw(driver_data_size, ops); 3450 if (!hw) 3451 goto err; 3452 3453 rtwdev = hw->priv; 3454 rtwdev->hw = hw; 3455 rtwdev->dev = device; 3456 rtwdev->ops = ops; 3457 rtwdev->chip = chip; 3458 rtwdev->fw.firmware = firmware; 3459 3460 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 3461 no_chanctx ? "without" : "with"); 3462 3463 return rtwdev; 3464 3465 err: 3466 kfree(ops); 3467 release_firmware(firmware); 3468 return NULL; 3469 } 3470 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 3471 3472 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 3473 { 3474 kfree(rtwdev->ops); 3475 release_firmware(rtwdev->fw.firmware); 3476 ieee80211_free_hw(rtwdev->hw); 3477 } 3478 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 3479 3480 MODULE_AUTHOR("Realtek Corporation"); 3481 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 3482 MODULE_LICENSE("Dual BSD/GPL"); 3483