1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 }; 81 82 static struct ieee80211_channel rtw89_channels_6ghz[] = { 83 RTW89_DEF_CHAN_6G(5955, 1), 84 RTW89_DEF_CHAN_6G(5975, 5), 85 RTW89_DEF_CHAN_6G(5995, 9), 86 RTW89_DEF_CHAN_6G(6015, 13), 87 RTW89_DEF_CHAN_6G(6035, 17), 88 RTW89_DEF_CHAN_6G(6055, 21), 89 RTW89_DEF_CHAN_6G(6075, 25), 90 RTW89_DEF_CHAN_6G(6095, 29), 91 RTW89_DEF_CHAN_6G(6115, 33), 92 RTW89_DEF_CHAN_6G(6135, 37), 93 RTW89_DEF_CHAN_6G(6155, 41), 94 RTW89_DEF_CHAN_6G(6175, 45), 95 RTW89_DEF_CHAN_6G(6195, 49), 96 RTW89_DEF_CHAN_6G(6215, 53), 97 RTW89_DEF_CHAN_6G(6235, 57), 98 RTW89_DEF_CHAN_6G(6255, 61), 99 RTW89_DEF_CHAN_6G(6275, 65), 100 RTW89_DEF_CHAN_6G(6295, 69), 101 RTW89_DEF_CHAN_6G(6315, 73), 102 RTW89_DEF_CHAN_6G(6335, 77), 103 RTW89_DEF_CHAN_6G(6355, 81), 104 RTW89_DEF_CHAN_6G(6375, 85), 105 RTW89_DEF_CHAN_6G(6395, 89), 106 RTW89_DEF_CHAN_6G(6415, 93), 107 RTW89_DEF_CHAN_6G(6435, 97), 108 RTW89_DEF_CHAN_6G(6455, 101), 109 RTW89_DEF_CHAN_6G(6475, 105), 110 RTW89_DEF_CHAN_6G(6495, 109), 111 RTW89_DEF_CHAN_6G(6515, 113), 112 RTW89_DEF_CHAN_6G(6535, 117), 113 RTW89_DEF_CHAN_6G(6555, 121), 114 RTW89_DEF_CHAN_6G(6575, 125), 115 RTW89_DEF_CHAN_6G(6595, 129), 116 RTW89_DEF_CHAN_6G(6615, 133), 117 RTW89_DEF_CHAN_6G(6635, 137), 118 RTW89_DEF_CHAN_6G(6655, 141), 119 RTW89_DEF_CHAN_6G(6675, 145), 120 RTW89_DEF_CHAN_6G(6695, 149), 121 RTW89_DEF_CHAN_6G(6715, 153), 122 RTW89_DEF_CHAN_6G(6735, 157), 123 RTW89_DEF_CHAN_6G(6755, 161), 124 RTW89_DEF_CHAN_6G(6775, 165), 125 RTW89_DEF_CHAN_6G(6795, 169), 126 RTW89_DEF_CHAN_6G(6815, 173), 127 RTW89_DEF_CHAN_6G(6835, 177), 128 RTW89_DEF_CHAN_6G(6855, 181), 129 RTW89_DEF_CHAN_6G(6875, 185), 130 RTW89_DEF_CHAN_6G(6895, 189), 131 RTW89_DEF_CHAN_6G(6915, 193), 132 RTW89_DEF_CHAN_6G(6935, 197), 133 RTW89_DEF_CHAN_6G(6955, 201), 134 RTW89_DEF_CHAN_6G(6975, 205), 135 RTW89_DEF_CHAN_6G(6995, 209), 136 RTW89_DEF_CHAN_6G(7015, 213), 137 RTW89_DEF_CHAN_6G(7035, 217), 138 RTW89_DEF_CHAN_6G(7055, 221), 139 RTW89_DEF_CHAN_6G(7075, 225), 140 RTW89_DEF_CHAN_6G(7095, 229), 141 RTW89_DEF_CHAN_6G(7115, 233), 142 }; 143 144 static struct ieee80211_rate rtw89_bitrates[] = { 145 { .bitrate = 10, .hw_value = 0x00, }, 146 { .bitrate = 20, .hw_value = 0x01, }, 147 { .bitrate = 55, .hw_value = 0x02, }, 148 { .bitrate = 110, .hw_value = 0x03, }, 149 { .bitrate = 60, .hw_value = 0x04, }, 150 { .bitrate = 90, .hw_value = 0x05, }, 151 { .bitrate = 120, .hw_value = 0x06, }, 152 { .bitrate = 180, .hw_value = 0x07, }, 153 { .bitrate = 240, .hw_value = 0x08, }, 154 { .bitrate = 360, .hw_value = 0x09, }, 155 { .bitrate = 480, .hw_value = 0x0a, }, 156 { .bitrate = 540, .hw_value = 0x0b, }, 157 }; 158 159 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 160 { 161 struct ieee80211_rate rate; 162 163 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 164 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 165 return false; 166 } 167 168 rate = rtw89_bitrates[rpt_rate]; 169 *bitrate = rate.bitrate; 170 171 return true; 172 } 173 174 static struct ieee80211_supported_band rtw89_sband_2ghz = { 175 .band = NL80211_BAND_2GHZ, 176 .channels = rtw89_channels_2ghz, 177 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 178 .bitrates = rtw89_bitrates, 179 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 180 .ht_cap = {0}, 181 .vht_cap = {0}, 182 }; 183 184 static struct ieee80211_supported_band rtw89_sband_5ghz = { 185 .band = NL80211_BAND_5GHZ, 186 .channels = rtw89_channels_5ghz, 187 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 188 189 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 190 .bitrates = rtw89_bitrates + 4, 191 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 192 .ht_cap = {0}, 193 .vht_cap = {0}, 194 }; 195 196 static struct ieee80211_supported_band rtw89_sband_6ghz = { 197 .band = NL80211_BAND_6GHZ, 198 .channels = rtw89_channels_6ghz, 199 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 200 201 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 202 .bitrates = rtw89_bitrates + 4, 203 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 204 }; 205 206 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 207 struct rtw89_traffic_stats *stats, 208 struct sk_buff *skb, bool tx) 209 { 210 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 211 212 if (!ieee80211_is_data(hdr->frame_control)) 213 return; 214 215 if (is_broadcast_ether_addr(hdr->addr1) || 216 is_multicast_ether_addr(hdr->addr1)) 217 return; 218 219 if (tx) { 220 stats->tx_cnt++; 221 stats->tx_unicast += skb->len; 222 } else { 223 stats->rx_cnt++; 224 stats->rx_unicast += skb->len; 225 } 226 } 227 228 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 229 { 230 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 231 NL80211_CHAN_NO_HT); 232 } 233 234 static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 235 struct rtw89_chan *chan) 236 { 237 struct ieee80211_channel *channel = chandef->chan; 238 enum nl80211_chan_width width = chandef->width; 239 u32 primary_freq, center_freq; 240 u8 center_chan; 241 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 242 u32 offset; 243 u8 band; 244 245 center_chan = channel->hw_value; 246 primary_freq = channel->center_freq; 247 center_freq = chandef->center_freq1; 248 249 switch (width) { 250 case NL80211_CHAN_WIDTH_20_NOHT: 251 case NL80211_CHAN_WIDTH_20: 252 bandwidth = RTW89_CHANNEL_WIDTH_20; 253 break; 254 case NL80211_CHAN_WIDTH_40: 255 bandwidth = RTW89_CHANNEL_WIDTH_40; 256 if (primary_freq > center_freq) { 257 center_chan -= 2; 258 } else { 259 center_chan += 2; 260 } 261 break; 262 case NL80211_CHAN_WIDTH_80: 263 case NL80211_CHAN_WIDTH_160: 264 bandwidth = nl_to_rtw89_bandwidth(width); 265 if (primary_freq > center_freq) { 266 offset = (primary_freq - center_freq - 10) / 20; 267 center_chan -= 2 + offset * 4; 268 } else { 269 offset = (center_freq - primary_freq - 10) / 20; 270 center_chan += 2 + offset * 4; 271 } 272 break; 273 default: 274 center_chan = 0; 275 break; 276 } 277 278 switch (channel->band) { 279 default: 280 case NL80211_BAND_2GHZ: 281 band = RTW89_BAND_2G; 282 break; 283 case NL80211_BAND_5GHZ: 284 band = RTW89_BAND_5G; 285 break; 286 case NL80211_BAND_6GHZ: 287 band = RTW89_BAND_6G; 288 break; 289 } 290 291 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 292 } 293 294 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 295 { 296 const struct rtw89_chip_info *chip = rtwdev->chip; 297 const struct rtw89_chan *chan; 298 enum rtw89_sub_entity_idx sub_entity_idx; 299 enum rtw89_phy_idx phy_idx; 300 enum rtw89_entity_mode mode; 301 bool entity_active; 302 303 entity_active = rtw89_get_entity_state(rtwdev); 304 if (!entity_active) 305 return; 306 307 mode = rtw89_get_entity_mode(rtwdev); 308 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 309 return; 310 311 sub_entity_idx = RTW89_SUB_ENTITY_0; 312 phy_idx = RTW89_PHY_0; 313 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 314 if (chip->ops->set_txpwr) 315 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 316 } 317 318 void rtw89_set_channel(struct rtw89_dev *rtwdev) 319 { 320 const struct rtw89_chip_info *chip = rtwdev->chip; 321 const struct cfg80211_chan_def *chandef; 322 enum rtw89_sub_entity_idx sub_entity_idx; 323 enum rtw89_mac_idx mac_idx; 324 enum rtw89_phy_idx phy_idx; 325 struct rtw89_chan chan; 326 struct rtw89_channel_help_params bak; 327 enum rtw89_entity_mode mode; 328 bool band_changed; 329 bool entity_active; 330 331 entity_active = rtw89_get_entity_state(rtwdev); 332 333 mode = rtw89_entity_recalc(rtwdev); 334 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 335 return; 336 337 sub_entity_idx = RTW89_SUB_ENTITY_0; 338 mac_idx = RTW89_MAC_0; 339 phy_idx = RTW89_PHY_0; 340 chandef = rtw89_chandef_get(rtwdev, sub_entity_idx); 341 rtw89_get_channel_params(chandef, &chan); 342 if (WARN(chan.channel == 0, "Invalid channel\n")) 343 return; 344 345 band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan); 346 347 rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx); 348 349 chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx); 350 351 rtw89_core_set_chip_txpwr(rtwdev); 352 353 rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx); 354 355 if (!entity_active || band_changed) { 356 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type); 357 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 358 } 359 360 rtw89_set_entity_state(rtwdev, true); 361 } 362 363 static enum rtw89_core_tx_type 364 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 365 struct sk_buff *skb) 366 { 367 struct ieee80211_hdr *hdr = (void *)skb->data; 368 __le16 fc = hdr->frame_control; 369 370 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 371 return RTW89_CORE_TX_TYPE_MGMT; 372 373 return RTW89_CORE_TX_TYPE_DATA; 374 } 375 376 static void 377 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 378 struct rtw89_core_tx_request *tx_req, 379 enum btc_pkt_type pkt_type) 380 { 381 struct ieee80211_sta *sta = tx_req->sta; 382 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 383 struct sk_buff *skb = tx_req->skb; 384 struct rtw89_sta *rtwsta; 385 u8 ampdu_num; 386 u8 tid; 387 388 if (pkt_type == PACKET_EAPOL) { 389 desc_info->bk = true; 390 return; 391 } 392 393 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 394 return; 395 396 if (!sta) { 397 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 398 return; 399 } 400 401 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 402 rtwsta = (struct rtw89_sta *)sta->drv_priv; 403 404 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 405 rtwsta->ampdu_params[tid].agg_num : 406 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 407 408 desc_info->agg_en = true; 409 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 410 desc_info->ampdu_num = ampdu_num; 411 } 412 413 static void 414 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 415 struct rtw89_core_tx_request *tx_req) 416 { 417 const struct rtw89_chip_info *chip = rtwdev->chip; 418 struct ieee80211_vif *vif = tx_req->vif; 419 struct ieee80211_sta *sta = tx_req->sta; 420 struct ieee80211_tx_info *info; 421 struct ieee80211_key_conf *key; 422 struct rtw89_vif *rtwvif; 423 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 424 struct rtw89_addr_cam_entry *addr_cam; 425 struct rtw89_sec_cam_entry *sec_cam; 426 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 427 struct sk_buff *skb = tx_req->skb; 428 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 429 u64 pn64; 430 431 if (!vif) { 432 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 433 return; 434 } 435 436 rtwvif = (struct rtw89_vif *)vif->drv_priv; 437 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 438 439 info = IEEE80211_SKB_CB(skb); 440 key = info->control.hw_key; 441 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 442 if (!sec_cam) { 443 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 444 return; 445 } 446 447 switch (key->cipher) { 448 case WLAN_CIPHER_SUITE_WEP40: 449 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 450 break; 451 case WLAN_CIPHER_SUITE_WEP104: 452 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 453 break; 454 case WLAN_CIPHER_SUITE_TKIP: 455 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 456 break; 457 case WLAN_CIPHER_SUITE_CCMP: 458 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 459 break; 460 case WLAN_CIPHER_SUITE_CCMP_256: 461 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 462 break; 463 case WLAN_CIPHER_SUITE_GCMP: 464 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 465 break; 466 case WLAN_CIPHER_SUITE_GCMP_256: 467 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 468 break; 469 default: 470 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 471 return; 472 } 473 474 desc_info->sec_en = true; 475 desc_info->sec_keyid = key->keyidx; 476 desc_info->sec_type = sec_type; 477 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 478 479 if (!chip->hw_sec_hdr) 480 return; 481 482 pn64 = atomic64_inc_return(&key->tx_pn); 483 desc_info->sec_seq[0] = pn64; 484 desc_info->sec_seq[1] = pn64 >> 8; 485 desc_info->sec_seq[2] = pn64 >> 16; 486 desc_info->sec_seq[3] = pn64 >> 24; 487 desc_info->sec_seq[4] = pn64 >> 32; 488 desc_info->sec_seq[5] = pn64 >> 40; 489 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 490 } 491 492 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 493 struct rtw89_core_tx_request *tx_req) 494 { 495 struct sk_buff *skb = tx_req->skb; 496 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 497 struct ieee80211_vif *vif = tx_info->control.vif; 498 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 499 u16 lowest_rate = chan->band_type == RTW89_BAND_2G ? 500 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6; 501 502 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 503 return lowest_rate; 504 505 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 506 } 507 508 static void 509 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 510 struct rtw89_core_tx_request *tx_req) 511 { 512 struct ieee80211_vif *vif = tx_req->vif; 513 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 514 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 515 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 516 u8 qsel, ch_dma; 517 518 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 519 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 520 521 desc_info->qsel = qsel; 522 desc_info->ch_dma = ch_dma; 523 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 524 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 525 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 526 527 /* fixed data rate for mgmt frames */ 528 desc_info->en_wd_info = true; 529 desc_info->use_rate = true; 530 desc_info->dis_data_fb = true; 531 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); 532 533 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 534 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 535 desc_info->data_rate, chan->channel, chan->band_type, 536 chan->band_width); 537 } 538 539 static void 540 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 541 struct rtw89_core_tx_request *tx_req) 542 { 543 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 544 545 desc_info->is_bmc = false; 546 desc_info->wd_page = false; 547 desc_info->ch_dma = RTW89_DMA_H2C; 548 } 549 550 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) 551 { 552 static const u8 rtw89_bandwidth_to_om[] = { 553 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 554 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 555 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 556 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 557 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 558 }; 559 const struct rtw89_chip_info *chip = rtwdev->chip; 560 struct rtw89_hal *hal = &rtwdev->hal; 561 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 562 u8 om_bandwidth; 563 564 if (!chip->dis_2g_40m_ul_ofdma || 565 chan->band_type != RTW89_BAND_2G || 566 chan->band_width != RTW89_CHANNEL_WIDTH_40) 567 return; 568 569 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 570 rtw89_bandwidth_to_om[chan->band_width] : 0; 571 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 572 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 573 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 574 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 575 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 576 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 577 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 578 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 579 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 580 } 581 582 static bool 583 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 584 struct rtw89_core_tx_request *tx_req, 585 enum btc_pkt_type pkt_type) 586 { 587 struct ieee80211_sta *sta = tx_req->sta; 588 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 589 struct sk_buff *skb = tx_req->skb; 590 struct ieee80211_hdr *hdr = (void *)skb->data; 591 __le16 fc = hdr->frame_control; 592 593 /* AP IOT issue with EAPoL, ARP and DHCP */ 594 if (pkt_type < PACKET_MAX) 595 return false; 596 597 if (!sta || !sta->deflink.he_cap.has_he) 598 return false; 599 600 if (!ieee80211_is_data_qos(fc)) 601 return false; 602 603 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 604 return false; 605 606 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 607 return false; 608 609 return true; 610 } 611 612 static void 613 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 614 struct rtw89_core_tx_request *tx_req) 615 { 616 struct ieee80211_sta *sta = tx_req->sta; 617 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 618 struct sk_buff *skb = tx_req->skb; 619 struct ieee80211_hdr *hdr = (void *)skb->data; 620 __le16 fc = hdr->frame_control; 621 void *data; 622 __le32 *htc; 623 u8 *qc; 624 int hdr_len; 625 626 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 627 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 628 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 629 630 hdr = data; 631 htc = data + hdr_len; 632 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 633 *htc = rtwsta->htc_template ? rtwsta->htc_template : 634 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 635 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 636 637 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 638 qc[0] |= IEEE80211_QOS_CTL_EOSP; 639 } 640 641 static void 642 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 643 struct rtw89_core_tx_request *tx_req, 644 enum btc_pkt_type pkt_type) 645 { 646 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 647 struct ieee80211_vif *vif = tx_req->vif; 648 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 649 650 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 651 goto desc_bk; 652 653 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 654 655 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 656 desc_info->a_ctrl_bsr = true; 657 658 desc_bk: 659 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 660 return; 661 662 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 663 desc_info->bk = true; 664 } 665 666 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 667 struct rtw89_core_tx_request *tx_req) 668 { 669 struct ieee80211_vif *vif = tx_req->vif; 670 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 671 struct ieee80211_sta *sta = tx_req->sta; 672 struct rtw89_sta *rtwsta; 673 674 if (!sta) 675 return rtwvif->mac_id; 676 677 rtwsta = (struct rtw89_sta *)sta->drv_priv; 678 return rtwsta->mac_id; 679 } 680 681 static void 682 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 683 struct rtw89_core_tx_request *tx_req) 684 { 685 struct ieee80211_vif *vif = tx_req->vif; 686 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 687 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 688 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 689 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 690 struct sk_buff *skb = tx_req->skb; 691 u8 tid, tid_indicate; 692 u8 qsel, ch_dma; 693 694 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 695 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 696 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 697 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 698 699 desc_info->ch_dma = ch_dma; 700 desc_info->tid_indicate = tid_indicate; 701 desc_info->qsel = qsel; 702 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 703 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 704 705 /* enable wd_info for AMPDU */ 706 desc_info->en_wd_info = true; 707 708 if (IEEE80211_SKB_CB(skb)->control.hw_key) 709 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 710 711 if (rate_pattern->enable) 712 desc_info->data_retry_lowest_rate = rate_pattern->rate; 713 else if (chan->band_type == RTW89_BAND_2G) 714 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_CCK1; 715 else 716 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 717 } 718 719 static enum btc_pkt_type 720 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 721 struct rtw89_core_tx_request *tx_req) 722 { 723 struct sk_buff *skb = tx_req->skb; 724 struct udphdr *udphdr; 725 726 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 727 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 728 return PACKET_EAPOL; 729 } 730 731 if (skb->protocol == htons(ETH_P_ARP)) { 732 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 733 return PACKET_ARP; 734 } 735 736 if (skb->protocol == htons(ETH_P_IP) && 737 ip_hdr(skb)->protocol == IPPROTO_UDP) { 738 udphdr = udp_hdr(skb); 739 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 740 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 741 skb->len > 282) { 742 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 743 return PACKET_DHCP; 744 } 745 } 746 747 if (skb->protocol == htons(ETH_P_IP) && 748 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 749 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 750 return PACKET_ICMP; 751 } 752 753 return PACKET_MAX; 754 } 755 756 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 757 struct rtw89_tx_desc_info *desc_info, 758 struct sk_buff *skb) 759 { 760 struct ieee80211_hdr *hdr = (void *)skb->data; 761 __le16 fc = hdr->frame_control; 762 763 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 764 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 765 } 766 767 static void 768 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 769 struct rtw89_core_tx_request *tx_req) 770 { 771 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 772 return; 773 774 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 775 return; 776 777 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 778 return; 779 780 rtw89_mac_notify_wake(rtwdev); 781 } 782 783 static void 784 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 785 struct rtw89_core_tx_request *tx_req) 786 { 787 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 788 struct sk_buff *skb = tx_req->skb; 789 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 790 struct ieee80211_hdr *hdr = (void *)skb->data; 791 enum rtw89_core_tx_type tx_type; 792 enum btc_pkt_type pkt_type; 793 bool is_bmc; 794 u16 seq; 795 796 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 797 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 798 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 799 tx_req->tx_type = tx_type; 800 } 801 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 802 is_multicast_ether_addr(hdr->addr1)); 803 804 desc_info->seq = seq; 805 desc_info->pkt_size = skb->len; 806 desc_info->is_bmc = is_bmc; 807 desc_info->wd_page = true; 808 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 809 810 switch (tx_req->tx_type) { 811 case RTW89_CORE_TX_TYPE_MGMT: 812 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 813 break; 814 case RTW89_CORE_TX_TYPE_DATA: 815 rtw89_core_tx_update_data_info(rtwdev, tx_req); 816 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 817 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 818 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 819 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 820 break; 821 case RTW89_CORE_TX_TYPE_FWCMD: 822 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 823 break; 824 } 825 } 826 827 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 828 { 829 u8 ch_dma; 830 831 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 832 833 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 834 } 835 836 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 837 struct sk_buff *skb, bool fwdl) 838 { 839 struct rtw89_core_tx_request tx_req = {0}; 840 u32 cnt; 841 int ret; 842 843 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 844 rtw89_debug(rtwdev, RTW89_DBG_FW, 845 "ignore h2c due to power is off with firmware state=%d\n", 846 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 847 return 0; 848 } 849 850 tx_req.skb = skb; 851 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 852 if (fwdl) 853 tx_req.desc_info.fw_dl = true; 854 855 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 856 857 if (!fwdl) 858 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 859 860 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 861 if (cnt == 0) { 862 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 863 return -ENOSPC; 864 } 865 866 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 867 if (ret) { 868 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 869 return ret; 870 } 871 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 872 873 return 0; 874 } 875 876 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 877 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 878 { 879 struct rtw89_core_tx_request tx_req = {0}; 880 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 881 int ret; 882 883 tx_req.skb = skb; 884 tx_req.sta = sta; 885 tx_req.vif = vif; 886 887 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 888 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 889 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 890 rtw89_core_tx_wake(rtwdev, &tx_req); 891 892 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 893 if (ret) { 894 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 895 return ret; 896 } 897 898 if (qsel) 899 *qsel = tx_req.desc_info.qsel; 900 901 return 0; 902 } 903 904 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 905 { 906 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 907 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 908 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 909 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 910 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 911 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 912 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 913 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 914 915 return cpu_to_le32(dword); 916 } 917 918 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 919 { 920 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 921 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 922 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 923 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 924 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 925 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 926 927 return cpu_to_le32(dword); 928 } 929 930 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 931 { 932 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 933 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 934 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 935 936 return cpu_to_le32(dword); 937 } 938 939 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 940 { 941 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 942 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 943 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 944 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 945 946 return cpu_to_le32(dword); 947 } 948 949 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 950 { 951 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 952 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 953 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 954 955 return cpu_to_le32(dword); 956 } 957 958 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 959 { 960 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 961 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 962 963 return cpu_to_le32(dword); 964 } 965 966 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 967 { 968 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 969 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 970 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 971 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 972 973 return cpu_to_le32(dword); 974 } 975 976 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 977 { 978 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 979 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 980 981 return cpu_to_le32(dword); 982 } 983 984 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 985 { 986 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 987 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 988 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 989 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 990 991 return cpu_to_le32(dword); 992 } 993 994 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 995 { 996 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb); 997 998 return cpu_to_le32(dword); 999 } 1000 1001 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1002 { 1003 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1004 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1005 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1006 desc_info->data_retry_lowest_rate); 1007 1008 return cpu_to_le32(dword); 1009 } 1010 1011 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1012 { 1013 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1014 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1015 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1016 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1017 1018 return cpu_to_le32(dword); 1019 } 1020 1021 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1022 { 1023 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1024 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1025 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1026 1027 return cpu_to_le32(dword); 1028 } 1029 1030 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1031 { 1032 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1033 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1034 1035 return cpu_to_le32(dword); 1036 } 1037 1038 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1039 struct rtw89_tx_desc_info *desc_info, 1040 void *txdesc) 1041 { 1042 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1043 struct rtw89_txwd_info *txwd_info; 1044 1045 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1046 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1047 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1048 1049 if (!desc_info->en_wd_info) 1050 return; 1051 1052 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1053 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1054 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1055 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1056 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1057 1058 } 1059 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1060 1061 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1062 struct rtw89_tx_desc_info *desc_info, 1063 void *txdesc) 1064 { 1065 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1066 struct rtw89_txwd_info *txwd_info; 1067 1068 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1069 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1070 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1071 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1072 if (desc_info->sec_en) { 1073 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1074 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1075 } 1076 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1077 1078 if (!desc_info->en_wd_info) 1079 return; 1080 1081 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1082 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1083 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1084 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1085 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1086 } 1087 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1088 1089 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1090 { 1091 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1092 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1093 RTW89_CORE_RX_TYPE_FWDL : 1094 RTW89_CORE_RX_TYPE_H2C); 1095 1096 return cpu_to_le32(dword); 1097 } 1098 1099 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1100 struct rtw89_tx_desc_info *desc_info, 1101 void *txdesc) 1102 { 1103 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1104 1105 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1106 } 1107 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1108 1109 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1110 struct sk_buff *skb, 1111 struct rtw89_rx_phy_ppdu *phy_ppdu) 1112 { 1113 bool rx_cnt_valid = false; 1114 u8 plcp_size = 0; 1115 u8 usr_num = 0; 1116 u8 *phy_sts; 1117 1118 rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); 1119 plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; 1120 usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); 1121 if (usr_num > RTW89_PPDU_MAX_USR) { 1122 rtw89_warn(rtwdev, "Invalid user number in mac info\n"); 1123 return -EINVAL; 1124 } 1125 1126 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1127 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1128 /* 8-byte alignment */ 1129 if (usr_num & BIT(0)) 1130 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1131 if (rx_cnt_valid) 1132 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; 1133 phy_sts += plcp_size; 1134 1135 phy_ppdu->buf = phy_sts; 1136 phy_ppdu->len = skb->data + skb->len - phy_sts; 1137 1138 return 0; 1139 } 1140 1141 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1142 struct ieee80211_sta *sta) 1143 { 1144 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1145 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1146 1147 if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) 1148 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1149 } 1150 1151 #define VAR_LEN 0xff 1152 #define VAR_LEN_UNIT 8 1153 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) 1154 { 1155 static const u8 physts_ie_len_tab[32] = { 1156 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1157 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1158 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1159 }; 1160 u16 ie_len; 1161 u8 ie; 1162 1163 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1164 if (physts_ie_len_tab[ie] != VAR_LEN) 1165 ie_len = physts_ie_len_tab[ie]; 1166 else 1167 ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; 1168 1169 return ie_len; 1170 } 1171 1172 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, 1173 struct rtw89_rx_phy_ppdu *phy_ppdu) 1174 { 1175 s16 cfo; 1176 1177 phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr); 1178 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1179 return; 1180 /* sign conversion for S(12,2) */ 1181 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_CFO(addr), 11); 1182 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1183 } 1184 1185 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, 1186 struct rtw89_rx_phy_ppdu *phy_ppdu) 1187 { 1188 u8 ie; 1189 1190 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1191 switch (ie) { 1192 case RTW89_PHYSTS_IE01_CMN_OFDM: 1193 rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); 1194 break; 1195 default: 1196 break; 1197 } 1198 1199 return 0; 1200 } 1201 1202 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1203 { 1204 s8 *rssi = phy_ppdu->rssi; 1205 u8 *buf = phy_ppdu->buf; 1206 1207 phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf); 1208 phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); 1209 rssi[RF_PATH_A] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_A(buf)); 1210 rssi[RF_PATH_B] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_B(buf)); 1211 rssi[RF_PATH_C] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_C(buf)); 1212 rssi[RF_PATH_D] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_D(buf)); 1213 } 1214 1215 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1216 struct rtw89_rx_phy_ppdu *phy_ppdu) 1217 { 1218 if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { 1219 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1220 return -EINVAL; 1221 } 1222 rtw89_core_update_phy_ppdu(phy_ppdu); 1223 ieee80211_iterate_stations_atomic(rtwdev->hw, 1224 rtw89_core_rx_process_phy_ppdu_iter, 1225 phy_ppdu); 1226 1227 return 0; 1228 } 1229 1230 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1231 struct rtw89_rx_phy_ppdu *phy_ppdu) 1232 { 1233 u16 ie_len; 1234 u8 *pos, *end; 1235 1236 /* mark invalid reports and bypass them */ 1237 if (phy_ppdu->ie < RTW89_CCK_PKT) 1238 return -EINVAL; 1239 1240 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1241 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1242 while (pos < end) { 1243 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); 1244 rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); 1245 pos += ie_len; 1246 if (pos > end || ie_len == 0) { 1247 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1248 "phy status parse failed\n"); 1249 return -EINVAL; 1250 } 1251 } 1252 1253 return 0; 1254 } 1255 1256 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1257 struct rtw89_rx_phy_ppdu *phy_ppdu) 1258 { 1259 int ret; 1260 1261 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1262 if (ret) 1263 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1264 else 1265 phy_ppdu->valid = true; 1266 } 1267 1268 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1269 const struct rtw89_rx_desc_info *desc_info, 1270 bool rx_status) 1271 { 1272 switch (desc_info->gi_ltf) { 1273 case RTW89_GILTF_SGI_4XHE08: 1274 case RTW89_GILTF_2XHE08: 1275 case RTW89_GILTF_1XHE08: 1276 return NL80211_RATE_INFO_HE_GI_0_8; 1277 case RTW89_GILTF_2XHE16: 1278 case RTW89_GILTF_1XHE16: 1279 return NL80211_RATE_INFO_HE_GI_1_6; 1280 case RTW89_GILTF_LGI_4XHE32: 1281 return NL80211_RATE_INFO_HE_GI_3_2; 1282 default: 1283 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); 1284 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; 1285 } 1286 } 1287 1288 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1289 struct rtw89_rx_desc_info *desc_info, 1290 struct ieee80211_rx_status *status) 1291 { 1292 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1293 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1294 u16 data_rate; 1295 bool ret; 1296 1297 data_rate = desc_info->data_rate; 1298 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1299 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1300 rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1301 /* rate_idx is still hardware value here */ 1302 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1303 rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1304 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1305 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1306 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1307 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1308 } else { 1309 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1310 } 1311 1312 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1313 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); 1314 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1315 status->rate_idx == rate_idx && 1316 status->he_gi == gi_ltf && 1317 status->bw == bw; 1318 1319 return ret; 1320 } 1321 1322 struct rtw89_vif_rx_stats_iter_data { 1323 struct rtw89_dev *rtwdev; 1324 struct rtw89_rx_phy_ppdu *phy_ppdu; 1325 struct rtw89_rx_desc_info *desc_info; 1326 struct sk_buff *skb; 1327 const u8 *bssid; 1328 }; 1329 1330 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1331 struct ieee80211_vif *vif, 1332 struct sk_buff *skb) 1333 { 1334 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1335 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1336 u8 *pos, *end, type; 1337 u16 aid; 1338 1339 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1340 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1341 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1342 return; 1343 1344 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1345 if (type != IEEE80211_TRIGGER_TYPE_BASIC) 1346 return; 1347 1348 end = (u8 *)tf + skb->len; 1349 pos = tf->variable; 1350 1351 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1352 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1353 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1354 "[TF] aid: %d, ul_mcs: %d, rua: %d\n", 1355 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1356 RTW89_GET_TF_USER_INFO_RUA(pos)); 1357 1358 if (aid == RTW89_TF_PAD) 1359 break; 1360 1361 if (aid == vif->cfg.aid) { 1362 rtwvif->stats.rx_tf_acc++; 1363 rtwdev->stats.rx_tf_acc++; 1364 break; 1365 } 1366 1367 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1368 } 1369 } 1370 1371 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1372 struct ieee80211_vif *vif) 1373 { 1374 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1375 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1376 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1377 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1378 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1379 struct sk_buff *skb = iter_data->skb; 1380 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1381 const u8 *bssid = iter_data->bssid; 1382 1383 if (ieee80211_is_trigger(hdr->frame_control)) { 1384 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1385 return; 1386 } 1387 1388 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1389 return; 1390 1391 if (ieee80211_is_beacon(hdr->frame_control)) 1392 pkt_stat->beacon_nr++; 1393 1394 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1395 return; 1396 1397 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1398 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1399 1400 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1401 } 1402 1403 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1404 struct rtw89_rx_phy_ppdu *phy_ppdu, 1405 struct rtw89_rx_desc_info *desc_info, 1406 struct sk_buff *skb) 1407 { 1408 struct rtw89_vif_rx_stats_iter_data iter_data; 1409 1410 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1411 1412 iter_data.rtwdev = rtwdev; 1413 iter_data.phy_ppdu = phy_ppdu; 1414 iter_data.desc_info = desc_info; 1415 iter_data.skb = skb; 1416 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1417 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1418 } 1419 1420 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1421 struct ieee80211_rx_status *status) 1422 { 1423 const struct rtw89_chan_rcd *rcd = 1424 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1425 u16 chan = rcd->prev_primary_channel; 1426 u8 band = rcd->prev_band_type == RTW89_BAND_2G ? 1427 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1428 1429 if (status->band != NL80211_BAND_2GHZ && 1430 status->encoding == RX_ENC_LEGACY && 1431 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1432 status->freq = ieee80211_channel_to_frequency(chan, band); 1433 status->band = band; 1434 } 1435 } 1436 1437 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1438 { 1439 if (rx_status->band == NL80211_BAND_2GHZ || 1440 rx_status->encoding != RX_ENC_LEGACY) 1441 return; 1442 1443 /* Some control frames' freq(ACKs in this case) are reported wrong due 1444 * to FW notify timing, set to lowest rate to prevent overflow. 1445 */ 1446 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1447 rx_status->rate_idx = 0; 1448 return; 1449 } 1450 1451 /* No 4 CCK rates for non-2G */ 1452 rx_status->rate_idx -= 4; 1453 } 1454 1455 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 1456 struct rtw89_rx_phy_ppdu *phy_ppdu, 1457 struct rtw89_rx_desc_info *desc_info, 1458 struct sk_buff *skb_ppdu, 1459 struct ieee80211_rx_status *rx_status) 1460 { 1461 struct napi_struct *napi = &rtwdev->napi; 1462 1463 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 1464 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state))) 1465 napi = NULL; 1466 1467 rtw89_core_hw_to_sband_rate(rx_status); 1468 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 1469 /* In low power mode, it does RX in thread context. */ 1470 local_bh_disable(); 1471 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 1472 local_bh_enable(); 1473 rtwdev->napi_budget_countdown--; 1474 } 1475 1476 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 1477 struct rtw89_rx_phy_ppdu *phy_ppdu, 1478 struct rtw89_rx_desc_info *desc_info, 1479 struct sk_buff *skb) 1480 { 1481 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1482 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 1483 struct sk_buff *skb_ppdu = NULL, *tmp; 1484 struct ieee80211_rx_status *rx_status; 1485 1486 if (curr > RTW89_MAX_PPDU_CNT) 1487 return; 1488 1489 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 1490 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 1491 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1492 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 1493 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 1494 rtw89_correct_cck_chan(rtwdev, rx_status); 1495 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 1496 } 1497 } 1498 1499 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 1500 struct rtw89_rx_desc_info *desc_info, 1501 struct sk_buff *skb) 1502 { 1503 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 1504 .len = skb->len, 1505 .to_self = desc_info->addr1_match, 1506 .rate = desc_info->data_rate, 1507 .mac_id = desc_info->mac_id}; 1508 int ret; 1509 1510 if (desc_info->mac_info_valid) 1511 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 1512 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 1513 if (ret) 1514 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); 1515 1516 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 1517 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 1518 dev_kfree_skb_any(skb); 1519 } 1520 1521 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 1522 struct rtw89_rx_desc_info *desc_info, 1523 struct sk_buff *skb) 1524 { 1525 switch (desc_info->pkt_type) { 1526 case RTW89_CORE_RX_TYPE_C2H: 1527 rtw89_fw_c2h_irqsafe(rtwdev, skb); 1528 break; 1529 case RTW89_CORE_RX_TYPE_PPDU_STAT: 1530 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 1531 break; 1532 default: 1533 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 1534 desc_info->pkt_type); 1535 dev_kfree_skb_any(skb); 1536 break; 1537 } 1538 } 1539 1540 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 1541 struct rtw89_rx_desc_info *desc_info, 1542 u8 *data, u32 data_offset) 1543 { 1544 const struct rtw89_chip_info *chip = rtwdev->chip; 1545 struct rtw89_rxdesc_short *rxd_s; 1546 struct rtw89_rxdesc_long *rxd_l; 1547 u8 shift_len, drv_info_len; 1548 1549 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 1550 desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); 1551 desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); 1552 desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); 1553 desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); 1554 desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); 1555 if (chip->chip_id == RTL8852C) 1556 desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s); 1557 else 1558 desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); 1559 desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); 1560 desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); 1561 desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); 1562 desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); 1563 desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); 1564 desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); 1565 desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); 1566 desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); 1567 desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); 1568 desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); 1569 desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); 1570 desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); 1571 1572 shift_len = desc_info->shift << 1; /* 2-byte unit */ 1573 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 1574 desc_info->offset = data_offset + shift_len + drv_info_len; 1575 desc_info->ready = true; 1576 1577 if (!desc_info->long_rxdesc) 1578 return; 1579 1580 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 1581 desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); 1582 desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); 1583 desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); 1584 desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); 1585 desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); 1586 desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); 1587 } 1588 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 1589 1590 struct rtw89_core_iter_rx_status { 1591 struct rtw89_dev *rtwdev; 1592 struct ieee80211_rx_status *rx_status; 1593 struct rtw89_rx_desc_info *desc_info; 1594 u8 mac_id; 1595 }; 1596 1597 static 1598 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 1599 { 1600 struct rtw89_core_iter_rx_status *iter_data = 1601 (struct rtw89_core_iter_rx_status *)data; 1602 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 1603 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1604 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1605 u8 mac_id = iter_data->mac_id; 1606 1607 if (mac_id != rtwsta->mac_id) 1608 return; 1609 1610 rtwsta->rx_status = *rx_status; 1611 rtwsta->rx_hw_rate = desc_info->data_rate; 1612 } 1613 1614 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 1615 struct rtw89_rx_desc_info *desc_info, 1616 struct ieee80211_rx_status *rx_status) 1617 { 1618 struct rtw89_core_iter_rx_status iter_data; 1619 1620 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 1621 return; 1622 1623 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 1624 return; 1625 1626 iter_data.rtwdev = rtwdev; 1627 iter_data.rx_status = rx_status; 1628 iter_data.desc_info = desc_info; 1629 iter_data.mac_id = desc_info->mac_id; 1630 ieee80211_iterate_stations_atomic(rtwdev->hw, 1631 rtw89_core_stats_sta_rx_status_iter, 1632 &iter_data); 1633 } 1634 1635 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 1636 struct rtw89_rx_desc_info *desc_info, 1637 struct ieee80211_rx_status *rx_status) 1638 { 1639 const struct cfg80211_chan_def *chandef = 1640 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 1641 const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1642 u16 data_rate; 1643 u8 data_rate_mode; 1644 1645 /* currently using single PHY */ 1646 rx_status->freq = chandef->chan->center_freq; 1647 rx_status->band = chandef->chan->band; 1648 1649 if (rtwdev->scanning && 1650 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 1651 u8 chan = cur->primary_channel; 1652 u8 band = cur->band_type; 1653 enum nl80211_band nl_band; 1654 1655 nl_band = rtw89_hw_to_nl80211_band(band); 1656 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 1657 rx_status->band = nl_band; 1658 } 1659 1660 if (desc_info->icv_err || desc_info->crc32_err) 1661 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 1662 1663 if (desc_info->hw_dec && 1664 !(desc_info->sw_dec || desc_info->icv_err)) 1665 rx_status->flag |= RX_FLAG_DECRYPTED; 1666 1667 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1668 1669 data_rate = desc_info->data_rate; 1670 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1671 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1672 rx_status->encoding = RX_ENC_LEGACY; 1673 rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1674 /* convert rate_idx after we get the correct band */ 1675 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1676 rx_status->encoding = RX_ENC_HT; 1677 rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1678 if (desc_info->gi_ltf) 1679 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1680 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1681 rx_status->encoding = RX_ENC_VHT; 1682 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1683 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1684 if (desc_info->gi_ltf) 1685 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1686 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1687 rx_status->encoding = RX_ENC_HE; 1688 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1689 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1690 } else { 1691 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1692 } 1693 1694 /* he_gi is used to match ppdu, so we always fill it. */ 1695 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); 1696 rx_status->flag |= RX_FLAG_MACTIME_START; 1697 rx_status->mactime = desc_info->free_run_cnt; 1698 1699 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 1700 } 1701 1702 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 1703 { 1704 const struct rtw89_chip_info *chip = rtwdev->chip; 1705 1706 if (rtw89_disable_ps_mode || !chip->ps_mode_supported) 1707 return RTW89_PS_MODE_NONE; 1708 1709 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) 1710 return RTW89_PS_MODE_PWR_GATED; 1711 1712 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 1713 return RTW89_PS_MODE_CLK_GATED; 1714 1715 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 1716 return RTW89_PS_MODE_RFOFF; 1717 1718 return RTW89_PS_MODE_NONE; 1719 } 1720 1721 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 1722 struct rtw89_rx_desc_info *desc_info) 1723 { 1724 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1725 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1726 struct ieee80211_rx_status *rx_status; 1727 struct sk_buff *skb_ppdu, *tmp; 1728 1729 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 1730 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 1731 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1732 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 1733 } 1734 } 1735 1736 void rtw89_core_rx(struct rtw89_dev *rtwdev, 1737 struct rtw89_rx_desc_info *desc_info, 1738 struct sk_buff *skb) 1739 { 1740 struct ieee80211_rx_status *rx_status; 1741 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1742 u8 ppdu_cnt = desc_info->ppdu_cnt; 1743 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1744 1745 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 1746 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 1747 return; 1748 } 1749 1750 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 1751 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 1752 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 1753 } 1754 1755 rx_status = IEEE80211_SKB_RXCB(skb); 1756 memset(rx_status, 0, sizeof(*rx_status)); 1757 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 1758 if (desc_info->long_rxdesc && 1759 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 1760 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 1761 else 1762 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 1763 } 1764 EXPORT_SYMBOL(rtw89_core_rx); 1765 1766 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 1767 { 1768 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1769 return; 1770 1771 napi_enable(&rtwdev->napi); 1772 } 1773 EXPORT_SYMBOL(rtw89_core_napi_start); 1774 1775 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 1776 { 1777 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1778 return; 1779 1780 napi_synchronize(&rtwdev->napi); 1781 napi_disable(&rtwdev->napi); 1782 } 1783 EXPORT_SYMBOL(rtw89_core_napi_stop); 1784 1785 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 1786 { 1787 init_dummy_netdev(&rtwdev->netdev); 1788 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 1789 rtwdev->hci.ops->napi_poll, NAPI_POLL_WEIGHT); 1790 } 1791 EXPORT_SYMBOL(rtw89_core_napi_init); 1792 1793 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 1794 { 1795 rtw89_core_napi_stop(rtwdev); 1796 netif_napi_del(&rtwdev->napi); 1797 } 1798 EXPORT_SYMBOL(rtw89_core_napi_deinit); 1799 1800 static void rtw89_core_ba_work(struct work_struct *work) 1801 { 1802 struct rtw89_dev *rtwdev = 1803 container_of(work, struct rtw89_dev, ba_work); 1804 struct rtw89_txq *rtwtxq, *tmp; 1805 int ret; 1806 1807 spin_lock_bh(&rtwdev->ba_lock); 1808 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1809 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1810 struct ieee80211_sta *sta = txq->sta; 1811 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1812 u8 tid = txq->tid; 1813 1814 if (!sta) { 1815 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 1816 goto skip_ba_work; 1817 } 1818 1819 if (rtwsta->disassoc) { 1820 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1821 "cannot start BA with disassoc sta\n"); 1822 goto skip_ba_work; 1823 } 1824 1825 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 1826 if (ret) { 1827 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1828 "failed to setup BA session for %pM:%2d: %d\n", 1829 sta->addr, tid, ret); 1830 if (ret == -EINVAL) 1831 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 1832 } 1833 skip_ba_work: 1834 list_del_init(&rtwtxq->list); 1835 } 1836 spin_unlock_bh(&rtwdev->ba_lock); 1837 } 1838 1839 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 1840 struct ieee80211_sta *sta) 1841 { 1842 struct rtw89_txq *rtwtxq, *tmp; 1843 1844 spin_lock_bh(&rtwdev->ba_lock); 1845 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1846 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1847 1848 if (sta == txq->sta) 1849 list_del_init(&rtwtxq->list); 1850 } 1851 spin_unlock_bh(&rtwdev->ba_lock); 1852 } 1853 1854 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 1855 struct ieee80211_sta *sta) 1856 { 1857 struct rtw89_txq *rtwtxq, *tmp; 1858 1859 spin_lock_bh(&rtwdev->ba_lock); 1860 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 1861 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1862 1863 if (sta == txq->sta) { 1864 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 1865 list_del_init(&rtwtxq->list); 1866 } 1867 } 1868 spin_unlock_bh(&rtwdev->ba_lock); 1869 } 1870 1871 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 1872 struct rtw89_txq *rtwtxq) 1873 { 1874 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1875 struct ieee80211_sta *sta = txq->sta; 1876 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1877 1878 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 1879 return; 1880 1881 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 1882 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1883 return; 1884 1885 spin_lock_bh(&rtwdev->ba_lock); 1886 if (!list_empty(&rtwtxq->list)) { 1887 list_del_init(&rtwtxq->list); 1888 goto out; 1889 } 1890 1891 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 1892 1893 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 1894 ieee80211_stop_tx_ba_session(sta, txq->tid); 1895 cancel_delayed_work(&rtwdev->forbid_ba_work); 1896 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 1897 RTW89_FORBID_BA_TIMER); 1898 1899 out: 1900 spin_unlock_bh(&rtwdev->ba_lock); 1901 } 1902 1903 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 1904 struct rtw89_txq *rtwtxq, 1905 struct sk_buff *skb) 1906 { 1907 struct ieee80211_hw *hw = rtwdev->hw; 1908 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1909 struct ieee80211_sta *sta = txq->sta; 1910 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1911 1912 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 1913 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 1914 return; 1915 } 1916 1917 if (unlikely(!sta)) 1918 return; 1919 1920 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1921 return; 1922 1923 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 1924 return; 1925 1926 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 1927 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 1928 return; 1929 } 1930 1931 spin_lock_bh(&rtwdev->ba_lock); 1932 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 1933 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 1934 ieee80211_queue_work(hw, &rtwdev->ba_work); 1935 } 1936 spin_unlock_bh(&rtwdev->ba_lock); 1937 } 1938 1939 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 1940 struct rtw89_txq *rtwtxq, 1941 unsigned long frame_cnt, 1942 unsigned long byte_cnt) 1943 { 1944 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1945 struct ieee80211_vif *vif = txq->vif; 1946 struct ieee80211_sta *sta = txq->sta; 1947 struct sk_buff *skb; 1948 unsigned long i; 1949 int ret; 1950 1951 rcu_read_lock(); 1952 for (i = 0; i < frame_cnt; i++) { 1953 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 1954 if (!skb) { 1955 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 1956 goto out; 1957 } 1958 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 1959 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 1960 if (ret) { 1961 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 1962 ieee80211_free_txskb(rtwdev->hw, skb); 1963 break; 1964 } 1965 } 1966 out: 1967 rcu_read_unlock(); 1968 } 1969 1970 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 1971 { 1972 u8 qsel, ch_dma; 1973 1974 qsel = rtw89_core_get_qsel(rtwdev, tid); 1975 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1976 1977 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 1978 } 1979 1980 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 1981 struct ieee80211_txq *txq, 1982 unsigned long *frame_cnt, 1983 bool *sched_txq, bool *reinvoke) 1984 { 1985 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 1986 struct ieee80211_sta *sta = txq->sta; 1987 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1988 1989 if (!sta || rtwsta->max_agg_wait <= 0) 1990 return false; 1991 1992 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 1993 return false; 1994 1995 if (*frame_cnt > 1) { 1996 *frame_cnt -= 1; 1997 *sched_txq = true; 1998 *reinvoke = true; 1999 rtwtxq->wait_cnt = 1; 2000 return false; 2001 } 2002 2003 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2004 *reinvoke = true; 2005 rtwtxq->wait_cnt++; 2006 return true; 2007 } 2008 2009 rtwtxq->wait_cnt = 0; 2010 return false; 2011 } 2012 2013 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2014 { 2015 struct ieee80211_hw *hw = rtwdev->hw; 2016 struct ieee80211_txq *txq; 2017 struct rtw89_txq *rtwtxq; 2018 unsigned long frame_cnt; 2019 unsigned long byte_cnt; 2020 u32 tx_resource; 2021 bool sched_txq; 2022 2023 ieee80211_txq_schedule_start(hw, ac); 2024 while ((txq = ieee80211_next_txq(hw, ac))) { 2025 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2026 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2027 sched_txq = false; 2028 2029 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2030 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2031 ieee80211_return_txq(hw, txq, true); 2032 continue; 2033 } 2034 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2035 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2036 ieee80211_return_txq(hw, txq, sched_txq); 2037 if (frame_cnt != 0) 2038 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2039 2040 /* bound of tx_resource could get stuck due to burst traffic */ 2041 if (frame_cnt == tx_resource) 2042 *reinvoke = true; 2043 } 2044 ieee80211_txq_schedule_end(hw, ac); 2045 } 2046 2047 static void rtw89_ips_work(struct work_struct *work) 2048 { 2049 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2050 ips_work); 2051 mutex_lock(&rtwdev->mutex); 2052 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 2053 rtw89_enter_ips(rtwdev); 2054 mutex_unlock(&rtwdev->mutex); 2055 } 2056 2057 static void rtw89_core_txq_work(struct work_struct *w) 2058 { 2059 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2060 bool reinvoke = false; 2061 u8 ac; 2062 2063 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2064 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2065 2066 if (reinvoke) { 2067 /* reinvoke to process the last frame */ 2068 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2069 } 2070 } 2071 2072 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2073 { 2074 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2075 txq_reinvoke_work.work); 2076 2077 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2078 } 2079 2080 static void rtw89_forbid_ba_work(struct work_struct *w) 2081 { 2082 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2083 forbid_ba_work.work); 2084 struct rtw89_txq *rtwtxq, *tmp; 2085 2086 spin_lock_bh(&rtwdev->ba_lock); 2087 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2088 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2089 list_del_init(&rtwtxq->list); 2090 } 2091 spin_unlock_bh(&rtwdev->ba_lock); 2092 } 2093 2094 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2095 u32 throughput, u64 cnt) 2096 { 2097 if (cnt < 100) 2098 return RTW89_TFC_IDLE; 2099 if (throughput > 50) 2100 return RTW89_TFC_HIGH; 2101 if (throughput > 10) 2102 return RTW89_TFC_MID; 2103 if (throughput > 2) 2104 return RTW89_TFC_LOW; 2105 return RTW89_TFC_ULTRA_LOW; 2106 } 2107 2108 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2109 struct rtw89_traffic_stats *stats) 2110 { 2111 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2112 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2113 2114 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2115 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2116 2117 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 2118 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 2119 2120 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 2121 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 2122 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 2123 stats->tx_cnt); 2124 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 2125 stats->rx_cnt); 2126 stats->tx_avg_len = stats->tx_cnt ? 2127 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 2128 stats->rx_avg_len = stats->rx_cnt ? 2129 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 2130 2131 stats->tx_unicast = 0; 2132 stats->rx_unicast = 0; 2133 stats->tx_cnt = 0; 2134 stats->rx_cnt = 0; 2135 stats->rx_tf_periodic = stats->rx_tf_acc; 2136 stats->rx_tf_acc = 0; 2137 2138 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 2139 return true; 2140 2141 return false; 2142 } 2143 2144 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 2145 { 2146 struct rtw89_vif *rtwvif; 2147 bool tfc_changed; 2148 2149 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 2150 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2151 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 2152 2153 return tfc_changed; 2154 } 2155 2156 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2157 { 2158 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2159 return; 2160 2161 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 2162 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 2163 rtw89_enter_lps(rtwdev, rtwvif->mac_id); 2164 } 2165 2166 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 2167 { 2168 struct rtw89_vif *rtwvif; 2169 2170 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2171 rtw89_vif_enter_lps(rtwdev, rtwvif); 2172 } 2173 2174 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 2175 struct rtw89_traffic_stats *stats) 2176 { 2177 stats->tx_unicast = 0; 2178 stats->rx_unicast = 0; 2179 stats->tx_cnt = 0; 2180 stats->rx_cnt = 0; 2181 ewma_tp_init(&stats->tx_ewma_tp); 2182 ewma_tp_init(&stats->rx_ewma_tp); 2183 } 2184 2185 static void rtw89_track_work(struct work_struct *work) 2186 { 2187 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2188 track_work.work); 2189 bool tfc_changed; 2190 2191 mutex_lock(&rtwdev->mutex); 2192 2193 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2194 goto out; 2195 2196 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2197 RTW89_TRACK_WORK_PERIOD); 2198 2199 tfc_changed = rtw89_traffic_stats_track(rtwdev); 2200 if (rtwdev->scanning) 2201 goto out; 2202 2203 rtw89_leave_lps(rtwdev); 2204 2205 if (tfc_changed) { 2206 rtw89_hci_recalc_int_mit(rtwdev); 2207 rtw89_btc_ntfy_wl_sta(rtwdev); 2208 } 2209 rtw89_mac_bf_monitor_track(rtwdev); 2210 rtw89_phy_stat_track(rtwdev); 2211 rtw89_phy_env_monitor_track(rtwdev); 2212 rtw89_phy_dig(rtwdev); 2213 rtw89_chip_rfk_track(rtwdev); 2214 rtw89_phy_ra_update(rtwdev); 2215 rtw89_phy_cfo_track(rtwdev); 2216 2217 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 2218 rtw89_enter_lps_track(rtwdev); 2219 2220 out: 2221 mutex_unlock(&rtwdev->mutex); 2222 } 2223 2224 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 2225 { 2226 unsigned long bit; 2227 2228 bit = find_first_zero_bit(addr, size); 2229 if (bit < size) 2230 set_bit(bit, addr); 2231 2232 return bit; 2233 } 2234 2235 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 2236 { 2237 clear_bit(bit, addr); 2238 } 2239 2240 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 2241 { 2242 bitmap_zero(addr, nbits); 2243 } 2244 2245 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 2246 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2247 { 2248 const struct rtw89_chip_info *chip = rtwdev->chip; 2249 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2250 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2251 u8 idx; 2252 int i; 2253 2254 lockdep_assert_held(&rtwdev->mutex); 2255 2256 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 2257 if (idx == chip->bacam_num) { 2258 /* allocate a static BA CAM to tid=0/5, so replace the existing 2259 * one if BA CAM is full. Hardware will process the original tid 2260 * automatically. 2261 */ 2262 if (tid != 0 && tid != 5) 2263 return -ENOSPC; 2264 2265 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 2266 tmp = &cam_info->ba_cam_entry[i]; 2267 if (tmp->tid == 0 || tmp->tid == 5) 2268 continue; 2269 2270 idx = i; 2271 entry = tmp; 2272 list_del(&entry->list); 2273 break; 2274 } 2275 2276 if (!entry) 2277 return -ENOSPC; 2278 } else { 2279 entry = &cam_info->ba_cam_entry[idx]; 2280 } 2281 2282 entry->tid = tid; 2283 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 2284 2285 *cam_idx = idx; 2286 2287 return 0; 2288 } 2289 2290 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 2291 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2292 { 2293 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2294 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2295 u8 idx; 2296 2297 lockdep_assert_held(&rtwdev->mutex); 2298 2299 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 2300 if (entry->tid != tid) 2301 continue; 2302 2303 idx = entry - cam_info->ba_cam_entry; 2304 list_del(&entry->list); 2305 2306 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 2307 *cam_idx = idx; 2308 return 0; 2309 } 2310 2311 return -ENOENT; 2312 } 2313 2314 #define RTW89_TYPE_MAPPING(_type) \ 2315 case NL80211_IFTYPE_ ## _type: \ 2316 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 2317 break 2318 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 2319 { 2320 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2321 2322 switch (vif->type) { 2323 RTW89_TYPE_MAPPING(ADHOC); 2324 RTW89_TYPE_MAPPING(STATION); 2325 RTW89_TYPE_MAPPING(AP); 2326 RTW89_TYPE_MAPPING(MONITOR); 2327 RTW89_TYPE_MAPPING(MESH_POINT); 2328 default: 2329 WARN_ON(1); 2330 break; 2331 } 2332 2333 switch (vif->type) { 2334 case NL80211_IFTYPE_AP: 2335 case NL80211_IFTYPE_MESH_POINT: 2336 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 2337 rtwvif->self_role = RTW89_SELF_ROLE_AP; 2338 break; 2339 case NL80211_IFTYPE_ADHOC: 2340 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 2341 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2342 break; 2343 case NL80211_IFTYPE_STATION: 2344 if (assoc) { 2345 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 2346 rtwvif->trigger = vif->bss_conf.he_support; 2347 } else { 2348 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 2349 rtwvif->trigger = false; 2350 } 2351 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2352 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 2353 break; 2354 default: 2355 WARN_ON(1); 2356 break; 2357 } 2358 } 2359 2360 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 2361 struct ieee80211_vif *vif, 2362 struct ieee80211_sta *sta) 2363 { 2364 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2365 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2366 int i; 2367 2368 rtwsta->rtwvif = rtwvif; 2369 rtwsta->prev_rssi = 0; 2370 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 2371 2372 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 2373 rtw89_core_txq_init(rtwdev, sta->txq[i]); 2374 2375 ewma_rssi_init(&rtwsta->avg_rssi); 2376 2377 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2378 /* for station mode, assign the mac_id from itself */ 2379 rtwsta->mac_id = rtwvif->mac_id; 2380 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2381 BTC_ROLE_MSTS_STA_CONN_START); 2382 rtw89_chip_rfk_channel(rtwdev); 2383 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2384 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 2385 RTW89_MAX_MAC_ID_NUM); 2386 } 2387 2388 return 0; 2389 } 2390 2391 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 2392 struct ieee80211_vif *vif, 2393 struct ieee80211_sta *sta) 2394 { 2395 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2396 2397 rtwdev->total_sta_assoc--; 2398 rtwsta->disassoc = true; 2399 2400 return 0; 2401 } 2402 2403 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 2404 struct ieee80211_vif *vif, 2405 struct ieee80211_sta *sta) 2406 { 2407 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2408 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2409 int ret; 2410 2411 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 2412 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 2413 rtw89_core_free_sta_pending_ba(rtwdev, sta); 2414 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 2415 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2416 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 2417 if (sta->tdls) 2418 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 2419 2420 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2421 rtw89_vif_type_mapping(vif, false); 2422 2423 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2424 if (ret) { 2425 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2426 return ret; 2427 } 2428 2429 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 2430 if (ret) { 2431 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2432 return ret; 2433 } 2434 2435 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2436 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_REMOVE); 2437 if (ret) { 2438 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2439 return ret; 2440 } 2441 } 2442 2443 /* update cam aid mac_id net_type */ 2444 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2445 if (ret) { 2446 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2447 return ret; 2448 } 2449 2450 return ret; 2451 } 2452 2453 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 2454 struct ieee80211_vif *vif, 2455 struct ieee80211_sta *sta) 2456 { 2457 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2458 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2459 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 2460 int ret; 2461 2462 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2463 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 2464 if (ret) { 2465 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 2466 return ret; 2467 } 2468 2469 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_CREATE); 2470 if (ret) { 2471 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2472 return ret; 2473 } 2474 2475 if (sta->tdls) { 2476 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 2477 if (ret) { 2478 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 2479 return ret; 2480 } 2481 } 2482 2483 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 2484 if (ret) { 2485 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 2486 return ret; 2487 } 2488 } 2489 2490 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2491 if (ret) { 2492 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2493 return ret; 2494 } 2495 2496 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 2497 if (ret) { 2498 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2499 return ret; 2500 } 2501 2502 /* update cam aid mac_id net_type */ 2503 rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2504 if (ret) { 2505 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2506 return ret; 2507 } 2508 2509 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwsta->mac_id); 2510 if (ret) { 2511 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 2512 return ret; 2513 } 2514 2515 rtwdev->total_sta_assoc++; 2516 rtw89_phy_ra_assoc(rtwdev, sta); 2517 rtw89_mac_bf_assoc(rtwdev, vif, sta); 2518 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 2519 2520 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2521 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2522 BTC_ROLE_MSTS_STA_CONN_END); 2523 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); 2524 } 2525 2526 return ret; 2527 } 2528 2529 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 2530 struct ieee80211_vif *vif, 2531 struct ieee80211_sta *sta) 2532 { 2533 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2534 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2535 2536 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2537 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2538 BTC_ROLE_MSTS_STA_DIS_CONN); 2539 else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2540 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2541 2542 return 0; 2543 } 2544 2545 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 2546 struct ieee80211_sta_ht_cap *ht_cap) 2547 { 2548 static const __le16 highest[RF_PATH_MAX] = { 2549 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 2550 }; 2551 struct rtw89_hal *hal = &rtwdev->hal; 2552 u8 nss = hal->rx_nss; 2553 int i; 2554 2555 ht_cap->ht_supported = true; 2556 ht_cap->cap = 0; 2557 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 2558 IEEE80211_HT_CAP_MAX_AMSDU | 2559 IEEE80211_HT_CAP_TX_STBC | 2560 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 2561 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 2562 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 2563 IEEE80211_HT_CAP_DSSSCCK40 | 2564 IEEE80211_HT_CAP_SGI_40; 2565 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 2566 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 2567 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 2568 for (i = 0; i < nss; i++) 2569 ht_cap->mcs.rx_mask[i] = 0xFF; 2570 ht_cap->mcs.rx_mask[4] = 0x01; 2571 ht_cap->mcs.rx_highest = highest[nss - 1]; 2572 } 2573 2574 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 2575 struct ieee80211_sta_vht_cap *vht_cap) 2576 { 2577 static const __le16 highest_bw80[RF_PATH_MAX] = { 2578 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 2579 }; 2580 static const __le16 highest_bw160[RF_PATH_MAX] = { 2581 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 2582 }; 2583 const struct rtw89_chip_info *chip = rtwdev->chip; 2584 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 2585 struct rtw89_hal *hal = &rtwdev->hal; 2586 u16 tx_mcs_map = 0, rx_mcs_map = 0; 2587 u8 sts_cap = 3; 2588 int i; 2589 2590 for (i = 0; i < 8; i++) { 2591 if (i < hal->tx_nss) 2592 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2593 else 2594 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2595 if (i < hal->rx_nss) 2596 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2597 else 2598 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2599 } 2600 2601 vht_cap->vht_supported = true; 2602 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 2603 IEEE80211_VHT_CAP_SHORT_GI_80 | 2604 IEEE80211_VHT_CAP_RXSTBC_1 | 2605 IEEE80211_VHT_CAP_HTC_VHT | 2606 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 2607 0; 2608 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 2609 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 2610 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 2611 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 2612 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 2613 if (chip->support_bw160) 2614 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 2615 IEEE80211_VHT_CAP_SHORT_GI_160; 2616 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 2617 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 2618 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 2619 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 2620 } 2621 2622 #define RTW89_SBAND_IFTYPES_NR 2 2623 2624 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 2625 enum nl80211_band band, 2626 struct ieee80211_supported_band *sband) 2627 { 2628 const struct rtw89_chip_info *chip = rtwdev->chip; 2629 struct rtw89_hal *hal = &rtwdev->hal; 2630 struct ieee80211_sband_iftype_data *iftype_data; 2631 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 2632 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 2633 u16 mcs_map = 0; 2634 int i; 2635 int nss = hal->rx_nss; 2636 int idx = 0; 2637 2638 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 2639 if (!iftype_data) 2640 return; 2641 2642 for (i = 0; i < 8; i++) { 2643 if (i < nss) 2644 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 2645 else 2646 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 2647 } 2648 2649 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 2650 struct ieee80211_sta_he_cap *he_cap; 2651 u8 *mac_cap_info; 2652 u8 *phy_cap_info; 2653 2654 switch (i) { 2655 case NL80211_IFTYPE_STATION: 2656 case NL80211_IFTYPE_AP: 2657 break; 2658 default: 2659 continue; 2660 } 2661 2662 if (idx >= RTW89_SBAND_IFTYPES_NR) { 2663 rtw89_warn(rtwdev, "run out of iftype_data\n"); 2664 break; 2665 } 2666 2667 iftype_data[idx].types_mask = BIT(i); 2668 he_cap = &iftype_data[idx].he_cap; 2669 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 2670 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 2671 2672 he_cap->has_he = true; 2673 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 2674 if (i == NL80211_IFTYPE_STATION) 2675 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 2676 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 2677 IEEE80211_HE_MAC_CAP2_BSR; 2678 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 2679 if (i == NL80211_IFTYPE_AP) 2680 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 2681 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 2682 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 2683 if (i == NL80211_IFTYPE_STATION) 2684 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 2685 if (band == NL80211_BAND_2GHZ) { 2686 phy_cap_info[0] = 2687 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 2688 } else { 2689 phy_cap_info[0] = 2690 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 2691 if (chip->support_bw160) 2692 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 2693 } 2694 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 2695 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 2696 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 2697 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 2698 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 2699 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 2700 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 2701 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 2702 if (i == NL80211_IFTYPE_STATION) 2703 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 2704 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 2705 if (i == NL80211_IFTYPE_AP) 2706 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 2707 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 2708 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 2709 if (chip->support_bw160) 2710 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 2711 phy_cap_info[5] = no_ng16 ? 0 : 2712 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 2713 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 2714 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 2715 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 2716 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 2717 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 2718 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 2719 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 2720 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 2721 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 2722 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 2723 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 2724 if (chip->support_bw160) 2725 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 2726 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 2727 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 2728 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 2729 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 2730 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 2731 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 2732 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 2733 if (i == NL80211_IFTYPE_STATION) 2734 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 2735 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 2736 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 2737 if (chip->support_bw160) { 2738 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 2739 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 2740 } 2741 2742 if (band == NL80211_BAND_6GHZ) { 2743 __le16 capa; 2744 2745 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 2746 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 2747 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 2748 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 2749 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 2750 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 2751 iftype_data[idx].he_6ghz_capa.capa = capa; 2752 } 2753 2754 idx++; 2755 } 2756 2757 sband->iftype_data = iftype_data; 2758 sband->n_iftype_data = idx; 2759 } 2760 2761 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 2762 { 2763 struct ieee80211_hw *hw = rtwdev->hw; 2764 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 2765 struct ieee80211_supported_band *sband_6ghz = NULL; 2766 u32 size = sizeof(struct ieee80211_supported_band); 2767 u8 support_bands = rtwdev->chip->support_bands; 2768 2769 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 2770 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 2771 if (!sband_2ghz) 2772 goto err; 2773 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 2774 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 2775 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 2776 } 2777 2778 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 2779 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 2780 if (!sband_5ghz) 2781 goto err; 2782 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 2783 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 2784 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 2785 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 2786 } 2787 2788 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 2789 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 2790 if (!sband_6ghz) 2791 goto err; 2792 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 2793 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 2794 } 2795 2796 return 0; 2797 2798 err: 2799 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2800 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2801 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2802 if (sband_2ghz) 2803 kfree(sband_2ghz->iftype_data); 2804 if (sband_5ghz) 2805 kfree(sband_5ghz->iftype_data); 2806 if (sband_6ghz) 2807 kfree(sband_6ghz->iftype_data); 2808 kfree(sband_2ghz); 2809 kfree(sband_5ghz); 2810 kfree(sband_6ghz); 2811 return -ENOMEM; 2812 } 2813 2814 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 2815 { 2816 struct ieee80211_hw *hw = rtwdev->hw; 2817 2818 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 2819 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 2820 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 2821 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 2822 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 2823 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 2824 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 2825 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2826 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2827 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2828 } 2829 2830 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 2831 { 2832 int i; 2833 2834 for (i = 0; i < RTW89_PHY_MAX; i++) 2835 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 2836 for (i = 0; i < RTW89_PHY_MAX; i++) 2837 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 2838 } 2839 2840 void rtw89_core_update_beacon_work(struct work_struct *work) 2841 { 2842 struct rtw89_dev *rtwdev; 2843 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2844 update_beacon_work); 2845 2846 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 2847 return; 2848 2849 rtwdev = rtwvif->rtwdev; 2850 mutex_lock(&rtwdev->mutex); 2851 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 2852 mutex_unlock(&rtwdev->mutex); 2853 } 2854 2855 int rtw89_core_start(struct rtw89_dev *rtwdev) 2856 { 2857 int ret; 2858 2859 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 2860 ret = rtw89_mac_init(rtwdev); 2861 if (ret) { 2862 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 2863 return ret; 2864 } 2865 2866 rtw89_btc_ntfy_poweron(rtwdev); 2867 2868 /* efuse process */ 2869 2870 /* pre-config BB/RF, BB reset/RFC reset */ 2871 rtw89_chip_disable_bb_rf(rtwdev); 2872 ret = rtw89_chip_enable_bb_rf(rtwdev); 2873 if (ret) 2874 return ret; 2875 2876 rtw89_phy_init_bb_reg(rtwdev); 2877 rtw89_phy_init_rf_reg(rtwdev); 2878 2879 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 2880 2881 rtw89_phy_dm_init(rtwdev); 2882 2883 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 2884 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 2885 2886 ret = rtw89_hci_start(rtwdev); 2887 if (ret) { 2888 rtw89_err(rtwdev, "failed to start hci\n"); 2889 return ret; 2890 } 2891 2892 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2893 RTW89_TRACK_WORK_PERIOD); 2894 2895 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 2896 2897 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 2898 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); 2899 rtw89_fw_h2c_init_ba_cam(rtwdev); 2900 2901 return 0; 2902 } 2903 2904 void rtw89_core_stop(struct rtw89_dev *rtwdev) 2905 { 2906 struct rtw89_btc *btc = &rtwdev->btc; 2907 2908 /* Prvent to stop twice; enter_ips and ops_stop */ 2909 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2910 return; 2911 2912 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 2913 2914 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 2915 2916 mutex_unlock(&rtwdev->mutex); 2917 2918 cancel_work_sync(&rtwdev->c2h_work); 2919 cancel_work_sync(&btc->eapol_notify_work); 2920 cancel_work_sync(&btc->arp_notify_work); 2921 cancel_work_sync(&btc->dhcp_notify_work); 2922 cancel_work_sync(&btc->icmp_notify_work); 2923 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 2924 cancel_delayed_work_sync(&rtwdev->track_work); 2925 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 2926 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 2927 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 2928 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 2929 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 2930 2931 mutex_lock(&rtwdev->mutex); 2932 2933 rtw89_btc_ntfy_poweroff(rtwdev); 2934 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 2935 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 2936 rtw89_hci_stop(rtwdev); 2937 rtw89_hci_deinit(rtwdev); 2938 rtw89_mac_pwr_off(rtwdev); 2939 rtw89_hci_reset(rtwdev); 2940 } 2941 2942 int rtw89_core_init(struct rtw89_dev *rtwdev) 2943 { 2944 struct rtw89_btc *btc = &rtwdev->btc; 2945 int ret; 2946 u8 band; 2947 2948 INIT_LIST_HEAD(&rtwdev->ba_list); 2949 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 2950 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 2951 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 2952 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 2953 if (!(rtwdev->chip->support_bands & BIT(band))) 2954 continue; 2955 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 2956 } 2957 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 2958 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 2959 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 2960 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 2961 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 2962 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 2963 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 2964 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 2965 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 2966 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2967 spin_lock_init(&rtwdev->ba_lock); 2968 spin_lock_init(&rtwdev->rpwm_lock); 2969 mutex_init(&rtwdev->mutex); 2970 mutex_init(&rtwdev->rf_mutex); 2971 rtwdev->total_sta_assoc = 0; 2972 2973 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 2974 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 2975 skb_queue_head_init(&rtwdev->c2h_queue); 2976 rtw89_core_ppdu_sts_init(rtwdev); 2977 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 2978 2979 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 2980 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 2981 2982 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 2983 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 2984 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 2985 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 2986 2987 ret = rtw89_load_firmware(rtwdev); 2988 if (ret) { 2989 rtw89_warn(rtwdev, "no firmware loaded\n"); 2990 return ret; 2991 } 2992 rtw89_ser_init(rtwdev); 2993 rtw89_entity_init(rtwdev); 2994 2995 return 0; 2996 } 2997 EXPORT_SYMBOL(rtw89_core_init); 2998 2999 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 3000 { 3001 rtw89_ser_deinit(rtwdev); 3002 rtw89_unload_firmware(rtwdev); 3003 rtw89_fw_free_all_early_h2c(rtwdev); 3004 3005 destroy_workqueue(rtwdev->txq_wq); 3006 mutex_destroy(&rtwdev->rf_mutex); 3007 mutex_destroy(&rtwdev->mutex); 3008 } 3009 EXPORT_SYMBOL(rtw89_core_deinit); 3010 3011 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3012 const u8 *mac_addr, bool hw_scan) 3013 { 3014 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3015 3016 rtwdev->scanning = true; 3017 rtw89_leave_lps(rtwdev); 3018 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3019 rtw89_leave_ips(rtwdev); 3020 3021 ether_addr_copy(rtwvif->mac_addr, mac_addr); 3022 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 3023 rtw89_chip_rfk_scan(rtwdev, true); 3024 rtw89_hci_recalc_int_mit(rtwdev); 3025 3026 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 3027 } 3028 3029 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3030 struct ieee80211_vif *vif, bool hw_scan) 3031 { 3032 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3033 3034 if (!rtwvif) 3035 return; 3036 3037 ether_addr_copy(rtwvif->mac_addr, vif->addr); 3038 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3039 3040 rtw89_chip_rfk_scan(rtwdev, false); 3041 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 3042 3043 rtwdev->scanning = false; 3044 rtwdev->dig.bypass_dig = true; 3045 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3046 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 3047 } 3048 3049 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 3050 { 3051 const struct rtw89_chip_info *chip = rtwdev->chip; 3052 u8 cv; 3053 3054 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 3055 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 3056 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 3057 cv = CHIP_CAV; 3058 else 3059 cv = CHIP_CBV; 3060 } 3061 3062 rtwdev->hal.cv = cv; 3063 } 3064 3065 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 3066 { 3067 rtwdev->hal.support_cckpd = 3068 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 3069 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 3070 rtwdev->hal.support_igi = 3071 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 3072 } 3073 3074 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 3075 { 3076 int ret; 3077 3078 ret = rtw89_mac_partial_init(rtwdev); 3079 if (ret) 3080 return ret; 3081 3082 ret = rtw89_parse_efuse_map(rtwdev); 3083 if (ret) 3084 return ret; 3085 3086 ret = rtw89_parse_phycap_map(rtwdev); 3087 if (ret) 3088 return ret; 3089 3090 ret = rtw89_mac_setup_phycap(rtwdev); 3091 if (ret) 3092 return ret; 3093 3094 rtw89_core_setup_phycap(rtwdev); 3095 3096 rtw89_mac_pwr_off(rtwdev); 3097 3098 return 0; 3099 } 3100 3101 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 3102 { 3103 rtw89_chip_fem_setup(rtwdev); 3104 3105 return 0; 3106 } 3107 3108 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 3109 { 3110 int ret; 3111 3112 rtw89_read_chip_ver(rtwdev); 3113 3114 ret = rtw89_wait_firmware_completion(rtwdev); 3115 if (ret) { 3116 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 3117 return ret; 3118 } 3119 3120 ret = rtw89_fw_recognize(rtwdev); 3121 if (ret) { 3122 rtw89_err(rtwdev, "failed to recognize firmware\n"); 3123 return ret; 3124 } 3125 3126 ret = rtw89_chip_efuse_info_setup(rtwdev); 3127 if (ret) 3128 return ret; 3129 3130 ret = rtw89_chip_board_info_setup(rtwdev); 3131 if (ret) 3132 return ret; 3133 3134 return 0; 3135 } 3136 EXPORT_SYMBOL(rtw89_chip_info_setup); 3137 3138 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 3139 { 3140 struct ieee80211_hw *hw = rtwdev->hw; 3141 struct rtw89_efuse *efuse = &rtwdev->efuse; 3142 int ret; 3143 int tx_headroom = IEEE80211_HT_CTL_LEN; 3144 3145 hw->vif_data_size = sizeof(struct rtw89_vif); 3146 hw->sta_data_size = sizeof(struct rtw89_sta); 3147 hw->txq_data_size = sizeof(struct rtw89_txq); 3148 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 3149 3150 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 3151 3152 hw->extra_tx_headroom = tx_headroom; 3153 hw->queues = IEEE80211_NUM_ACS; 3154 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 3155 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 3156 3157 ieee80211_hw_set(hw, SIGNAL_DBM); 3158 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 3159 ieee80211_hw_set(hw, MFP_CAPABLE); 3160 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 3161 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 3162 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 3163 ieee80211_hw_set(hw, TX_AMSDU); 3164 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 3165 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 3166 ieee80211_hw_set(hw, SUPPORTS_PS); 3167 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 3168 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 3169 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 3170 3171 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 3172 BIT(NL80211_IFTYPE_AP); 3173 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 3174 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 3175 3176 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 3177 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 3178 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 3179 3180 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 3181 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 3182 3183 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 3184 3185 ret = rtw89_core_set_supported_band(rtwdev); 3186 if (ret) { 3187 rtw89_err(rtwdev, "failed to set supported band\n"); 3188 return ret; 3189 } 3190 3191 hw->wiphy->reg_notifier = rtw89_regd_notifier; 3192 hw->wiphy->sar_capa = &rtw89_sar_capa; 3193 3194 ret = ieee80211_register_hw(hw); 3195 if (ret) { 3196 rtw89_err(rtwdev, "failed to register hw\n"); 3197 goto err; 3198 } 3199 3200 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 3201 if (ret) { 3202 rtw89_err(rtwdev, "failed to init regd\n"); 3203 goto err; 3204 } 3205 3206 return 0; 3207 3208 err: 3209 return ret; 3210 } 3211 3212 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 3213 { 3214 struct ieee80211_hw *hw = rtwdev->hw; 3215 3216 ieee80211_unregister_hw(hw); 3217 rtw89_core_clr_supported_band(rtwdev); 3218 } 3219 3220 int rtw89_core_register(struct rtw89_dev *rtwdev) 3221 { 3222 int ret; 3223 3224 ret = rtw89_core_register_hw(rtwdev); 3225 if (ret) { 3226 rtw89_err(rtwdev, "failed to register core hw\n"); 3227 return ret; 3228 } 3229 3230 rtw89_debugfs_init(rtwdev); 3231 3232 return 0; 3233 } 3234 EXPORT_SYMBOL(rtw89_core_register); 3235 3236 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 3237 { 3238 rtw89_core_unregister_hw(rtwdev); 3239 } 3240 EXPORT_SYMBOL(rtw89_core_unregister); 3241 3242 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 3243 u32 bus_data_size, 3244 const struct rtw89_chip_info *chip) 3245 { 3246 struct ieee80211_hw *hw; 3247 struct rtw89_dev *rtwdev; 3248 struct ieee80211_ops *ops; 3249 u32 driver_data_size; 3250 u32 early_feat_map = 0; 3251 bool no_chanctx; 3252 3253 rtw89_early_fw_feature_recognize(device, chip, &early_feat_map); 3254 3255 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 3256 if (!ops) 3257 goto err; 3258 3259 no_chanctx = chip->support_chanctx_num == 0 || 3260 !(early_feat_map & BIT(RTW89_FW_FEATURE_SCAN_OFFLOAD)); 3261 3262 if (no_chanctx) { 3263 ops->add_chanctx = NULL; 3264 ops->remove_chanctx = NULL; 3265 ops->change_chanctx = NULL; 3266 ops->assign_vif_chanctx = NULL; 3267 ops->unassign_vif_chanctx = NULL; 3268 } 3269 3270 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 3271 hw = ieee80211_alloc_hw(driver_data_size, ops); 3272 if (!hw) 3273 goto err; 3274 3275 rtwdev = hw->priv; 3276 rtwdev->hw = hw; 3277 rtwdev->dev = device; 3278 rtwdev->ops = ops; 3279 rtwdev->chip = chip; 3280 3281 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 3282 no_chanctx ? "without" : "with"); 3283 3284 return rtwdev; 3285 3286 err: 3287 kfree(ops); 3288 return NULL; 3289 } 3290 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 3291 3292 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 3293 { 3294 kfree(rtwdev->ops); 3295 ieee80211_free_hw(rtwdev->hw); 3296 } 3297 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 3298 3299 MODULE_AUTHOR("Realtek Corporation"); 3300 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 3301 MODULE_LICENSE("Dual BSD/GPL"); 3302