1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 }; 81 82 static struct ieee80211_channel rtw89_channels_6ghz[] = { 83 RTW89_DEF_CHAN_6G(5955, 1), 84 RTW89_DEF_CHAN_6G(5975, 5), 85 RTW89_DEF_CHAN_6G(5995, 9), 86 RTW89_DEF_CHAN_6G(6015, 13), 87 RTW89_DEF_CHAN_6G(6035, 17), 88 RTW89_DEF_CHAN_6G(6055, 21), 89 RTW89_DEF_CHAN_6G(6075, 25), 90 RTW89_DEF_CHAN_6G(6095, 29), 91 RTW89_DEF_CHAN_6G(6115, 33), 92 RTW89_DEF_CHAN_6G(6135, 37), 93 RTW89_DEF_CHAN_6G(6155, 41), 94 RTW89_DEF_CHAN_6G(6175, 45), 95 RTW89_DEF_CHAN_6G(6195, 49), 96 RTW89_DEF_CHAN_6G(6215, 53), 97 RTW89_DEF_CHAN_6G(6235, 57), 98 RTW89_DEF_CHAN_6G(6255, 61), 99 RTW89_DEF_CHAN_6G(6275, 65), 100 RTW89_DEF_CHAN_6G(6295, 69), 101 RTW89_DEF_CHAN_6G(6315, 73), 102 RTW89_DEF_CHAN_6G(6335, 77), 103 RTW89_DEF_CHAN_6G(6355, 81), 104 RTW89_DEF_CHAN_6G(6375, 85), 105 RTW89_DEF_CHAN_6G(6395, 89), 106 RTW89_DEF_CHAN_6G(6415, 93), 107 RTW89_DEF_CHAN_6G(6435, 97), 108 RTW89_DEF_CHAN_6G(6455, 101), 109 RTW89_DEF_CHAN_6G(6475, 105), 110 RTW89_DEF_CHAN_6G(6495, 109), 111 RTW89_DEF_CHAN_6G(6515, 113), 112 RTW89_DEF_CHAN_6G(6535, 117), 113 RTW89_DEF_CHAN_6G(6555, 121), 114 RTW89_DEF_CHAN_6G(6575, 125), 115 RTW89_DEF_CHAN_6G(6595, 129), 116 RTW89_DEF_CHAN_6G(6615, 133), 117 RTW89_DEF_CHAN_6G(6635, 137), 118 RTW89_DEF_CHAN_6G(6655, 141), 119 RTW89_DEF_CHAN_6G(6675, 145), 120 RTW89_DEF_CHAN_6G(6695, 149), 121 RTW89_DEF_CHAN_6G(6715, 153), 122 RTW89_DEF_CHAN_6G(6735, 157), 123 RTW89_DEF_CHAN_6G(6755, 161), 124 RTW89_DEF_CHAN_6G(6775, 165), 125 RTW89_DEF_CHAN_6G(6795, 169), 126 RTW89_DEF_CHAN_6G(6815, 173), 127 RTW89_DEF_CHAN_6G(6835, 177), 128 RTW89_DEF_CHAN_6G(6855, 181), 129 RTW89_DEF_CHAN_6G(6875, 185), 130 RTW89_DEF_CHAN_6G(6895, 189), 131 RTW89_DEF_CHAN_6G(6915, 193), 132 RTW89_DEF_CHAN_6G(6935, 197), 133 RTW89_DEF_CHAN_6G(6955, 201), 134 RTW89_DEF_CHAN_6G(6975, 205), 135 RTW89_DEF_CHAN_6G(6995, 209), 136 RTW89_DEF_CHAN_6G(7015, 213), 137 RTW89_DEF_CHAN_6G(7035, 217), 138 RTW89_DEF_CHAN_6G(7055, 221), 139 RTW89_DEF_CHAN_6G(7075, 225), 140 RTW89_DEF_CHAN_6G(7095, 229), 141 RTW89_DEF_CHAN_6G(7115, 233), 142 }; 143 144 static struct ieee80211_rate rtw89_bitrates[] = { 145 { .bitrate = 10, .hw_value = 0x00, }, 146 { .bitrate = 20, .hw_value = 0x01, }, 147 { .bitrate = 55, .hw_value = 0x02, }, 148 { .bitrate = 110, .hw_value = 0x03, }, 149 { .bitrate = 60, .hw_value = 0x04, }, 150 { .bitrate = 90, .hw_value = 0x05, }, 151 { .bitrate = 120, .hw_value = 0x06, }, 152 { .bitrate = 180, .hw_value = 0x07, }, 153 { .bitrate = 240, .hw_value = 0x08, }, 154 { .bitrate = 360, .hw_value = 0x09, }, 155 { .bitrate = 480, .hw_value = 0x0a, }, 156 { .bitrate = 540, .hw_value = 0x0b, }, 157 }; 158 159 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 160 { 161 .max = 1, 162 .types = BIT(NL80211_IFTYPE_STATION), 163 }, 164 { 165 .max = 1, 166 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 167 BIT(NL80211_IFTYPE_P2P_GO) | 168 BIT(NL80211_IFTYPE_AP), 169 }, 170 }; 171 172 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 173 { 174 .limits = rtw89_iface_limits, 175 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 176 .max_interfaces = 2, 177 .num_different_channels = 1, 178 } 179 }; 180 181 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 182 { 183 struct ieee80211_rate rate; 184 185 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 186 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 187 return false; 188 } 189 190 rate = rtw89_bitrates[rpt_rate]; 191 *bitrate = rate.bitrate; 192 193 return true; 194 } 195 196 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 197 .band = NL80211_BAND_2GHZ, 198 .channels = rtw89_channels_2ghz, 199 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 200 .bitrates = rtw89_bitrates, 201 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 202 .ht_cap = {0}, 203 .vht_cap = {0}, 204 }; 205 206 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 207 .band = NL80211_BAND_5GHZ, 208 .channels = rtw89_channels_5ghz, 209 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 210 211 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 212 .bitrates = rtw89_bitrates + 4, 213 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 214 .ht_cap = {0}, 215 .vht_cap = {0}, 216 }; 217 218 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 219 .band = NL80211_BAND_6GHZ, 220 .channels = rtw89_channels_6ghz, 221 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 222 223 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 224 .bitrates = rtw89_bitrates + 4, 225 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 226 }; 227 228 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 229 struct rtw89_traffic_stats *stats, 230 struct sk_buff *skb, bool tx) 231 { 232 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 233 234 if (!ieee80211_is_data(hdr->frame_control)) 235 return; 236 237 if (is_broadcast_ether_addr(hdr->addr1) || 238 is_multicast_ether_addr(hdr->addr1)) 239 return; 240 241 if (tx) { 242 stats->tx_cnt++; 243 stats->tx_unicast += skb->len; 244 } else { 245 stats->rx_cnt++; 246 stats->rx_unicast += skb->len; 247 } 248 } 249 250 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 251 { 252 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 253 NL80211_CHAN_NO_HT); 254 } 255 256 static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 257 struct rtw89_chan *chan) 258 { 259 struct ieee80211_channel *channel = chandef->chan; 260 enum nl80211_chan_width width = chandef->width; 261 u32 primary_freq, center_freq; 262 u8 center_chan; 263 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 264 u32 offset; 265 u8 band; 266 267 center_chan = channel->hw_value; 268 primary_freq = channel->center_freq; 269 center_freq = chandef->center_freq1; 270 271 switch (width) { 272 case NL80211_CHAN_WIDTH_20_NOHT: 273 case NL80211_CHAN_WIDTH_20: 274 bandwidth = RTW89_CHANNEL_WIDTH_20; 275 break; 276 case NL80211_CHAN_WIDTH_40: 277 bandwidth = RTW89_CHANNEL_WIDTH_40; 278 if (primary_freq > center_freq) { 279 center_chan -= 2; 280 } else { 281 center_chan += 2; 282 } 283 break; 284 case NL80211_CHAN_WIDTH_80: 285 case NL80211_CHAN_WIDTH_160: 286 bandwidth = nl_to_rtw89_bandwidth(width); 287 if (primary_freq > center_freq) { 288 offset = (primary_freq - center_freq - 10) / 20; 289 center_chan -= 2 + offset * 4; 290 } else { 291 offset = (center_freq - primary_freq - 10) / 20; 292 center_chan += 2 + offset * 4; 293 } 294 break; 295 default: 296 center_chan = 0; 297 break; 298 } 299 300 switch (channel->band) { 301 default: 302 case NL80211_BAND_2GHZ: 303 band = RTW89_BAND_2G; 304 break; 305 case NL80211_BAND_5GHZ: 306 band = RTW89_BAND_5G; 307 break; 308 case NL80211_BAND_6GHZ: 309 band = RTW89_BAND_6G; 310 break; 311 } 312 313 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 314 } 315 316 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 317 { 318 const struct rtw89_chip_info *chip = rtwdev->chip; 319 const struct rtw89_chan *chan; 320 enum rtw89_sub_entity_idx sub_entity_idx; 321 enum rtw89_phy_idx phy_idx; 322 enum rtw89_entity_mode mode; 323 bool entity_active; 324 325 entity_active = rtw89_get_entity_state(rtwdev); 326 if (!entity_active) 327 return; 328 329 mode = rtw89_get_entity_mode(rtwdev); 330 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 331 return; 332 333 sub_entity_idx = RTW89_SUB_ENTITY_0; 334 phy_idx = RTW89_PHY_0; 335 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 336 if (chip->ops->set_txpwr) 337 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 338 } 339 340 void rtw89_set_channel(struct rtw89_dev *rtwdev) 341 { 342 const struct rtw89_chip_info *chip = rtwdev->chip; 343 const struct cfg80211_chan_def *chandef; 344 enum rtw89_sub_entity_idx sub_entity_idx; 345 enum rtw89_mac_idx mac_idx; 346 enum rtw89_phy_idx phy_idx; 347 struct rtw89_chan chan; 348 struct rtw89_channel_help_params bak; 349 enum rtw89_entity_mode mode; 350 bool band_changed; 351 bool entity_active; 352 353 entity_active = rtw89_get_entity_state(rtwdev); 354 355 mode = rtw89_entity_recalc(rtwdev); 356 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 357 return; 358 359 sub_entity_idx = RTW89_SUB_ENTITY_0; 360 mac_idx = RTW89_MAC_0; 361 phy_idx = RTW89_PHY_0; 362 chandef = rtw89_chandef_get(rtwdev, sub_entity_idx); 363 rtw89_get_channel_params(chandef, &chan); 364 if (WARN(chan.channel == 0, "Invalid channel\n")) 365 return; 366 367 band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan); 368 369 rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx); 370 371 chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx); 372 373 rtw89_core_set_chip_txpwr(rtwdev); 374 375 rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx); 376 377 if (!entity_active || band_changed) { 378 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type); 379 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 380 } 381 382 rtw89_set_entity_state(rtwdev, true); 383 } 384 385 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 386 struct rtw89_chan *chan) 387 { 388 const struct cfg80211_chan_def *chandef; 389 390 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 391 rtw89_get_channel_params(chandef, chan); 392 } 393 394 static enum rtw89_core_tx_type 395 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 396 struct sk_buff *skb) 397 { 398 struct ieee80211_hdr *hdr = (void *)skb->data; 399 __le16 fc = hdr->frame_control; 400 401 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 402 return RTW89_CORE_TX_TYPE_MGMT; 403 404 return RTW89_CORE_TX_TYPE_DATA; 405 } 406 407 static void 408 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 409 struct rtw89_core_tx_request *tx_req, 410 enum btc_pkt_type pkt_type) 411 { 412 struct ieee80211_sta *sta = tx_req->sta; 413 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 414 struct sk_buff *skb = tx_req->skb; 415 struct rtw89_sta *rtwsta; 416 u8 ampdu_num; 417 u8 tid; 418 419 if (pkt_type == PACKET_EAPOL) { 420 desc_info->bk = true; 421 return; 422 } 423 424 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 425 return; 426 427 if (!sta) { 428 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 429 return; 430 } 431 432 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 433 rtwsta = (struct rtw89_sta *)sta->drv_priv; 434 435 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 436 rtwsta->ampdu_params[tid].agg_num : 437 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 438 439 desc_info->agg_en = true; 440 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 441 desc_info->ampdu_num = ampdu_num; 442 } 443 444 static void 445 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 446 struct rtw89_core_tx_request *tx_req) 447 { 448 const struct rtw89_chip_info *chip = rtwdev->chip; 449 struct ieee80211_vif *vif = tx_req->vif; 450 struct ieee80211_sta *sta = tx_req->sta; 451 struct ieee80211_tx_info *info; 452 struct ieee80211_key_conf *key; 453 struct rtw89_vif *rtwvif; 454 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 455 struct rtw89_addr_cam_entry *addr_cam; 456 struct rtw89_sec_cam_entry *sec_cam; 457 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 458 struct sk_buff *skb = tx_req->skb; 459 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 460 u64 pn64; 461 462 if (!vif) { 463 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 464 return; 465 } 466 467 rtwvif = (struct rtw89_vif *)vif->drv_priv; 468 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 469 470 info = IEEE80211_SKB_CB(skb); 471 key = info->control.hw_key; 472 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 473 if (!sec_cam) { 474 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 475 return; 476 } 477 478 switch (key->cipher) { 479 case WLAN_CIPHER_SUITE_WEP40: 480 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 481 break; 482 case WLAN_CIPHER_SUITE_WEP104: 483 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 484 break; 485 case WLAN_CIPHER_SUITE_TKIP: 486 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 487 break; 488 case WLAN_CIPHER_SUITE_CCMP: 489 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 490 break; 491 case WLAN_CIPHER_SUITE_CCMP_256: 492 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 493 break; 494 case WLAN_CIPHER_SUITE_GCMP: 495 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 496 break; 497 case WLAN_CIPHER_SUITE_GCMP_256: 498 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 499 break; 500 default: 501 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 502 return; 503 } 504 505 desc_info->sec_en = true; 506 desc_info->sec_keyid = key->keyidx; 507 desc_info->sec_type = sec_type; 508 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 509 510 if (!chip->hw_sec_hdr) 511 return; 512 513 pn64 = atomic64_inc_return(&key->tx_pn); 514 desc_info->sec_seq[0] = pn64; 515 desc_info->sec_seq[1] = pn64 >> 8; 516 desc_info->sec_seq[2] = pn64 >> 16; 517 desc_info->sec_seq[3] = pn64 >> 24; 518 desc_info->sec_seq[4] = pn64 >> 32; 519 desc_info->sec_seq[5] = pn64 >> 40; 520 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 521 } 522 523 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 524 struct rtw89_core_tx_request *tx_req) 525 { 526 struct sk_buff *skb = tx_req->skb; 527 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 528 struct ieee80211_vif *vif = tx_info->control.vif; 529 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 530 u16 lowest_rate; 531 532 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 533 (vif && vif->p2p)) 534 lowest_rate = RTW89_HW_RATE_OFDM6; 535 else if (chan->band_type == RTW89_BAND_2G) 536 lowest_rate = RTW89_HW_RATE_CCK1; 537 else 538 lowest_rate = RTW89_HW_RATE_OFDM6; 539 540 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 541 return lowest_rate; 542 543 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 544 } 545 546 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 547 struct rtw89_core_tx_request *tx_req) 548 { 549 struct ieee80211_vif *vif = tx_req->vif; 550 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 551 struct ieee80211_sta *sta = tx_req->sta; 552 struct rtw89_sta *rtwsta; 553 554 if (!sta) 555 return rtwvif->mac_id; 556 557 rtwsta = (struct rtw89_sta *)sta->drv_priv; 558 return rtwsta->mac_id; 559 } 560 561 static void 562 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 563 struct rtw89_core_tx_request *tx_req) 564 { 565 struct ieee80211_vif *vif = tx_req->vif; 566 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 567 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 568 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 569 u8 qsel, ch_dma; 570 571 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 572 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 573 574 desc_info->qsel = qsel; 575 desc_info->ch_dma = ch_dma; 576 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 577 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 578 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 579 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 580 581 /* fixed data rate for mgmt frames */ 582 desc_info->en_wd_info = true; 583 desc_info->use_rate = true; 584 desc_info->dis_data_fb = true; 585 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); 586 587 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 588 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 589 desc_info->data_rate, chan->channel, chan->band_type, 590 chan->band_width); 591 } 592 593 static void 594 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 595 struct rtw89_core_tx_request *tx_req) 596 { 597 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 598 599 desc_info->is_bmc = false; 600 desc_info->wd_page = false; 601 desc_info->ch_dma = RTW89_DMA_H2C; 602 } 603 604 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) 605 { 606 static const u8 rtw89_bandwidth_to_om[] = { 607 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 608 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 609 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 610 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 611 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 612 }; 613 const struct rtw89_chip_info *chip = rtwdev->chip; 614 struct rtw89_hal *hal = &rtwdev->hal; 615 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 616 u8 om_bandwidth; 617 618 if (!chip->dis_2g_40m_ul_ofdma || 619 chan->band_type != RTW89_BAND_2G || 620 chan->band_width != RTW89_CHANNEL_WIDTH_40) 621 return; 622 623 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 624 rtw89_bandwidth_to_om[chan->band_width] : 0; 625 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 626 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 627 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 628 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 629 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 630 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 631 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 632 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 633 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 634 } 635 636 static bool 637 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 638 struct rtw89_core_tx_request *tx_req, 639 enum btc_pkt_type pkt_type) 640 { 641 struct ieee80211_sta *sta = tx_req->sta; 642 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 643 struct sk_buff *skb = tx_req->skb; 644 struct ieee80211_hdr *hdr = (void *)skb->data; 645 __le16 fc = hdr->frame_control; 646 647 /* AP IOT issue with EAPoL, ARP and DHCP */ 648 if (pkt_type < PACKET_MAX) 649 return false; 650 651 if (!sta || !sta->deflink.he_cap.has_he) 652 return false; 653 654 if (!ieee80211_is_data_qos(fc)) 655 return false; 656 657 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 658 return false; 659 660 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 661 return false; 662 663 return true; 664 } 665 666 static void 667 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 668 struct rtw89_core_tx_request *tx_req) 669 { 670 struct ieee80211_sta *sta = tx_req->sta; 671 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 672 struct sk_buff *skb = tx_req->skb; 673 struct ieee80211_hdr *hdr = (void *)skb->data; 674 __le16 fc = hdr->frame_control; 675 void *data; 676 __le32 *htc; 677 u8 *qc; 678 int hdr_len; 679 680 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 681 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 682 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 683 684 hdr = data; 685 htc = data + hdr_len; 686 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 687 *htc = rtwsta->htc_template ? rtwsta->htc_template : 688 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 689 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 690 691 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 692 qc[0] |= IEEE80211_QOS_CTL_EOSP; 693 } 694 695 static void 696 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 697 struct rtw89_core_tx_request *tx_req, 698 enum btc_pkt_type pkt_type) 699 { 700 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 701 struct ieee80211_vif *vif = tx_req->vif; 702 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 703 704 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 705 goto desc_bk; 706 707 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 708 709 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 710 desc_info->a_ctrl_bsr = true; 711 712 desc_bk: 713 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 714 return; 715 716 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 717 desc_info->bk = true; 718 } 719 720 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 721 struct rtw89_core_tx_request *tx_req) 722 { 723 struct ieee80211_vif *vif = tx_req->vif; 724 struct ieee80211_sta *sta = tx_req->sta; 725 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 726 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 727 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 728 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 729 u16 lowest_rate; 730 731 if (rate_pattern->enable) 732 return rate_pattern->rate; 733 734 if (vif->p2p) 735 lowest_rate = RTW89_HW_RATE_OFDM6; 736 else if (chan->band_type == RTW89_BAND_2G) 737 lowest_rate = RTW89_HW_RATE_CCK1; 738 else 739 lowest_rate = RTW89_HW_RATE_OFDM6; 740 741 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 742 return lowest_rate; 743 744 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 745 } 746 747 static void 748 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 749 struct rtw89_core_tx_request *tx_req) 750 { 751 struct ieee80211_vif *vif = tx_req->vif; 752 struct ieee80211_sta *sta = tx_req->sta; 753 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 754 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 755 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 756 struct sk_buff *skb = tx_req->skb; 757 u8 tid, tid_indicate; 758 u8 qsel, ch_dma; 759 760 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 761 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 762 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 763 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 764 765 desc_info->ch_dma = ch_dma; 766 desc_info->tid_indicate = tid_indicate; 767 desc_info->qsel = qsel; 768 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 769 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 770 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 771 772 /* enable wd_info for AMPDU */ 773 desc_info->en_wd_info = true; 774 775 if (IEEE80211_SKB_CB(skb)->control.hw_key) 776 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 777 778 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 779 } 780 781 static enum btc_pkt_type 782 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 783 struct rtw89_core_tx_request *tx_req) 784 { 785 struct sk_buff *skb = tx_req->skb; 786 struct udphdr *udphdr; 787 788 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 789 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 790 return PACKET_EAPOL; 791 } 792 793 if (skb->protocol == htons(ETH_P_ARP)) { 794 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 795 return PACKET_ARP; 796 } 797 798 if (skb->protocol == htons(ETH_P_IP) && 799 ip_hdr(skb)->protocol == IPPROTO_UDP) { 800 udphdr = udp_hdr(skb); 801 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 802 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 803 skb->len > 282) { 804 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 805 return PACKET_DHCP; 806 } 807 } 808 809 if (skb->protocol == htons(ETH_P_IP) && 810 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 811 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 812 return PACKET_ICMP; 813 } 814 815 return PACKET_MAX; 816 } 817 818 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 819 struct rtw89_tx_desc_info *desc_info, 820 struct sk_buff *skb) 821 { 822 struct ieee80211_hdr *hdr = (void *)skb->data; 823 __le16 fc = hdr->frame_control; 824 825 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 826 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 827 } 828 829 static void 830 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 831 struct rtw89_core_tx_request *tx_req) 832 { 833 const struct rtw89_chip_info *chip = rtwdev->chip; 834 835 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 836 return; 837 838 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 839 return; 840 841 if (chip->chip_id != RTL8852C && 842 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 843 return; 844 845 rtw89_mac_notify_wake(rtwdev); 846 } 847 848 static void 849 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 850 struct rtw89_core_tx_request *tx_req) 851 { 852 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 853 struct sk_buff *skb = tx_req->skb; 854 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 855 struct ieee80211_hdr *hdr = (void *)skb->data; 856 enum rtw89_core_tx_type tx_type; 857 enum btc_pkt_type pkt_type; 858 bool is_bmc; 859 u16 seq; 860 861 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 862 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 863 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 864 tx_req->tx_type = tx_type; 865 } 866 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 867 is_multicast_ether_addr(hdr->addr1)); 868 869 desc_info->seq = seq; 870 desc_info->pkt_size = skb->len; 871 desc_info->is_bmc = is_bmc; 872 desc_info->wd_page = true; 873 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 874 875 switch (tx_req->tx_type) { 876 case RTW89_CORE_TX_TYPE_MGMT: 877 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 878 break; 879 case RTW89_CORE_TX_TYPE_DATA: 880 rtw89_core_tx_update_data_info(rtwdev, tx_req); 881 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 882 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 883 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 884 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 885 break; 886 case RTW89_CORE_TX_TYPE_FWCMD: 887 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 888 break; 889 } 890 } 891 892 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 893 { 894 u8 ch_dma; 895 896 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 897 898 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 899 } 900 901 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 902 int qsel, unsigned int timeout) 903 { 904 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 905 struct rtw89_tx_wait_info *wait; 906 unsigned long time_left; 907 int ret = 0; 908 909 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 910 if (!wait) { 911 rtw89_core_tx_kick_off(rtwdev, qsel); 912 return 0; 913 } 914 915 init_completion(&wait->completion); 916 rcu_assign_pointer(skb_data->wait, wait); 917 918 rtw89_core_tx_kick_off(rtwdev, qsel); 919 time_left = wait_for_completion_timeout(&wait->completion, 920 msecs_to_jiffies(timeout)); 921 if (time_left == 0) 922 ret = -ETIMEDOUT; 923 else if (!wait->tx_done) 924 ret = -EAGAIN; 925 926 rcu_assign_pointer(skb_data->wait, NULL); 927 kfree_rcu(wait, rcu_head); 928 929 return ret; 930 } 931 932 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 933 struct sk_buff *skb, bool fwdl) 934 { 935 struct rtw89_core_tx_request tx_req = {0}; 936 u32 cnt; 937 int ret; 938 939 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 940 rtw89_debug(rtwdev, RTW89_DBG_FW, 941 "ignore h2c due to power is off with firmware state=%d\n", 942 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 943 dev_kfree_skb(skb); 944 return 0; 945 } 946 947 tx_req.skb = skb; 948 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 949 if (fwdl) 950 tx_req.desc_info.fw_dl = true; 951 952 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 953 954 if (!fwdl) 955 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 956 957 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 958 if (cnt == 0) { 959 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 960 return -ENOSPC; 961 } 962 963 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 964 if (ret) { 965 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 966 return ret; 967 } 968 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 969 970 return 0; 971 } 972 973 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 974 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 975 { 976 struct rtw89_core_tx_request tx_req = {0}; 977 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 978 int ret; 979 980 tx_req.skb = skb; 981 tx_req.sta = sta; 982 tx_req.vif = vif; 983 984 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 985 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 986 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 987 rtw89_core_tx_wake(rtwdev, &tx_req); 988 989 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 990 if (ret) { 991 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 992 return ret; 993 } 994 995 if (qsel) 996 *qsel = tx_req.desc_info.qsel; 997 998 return 0; 999 } 1000 1001 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1002 { 1003 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1004 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1005 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1006 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1007 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1008 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1009 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1010 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1011 1012 return cpu_to_le32(dword); 1013 } 1014 1015 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1016 { 1017 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1018 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1019 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1020 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1021 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1022 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1023 1024 return cpu_to_le32(dword); 1025 } 1026 1027 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1028 { 1029 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1030 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1031 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1032 1033 return cpu_to_le32(dword); 1034 } 1035 1036 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1037 { 1038 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1039 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1040 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1041 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1042 1043 return cpu_to_le32(dword); 1044 } 1045 1046 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1047 { 1048 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1049 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1050 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1051 1052 return cpu_to_le32(dword); 1053 } 1054 1055 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1056 { 1057 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1058 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1059 1060 return cpu_to_le32(dword); 1061 } 1062 1063 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1064 { 1065 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1066 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1067 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1068 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1069 1070 return cpu_to_le32(dword); 1071 } 1072 1073 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1074 { 1075 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1076 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1077 1078 return cpu_to_le32(dword); 1079 } 1080 1081 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1082 { 1083 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1084 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1085 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1086 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1087 1088 return cpu_to_le32(dword); 1089 } 1090 1091 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1092 { 1093 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1094 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1095 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1096 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1097 1098 return cpu_to_le32(dword); 1099 } 1100 1101 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1102 { 1103 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1104 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1105 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1106 desc_info->data_retry_lowest_rate); 1107 1108 return cpu_to_le32(dword); 1109 } 1110 1111 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1112 { 1113 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1114 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1115 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1116 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1117 1118 return cpu_to_le32(dword); 1119 } 1120 1121 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1122 { 1123 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1124 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1125 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1126 1127 return cpu_to_le32(dword); 1128 } 1129 1130 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1131 { 1132 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1133 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1134 1135 return cpu_to_le32(dword); 1136 } 1137 1138 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1139 struct rtw89_tx_desc_info *desc_info, 1140 void *txdesc) 1141 { 1142 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1143 struct rtw89_txwd_info *txwd_info; 1144 1145 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1146 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1147 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1148 1149 if (!desc_info->en_wd_info) 1150 return; 1151 1152 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1153 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1154 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1155 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1156 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1157 1158 } 1159 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1160 1161 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1162 struct rtw89_tx_desc_info *desc_info, 1163 void *txdesc) 1164 { 1165 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1166 struct rtw89_txwd_info *txwd_info; 1167 1168 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1169 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1170 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1171 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1172 if (desc_info->sec_en) { 1173 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1174 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1175 } 1176 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1177 1178 if (!desc_info->en_wd_info) 1179 return; 1180 1181 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1182 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1183 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1184 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1185 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1186 } 1187 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1188 1189 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1190 { 1191 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1192 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1193 RTW89_CORE_RX_TYPE_FWDL : 1194 RTW89_CORE_RX_TYPE_H2C); 1195 1196 return cpu_to_le32(dword); 1197 } 1198 1199 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1200 struct rtw89_tx_desc_info *desc_info, 1201 void *txdesc) 1202 { 1203 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1204 1205 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1206 } 1207 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1208 1209 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1210 struct sk_buff *skb, 1211 struct rtw89_rx_phy_ppdu *phy_ppdu) 1212 { 1213 bool rx_cnt_valid = false; 1214 u8 plcp_size = 0; 1215 u8 usr_num = 0; 1216 u8 *phy_sts; 1217 1218 rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); 1219 plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; 1220 usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); 1221 if (usr_num > RTW89_PPDU_MAX_USR) { 1222 rtw89_warn(rtwdev, "Invalid user number in mac info\n"); 1223 return -EINVAL; 1224 } 1225 1226 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1227 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1228 /* 8-byte alignment */ 1229 if (usr_num & BIT(0)) 1230 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1231 if (rx_cnt_valid) 1232 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; 1233 phy_sts += plcp_size; 1234 1235 phy_ppdu->buf = phy_sts; 1236 phy_ppdu->len = skb->data + skb->len - phy_sts; 1237 1238 return 0; 1239 } 1240 1241 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1242 struct ieee80211_sta *sta) 1243 { 1244 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1245 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1246 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1247 int i; 1248 1249 if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) { 1250 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1251 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1252 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1253 } 1254 } 1255 1256 #define VAR_LEN 0xff 1257 #define VAR_LEN_UNIT 8 1258 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) 1259 { 1260 static const u8 physts_ie_len_tab[32] = { 1261 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1262 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1263 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1264 }; 1265 u16 ie_len; 1266 u8 ie; 1267 1268 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1269 if (physts_ie_len_tab[ie] != VAR_LEN) 1270 ie_len = physts_ie_len_tab[ie]; 1271 else 1272 ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; 1273 1274 return ie_len; 1275 } 1276 1277 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, 1278 struct rtw89_rx_phy_ppdu *phy_ppdu) 1279 { 1280 s16 cfo; 1281 1282 phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr); 1283 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1284 return; 1285 1286 if (!phy_ppdu->to_self) 1287 return; 1288 1289 /* sign conversion for S(12,2) */ 1290 if (rtwdev->chip->cfo_src_fd) 1291 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_FD_CFO(addr), 11); 1292 else 1293 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_PREMB_CFO(addr), 11); 1294 1295 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1296 } 1297 1298 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, 1299 struct rtw89_rx_phy_ppdu *phy_ppdu) 1300 { 1301 u8 ie; 1302 1303 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1304 switch (ie) { 1305 case RTW89_PHYSTS_IE01_CMN_OFDM: 1306 rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); 1307 break; 1308 default: 1309 break; 1310 } 1311 1312 return 0; 1313 } 1314 1315 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1316 { 1317 u8 *rssi = phy_ppdu->rssi; 1318 u8 *buf = phy_ppdu->buf; 1319 1320 phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf); 1321 phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); 1322 rssi[RF_PATH_A] = RTW89_GET_PHY_STS_RSSI_A(buf); 1323 rssi[RF_PATH_B] = RTW89_GET_PHY_STS_RSSI_B(buf); 1324 rssi[RF_PATH_C] = RTW89_GET_PHY_STS_RSSI_C(buf); 1325 rssi[RF_PATH_D] = RTW89_GET_PHY_STS_RSSI_D(buf); 1326 } 1327 1328 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1329 struct rtw89_rx_phy_ppdu *phy_ppdu) 1330 { 1331 if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { 1332 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1333 return -EINVAL; 1334 } 1335 rtw89_core_update_phy_ppdu(phy_ppdu); 1336 ieee80211_iterate_stations_atomic(rtwdev->hw, 1337 rtw89_core_rx_process_phy_ppdu_iter, 1338 phy_ppdu); 1339 1340 return 0; 1341 } 1342 1343 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1344 struct rtw89_rx_phy_ppdu *phy_ppdu) 1345 { 1346 u16 ie_len; 1347 u8 *pos, *end; 1348 1349 /* mark invalid reports and bypass them */ 1350 if (phy_ppdu->ie < RTW89_CCK_PKT) 1351 return -EINVAL; 1352 1353 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1354 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1355 while (pos < end) { 1356 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); 1357 rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); 1358 pos += ie_len; 1359 if (pos > end || ie_len == 0) { 1360 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1361 "phy status parse failed\n"); 1362 return -EINVAL; 1363 } 1364 } 1365 1366 return 0; 1367 } 1368 1369 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1370 struct rtw89_rx_phy_ppdu *phy_ppdu) 1371 { 1372 int ret; 1373 1374 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1375 if (ret) 1376 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1377 else 1378 phy_ppdu->valid = true; 1379 } 1380 1381 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1382 const struct rtw89_rx_desc_info *desc_info, 1383 bool rx_status) 1384 { 1385 switch (desc_info->gi_ltf) { 1386 case RTW89_GILTF_SGI_4XHE08: 1387 case RTW89_GILTF_2XHE08: 1388 case RTW89_GILTF_1XHE08: 1389 return NL80211_RATE_INFO_HE_GI_0_8; 1390 case RTW89_GILTF_2XHE16: 1391 case RTW89_GILTF_1XHE16: 1392 return NL80211_RATE_INFO_HE_GI_1_6; 1393 case RTW89_GILTF_LGI_4XHE32: 1394 return NL80211_RATE_INFO_HE_GI_3_2; 1395 default: 1396 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); 1397 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; 1398 } 1399 } 1400 1401 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1402 struct rtw89_rx_desc_info *desc_info, 1403 struct ieee80211_rx_status *status) 1404 { 1405 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1406 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1407 u16 data_rate; 1408 bool ret; 1409 1410 data_rate = desc_info->data_rate; 1411 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1412 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1413 rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1414 /* rate_idx is still hardware value here */ 1415 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1416 rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1417 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1418 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1419 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1420 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1421 } else { 1422 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1423 } 1424 1425 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1426 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); 1427 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1428 status->rate_idx == rate_idx && 1429 status->he_gi == gi_ltf && 1430 status->bw == bw; 1431 1432 return ret; 1433 } 1434 1435 struct rtw89_vif_rx_stats_iter_data { 1436 struct rtw89_dev *rtwdev; 1437 struct rtw89_rx_phy_ppdu *phy_ppdu; 1438 struct rtw89_rx_desc_info *desc_info; 1439 struct sk_buff *skb; 1440 const u8 *bssid; 1441 }; 1442 1443 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1444 struct ieee80211_vif *vif, 1445 struct sk_buff *skb) 1446 { 1447 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1448 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1449 u8 *pos, *end, type; 1450 u16 aid; 1451 1452 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1453 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1454 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1455 return; 1456 1457 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1458 if (type != IEEE80211_TRIGGER_TYPE_BASIC) 1459 return; 1460 1461 end = (u8 *)tf + skb->len; 1462 pos = tf->variable; 1463 1464 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1465 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1466 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1467 "[TF] aid: %d, ul_mcs: %d, rua: %d\n", 1468 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1469 RTW89_GET_TF_USER_INFO_RUA(pos)); 1470 1471 if (aid == RTW89_TF_PAD) 1472 break; 1473 1474 if (aid == vif->cfg.aid) { 1475 rtwvif->stats.rx_tf_acc++; 1476 rtwdev->stats.rx_tf_acc++; 1477 break; 1478 } 1479 1480 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1481 } 1482 } 1483 1484 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1485 struct sk_buff *skb) 1486 { 1487 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1488 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1489 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1490 struct rtw89_pktofld_info *info; 1491 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1492 1493 if (rx_status->band != NL80211_BAND_6GHZ) 1494 return; 1495 1496 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1497 1498 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1499 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1500 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1501 continue; 1502 } 1503 1504 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1505 continue; 1506 1507 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) 1508 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1509 } 1510 } 1511 1512 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1513 struct ieee80211_vif *vif) 1514 { 1515 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1516 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1517 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1518 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1519 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1520 struct sk_buff *skb = iter_data->skb; 1521 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1522 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1523 const u8 *bssid = iter_data->bssid; 1524 1525 if (rtwdev->scanning && 1526 (ieee80211_is_beacon(hdr->frame_control) || 1527 ieee80211_is_probe_resp(hdr->frame_control))) 1528 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1529 1530 if (!vif->bss_conf.bssid) 1531 return; 1532 1533 if (ieee80211_is_trigger(hdr->frame_control)) { 1534 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1535 return; 1536 } 1537 1538 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1539 return; 1540 1541 if (ieee80211_is_beacon(hdr->frame_control)) { 1542 if (vif->type == NL80211_IFTYPE_STATION) 1543 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1544 pkt_stat->beacon_nr++; 1545 } 1546 1547 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1548 return; 1549 1550 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1551 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1552 1553 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1554 } 1555 1556 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1557 struct rtw89_rx_phy_ppdu *phy_ppdu, 1558 struct rtw89_rx_desc_info *desc_info, 1559 struct sk_buff *skb) 1560 { 1561 struct rtw89_vif_rx_stats_iter_data iter_data; 1562 1563 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1564 1565 iter_data.rtwdev = rtwdev; 1566 iter_data.phy_ppdu = phy_ppdu; 1567 iter_data.desc_info = desc_info; 1568 iter_data.skb = skb; 1569 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1570 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1571 } 1572 1573 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1574 struct ieee80211_rx_status *status) 1575 { 1576 const struct rtw89_chan_rcd *rcd = 1577 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1578 u16 chan = rcd->prev_primary_channel; 1579 u8 band = rcd->prev_band_type == RTW89_BAND_2G ? 1580 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1581 1582 if (status->band != NL80211_BAND_2GHZ && 1583 status->encoding == RX_ENC_LEGACY && 1584 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1585 status->freq = ieee80211_channel_to_frequency(chan, band); 1586 status->band = band; 1587 } 1588 } 1589 1590 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1591 { 1592 if (rx_status->band == NL80211_BAND_2GHZ || 1593 rx_status->encoding != RX_ENC_LEGACY) 1594 return; 1595 1596 /* Some control frames' freq(ACKs in this case) are reported wrong due 1597 * to FW notify timing, set to lowest rate to prevent overflow. 1598 */ 1599 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1600 rx_status->rate_idx = 0; 1601 return; 1602 } 1603 1604 /* No 4 CCK rates for non-2G */ 1605 rx_status->rate_idx -= 4; 1606 } 1607 1608 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 1609 struct sk_buff *skb, 1610 struct ieee80211_rx_status *rx_status) 1611 { 1612 static const struct ieee80211_radiotap_he known_he = { 1613 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1614 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 1615 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 1616 }; 1617 struct ieee80211_radiotap_he *he; 1618 1619 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 1620 return; 1621 1622 if (rx_status->encoding == RX_ENC_HE) { 1623 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 1624 he = skb_push(skb, sizeof(*he)); 1625 *he = known_he; 1626 } 1627 } 1628 1629 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 1630 struct rtw89_rx_phy_ppdu *phy_ppdu, 1631 struct rtw89_rx_desc_info *desc_info, 1632 struct sk_buff *skb_ppdu, 1633 struct ieee80211_rx_status *rx_status) 1634 { 1635 struct napi_struct *napi = &rtwdev->napi; 1636 1637 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 1638 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state))) 1639 napi = NULL; 1640 1641 rtw89_core_hw_to_sband_rate(rx_status); 1642 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 1643 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 1644 /* In low power mode, it does RX in thread context. */ 1645 local_bh_disable(); 1646 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 1647 local_bh_enable(); 1648 rtwdev->napi_budget_countdown--; 1649 } 1650 1651 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 1652 struct rtw89_rx_phy_ppdu *phy_ppdu, 1653 struct rtw89_rx_desc_info *desc_info, 1654 struct sk_buff *skb) 1655 { 1656 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1657 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 1658 struct sk_buff *skb_ppdu = NULL, *tmp; 1659 struct ieee80211_rx_status *rx_status; 1660 1661 if (curr > RTW89_MAX_PPDU_CNT) 1662 return; 1663 1664 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 1665 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 1666 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1667 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 1668 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 1669 rtw89_correct_cck_chan(rtwdev, rx_status); 1670 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 1671 } 1672 } 1673 1674 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 1675 struct rtw89_rx_desc_info *desc_info, 1676 struct sk_buff *skb) 1677 { 1678 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 1679 .len = skb->len, 1680 .to_self = desc_info->addr1_match, 1681 .rate = desc_info->data_rate, 1682 .mac_id = desc_info->mac_id}; 1683 int ret; 1684 1685 if (desc_info->mac_info_valid) 1686 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 1687 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 1688 if (ret) 1689 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); 1690 1691 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 1692 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 1693 dev_kfree_skb_any(skb); 1694 } 1695 1696 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 1697 struct rtw89_rx_desc_info *desc_info, 1698 struct sk_buff *skb) 1699 { 1700 switch (desc_info->pkt_type) { 1701 case RTW89_CORE_RX_TYPE_C2H: 1702 rtw89_fw_c2h_irqsafe(rtwdev, skb); 1703 break; 1704 case RTW89_CORE_RX_TYPE_PPDU_STAT: 1705 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 1706 break; 1707 default: 1708 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 1709 desc_info->pkt_type); 1710 dev_kfree_skb_any(skb); 1711 break; 1712 } 1713 } 1714 1715 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 1716 struct rtw89_rx_desc_info *desc_info, 1717 u8 *data, u32 data_offset) 1718 { 1719 const struct rtw89_chip_info *chip = rtwdev->chip; 1720 struct rtw89_rxdesc_short *rxd_s; 1721 struct rtw89_rxdesc_long *rxd_l; 1722 u8 shift_len, drv_info_len; 1723 1724 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 1725 desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); 1726 desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); 1727 desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); 1728 desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); 1729 desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); 1730 if (chip->chip_id == RTL8852C) 1731 desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s); 1732 else 1733 desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); 1734 desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); 1735 desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); 1736 desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); 1737 desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); 1738 desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); 1739 desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); 1740 desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); 1741 desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); 1742 desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); 1743 desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); 1744 desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); 1745 desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); 1746 1747 shift_len = desc_info->shift << 1; /* 2-byte unit */ 1748 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 1749 desc_info->offset = data_offset + shift_len + drv_info_len; 1750 desc_info->ready = true; 1751 1752 if (!desc_info->long_rxdesc) 1753 return; 1754 1755 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 1756 desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); 1757 desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); 1758 desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); 1759 desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); 1760 desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); 1761 desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); 1762 } 1763 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 1764 1765 struct rtw89_core_iter_rx_status { 1766 struct rtw89_dev *rtwdev; 1767 struct ieee80211_rx_status *rx_status; 1768 struct rtw89_rx_desc_info *desc_info; 1769 u8 mac_id; 1770 }; 1771 1772 static 1773 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 1774 { 1775 struct rtw89_core_iter_rx_status *iter_data = 1776 (struct rtw89_core_iter_rx_status *)data; 1777 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 1778 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1779 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1780 u8 mac_id = iter_data->mac_id; 1781 1782 if (mac_id != rtwsta->mac_id) 1783 return; 1784 1785 rtwsta->rx_status = *rx_status; 1786 rtwsta->rx_hw_rate = desc_info->data_rate; 1787 } 1788 1789 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 1790 struct rtw89_rx_desc_info *desc_info, 1791 struct ieee80211_rx_status *rx_status) 1792 { 1793 struct rtw89_core_iter_rx_status iter_data; 1794 1795 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 1796 return; 1797 1798 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 1799 return; 1800 1801 iter_data.rtwdev = rtwdev; 1802 iter_data.rx_status = rx_status; 1803 iter_data.desc_info = desc_info; 1804 iter_data.mac_id = desc_info->mac_id; 1805 ieee80211_iterate_stations_atomic(rtwdev->hw, 1806 rtw89_core_stats_sta_rx_status_iter, 1807 &iter_data); 1808 } 1809 1810 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 1811 struct rtw89_rx_desc_info *desc_info, 1812 struct ieee80211_rx_status *rx_status) 1813 { 1814 const struct cfg80211_chan_def *chandef = 1815 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 1816 const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1817 u16 data_rate; 1818 u8 data_rate_mode; 1819 1820 /* currently using single PHY */ 1821 rx_status->freq = chandef->chan->center_freq; 1822 rx_status->band = chandef->chan->band; 1823 1824 if (rtwdev->scanning && 1825 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 1826 u8 chan = cur->primary_channel; 1827 u8 band = cur->band_type; 1828 enum nl80211_band nl_band; 1829 1830 nl_band = rtw89_hw_to_nl80211_band(band); 1831 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 1832 rx_status->band = nl_band; 1833 } 1834 1835 if (desc_info->icv_err || desc_info->crc32_err) 1836 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 1837 1838 if (desc_info->hw_dec && 1839 !(desc_info->sw_dec || desc_info->icv_err)) 1840 rx_status->flag |= RX_FLAG_DECRYPTED; 1841 1842 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1843 1844 data_rate = desc_info->data_rate; 1845 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1846 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1847 rx_status->encoding = RX_ENC_LEGACY; 1848 rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1849 /* convert rate_idx after we get the correct band */ 1850 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1851 rx_status->encoding = RX_ENC_HT; 1852 rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1853 if (desc_info->gi_ltf) 1854 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1855 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1856 rx_status->encoding = RX_ENC_VHT; 1857 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1858 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1859 if (desc_info->gi_ltf) 1860 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1861 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1862 rx_status->encoding = RX_ENC_HE; 1863 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1864 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1865 } else { 1866 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1867 } 1868 1869 /* he_gi is used to match ppdu, so we always fill it. */ 1870 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); 1871 rx_status->flag |= RX_FLAG_MACTIME_START; 1872 rx_status->mactime = desc_info->free_run_cnt; 1873 1874 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 1875 } 1876 1877 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 1878 { 1879 const struct rtw89_chip_info *chip = rtwdev->chip; 1880 1881 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 1882 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 1883 return RTW89_PS_MODE_NONE; 1884 1885 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 1886 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 1887 return RTW89_PS_MODE_PWR_GATED; 1888 1889 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 1890 return RTW89_PS_MODE_CLK_GATED; 1891 1892 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 1893 return RTW89_PS_MODE_RFOFF; 1894 1895 return RTW89_PS_MODE_NONE; 1896 } 1897 1898 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 1899 struct rtw89_rx_desc_info *desc_info) 1900 { 1901 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1902 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1903 struct ieee80211_rx_status *rx_status; 1904 struct sk_buff *skb_ppdu, *tmp; 1905 1906 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 1907 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 1908 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1909 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 1910 } 1911 } 1912 1913 void rtw89_core_rx(struct rtw89_dev *rtwdev, 1914 struct rtw89_rx_desc_info *desc_info, 1915 struct sk_buff *skb) 1916 { 1917 struct ieee80211_rx_status *rx_status; 1918 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1919 u8 ppdu_cnt = desc_info->ppdu_cnt; 1920 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1921 1922 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 1923 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 1924 return; 1925 } 1926 1927 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 1928 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 1929 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 1930 } 1931 1932 rx_status = IEEE80211_SKB_RXCB(skb); 1933 memset(rx_status, 0, sizeof(*rx_status)); 1934 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 1935 if (desc_info->long_rxdesc && 1936 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 1937 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 1938 else 1939 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 1940 } 1941 EXPORT_SYMBOL(rtw89_core_rx); 1942 1943 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 1944 { 1945 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1946 return; 1947 1948 napi_enable(&rtwdev->napi); 1949 } 1950 EXPORT_SYMBOL(rtw89_core_napi_start); 1951 1952 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 1953 { 1954 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1955 return; 1956 1957 napi_synchronize(&rtwdev->napi); 1958 napi_disable(&rtwdev->napi); 1959 } 1960 EXPORT_SYMBOL(rtw89_core_napi_stop); 1961 1962 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 1963 { 1964 init_dummy_netdev(&rtwdev->netdev); 1965 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 1966 rtwdev->hci.ops->napi_poll); 1967 } 1968 EXPORT_SYMBOL(rtw89_core_napi_init); 1969 1970 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 1971 { 1972 rtw89_core_napi_stop(rtwdev); 1973 netif_napi_del(&rtwdev->napi); 1974 } 1975 EXPORT_SYMBOL(rtw89_core_napi_deinit); 1976 1977 static void rtw89_core_ba_work(struct work_struct *work) 1978 { 1979 struct rtw89_dev *rtwdev = 1980 container_of(work, struct rtw89_dev, ba_work); 1981 struct rtw89_txq *rtwtxq, *tmp; 1982 int ret; 1983 1984 spin_lock_bh(&rtwdev->ba_lock); 1985 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1986 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1987 struct ieee80211_sta *sta = txq->sta; 1988 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1989 u8 tid = txq->tid; 1990 1991 if (!sta) { 1992 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 1993 goto skip_ba_work; 1994 } 1995 1996 if (rtwsta->disassoc) { 1997 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1998 "cannot start BA with disassoc sta\n"); 1999 goto skip_ba_work; 2000 } 2001 2002 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2003 if (ret) { 2004 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2005 "failed to setup BA session for %pM:%2d: %d\n", 2006 sta->addr, tid, ret); 2007 if (ret == -EINVAL) 2008 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2009 } 2010 skip_ba_work: 2011 list_del_init(&rtwtxq->list); 2012 } 2013 spin_unlock_bh(&rtwdev->ba_lock); 2014 } 2015 2016 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2017 struct ieee80211_sta *sta) 2018 { 2019 struct rtw89_txq *rtwtxq, *tmp; 2020 2021 spin_lock_bh(&rtwdev->ba_lock); 2022 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2023 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2024 2025 if (sta == txq->sta) 2026 list_del_init(&rtwtxq->list); 2027 } 2028 spin_unlock_bh(&rtwdev->ba_lock); 2029 } 2030 2031 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2032 struct ieee80211_sta *sta) 2033 { 2034 struct rtw89_txq *rtwtxq, *tmp; 2035 2036 spin_lock_bh(&rtwdev->ba_lock); 2037 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2038 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2039 2040 if (sta == txq->sta) { 2041 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2042 list_del_init(&rtwtxq->list); 2043 } 2044 } 2045 spin_unlock_bh(&rtwdev->ba_lock); 2046 } 2047 2048 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2049 struct ieee80211_sta *sta) 2050 { 2051 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2052 struct sk_buff *skb, *tmp; 2053 2054 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2055 skb_unlink(skb, &rtwsta->roc_queue); 2056 dev_kfree_skb_any(skb); 2057 } 2058 } 2059 2060 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2061 struct rtw89_txq *rtwtxq) 2062 { 2063 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2064 struct ieee80211_sta *sta = txq->sta; 2065 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2066 2067 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2068 return; 2069 2070 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2071 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2072 return; 2073 2074 spin_lock_bh(&rtwdev->ba_lock); 2075 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2076 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2077 spin_unlock_bh(&rtwdev->ba_lock); 2078 2079 ieee80211_stop_tx_ba_session(sta, txq->tid); 2080 cancel_delayed_work(&rtwdev->forbid_ba_work); 2081 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2082 RTW89_FORBID_BA_TIMER); 2083 } 2084 2085 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2086 struct rtw89_txq *rtwtxq, 2087 struct sk_buff *skb) 2088 { 2089 struct ieee80211_hw *hw = rtwdev->hw; 2090 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2091 struct ieee80211_sta *sta = txq->sta; 2092 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2093 2094 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2095 return; 2096 2097 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2098 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2099 return; 2100 } 2101 2102 if (unlikely(!sta)) 2103 return; 2104 2105 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2106 return; 2107 2108 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2109 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2110 return; 2111 } 2112 2113 spin_lock_bh(&rtwdev->ba_lock); 2114 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2115 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2116 ieee80211_queue_work(hw, &rtwdev->ba_work); 2117 } 2118 spin_unlock_bh(&rtwdev->ba_lock); 2119 } 2120 2121 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2122 struct rtw89_txq *rtwtxq, 2123 unsigned long frame_cnt, 2124 unsigned long byte_cnt) 2125 { 2126 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2127 struct ieee80211_vif *vif = txq->vif; 2128 struct ieee80211_sta *sta = txq->sta; 2129 struct sk_buff *skb; 2130 unsigned long i; 2131 int ret; 2132 2133 rcu_read_lock(); 2134 for (i = 0; i < frame_cnt; i++) { 2135 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2136 if (!skb) { 2137 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2138 goto out; 2139 } 2140 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2141 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2142 if (ret) { 2143 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2144 ieee80211_free_txskb(rtwdev->hw, skb); 2145 break; 2146 } 2147 } 2148 out: 2149 rcu_read_unlock(); 2150 } 2151 2152 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2153 { 2154 u8 qsel, ch_dma; 2155 2156 qsel = rtw89_core_get_qsel(rtwdev, tid); 2157 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2158 2159 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2160 } 2161 2162 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2163 struct ieee80211_txq *txq, 2164 unsigned long *frame_cnt, 2165 bool *sched_txq, bool *reinvoke) 2166 { 2167 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2168 struct ieee80211_sta *sta = txq->sta; 2169 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2170 2171 if (!sta || rtwsta->max_agg_wait <= 0) 2172 return false; 2173 2174 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2175 return false; 2176 2177 if (*frame_cnt > 1) { 2178 *frame_cnt -= 1; 2179 *sched_txq = true; 2180 *reinvoke = true; 2181 rtwtxq->wait_cnt = 1; 2182 return false; 2183 } 2184 2185 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2186 *reinvoke = true; 2187 rtwtxq->wait_cnt++; 2188 return true; 2189 } 2190 2191 rtwtxq->wait_cnt = 0; 2192 return false; 2193 } 2194 2195 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2196 { 2197 struct ieee80211_hw *hw = rtwdev->hw; 2198 struct ieee80211_txq *txq; 2199 struct rtw89_vif *rtwvif; 2200 struct rtw89_txq *rtwtxq; 2201 unsigned long frame_cnt; 2202 unsigned long byte_cnt; 2203 u32 tx_resource; 2204 bool sched_txq; 2205 2206 ieee80211_txq_schedule_start(hw, ac); 2207 while ((txq = ieee80211_next_txq(hw, ac))) { 2208 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2209 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2210 2211 if (rtwvif->offchan) { 2212 ieee80211_return_txq(hw, txq, true); 2213 continue; 2214 } 2215 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2216 sched_txq = false; 2217 2218 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2219 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2220 ieee80211_return_txq(hw, txq, true); 2221 continue; 2222 } 2223 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2224 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2225 ieee80211_return_txq(hw, txq, sched_txq); 2226 if (frame_cnt != 0) 2227 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2228 2229 /* bound of tx_resource could get stuck due to burst traffic */ 2230 if (frame_cnt == tx_resource) 2231 *reinvoke = true; 2232 } 2233 ieee80211_txq_schedule_end(hw, ac); 2234 } 2235 2236 static void rtw89_ips_work(struct work_struct *work) 2237 { 2238 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2239 ips_work); 2240 mutex_lock(&rtwdev->mutex); 2241 rtw89_enter_ips_by_hwflags(rtwdev); 2242 mutex_unlock(&rtwdev->mutex); 2243 } 2244 2245 static void rtw89_core_txq_work(struct work_struct *w) 2246 { 2247 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2248 bool reinvoke = false; 2249 u8 ac; 2250 2251 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2252 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2253 2254 if (reinvoke) { 2255 /* reinvoke to process the last frame */ 2256 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2257 } 2258 } 2259 2260 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2261 { 2262 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2263 txq_reinvoke_work.work); 2264 2265 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2266 } 2267 2268 static void rtw89_forbid_ba_work(struct work_struct *w) 2269 { 2270 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2271 forbid_ba_work.work); 2272 struct rtw89_txq *rtwtxq, *tmp; 2273 2274 spin_lock_bh(&rtwdev->ba_lock); 2275 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2276 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2277 list_del_init(&rtwtxq->list); 2278 } 2279 spin_unlock_bh(&rtwdev->ba_lock); 2280 } 2281 2282 static void rtw89_core_sta_pending_tx_iter(void *data, 2283 struct ieee80211_sta *sta) 2284 { 2285 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2286 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2287 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2288 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2289 struct sk_buff *skb, *tmp; 2290 int qsel, ret; 2291 2292 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2293 return; 2294 2295 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2296 return; 2297 2298 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2299 skb_unlink(skb, &rtwsta->roc_queue); 2300 2301 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2302 if (ret) { 2303 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2304 dev_kfree_skb_any(skb); 2305 } else { 2306 rtw89_core_tx_kick_off(rtwdev, qsel); 2307 } 2308 } 2309 } 2310 2311 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2312 struct rtw89_vif *rtwvif) 2313 { 2314 ieee80211_iterate_stations_atomic(rtwdev->hw, 2315 rtw89_core_sta_pending_tx_iter, 2316 rtwvif); 2317 } 2318 2319 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2320 struct rtw89_vif *rtwvif, bool qos, bool ps) 2321 { 2322 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2323 struct ieee80211_sta *sta; 2324 struct ieee80211_hdr *hdr; 2325 struct sk_buff *skb; 2326 int ret, qsel; 2327 2328 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2329 return 0; 2330 2331 rcu_read_lock(); 2332 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2333 if (!sta) { 2334 ret = -EINVAL; 2335 goto out; 2336 } 2337 2338 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2339 if (!skb) { 2340 ret = -ENOMEM; 2341 goto out; 2342 } 2343 2344 hdr = (struct ieee80211_hdr *)skb->data; 2345 if (ps) 2346 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2347 2348 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2349 if (ret) { 2350 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2351 dev_kfree_skb_any(skb); 2352 goto out; 2353 } 2354 2355 rcu_read_unlock(); 2356 2357 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2358 RTW89_ROC_TX_TIMEOUT); 2359 out: 2360 rcu_read_unlock(); 2361 2362 return ret; 2363 } 2364 2365 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2366 { 2367 struct ieee80211_hw *hw = rtwdev->hw; 2368 struct rtw89_roc *roc = &rtwvif->roc; 2369 struct cfg80211_chan_def roc_chan; 2370 struct rtw89_vif *tmp; 2371 int ret; 2372 2373 lockdep_assert_held(&rtwdev->mutex); 2374 2375 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 2376 msecs_to_jiffies(rtwvif->roc.duration)); 2377 2378 rtw89_leave_ips_by_hwflags(rtwdev); 2379 rtw89_leave_lps(rtwdev); 2380 2381 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2382 if (ret) 2383 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2384 "roc send null-1 failed: %d\n", ret); 2385 2386 rtw89_for_each_rtwvif(rtwdev, tmp) 2387 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2388 tmp->offchan = true; 2389 2390 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2391 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2392 rtw89_set_channel(rtwdev); 2393 rtw89_write32_clr(rtwdev, 2394 rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), 2395 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2396 2397 ieee80211_ready_on_channel(hw); 2398 } 2399 2400 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2401 { 2402 struct ieee80211_hw *hw = rtwdev->hw; 2403 struct rtw89_roc *roc = &rtwvif->roc; 2404 struct rtw89_vif *tmp; 2405 int ret; 2406 2407 lockdep_assert_held(&rtwdev->mutex); 2408 2409 ieee80211_remain_on_channel_expired(hw); 2410 2411 rtw89_leave_ips_by_hwflags(rtwdev); 2412 rtw89_leave_lps(rtwdev); 2413 2414 rtw89_write32_mask(rtwdev, 2415 rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), 2416 B_AX_RX_FLTR_CFG_MASK, 2417 rtwdev->hal.rx_fltr); 2418 2419 roc->state = RTW89_ROC_IDLE; 2420 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 2421 rtw89_set_channel(rtwdev); 2422 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 2423 if (ret) 2424 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2425 "roc send null-0 failed: %d\n", ret); 2426 2427 rtw89_for_each_rtwvif(rtwdev, tmp) 2428 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2429 tmp->offchan = false; 2430 2431 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 2432 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2433 2434 if (hw->conf.flags & IEEE80211_CONF_IDLE) 2435 ieee80211_queue_delayed_work(hw, &roc->roc_work, 2436 RTW89_ROC_IDLE_TIMEOUT); 2437 } 2438 2439 void rtw89_roc_work(struct work_struct *work) 2440 { 2441 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2442 roc.roc_work.work); 2443 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2444 struct rtw89_roc *roc = &rtwvif->roc; 2445 2446 mutex_lock(&rtwdev->mutex); 2447 2448 switch (roc->state) { 2449 case RTW89_ROC_IDLE: 2450 rtw89_enter_ips_by_hwflags(rtwdev); 2451 break; 2452 case RTW89_ROC_MGMT: 2453 case RTW89_ROC_NORMAL: 2454 rtw89_roc_end(rtwdev, rtwvif); 2455 break; 2456 default: 2457 break; 2458 } 2459 2460 mutex_unlock(&rtwdev->mutex); 2461 } 2462 2463 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2464 u32 throughput, u64 cnt) 2465 { 2466 if (cnt < 100) 2467 return RTW89_TFC_IDLE; 2468 if (throughput > 50) 2469 return RTW89_TFC_HIGH; 2470 if (throughput > 10) 2471 return RTW89_TFC_MID; 2472 if (throughput > 2) 2473 return RTW89_TFC_LOW; 2474 return RTW89_TFC_ULTRA_LOW; 2475 } 2476 2477 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2478 struct rtw89_traffic_stats *stats) 2479 { 2480 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2481 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2482 2483 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2484 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2485 2486 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 2487 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 2488 2489 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 2490 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 2491 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 2492 stats->tx_cnt); 2493 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 2494 stats->rx_cnt); 2495 stats->tx_avg_len = stats->tx_cnt ? 2496 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 2497 stats->rx_avg_len = stats->rx_cnt ? 2498 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 2499 2500 stats->tx_unicast = 0; 2501 stats->rx_unicast = 0; 2502 stats->tx_cnt = 0; 2503 stats->rx_cnt = 0; 2504 stats->rx_tf_periodic = stats->rx_tf_acc; 2505 stats->rx_tf_acc = 0; 2506 2507 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 2508 return true; 2509 2510 return false; 2511 } 2512 2513 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 2514 { 2515 struct rtw89_vif *rtwvif; 2516 bool tfc_changed; 2517 2518 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 2519 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 2520 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 2521 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 2522 } 2523 2524 return tfc_changed; 2525 } 2526 2527 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2528 { 2529 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 2530 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 2531 rtwvif->tdls_peer) 2532 return; 2533 2534 if (rtwdev->total_sta_assoc > 1) 2535 return; 2536 2537 if (rtwvif->offchan) 2538 return; 2539 2540 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 2541 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 2542 rtw89_enter_lps(rtwdev, rtwvif, true); 2543 } 2544 2545 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 2546 { 2547 struct rtw89_vif *rtwvif; 2548 2549 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2550 rtw89_vif_enter_lps(rtwdev, rtwvif); 2551 } 2552 2553 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 2554 struct rtw89_traffic_stats *stats) 2555 { 2556 stats->tx_unicast = 0; 2557 stats->rx_unicast = 0; 2558 stats->tx_cnt = 0; 2559 stats->rx_cnt = 0; 2560 ewma_tp_init(&stats->tx_ewma_tp); 2561 ewma_tp_init(&stats->rx_ewma_tp); 2562 } 2563 2564 static void rtw89_track_work(struct work_struct *work) 2565 { 2566 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2567 track_work.work); 2568 bool tfc_changed; 2569 2570 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 2571 return; 2572 2573 mutex_lock(&rtwdev->mutex); 2574 2575 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2576 goto out; 2577 2578 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2579 RTW89_TRACK_WORK_PERIOD); 2580 2581 tfc_changed = rtw89_traffic_stats_track(rtwdev); 2582 if (rtwdev->scanning) 2583 goto out; 2584 2585 rtw89_leave_lps(rtwdev); 2586 2587 if (tfc_changed) { 2588 rtw89_hci_recalc_int_mit(rtwdev); 2589 rtw89_btc_ntfy_wl_sta(rtwdev); 2590 } 2591 rtw89_mac_bf_monitor_track(rtwdev); 2592 rtw89_phy_stat_track(rtwdev); 2593 rtw89_phy_env_monitor_track(rtwdev); 2594 rtw89_phy_dig(rtwdev); 2595 rtw89_chip_rfk_track(rtwdev); 2596 rtw89_phy_ra_update(rtwdev); 2597 rtw89_phy_cfo_track(rtwdev); 2598 rtw89_phy_tx_path_div_track(rtwdev); 2599 rtw89_phy_ul_tb_ctrl_track(rtwdev); 2600 2601 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 2602 rtw89_enter_lps_track(rtwdev); 2603 2604 out: 2605 mutex_unlock(&rtwdev->mutex); 2606 } 2607 2608 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 2609 { 2610 unsigned long bit; 2611 2612 bit = find_first_zero_bit(addr, size); 2613 if (bit < size) 2614 set_bit(bit, addr); 2615 2616 return bit; 2617 } 2618 2619 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 2620 { 2621 clear_bit(bit, addr); 2622 } 2623 2624 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 2625 { 2626 bitmap_zero(addr, nbits); 2627 } 2628 2629 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 2630 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2631 { 2632 const struct rtw89_chip_info *chip = rtwdev->chip; 2633 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2634 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2635 u8 idx; 2636 int i; 2637 2638 lockdep_assert_held(&rtwdev->mutex); 2639 2640 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 2641 if (idx == chip->bacam_num) { 2642 /* allocate a static BA CAM to tid=0/5, so replace the existing 2643 * one if BA CAM is full. Hardware will process the original tid 2644 * automatically. 2645 */ 2646 if (tid != 0 && tid != 5) 2647 return -ENOSPC; 2648 2649 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 2650 tmp = &cam_info->ba_cam_entry[i]; 2651 if (tmp->tid == 0 || tmp->tid == 5) 2652 continue; 2653 2654 idx = i; 2655 entry = tmp; 2656 list_del(&entry->list); 2657 break; 2658 } 2659 2660 if (!entry) 2661 return -ENOSPC; 2662 } else { 2663 entry = &cam_info->ba_cam_entry[idx]; 2664 } 2665 2666 entry->tid = tid; 2667 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 2668 2669 *cam_idx = idx; 2670 2671 return 0; 2672 } 2673 2674 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 2675 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2676 { 2677 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2678 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2679 u8 idx; 2680 2681 lockdep_assert_held(&rtwdev->mutex); 2682 2683 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 2684 if (entry->tid != tid) 2685 continue; 2686 2687 idx = entry - cam_info->ba_cam_entry; 2688 list_del(&entry->list); 2689 2690 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 2691 *cam_idx = idx; 2692 return 0; 2693 } 2694 2695 return -ENOENT; 2696 } 2697 2698 #define RTW89_TYPE_MAPPING(_type) \ 2699 case NL80211_IFTYPE_ ## _type: \ 2700 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 2701 break 2702 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 2703 { 2704 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2705 2706 switch (vif->type) { 2707 case NL80211_IFTYPE_STATION: 2708 if (vif->p2p) 2709 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 2710 else 2711 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 2712 break; 2713 case NL80211_IFTYPE_AP: 2714 if (vif->p2p) 2715 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 2716 else 2717 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 2718 break; 2719 RTW89_TYPE_MAPPING(ADHOC); 2720 RTW89_TYPE_MAPPING(MONITOR); 2721 RTW89_TYPE_MAPPING(MESH_POINT); 2722 default: 2723 WARN_ON(1); 2724 break; 2725 } 2726 2727 switch (vif->type) { 2728 case NL80211_IFTYPE_AP: 2729 case NL80211_IFTYPE_MESH_POINT: 2730 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 2731 rtwvif->self_role = RTW89_SELF_ROLE_AP; 2732 break; 2733 case NL80211_IFTYPE_ADHOC: 2734 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 2735 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2736 break; 2737 case NL80211_IFTYPE_STATION: 2738 if (assoc) { 2739 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 2740 rtwvif->trigger = vif->bss_conf.he_support; 2741 } else { 2742 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 2743 rtwvif->trigger = false; 2744 } 2745 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2746 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 2747 break; 2748 case NL80211_IFTYPE_MONITOR: 2749 break; 2750 default: 2751 WARN_ON(1); 2752 break; 2753 } 2754 } 2755 2756 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 2757 struct ieee80211_vif *vif, 2758 struct ieee80211_sta *sta) 2759 { 2760 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2761 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2762 int i; 2763 int ret; 2764 2765 rtwsta->rtwdev = rtwdev; 2766 rtwsta->rtwvif = rtwvif; 2767 rtwsta->prev_rssi = 0; 2768 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 2769 skb_queue_head_init(&rtwsta->roc_queue); 2770 2771 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 2772 rtw89_core_txq_init(rtwdev, sta->txq[i]); 2773 2774 ewma_rssi_init(&rtwsta->avg_rssi); 2775 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2776 ewma_rssi_init(&rtwsta->rssi[i]); 2777 2778 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2779 /* for station mode, assign the mac_id from itself */ 2780 rtwsta->mac_id = rtwvif->mac_id; 2781 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2782 BTC_ROLE_MSTS_STA_CONN_START); 2783 rtw89_chip_rfk_channel(rtwdev); 2784 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2785 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 2786 RTW89_MAX_MAC_ID_NUM); 2787 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 2788 return -ENOSPC; 2789 2790 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 2791 if (ret) { 2792 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2793 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 2794 return ret; 2795 } 2796 2797 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 2798 RTW89_ROLE_CREATE); 2799 if (ret) { 2800 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2801 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2802 return ret; 2803 } 2804 } 2805 2806 return 0; 2807 } 2808 2809 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 2810 struct ieee80211_vif *vif, 2811 struct ieee80211_sta *sta) 2812 { 2813 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2814 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2815 2816 if (vif->type == NL80211_IFTYPE_STATION) 2817 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 2818 2819 rtwdev->total_sta_assoc--; 2820 if (sta->tdls) 2821 rtwvif->tdls_peer--; 2822 rtwsta->disassoc = true; 2823 2824 return 0; 2825 } 2826 2827 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 2828 struct ieee80211_vif *vif, 2829 struct ieee80211_sta *sta) 2830 { 2831 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2832 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2833 int ret; 2834 2835 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 2836 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 2837 rtw89_core_free_sta_pending_ba(rtwdev, sta); 2838 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 2839 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 2840 2841 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2842 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 2843 if (sta->tdls) 2844 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 2845 2846 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2847 rtw89_vif_type_mapping(vif, false); 2848 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 2849 } 2850 2851 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2852 if (ret) { 2853 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2854 return ret; 2855 } 2856 2857 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 2858 if (ret) { 2859 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2860 return ret; 2861 } 2862 2863 /* update cam aid mac_id net_type */ 2864 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2865 if (ret) { 2866 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2867 return ret; 2868 } 2869 2870 return ret; 2871 } 2872 2873 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 2874 struct ieee80211_vif *vif, 2875 struct ieee80211_sta *sta) 2876 { 2877 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2878 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2879 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 2880 int ret; 2881 2882 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2883 if (sta->tdls) { 2884 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 2885 if (ret) { 2886 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 2887 return ret; 2888 } 2889 } 2890 2891 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 2892 if (ret) { 2893 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 2894 return ret; 2895 } 2896 } 2897 2898 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2899 if (ret) { 2900 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2901 return ret; 2902 } 2903 2904 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 2905 if (ret) { 2906 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2907 return ret; 2908 } 2909 2910 /* update cam aid mac_id net_type */ 2911 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2912 if (ret) { 2913 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2914 return ret; 2915 } 2916 2917 rtwdev->total_sta_assoc++; 2918 if (sta->tdls) 2919 rtwvif->tdls_peer++; 2920 rtw89_phy_ra_assoc(rtwdev, sta); 2921 rtw89_mac_bf_assoc(rtwdev, vif, sta); 2922 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 2923 2924 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2925 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 2926 2927 if (bss_conf->he_support && 2928 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 2929 rtwsta->er_cap = true; 2930 2931 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2932 BTC_ROLE_MSTS_STA_CONN_END); 2933 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); 2934 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 2935 2936 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 2937 if (ret) { 2938 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 2939 return ret; 2940 } 2941 } 2942 2943 return ret; 2944 } 2945 2946 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 2947 struct ieee80211_vif *vif, 2948 struct ieee80211_sta *sta) 2949 { 2950 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2951 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2952 int ret; 2953 2954 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2955 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2956 BTC_ROLE_MSTS_STA_DIS_CONN); 2957 else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2958 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2959 2960 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 2961 RTW89_ROLE_REMOVE); 2962 if (ret) { 2963 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2964 return ret; 2965 } 2966 } 2967 2968 return 0; 2969 } 2970 2971 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 2972 struct ieee80211_sta *sta, 2973 struct cfg80211_tid_cfg *tid_conf) 2974 { 2975 struct ieee80211_txq *txq; 2976 struct rtw89_txq *rtwtxq; 2977 u32 mask = tid_conf->mask; 2978 u8 tids = tid_conf->tids; 2979 int tids_nbit = BITS_PER_BYTE; 2980 int i; 2981 2982 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 2983 if (!tids) 2984 break; 2985 2986 if (!(tids & BIT(0))) 2987 continue; 2988 2989 txq = sta->txq[i]; 2990 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2991 2992 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 2993 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 2994 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2995 } else { 2996 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 2997 ieee80211_stop_tx_ba_session(sta, txq->tid); 2998 spin_lock_bh(&rtwdev->ba_lock); 2999 list_del_init(&rtwtxq->list); 3000 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3001 spin_unlock_bh(&rtwdev->ba_lock); 3002 } 3003 } 3004 3005 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3006 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3007 sta->max_amsdu_subframes = 0; 3008 else 3009 sta->max_amsdu_subframes = 1; 3010 } 3011 } 3012 } 3013 3014 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3015 struct ieee80211_sta *sta, 3016 struct cfg80211_tid_config *tid_config) 3017 { 3018 int i; 3019 3020 for (i = 0; i < tid_config->n_tid_conf; i++) 3021 _rtw89_core_set_tid_config(rtwdev, sta, 3022 &tid_config->tid_conf[i]); 3023 } 3024 3025 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3026 struct ieee80211_sta_ht_cap *ht_cap) 3027 { 3028 static const __le16 highest[RF_PATH_MAX] = { 3029 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3030 }; 3031 struct rtw89_hal *hal = &rtwdev->hal; 3032 u8 nss = hal->rx_nss; 3033 int i; 3034 3035 ht_cap->ht_supported = true; 3036 ht_cap->cap = 0; 3037 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3038 IEEE80211_HT_CAP_MAX_AMSDU | 3039 IEEE80211_HT_CAP_TX_STBC | 3040 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3041 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3042 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3043 IEEE80211_HT_CAP_DSSSCCK40 | 3044 IEEE80211_HT_CAP_SGI_40; 3045 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3046 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3047 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3048 for (i = 0; i < nss; i++) 3049 ht_cap->mcs.rx_mask[i] = 0xFF; 3050 ht_cap->mcs.rx_mask[4] = 0x01; 3051 ht_cap->mcs.rx_highest = highest[nss - 1]; 3052 } 3053 3054 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3055 struct ieee80211_sta_vht_cap *vht_cap) 3056 { 3057 static const __le16 highest_bw80[RF_PATH_MAX] = { 3058 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3059 }; 3060 static const __le16 highest_bw160[RF_PATH_MAX] = { 3061 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3062 }; 3063 const struct rtw89_chip_info *chip = rtwdev->chip; 3064 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 3065 struct rtw89_hal *hal = &rtwdev->hal; 3066 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3067 u8 sts_cap = 3; 3068 int i; 3069 3070 for (i = 0; i < 8; i++) { 3071 if (i < hal->tx_nss) 3072 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3073 else 3074 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3075 if (i < hal->rx_nss) 3076 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3077 else 3078 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3079 } 3080 3081 vht_cap->vht_supported = true; 3082 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3083 IEEE80211_VHT_CAP_SHORT_GI_80 | 3084 IEEE80211_VHT_CAP_RXSTBC_1 | 3085 IEEE80211_VHT_CAP_HTC_VHT | 3086 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3087 0; 3088 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3089 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3090 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3091 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3092 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3093 if (chip->support_bw160) 3094 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3095 IEEE80211_VHT_CAP_SHORT_GI_160; 3096 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3097 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3098 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3099 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3100 } 3101 3102 #define RTW89_SBAND_IFTYPES_NR 2 3103 3104 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3105 enum nl80211_band band, 3106 struct ieee80211_supported_band *sband) 3107 { 3108 const struct rtw89_chip_info *chip = rtwdev->chip; 3109 struct rtw89_hal *hal = &rtwdev->hal; 3110 struct ieee80211_sband_iftype_data *iftype_data; 3111 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3112 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3113 u16 mcs_map = 0; 3114 int i; 3115 int nss = hal->rx_nss; 3116 int idx = 0; 3117 3118 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3119 if (!iftype_data) 3120 return; 3121 3122 for (i = 0; i < 8; i++) { 3123 if (i < nss) 3124 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3125 else 3126 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3127 } 3128 3129 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 3130 struct ieee80211_sta_he_cap *he_cap; 3131 u8 *mac_cap_info; 3132 u8 *phy_cap_info; 3133 3134 switch (i) { 3135 case NL80211_IFTYPE_STATION: 3136 case NL80211_IFTYPE_AP: 3137 break; 3138 default: 3139 continue; 3140 } 3141 3142 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3143 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3144 break; 3145 } 3146 3147 iftype_data[idx].types_mask = BIT(i); 3148 he_cap = &iftype_data[idx].he_cap; 3149 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3150 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3151 3152 he_cap->has_he = true; 3153 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3154 if (i == NL80211_IFTYPE_STATION) 3155 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3156 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3157 IEEE80211_HE_MAC_CAP2_BSR; 3158 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3159 if (i == NL80211_IFTYPE_AP) 3160 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3161 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3162 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3163 if (i == NL80211_IFTYPE_STATION) 3164 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3165 if (band == NL80211_BAND_2GHZ) { 3166 phy_cap_info[0] = 3167 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3168 } else { 3169 phy_cap_info[0] = 3170 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3171 if (chip->support_bw160) 3172 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3173 } 3174 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3175 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3176 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3177 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3178 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3179 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3180 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3181 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3182 if (i == NL80211_IFTYPE_STATION) 3183 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3184 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3185 if (i == NL80211_IFTYPE_AP) 3186 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3187 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3188 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3189 if (chip->support_bw160) 3190 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3191 phy_cap_info[5] = no_ng16 ? 0 : 3192 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3193 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3194 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3195 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3196 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3197 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3198 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3199 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3200 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3201 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3202 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3203 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3204 if (chip->support_bw160) 3205 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3206 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3207 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3208 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3209 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3210 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3211 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3212 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3213 if (i == NL80211_IFTYPE_STATION) 3214 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3215 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3216 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3217 if (chip->support_bw160) { 3218 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3219 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3220 } 3221 3222 if (band == NL80211_BAND_6GHZ) { 3223 __le16 capa; 3224 3225 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3226 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3227 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3228 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3229 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3230 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3231 iftype_data[idx].he_6ghz_capa.capa = capa; 3232 } 3233 3234 idx++; 3235 } 3236 3237 sband->iftype_data = iftype_data; 3238 sband->n_iftype_data = idx; 3239 } 3240 3241 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3242 { 3243 struct ieee80211_hw *hw = rtwdev->hw; 3244 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 3245 struct ieee80211_supported_band *sband_6ghz = NULL; 3246 u32 size = sizeof(struct ieee80211_supported_band); 3247 u8 support_bands = rtwdev->chip->support_bands; 3248 3249 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 3250 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 3251 if (!sband_2ghz) 3252 goto err; 3253 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 3254 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 3255 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 3256 } 3257 3258 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 3259 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 3260 if (!sband_5ghz) 3261 goto err; 3262 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 3263 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 3264 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 3265 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 3266 } 3267 3268 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 3269 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 3270 if (!sband_6ghz) 3271 goto err; 3272 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 3273 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 3274 } 3275 3276 return 0; 3277 3278 err: 3279 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3280 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3281 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3282 if (sband_2ghz) 3283 kfree(sband_2ghz->iftype_data); 3284 if (sband_5ghz) 3285 kfree(sband_5ghz->iftype_data); 3286 if (sband_6ghz) 3287 kfree(sband_6ghz->iftype_data); 3288 kfree(sband_2ghz); 3289 kfree(sband_5ghz); 3290 kfree(sband_6ghz); 3291 return -ENOMEM; 3292 } 3293 3294 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 3295 { 3296 struct ieee80211_hw *hw = rtwdev->hw; 3297 3298 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 3299 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 3300 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 3301 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 3302 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 3303 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 3304 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 3305 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3306 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3307 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3308 } 3309 3310 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 3311 { 3312 int i; 3313 3314 for (i = 0; i < RTW89_PHY_MAX; i++) 3315 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 3316 for (i = 0; i < RTW89_PHY_MAX; i++) 3317 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 3318 } 3319 3320 void rtw89_core_update_beacon_work(struct work_struct *work) 3321 { 3322 struct rtw89_dev *rtwdev; 3323 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3324 update_beacon_work); 3325 3326 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 3327 return; 3328 3329 rtwdev = rtwvif->rtwdev; 3330 mutex_lock(&rtwdev->mutex); 3331 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 3332 mutex_unlock(&rtwdev->mutex); 3333 } 3334 3335 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 3336 { 3337 struct completion *cmpl = &wait->completion; 3338 unsigned long timeout; 3339 unsigned int cur; 3340 3341 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 3342 if (cur != RTW89_WAIT_COND_IDLE) 3343 return -EBUSY; 3344 3345 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 3346 if (timeout == 0) { 3347 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3348 return -ETIMEDOUT; 3349 } 3350 3351 if (wait->data.err) 3352 return -EFAULT; 3353 3354 return 0; 3355 } 3356 3357 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 3358 const struct rtw89_completion_data *data) 3359 { 3360 unsigned int cur; 3361 3362 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 3363 if (cur != cond) 3364 return; 3365 3366 wait->data = *data; 3367 complete(&wait->completion); 3368 } 3369 3370 int rtw89_core_start(struct rtw89_dev *rtwdev) 3371 { 3372 int ret; 3373 3374 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 3375 ret = rtw89_mac_init(rtwdev); 3376 if (ret) { 3377 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 3378 return ret; 3379 } 3380 3381 rtw89_btc_ntfy_poweron(rtwdev); 3382 3383 /* efuse process */ 3384 3385 /* pre-config BB/RF, BB reset/RFC reset */ 3386 ret = rtw89_chip_disable_bb_rf(rtwdev); 3387 if (ret) 3388 return ret; 3389 ret = rtw89_chip_enable_bb_rf(rtwdev); 3390 if (ret) 3391 return ret; 3392 3393 rtw89_phy_init_bb_reg(rtwdev); 3394 rtw89_phy_init_rf_reg(rtwdev, false); 3395 3396 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 3397 3398 rtw89_phy_dm_init(rtwdev); 3399 3400 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 3401 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 3402 3403 ret = rtw89_hci_start(rtwdev); 3404 if (ret) { 3405 rtw89_err(rtwdev, "failed to start hci\n"); 3406 return ret; 3407 } 3408 3409 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3410 RTW89_TRACK_WORK_PERIOD); 3411 3412 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3413 3414 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 3415 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); 3416 rtw89_fw_h2c_init_ba_cam(rtwdev); 3417 3418 return 0; 3419 } 3420 3421 void rtw89_core_stop(struct rtw89_dev *rtwdev) 3422 { 3423 struct rtw89_btc *btc = &rtwdev->btc; 3424 3425 /* Prvent to stop twice; enter_ips and ops_stop */ 3426 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3427 return; 3428 3429 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 3430 3431 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3432 3433 mutex_unlock(&rtwdev->mutex); 3434 3435 cancel_work_sync(&rtwdev->c2h_work); 3436 cancel_work_sync(&btc->eapol_notify_work); 3437 cancel_work_sync(&btc->arp_notify_work); 3438 cancel_work_sync(&btc->dhcp_notify_work); 3439 cancel_work_sync(&btc->icmp_notify_work); 3440 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 3441 cancel_delayed_work_sync(&rtwdev->track_work); 3442 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 3443 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 3444 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 3445 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 3446 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 3447 3448 mutex_lock(&rtwdev->mutex); 3449 3450 rtw89_btc_ntfy_poweroff(rtwdev); 3451 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3452 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3453 rtw89_hci_stop(rtwdev); 3454 rtw89_hci_deinit(rtwdev); 3455 rtw89_mac_pwr_off(rtwdev); 3456 rtw89_hci_reset(rtwdev); 3457 } 3458 3459 int rtw89_core_init(struct rtw89_dev *rtwdev) 3460 { 3461 struct rtw89_btc *btc = &rtwdev->btc; 3462 u8 band; 3463 3464 INIT_LIST_HEAD(&rtwdev->ba_list); 3465 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 3466 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 3467 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 3468 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 3469 if (!(rtwdev->chip->support_bands & BIT(band))) 3470 continue; 3471 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 3472 } 3473 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 3474 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 3475 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 3476 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 3477 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 3478 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 3479 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 3480 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 3481 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 3482 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 3483 if (!rtwdev->txq_wq) 3484 return -ENOMEM; 3485 spin_lock_init(&rtwdev->ba_lock); 3486 spin_lock_init(&rtwdev->rpwm_lock); 3487 mutex_init(&rtwdev->mutex); 3488 mutex_init(&rtwdev->rf_mutex); 3489 rtwdev->total_sta_assoc = 0; 3490 3491 rtw89_init_wait(&rtwdev->mcc.wait); 3492 3493 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 3494 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 3495 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 3496 3497 skb_queue_head_init(&rtwdev->c2h_queue); 3498 rtw89_core_ppdu_sts_init(rtwdev); 3499 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 3500 3501 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 3502 3503 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 3504 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 3505 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 3506 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 3507 3508 init_completion(&rtwdev->fw.req.completion); 3509 3510 schedule_work(&rtwdev->load_firmware_work); 3511 3512 rtw89_ser_init(rtwdev); 3513 rtw89_entity_init(rtwdev); 3514 3515 return 0; 3516 } 3517 EXPORT_SYMBOL(rtw89_core_init); 3518 3519 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 3520 { 3521 rtw89_ser_deinit(rtwdev); 3522 rtw89_unload_firmware(rtwdev); 3523 rtw89_fw_free_all_early_h2c(rtwdev); 3524 3525 destroy_workqueue(rtwdev->txq_wq); 3526 mutex_destroy(&rtwdev->rf_mutex); 3527 mutex_destroy(&rtwdev->mutex); 3528 } 3529 EXPORT_SYMBOL(rtw89_core_deinit); 3530 3531 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3532 const u8 *mac_addr, bool hw_scan) 3533 { 3534 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3535 3536 rtwdev->scanning = true; 3537 rtw89_leave_lps(rtwdev); 3538 if (hw_scan) 3539 rtw89_leave_ips_by_hwflags(rtwdev); 3540 3541 ether_addr_copy(rtwvif->mac_addr, mac_addr); 3542 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 3543 rtw89_chip_rfk_scan(rtwdev, true); 3544 rtw89_hci_recalc_int_mit(rtwdev); 3545 rtw89_phy_config_edcca(rtwdev, true); 3546 3547 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 3548 } 3549 3550 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3551 struct ieee80211_vif *vif, bool hw_scan) 3552 { 3553 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3554 3555 if (!rtwvif) 3556 return; 3557 3558 ether_addr_copy(rtwvif->mac_addr, vif->addr); 3559 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3560 3561 rtw89_chip_rfk_scan(rtwdev, false); 3562 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 3563 rtw89_phy_config_edcca(rtwdev, false); 3564 3565 rtwdev->scanning = false; 3566 rtwdev->dig.bypass_dig = true; 3567 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3568 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 3569 } 3570 3571 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 3572 { 3573 const struct rtw89_chip_info *chip = rtwdev->chip; 3574 int ret; 3575 u8 val; 3576 u8 cv; 3577 3578 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 3579 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 3580 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 3581 cv = CHIP_CAV; 3582 else 3583 cv = CHIP_CBV; 3584 } 3585 3586 rtwdev->hal.cv = cv; 3587 3588 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) { 3589 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 3590 if (!ret) 3591 return; 3592 3593 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 3594 } 3595 } 3596 3597 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 3598 { 3599 rtwdev->hal.support_cckpd = 3600 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 3601 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 3602 rtwdev->hal.support_igi = 3603 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 3604 } 3605 3606 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 3607 { 3608 const struct rtw89_chip_info *chip = rtwdev->chip; 3609 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 3610 struct rtw89_efuse *efuse = &rtwdev->efuse; 3611 u8 rfe_type = efuse->rfe_type; 3612 3613 if (!conf) 3614 goto out; 3615 3616 while (conf->rfe_parms) { 3617 if (rfe_type == conf->rfe_type) { 3618 rtwdev->rfe_parms = conf->rfe_parms; 3619 return; 3620 } 3621 conf++; 3622 } 3623 3624 out: 3625 rtwdev->rfe_parms = chip->dflt_parms; 3626 } 3627 3628 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 3629 { 3630 int ret; 3631 3632 ret = rtw89_mac_partial_init(rtwdev); 3633 if (ret) 3634 return ret; 3635 3636 ret = rtw89_parse_efuse_map(rtwdev); 3637 if (ret) 3638 return ret; 3639 3640 ret = rtw89_parse_phycap_map(rtwdev); 3641 if (ret) 3642 return ret; 3643 3644 ret = rtw89_mac_setup_phycap(rtwdev); 3645 if (ret) 3646 return ret; 3647 3648 rtw89_core_setup_phycap(rtwdev); 3649 rtw89_core_setup_rfe_parms(rtwdev); 3650 3651 rtw89_mac_pwr_off(rtwdev); 3652 3653 return 0; 3654 } 3655 3656 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 3657 { 3658 rtw89_chip_fem_setup(rtwdev); 3659 3660 return 0; 3661 } 3662 3663 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 3664 { 3665 int ret; 3666 3667 rtw89_read_chip_ver(rtwdev); 3668 3669 ret = rtw89_wait_firmware_completion(rtwdev); 3670 if (ret) { 3671 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 3672 return ret; 3673 } 3674 3675 ret = rtw89_fw_recognize(rtwdev); 3676 if (ret) { 3677 rtw89_err(rtwdev, "failed to recognize firmware\n"); 3678 return ret; 3679 } 3680 3681 ret = rtw89_chip_efuse_info_setup(rtwdev); 3682 if (ret) 3683 return ret; 3684 3685 ret = rtw89_chip_board_info_setup(rtwdev); 3686 if (ret) 3687 return ret; 3688 3689 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 3690 3691 return 0; 3692 } 3693 EXPORT_SYMBOL(rtw89_chip_info_setup); 3694 3695 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 3696 { 3697 struct ieee80211_hw *hw = rtwdev->hw; 3698 struct rtw89_efuse *efuse = &rtwdev->efuse; 3699 int ret; 3700 int tx_headroom = IEEE80211_HT_CTL_LEN; 3701 3702 hw->vif_data_size = sizeof(struct rtw89_vif); 3703 hw->sta_data_size = sizeof(struct rtw89_sta); 3704 hw->txq_data_size = sizeof(struct rtw89_txq); 3705 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 3706 3707 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 3708 3709 hw->extra_tx_headroom = tx_headroom; 3710 hw->queues = IEEE80211_NUM_ACS; 3711 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 3712 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 3713 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 3714 3715 ieee80211_hw_set(hw, SIGNAL_DBM); 3716 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 3717 ieee80211_hw_set(hw, MFP_CAPABLE); 3718 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 3719 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 3720 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 3721 ieee80211_hw_set(hw, TX_AMSDU); 3722 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 3723 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 3724 ieee80211_hw_set(hw, SUPPORTS_PS); 3725 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 3726 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 3727 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 3728 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 3729 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 3730 ieee80211_hw_set(hw, CONNECTION_MONITOR); 3731 3732 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 3733 BIT(NL80211_IFTYPE_AP) | 3734 BIT(NL80211_IFTYPE_P2P_CLIENT) | 3735 BIT(NL80211_IFTYPE_P2P_GO); 3736 3737 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 3738 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 3739 3740 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 3741 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 3742 WIPHY_FLAG_AP_UAPSD | WIPHY_FLAG_SPLIT_SCAN_6GHZ; 3743 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 3744 3745 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 3746 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 3747 3748 #ifdef CONFIG_PM 3749 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 3750 #endif 3751 3752 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3753 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3754 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3755 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3756 hw->wiphy->max_remain_on_channel_duration = 1000; 3757 3758 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 3759 3760 ret = rtw89_core_set_supported_band(rtwdev); 3761 if (ret) { 3762 rtw89_err(rtwdev, "failed to set supported band\n"); 3763 return ret; 3764 } 3765 3766 hw->wiphy->reg_notifier = rtw89_regd_notifier; 3767 hw->wiphy->sar_capa = &rtw89_sar_capa; 3768 3769 ret = ieee80211_register_hw(hw); 3770 if (ret) { 3771 rtw89_err(rtwdev, "failed to register hw\n"); 3772 goto err_free_supported_band; 3773 } 3774 3775 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 3776 if (ret) { 3777 rtw89_err(rtwdev, "failed to init regd\n"); 3778 goto err_unregister_hw; 3779 } 3780 3781 return 0; 3782 3783 err_unregister_hw: 3784 ieee80211_unregister_hw(hw); 3785 err_free_supported_band: 3786 rtw89_core_clr_supported_band(rtwdev); 3787 3788 return ret; 3789 } 3790 3791 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 3792 { 3793 struct ieee80211_hw *hw = rtwdev->hw; 3794 3795 ieee80211_unregister_hw(hw); 3796 rtw89_core_clr_supported_band(rtwdev); 3797 } 3798 3799 int rtw89_core_register(struct rtw89_dev *rtwdev) 3800 { 3801 int ret; 3802 3803 ret = rtw89_core_register_hw(rtwdev); 3804 if (ret) { 3805 rtw89_err(rtwdev, "failed to register core hw\n"); 3806 return ret; 3807 } 3808 3809 rtw89_debugfs_init(rtwdev); 3810 3811 return 0; 3812 } 3813 EXPORT_SYMBOL(rtw89_core_register); 3814 3815 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 3816 { 3817 rtw89_core_unregister_hw(rtwdev); 3818 } 3819 EXPORT_SYMBOL(rtw89_core_unregister); 3820 3821 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 3822 u32 bus_data_size, 3823 const struct rtw89_chip_info *chip) 3824 { 3825 struct rtw89_fw_info early_fw = {}; 3826 const struct firmware *firmware; 3827 struct ieee80211_hw *hw; 3828 struct rtw89_dev *rtwdev; 3829 struct ieee80211_ops *ops; 3830 u32 driver_data_size; 3831 int fw_format = -1; 3832 bool no_chanctx; 3833 3834 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 3835 3836 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 3837 if (!ops) 3838 goto err; 3839 3840 no_chanctx = chip->support_chanctx_num == 0 || 3841 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 3842 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 3843 3844 if (no_chanctx) { 3845 ops->add_chanctx = NULL; 3846 ops->remove_chanctx = NULL; 3847 ops->change_chanctx = NULL; 3848 ops->assign_vif_chanctx = NULL; 3849 ops->unassign_vif_chanctx = NULL; 3850 ops->remain_on_channel = NULL; 3851 ops->cancel_remain_on_channel = NULL; 3852 } 3853 3854 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 3855 hw = ieee80211_alloc_hw(driver_data_size, ops); 3856 if (!hw) 3857 goto err; 3858 3859 hw->wiphy->iface_combinations = rtw89_iface_combs; 3860 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 3861 3862 rtwdev = hw->priv; 3863 rtwdev->hw = hw; 3864 rtwdev->dev = device; 3865 rtwdev->ops = ops; 3866 rtwdev->chip = chip; 3867 rtwdev->fw.req.firmware = firmware; 3868 rtwdev->fw.fw_format = fw_format; 3869 3870 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 3871 no_chanctx ? "without" : "with"); 3872 3873 return rtwdev; 3874 3875 err: 3876 kfree(ops); 3877 release_firmware(firmware); 3878 return NULL; 3879 } 3880 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 3881 3882 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 3883 { 3884 kfree(rtwdev->ops); 3885 release_firmware(rtwdev->fw.req.firmware); 3886 ieee80211_free_hw(rtwdev->hw); 3887 } 3888 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 3889 3890 MODULE_AUTHOR("Realtek Corporation"); 3891 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 3892 MODULE_LICENSE("Dual BSD/GPL"); 3893