1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822c.h" 13 #include "rtw8822c_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "util.h" 18 #include "bf.h" 19 #include "efuse.h" 20 21 #define IQK_DONE_8822C 0xaa 22 23 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 24 u8 rx_path, bool is_tx2_path); 25 26 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 27 struct rtw8822c_efuse *map) 28 { 29 ether_addr_copy(efuse->addr, map->e.mac_addr); 30 } 31 32 static void rtw8822cu_efuse_parsing(struct rtw_efuse *efuse, 33 struct rtw8822c_efuse *map) 34 { 35 ether_addr_copy(efuse->addr, map->u.mac_addr); 36 } 37 38 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 39 { 40 struct rtw_efuse *efuse = &rtwdev->efuse; 41 struct rtw8822c_efuse *map; 42 int i; 43 44 map = (struct rtw8822c_efuse *)log_map; 45 46 efuse->rfe_option = map->rfe_option; 47 efuse->rf_board_option = map->rf_board_option; 48 efuse->crystal_cap = map->xtal_k & XCAP_MASK; 49 efuse->channel_plan = map->channel_plan; 50 efuse->country_code[0] = map->country_code[0]; 51 efuse->country_code[1] = map->country_code[1]; 52 efuse->bt_setting = map->rf_bt_setting; 53 efuse->regd = map->rf_board_option & 0x7; 54 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 55 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 56 efuse->thermal_meter_k = 57 (map->path_a_thermal + map->path_b_thermal) >> 1; 58 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 59 60 for (i = 0; i < 4; i++) 61 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 62 63 switch (rtw_hci_type(rtwdev)) { 64 case RTW_HCI_TYPE_PCIE: 65 rtw8822ce_efuse_parsing(efuse, map); 66 break; 67 case RTW_HCI_TYPE_USB: 68 rtw8822cu_efuse_parsing(efuse, map); 69 break; 70 default: 71 /* unsupported now */ 72 return -ENOTSUPP; 73 } 74 75 return 0; 76 } 77 78 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 79 { 80 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 81 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 82 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 83 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 84 85 if (pre) 86 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 87 else 88 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 89 } 90 91 static void rtw8822c_bb_reset(struct rtw_dev *rtwdev) 92 { 93 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB); 94 rtw_write16_clr(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB); 95 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB); 96 } 97 98 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 99 struct rtw_backup_info *backup, 100 struct rtw_backup_info *backup_rf) 101 { 102 u32 path, i; 103 u32 val; 104 u32 reg; 105 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 106 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 107 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 108 0x1a00, 0x1a14, 0x1d58, 0x1c38, 109 0x1e24, 0x1e28, 0x1860, 0x4160}; 110 111 for (i = 0; i < DACK_REG_8822C; i++) { 112 backup[i].len = 4; 113 backup[i].reg = addrs[i]; 114 backup[i].val = rtw_read32(rtwdev, addrs[i]); 115 } 116 117 for (path = 0; path < DACK_PATH_8822C; path++) { 118 for (i = 0; i < DACK_RF_8822C; i++) { 119 reg = rf_addr[i]; 120 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 121 backup_rf[path * i + i].reg = reg; 122 backup_rf[path * i + i].val = val; 123 } 124 } 125 } 126 127 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 128 struct rtw_backup_info *backup, 129 struct rtw_backup_info *backup_rf) 130 { 131 u32 path, i; 132 u32 val; 133 u32 reg; 134 135 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 136 137 for (path = 0; path < DACK_PATH_8822C; path++) { 138 for (i = 0; i < DACK_RF_8822C; i++) { 139 val = backup_rf[path * i + i].val; 140 reg = backup_rf[path * i + i].reg; 141 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 142 } 143 } 144 } 145 146 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 147 u32 *min, u32 *max) 148 { 149 if (value >= 0x200) { 150 if (*min >= 0x200) { 151 if (*min > value) 152 *min = value; 153 } else { 154 *min = value; 155 } 156 if (*max >= 0x200) { 157 if (*max < value) 158 *max = value; 159 } 160 } else { 161 if (*min < 0x200) { 162 if (*min > value) 163 *min = value; 164 } 165 166 if (*max >= 0x200) { 167 *max = value; 168 } else { 169 if (*max < value) 170 *max = value; 171 } 172 } 173 } 174 175 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 176 { 177 if (*v1 >= 0x200 && *v2 >= 0x200) { 178 if (*v1 > *v2) 179 swap(*v1, *v2); 180 } else if (*v1 < 0x200 && *v2 < 0x200) { 181 if (*v1 > *v2) 182 swap(*v1, *v2); 183 } else if (*v1 < 0x200 && *v2 >= 0x200) { 184 swap(*v1, *v2); 185 } 186 } 187 188 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 189 { 190 u32 i, j; 191 192 for (i = 0; i < DACK_SN_8822C - 1; i++) { 193 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 194 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 195 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 196 } 197 } 198 } 199 200 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 201 { 202 u32 p, m, t, i; 203 204 m = 0; 205 p = 0; 206 for (i = 10; i < DACK_SN_8822C - 10; i++) { 207 if (vec[i] > 0x200) 208 m = (0x400 - vec[i]) + m; 209 else 210 p = vec[i] + p; 211 } 212 213 if (p > m) { 214 t = p - m; 215 t = t / (DACK_SN_8822C - 20); 216 } else { 217 t = m - p; 218 t = t / (DACK_SN_8822C - 20); 219 if (t != 0x0) 220 t = 0x400 - t; 221 } 222 223 *val = t; 224 } 225 226 static u32 rtw8822c_get_path_write_addr(u8 path) 227 { 228 u32 base_addr; 229 230 switch (path) { 231 case RF_PATH_A: 232 base_addr = 0x1800; 233 break; 234 case RF_PATH_B: 235 base_addr = 0x4100; 236 break; 237 default: 238 WARN_ON(1); 239 return -1; 240 } 241 242 return base_addr; 243 } 244 245 static u32 rtw8822c_get_path_read_addr(u8 path) 246 { 247 u32 base_addr; 248 249 switch (path) { 250 case RF_PATH_A: 251 base_addr = 0x2800; 252 break; 253 case RF_PATH_B: 254 base_addr = 0x4500; 255 break; 256 default: 257 WARN_ON(1); 258 return -1; 259 } 260 261 return base_addr; 262 } 263 264 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 265 { 266 bool ret = true; 267 268 if ((value >= 0x200 && (0x400 - value) > 0x64) || 269 (value < 0x200 && value > 0x64)) { 270 ret = false; 271 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 272 } 273 274 return ret; 275 } 276 277 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 278 { 279 u32 temp; 280 int i = 0, cnt = 0; 281 282 while (i < DACK_SN_8822C && cnt < 10000) { 283 cnt++; 284 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 285 iv[i] = (temp & 0x3ff000) >> 12; 286 qv[i] = temp & 0x3ff; 287 288 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 289 rtw8822c_dac_iq_check(rtwdev, qv[i])) 290 i++; 291 } 292 } 293 294 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 295 u32 *iv, u32 *qv, 296 u32 *i_value, u32 *q_value) 297 { 298 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 299 u32 i_delta, q_delta; 300 u32 temp; 301 int i, cnt = 0; 302 303 do { 304 i_min = iv[0]; 305 i_max = iv[0]; 306 q_min = qv[0]; 307 q_max = qv[0]; 308 for (i = 0; i < DACK_SN_8822C; i++) { 309 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 310 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 311 } 312 313 if (i_max < 0x200 && i_min < 0x200) 314 i_delta = i_max - i_min; 315 else if (i_max >= 0x200 && i_min >= 0x200) 316 i_delta = i_max - i_min; 317 else 318 i_delta = i_max + (0x400 - i_min); 319 320 if (q_max < 0x200 && q_min < 0x200) 321 q_delta = q_max - q_min; 322 else if (q_max >= 0x200 && q_min >= 0x200) 323 q_delta = q_max - q_min; 324 else 325 q_delta = q_max + (0x400 - q_min); 326 327 rtw_dbg(rtwdev, RTW_DBG_RFK, 328 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 329 i_min, i_max, i_delta); 330 rtw_dbg(rtwdev, RTW_DBG_RFK, 331 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 332 q_min, q_max, q_delta); 333 334 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 335 336 if (i_delta > 5 || q_delta > 5) { 337 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 338 iv[0] = (temp & 0x3ff000) >> 12; 339 qv[0] = temp & 0x3ff; 340 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 341 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 342 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 343 } else { 344 break; 345 } 346 } while (cnt++ < 100); 347 348 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 349 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 350 } 351 352 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 353 u32 *i_value, u32 *q_value) 354 { 355 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 356 u32 rf_a, rf_b; 357 358 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 359 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 360 361 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 362 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 363 364 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 365 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 366 } 367 368 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 369 { 370 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 371 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 372 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 373 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 374 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 375 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 376 rtw_write32(rtwdev, 0x1b00, 0x00000008); 377 rtw_write8(rtwdev, 0x1bcc, 0x3f); 378 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 379 rtw_write8(rtwdev, 0x1bcc, 0x3f); 380 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 381 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 382 } 383 384 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 385 u8 path, u32 *adc_ic, u32 *adc_qc) 386 { 387 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 388 u32 ic = 0, qc = 0, temp = 0; 389 u32 base_addr; 390 u32 path_sel; 391 int i; 392 393 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 394 395 base_addr = rtw8822c_get_path_write_addr(path); 396 switch (path) { 397 case RF_PATH_A: 398 path_sel = 0xa0000; 399 break; 400 case RF_PATH_B: 401 path_sel = 0x80000; 402 break; 403 default: 404 WARN_ON(1); 405 return; 406 } 407 408 /* ADCK step1 */ 409 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 410 if (path == RF_PATH_B) 411 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 412 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 413 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 414 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 415 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 416 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 417 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 418 for (i = 0; i < 10; i++) { 419 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 420 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 421 rtw_write32(rtwdev, 0x1c24, 0x00010002); 422 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 423 rtw_dbg(rtwdev, RTW_DBG_RFK, 424 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 425 426 /* compensation value */ 427 if (ic != 0x0) { 428 ic = 0x400 - ic; 429 *adc_ic = ic; 430 } 431 if (qc != 0x0) { 432 qc = 0x400 - qc; 433 *adc_qc = qc; 434 } 435 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 436 rtw_write32(rtwdev, base_addr + 0x68, temp); 437 dm_info->dack_adck[path] = temp; 438 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 439 base_addr + 0x68, temp); 440 /* check ADC DC offset */ 441 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 442 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 443 rtw_dbg(rtwdev, RTW_DBG_RFK, 444 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 445 if (ic >= 0x200) 446 ic = 0x400 - ic; 447 if (qc >= 0x200) 448 qc = 0x400 - qc; 449 if (ic < 5 && qc < 5) 450 break; 451 } 452 453 /* ADCK step2 */ 454 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 455 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 456 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 457 458 /* release pull low switch on IQ path */ 459 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 460 } 461 462 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 463 { 464 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 465 u32 base_addr; 466 u32 read_addr; 467 468 base_addr = rtw8822c_get_path_write_addr(path); 469 read_addr = rtw8822c_get_path_read_addr(path); 470 471 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 472 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 473 if (path == RF_PATH_A) { 474 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 475 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 476 } 477 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 478 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 479 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 480 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 481 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 482 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 483 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 484 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 485 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 486 mdelay(2); 487 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 488 mdelay(2); 489 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 490 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 491 mdelay(1); 492 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 493 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 494 mdelay(20); 495 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 496 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 497 rtw_err(rtwdev, "failed to wait for dack ready\n"); 498 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 499 mdelay(1); 500 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 501 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 502 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 503 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 504 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 505 } 506 507 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 508 u8 path, u32 *ic_out, u32 *qc_out) 509 { 510 u32 base_addr; 511 u32 ic, qc, ic_in, qc_in; 512 513 base_addr = rtw8822c_get_path_write_addr(path); 514 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 515 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 516 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 517 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 518 519 rtw_write32(rtwdev, 0x1b00, 0x00000008); 520 rtw_write8(rtwdev, 0x1bcc, 0x03f); 521 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 522 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 523 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 524 525 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 526 ic = ic_in; 527 qc = qc_in; 528 529 /* compensation value */ 530 if (ic != 0x0) 531 ic = 0x400 - ic; 532 if (qc != 0x0) 533 qc = 0x400 - qc; 534 if (ic < 0x300) { 535 ic = ic * 2 * 6 / 5; 536 ic = ic + 0x80; 537 } else { 538 ic = (0x400 - ic) * 2 * 6 / 5; 539 ic = 0x7f - ic; 540 } 541 if (qc < 0x300) { 542 qc = qc * 2 * 6 / 5; 543 qc = qc + 0x80; 544 } else { 545 qc = (0x400 - qc) * 2 * 6 / 5; 546 qc = 0x7f - qc; 547 } 548 549 *ic_out = ic; 550 *qc_out = qc; 551 552 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 553 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 554 } 555 556 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 557 u32 adc_ic, u32 adc_qc, 558 u32 *ic_in, u32 *qc_in, 559 u32 *i_out, u32 *q_out) 560 { 561 u32 base_addr; 562 u32 read_addr; 563 u32 ic, qc; 564 u32 temp; 565 566 base_addr = rtw8822c_get_path_write_addr(path); 567 read_addr = rtw8822c_get_path_read_addr(path); 568 ic = *ic_in; 569 qc = *qc_in; 570 571 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 572 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 573 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 574 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 575 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 576 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 577 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 578 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 579 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 580 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 581 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 582 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 583 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 584 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 585 mdelay(2); 586 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 587 mdelay(2); 588 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 589 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 590 mdelay(1); 591 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 592 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 593 mdelay(20); 594 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 595 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 596 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 597 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 598 mdelay(1); 599 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 600 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 601 602 /* check DAC DC offset */ 603 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 604 rtw_write32(rtwdev, base_addr + 0x68, temp); 605 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 606 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 607 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 608 if (ic >= 0x10) 609 ic = ic - 0x10; 610 else 611 ic = 0x400 - (0x10 - ic); 612 613 if (qc >= 0x10) 614 qc = qc - 0x10; 615 else 616 qc = 0x400 - (0x10 - qc); 617 618 *i_out = ic; 619 *q_out = qc; 620 621 if (ic >= 0x200) 622 ic = 0x400 - ic; 623 if (qc >= 0x200) 624 qc = 0x400 - qc; 625 626 *ic_in = ic; 627 *qc_in = qc; 628 629 rtw_dbg(rtwdev, RTW_DBG_RFK, 630 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 631 } 632 633 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 634 { 635 u32 base_addr = rtw8822c_get_path_write_addr(path); 636 637 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 638 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 639 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 640 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 641 } 642 643 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 644 u8 path, u8 vec, u32 w_addr, u32 r_addr) 645 { 646 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 647 u16 val; 648 u32 i; 649 650 if (WARN_ON(vec >= 2)) 651 return; 652 653 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 654 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 655 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 656 dm_info->dack_msbk[path][vec][i] = val; 657 } 658 } 659 660 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 661 { 662 u32 w_off = 0x1c; 663 u32 r_off = 0x2c; 664 u32 w_addr, r_addr; 665 666 if (WARN_ON(path >= 2)) 667 return; 668 669 /* backup I vector */ 670 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 671 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 672 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 673 674 /* backup Q vector */ 675 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 676 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 677 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 678 } 679 680 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 681 { 682 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 683 u8 val; 684 685 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 686 dm_info->dack_dck[RF_PATH_A][0][0] = val; 687 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 688 dm_info->dack_dck[RF_PATH_A][0][1] = val; 689 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 690 dm_info->dack_dck[RF_PATH_A][1][0] = val; 691 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 692 dm_info->dack_dck[RF_PATH_A][1][1] = val; 693 694 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 695 dm_info->dack_dck[RF_PATH_B][0][0] = val; 696 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 697 dm_info->dack_dck[RF_PATH_B][1][0] = val; 698 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 699 dm_info->dack_dck[RF_PATH_B][0][1] = val; 700 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 701 dm_info->dack_dck[RF_PATH_B][1][1] = val; 702 } 703 704 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 705 { 706 u32 temp[3]; 707 708 temp[0] = rtw_read32(rtwdev, 0x1860); 709 temp[1] = rtw_read32(rtwdev, 0x4160); 710 temp[2] = rtw_read32(rtwdev, 0x9b4); 711 712 /* set clock */ 713 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 714 715 /* backup path-A I/Q */ 716 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 717 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 718 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 719 720 /* backup path-B I/Q */ 721 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 722 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 723 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 724 725 rtw8822c_dac_cal_backup_dck(rtwdev); 726 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 727 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 728 729 rtw_write32(rtwdev, 0x1860, temp[0]); 730 rtw_write32(rtwdev, 0x4160, temp[1]); 731 rtw_write32(rtwdev, 0x9b4, temp[2]); 732 } 733 734 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 735 { 736 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 737 u8 val; 738 739 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 740 val = dm_info->dack_dck[RF_PATH_A][0][0]; 741 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 742 val = dm_info->dack_dck[RF_PATH_A][0][1]; 743 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 744 745 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 746 val = dm_info->dack_dck[RF_PATH_A][1][0]; 747 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 748 val = dm_info->dack_dck[RF_PATH_A][1][1]; 749 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 750 751 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 752 val = dm_info->dack_dck[RF_PATH_B][0][0]; 753 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 754 val = dm_info->dack_dck[RF_PATH_B][0][1]; 755 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 756 757 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 758 val = dm_info->dack_dck[RF_PATH_B][1][0]; 759 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 760 val = dm_info->dack_dck[RF_PATH_B][1][1]; 761 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 762 } 763 764 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 765 { 766 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 767 768 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 769 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 770 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 771 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 772 773 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 774 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 775 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 776 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 777 778 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 779 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 780 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 781 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 782 783 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 784 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 785 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 786 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 787 788 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 789 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 790 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 791 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 792 793 rtw8822c_dac_cal_restore_dck(rtwdev); 794 795 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 796 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 797 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 798 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 799 800 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 801 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 802 803 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 804 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 805 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 806 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 807 808 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 809 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 810 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 811 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 812 813 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 814 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 815 } 816 817 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 818 u32 target_addr, u32 toggle_addr) 819 { 820 u32 cnt = 0; 821 822 do { 823 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 824 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 825 826 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 827 return true; 828 829 } while (cnt++ < 100); 830 831 return false; 832 } 833 834 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 835 { 836 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 837 u32 w_off = 0x1c; 838 u32 r_off = 0x2c; 839 u32 w_i, r_i, w_q, r_q; 840 u32 value; 841 u32 i; 842 843 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 844 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 845 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 846 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 847 848 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 849 return false; 850 851 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 852 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 853 value = dm_info->dack_msbk[path][0][i]; 854 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 855 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 856 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 857 } 858 859 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 860 861 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 862 return false; 863 864 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 865 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 866 value = dm_info->dack_msbk[path][1][i]; 867 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 868 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 869 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 870 } 871 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 872 873 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 874 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 875 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 876 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 877 878 return true; 879 } 880 881 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 882 { 883 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 884 return false; 885 886 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 887 return false; 888 889 return true; 890 } 891 892 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 893 { 894 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 895 u32 temp[3]; 896 897 /* sample the first element for both path's IQ vector */ 898 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 899 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 900 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 901 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 902 return false; 903 904 temp[0] = rtw_read32(rtwdev, 0x1860); 905 temp[1] = rtw_read32(rtwdev, 0x4160); 906 temp[2] = rtw_read32(rtwdev, 0x9b4); 907 908 rtw8822c_dac_cal_restore_prepare(rtwdev); 909 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 910 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 911 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 912 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 913 return false; 914 915 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 916 rtw_err(rtwdev, "failed to restore dack vectors\n"); 917 return false; 918 } 919 920 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 921 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 922 rtw_write32(rtwdev, 0x1860, temp[0]); 923 rtw_write32(rtwdev, 0x4160, temp[1]); 924 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 925 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 926 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 927 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 928 rtw_write32(rtwdev, 0x9b4, temp[2]); 929 930 return true; 931 } 932 933 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 934 { 935 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 936 struct rtw_backup_info backup[DACK_REG_8822C]; 937 u32 ic = 0, qc = 0, i; 938 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 939 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 940 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 941 942 if (rtw8822c_dac_cal_restore(rtwdev)) 943 return; 944 945 /* not able to restore, do it */ 946 947 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 948 949 rtw8822c_dac_bb_setting(rtwdev); 950 951 /* path-A */ 952 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 953 for (i = 0; i < 10; i++) { 954 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 955 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 956 ic_a = ic; 957 qc_a = qc; 958 959 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 960 &ic, &qc, &i_a, &q_a); 961 962 if (ic < 5 && qc < 5) 963 break; 964 } 965 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 966 967 /* path-B */ 968 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 969 for (i = 0; i < 10; i++) { 970 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 971 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 972 ic_b = ic; 973 qc_b = qc; 974 975 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 976 &ic, &qc, &i_b, &q_b); 977 978 if (ic < 5 && qc < 5) 979 break; 980 } 981 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 982 983 rtw_write32(rtwdev, 0x1b00, 0x00000008); 984 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 985 rtw_write8(rtwdev, 0x1bcc, 0x0); 986 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 987 rtw_write8(rtwdev, 0x1bcc, 0x0); 988 989 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 990 991 /* backup results to restore, saving a lot of time */ 992 rtw8822c_dac_cal_backup(rtwdev); 993 994 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 995 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 996 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 997 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 998 } 999 1000 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 1001 { 1002 u8 x2k_busy; 1003 1004 mdelay(1); 1005 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 1006 if (x2k_busy == 1) { 1007 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 1008 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 1009 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 1010 mdelay(1); 1011 } 1012 } 1013 1014 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8]) 1015 { 1016 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \ 1017 do { \ 1018 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ 1019 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ 1020 bb_gain[_path][_idx]); \ 1021 } while (0) 1022 u8 path; 1023 1024 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1025 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); 1026 RF_SET_POWER_TRIM(path, 0x0, 0); 1027 RF_SET_POWER_TRIM(path, 0x1, 1); 1028 RF_SET_POWER_TRIM(path, 0x2, 2); 1029 RF_SET_POWER_TRIM(path, 0x3, 2); 1030 RF_SET_POWER_TRIM(path, 0x4, 3); 1031 RF_SET_POWER_TRIM(path, 0x5, 4); 1032 RF_SET_POWER_TRIM(path, 0x6, 5); 1033 RF_SET_POWER_TRIM(path, 0x7, 6); 1034 RF_SET_POWER_TRIM(path, 0x8, 7); 1035 RF_SET_POWER_TRIM(path, 0x9, 3); 1036 RF_SET_POWER_TRIM(path, 0xa, 4); 1037 RF_SET_POWER_TRIM(path, 0xb, 5); 1038 RF_SET_POWER_TRIM(path, 0xc, 6); 1039 RF_SET_POWER_TRIM(path, 0xd, 7); 1040 RF_SET_POWER_TRIM(path, 0xe, 7); 1041 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); 1042 } 1043 #undef RF_SET_POWER_TRIM 1044 } 1045 1046 static void rtw8822c_power_trim(struct rtw_dev *rtwdev) 1047 { 1048 u8 pg_pwr = 0xff, i, path, idx; 1049 s8 bb_gain[2][8] = {}; 1050 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB}; 1051 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA, 1052 PPG_5GM2_TXA, PPG_5GH1_TXA}, 1053 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB, 1054 PPG_5GM2_TXB, PPG_5GH1_TXB} }; 1055 bool set = false; 1056 1057 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { 1058 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr); 1059 if (pg_pwr == EFUSE_READ_FAIL) 1060 continue; 1061 set = true; 1062 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr); 1063 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr); 1064 } 1065 1066 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { 1067 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1068 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i], 1069 &pg_pwr); 1070 if (pg_pwr == EFUSE_READ_FAIL) 1071 continue; 1072 set = true; 1073 idx = i + ARRAY_SIZE(rf_efuse_2g); 1074 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr); 1075 } 1076 } 1077 if (set) 1078 rtw8822c_set_power_trim(rtwdev, bb_gain); 1079 1080 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1081 } 1082 1083 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev) 1084 { 1085 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B}; 1086 u8 pg_therm = 0xff, thermal[2] = {0}, path; 1087 1088 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1089 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm); 1090 if (pg_therm == EFUSE_READ_FAIL) 1091 return; 1092 /* Efuse value of BIT(0) shall be move to BIT(3), and the value 1093 * of BIT(1) to BIT(3) should be right shifted 1 bit. 1094 */ 1095 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm); 1096 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); 1097 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); 1098 } 1099 } 1100 1101 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 1102 { 1103 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB}; 1104 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB}; 1105 u8 pg_pa_bias = 0xff, path; 1106 1107 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1108 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path], 1109 &pg_pa_bias); 1110 if (pg_pa_bias == EFUSE_READ_FAIL) 1111 return; 1112 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1113 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias); 1114 } 1115 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1116 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path], 1117 &pg_pa_bias); 1118 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1119 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias); 1120 } 1121 } 1122 1123 static void rtw8822c_rfk_handshake(struct rtw_dev *rtwdev, bool is_before_k) 1124 { 1125 struct rtw_dm_info *dm = &rtwdev->dm_info; 1126 u8 u1b_tmp; 1127 u8 u4b_tmp; 1128 int ret; 1129 1130 if (is_before_k) { 1131 rtw_dbg(rtwdev, RTW_DBG_RFK, 1132 "[RFK] WiFi / BT RFK handshake start!!\n"); 1133 1134 if (!dm->is_bt_iqk_timeout) { 1135 ret = read_poll_timeout(rtw_read32_mask, u4b_tmp, 1136 u4b_tmp == 0, 20, 600000, false, 1137 rtwdev, REG_PMC_DBG_CTRL1, 1138 BITS_PMC_BT_IQK_STS); 1139 if (ret) { 1140 rtw_dbg(rtwdev, RTW_DBG_RFK, 1141 "[RFK] Wait BT IQK finish timeout!!\n"); 1142 dm->is_bt_iqk_timeout = true; 1143 } 1144 } 1145 1146 rtw_fw_inform_rfk_status(rtwdev, true); 1147 1148 ret = read_poll_timeout(rtw_read8_mask, u1b_tmp, 1149 u1b_tmp == 1, 20, 100000, false, 1150 rtwdev, REG_ARFR4, BIT_WL_RFK); 1151 if (ret) 1152 rtw_dbg(rtwdev, RTW_DBG_RFK, 1153 "[RFK] Send WiFi RFK start H2C cmd FAIL!!\n"); 1154 } else { 1155 rtw_fw_inform_rfk_status(rtwdev, false); 1156 ret = read_poll_timeout(rtw_read8_mask, u1b_tmp, 1157 u1b_tmp == 1, 20, 100000, false, 1158 rtwdev, REG_ARFR4, 1159 BIT_WL_RFK); 1160 if (ret) 1161 rtw_dbg(rtwdev, RTW_DBG_RFK, 1162 "[RFK] Send WiFi RFK finish H2C cmd FAIL!!\n"); 1163 1164 rtw_dbg(rtwdev, RTW_DBG_RFK, 1165 "[RFK] WiFi / BT RFK handshake finish!!\n"); 1166 } 1167 } 1168 1169 static void rtw8822c_rfk_power_save(struct rtw_dev *rtwdev, 1170 bool is_power_save) 1171 { 1172 u8 path; 1173 1174 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1175 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1176 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_PS_EN, 1177 is_power_save ? 0 : 1); 1178 } 1179 } 1180 1181 static void rtw8822c_txgapk_backup_bb_reg(struct rtw_dev *rtwdev, const u32 reg[], 1182 u32 reg_backup[], u32 reg_num) 1183 { 1184 u32 i; 1185 1186 for (i = 0; i < reg_num; i++) { 1187 reg_backup[i] = rtw_read32(rtwdev, reg[i]); 1188 1189 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n", 1190 reg[i], reg_backup[i]); 1191 } 1192 } 1193 1194 static void rtw8822c_txgapk_reload_bb_reg(struct rtw_dev *rtwdev, 1195 const u32 reg[], u32 reg_backup[], 1196 u32 reg_num) 1197 { 1198 u32 i; 1199 1200 for (i = 0; i < reg_num; i++) { 1201 rtw_write32(rtwdev, reg[i], reg_backup[i]); 1202 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n", 1203 reg[i], reg_backup[i]); 1204 } 1205 } 1206 1207 static bool check_rf_status(struct rtw_dev *rtwdev, u8 status) 1208 { 1209 u8 reg_rf0_a, reg_rf0_b; 1210 1211 reg_rf0_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 1212 RF_MODE_TRXAGC, BIT_RF_MODE); 1213 reg_rf0_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 1214 RF_MODE_TRXAGC, BIT_RF_MODE); 1215 1216 if (reg_rf0_a == status || reg_rf0_b == status) 1217 return false; 1218 1219 return true; 1220 } 1221 1222 static void rtw8822c_txgapk_tx_pause(struct rtw_dev *rtwdev) 1223 { 1224 bool status; 1225 int ret; 1226 1227 rtw_write8(rtwdev, REG_TXPAUSE, BIT_AC_QUEUE); 1228 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2); 1229 1230 ret = read_poll_timeout_atomic(check_rf_status, status, status, 1231 2, 5000, false, rtwdev, 2); 1232 if (ret) 1233 rtw_warn(rtwdev, "failed to pause TX\n"); 1234 1235 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Tx pause!!\n"); 1236 } 1237 1238 static void rtw8822c_txgapk_bb_dpk(struct rtw_dev *rtwdev, u8 path) 1239 { 1240 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1241 1242 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1); 1243 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, 1244 BIT_IQK_DPK_CLOCK_SRC, 0x1); 1245 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, 1246 BIT_IQK_DPK_RESET_SRC, 0x1); 1247 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1); 1248 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0); 1249 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff); 1250 1251 if (path == RF_PATH_A) { 1252 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A, 1253 BIT_RFTXEN_GCK_FORCE_ON, 0x1); 1254 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1); 1255 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A, 1256 BIT_TX_SCALE_0DB, 0x1); 1257 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0); 1258 } else if (path == RF_PATH_B) { 1259 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B, 1260 BIT_RFTXEN_GCK_FORCE_ON, 0x1); 1261 rtw_write32_mask(rtwdev, REG_3WIRE2, 1262 BIT_DIS_SHARERX_TXGAT, 0x1); 1263 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B, 1264 BIT_TX_SCALE_0DB, 0x1); 1265 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0); 1266 } 1267 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2); 1268 } 1269 1270 static void rtw8822c_txgapk_afe_dpk(struct rtw_dev *rtwdev, u8 path) 1271 { 1272 u32 reg; 1273 1274 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1275 1276 if (path == RF_PATH_A) { 1277 reg = REG_ANAPAR_A; 1278 } else if (path == RF_PATH_B) { 1279 reg = REG_ANAPAR_B; 1280 } else { 1281 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path); 1282 return; 1283 } 1284 1285 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, MASKDWORD); 1286 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); 1287 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); 1288 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001); 1289 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001); 1290 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001); 1291 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001); 1292 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001); 1293 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001); 1294 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001); 1295 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001); 1296 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001); 1297 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001); 1298 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001); 1299 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001); 1300 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001); 1301 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001); 1302 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); 1303 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); 1304 } 1305 1306 static void rtw8822c_txgapk_afe_dpk_restore(struct rtw_dev *rtwdev, u8 path) 1307 { 1308 u32 reg; 1309 1310 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1311 1312 if (path == RF_PATH_A) { 1313 reg = REG_ANAPAR_A; 1314 } else if (path == RF_PATH_B) { 1315 reg = REG_ANAPAR_B; 1316 } else { 1317 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path); 1318 return; 1319 } 1320 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e); 1321 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041); 1322 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041); 1323 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041); 1324 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041); 1325 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041); 1326 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041); 1327 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041); 1328 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041); 1329 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041); 1330 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041); 1331 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041); 1332 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041); 1333 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041); 1334 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041); 1335 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041); 1336 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041); 1337 } 1338 1339 static void rtw8822c_txgapk_bb_dpk_restore(struct rtw_dev *rtwdev, u8 path) 1340 { 1341 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1342 1343 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0); 1344 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0); 1345 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0); 1346 1347 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); 1348 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1349 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1350 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); 1351 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1); 1352 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1353 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1354 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); 1355 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); 1356 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0); 1357 1358 if (path == RF_PATH_A) { 1359 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A, 1360 BIT_RFTXEN_GCK_FORCE_ON, 0x0); 1361 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0); 1362 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A, 1363 BIT_TX_SCALE_0DB, 0x0); 1364 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3); 1365 } else if (path == RF_PATH_B) { 1366 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B, 1367 BIT_RFTXEN_GCK_FORCE_ON, 0x0); 1368 rtw_write32_mask(rtwdev, REG_3WIRE2, 1369 BIT_DIS_SHARERX_TXGAT, 0x0); 1370 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B, 1371 BIT_TX_SCALE_0DB, 0x0); 1372 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3); 1373 } 1374 1375 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0); 1376 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5); 1377 } 1378 1379 static bool _rtw8822c_txgapk_gain_valid(struct rtw_dev *rtwdev, u32 gain) 1380 { 1381 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) && 1382 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe)) 1383 return true; 1384 1385 return false; 1386 } 1387 1388 static void _rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev, 1389 u8 band, u8 path) 1390 { 1391 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1392 u32 v, tmp_3f = 0; 1393 u8 gain, check_txgain; 1394 1395 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1396 1397 switch (band) { 1398 case RF_BAND_2G_OFDM: 1399 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); 1400 break; 1401 case RF_BAND_5G_L: 1402 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); 1403 break; 1404 case RF_BAND_5G_M: 1405 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); 1406 break; 1407 case RF_BAND_5G_H: 1408 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); 1409 break; 1410 default: 1411 break; 1412 } 1413 1414 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88); 1415 1416 check_txgain = 0; 1417 for (gain = 0; gain < RF_GAIN_NUM; gain++) { 1418 v = txgapk->rf3f_bp[band][gain][path]; 1419 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) { 1420 if (!check_txgain) { 1421 tmp_3f = txgapk->rf3f_bp[band][gain][path]; 1422 check_txgain = 1; 1423 } 1424 rtw_dbg(rtwdev, RTW_DBG_RFK, 1425 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", 1426 txgapk->rf3f_bp[band][gain][path]); 1427 } else { 1428 tmp_3f = txgapk->rf3f_bp[band][gain][path]; 1429 } 1430 1431 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN, tmp_3f); 1432 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_I_GAIN, gain); 1433 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1); 1434 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0); 1435 1436 rtw_dbg(rtwdev, RTW_DBG_RFK, 1437 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n", 1438 band, tmp_3f, path); 1439 } 1440 } 1441 1442 static void rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev) 1443 { 1444 u8 path, band; 1445 1446 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n", 1447 __func__, rtwdev->dm_info.gapk.channel); 1448 1449 for (band = 0; band < RF_BAND_MAX; band++) { 1450 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1451 _rtw8822c_txgapk_write_gain_bb_table(rtwdev, 1452 band, path); 1453 } 1454 } 1455 } 1456 1457 static void rtw8822c_txgapk_read_offset(struct rtw_dev *rtwdev, u8 path) 1458 { 1459 static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a}; 1460 static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b}; 1461 static const u32 set_pi[2] = {REG_RSV_CTRL, REG_WLRF1}; 1462 static const u32 path_setting[2] = {REG_ORITXCODE, REG_ORITXCODE2}; 1463 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1464 u8 channel = txgapk->channel; 1465 u32 val; 1466 int i; 1467 1468 if (path >= ARRAY_SIZE(cfg1_1b00) || 1469 path >= ARRAY_SIZE(cfg2_1b00) || 1470 path >= ARRAY_SIZE(set_pi) || 1471 path >= ARRAY_SIZE(path_setting)) { 1472 rtw_warn(rtwdev, "[TXGAPK] wrong path %d\n", path); 1473 return; 1474 } 1475 1476 rtw_write32_mask(rtwdev, REG_ANTMAP0, BIT_ANT_PATH, path + 1); 1477 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000); 1478 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3); 1479 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312); 1480 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1); 1481 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0); 1482 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1); 1483 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820); 1484 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1485 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); 1486 1487 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018); 1488 fsleep(1000); 1489 if (channel >= 1 && channel <= 14) 1490 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_2G_SWING); 1491 else 1492 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_5G_SWING); 1493 fsleep(1000); 1494 1495 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg1_1b00[path]); 1496 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg2_1b00[path]); 1497 1498 read_poll_timeout(rtw_read32_mask, val, 1499 val == 0x55, 1000, 100000, false, 1500 rtwdev, REG_RPT_CIP, BIT_RPT_CIP_STATUS); 1501 1502 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2); 1503 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1504 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1); 1505 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12); 1506 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3); 1507 val = rtw_read32(rtwdev, REG_STAT_RPT); 1508 1509 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); 1510 txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val); 1511 txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val); 1512 txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val); 1513 txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val); 1514 txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val); 1515 txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val); 1516 txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val); 1517 1518 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4); 1519 val = rtw_read32(rtwdev, REG_STAT_RPT); 1520 1521 txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); 1522 txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val); 1523 1524 for (i = 0; i < RF_HW_OFFSET_NUM; i++) 1525 if (txgapk->offset[i][path] & BIT(3)) 1526 txgapk->offset[i][path] = txgapk->offset[i][path] | 1527 0xf0; 1528 for (i = 0; i < RF_HW_OFFSET_NUM; i++) 1529 rtw_dbg(rtwdev, RTW_DBG_RFK, 1530 "[TXGAPK] offset %d %d path=%d\n", 1531 txgapk->offset[i][path], i, path); 1532 } 1533 1534 static void rtw8822c_txgapk_calculate_offset(struct rtw_dev *rtwdev, u8 path) 1535 { 1536 static const u32 bb_reg[] = {REG_ANTMAP0, REG_TXLGMAP, REG_TXANTSEG, 1537 REG_ORITXCODE, REG_ORITXCODE2}; 1538 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1539 u8 channel = txgapk->channel; 1540 u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0}; 1541 1542 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n", 1543 __func__, channel); 1544 1545 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg, 1546 reg_backup, ARRAY_SIZE(bb_reg)); 1547 1548 if (channel >= 1 && channel <= 14) { 1549 rtw_write32_mask(rtwdev, 1550 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1551 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1552 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); 1553 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1554 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 1555 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f); 1556 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0); 1557 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1); 1558 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f); 1559 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 1560 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 1561 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 1562 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); 1563 1564 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00); 1565 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); 1566 1567 rtw8822c_txgapk_read_offset(rtwdev, path); 1568 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n"); 1569 1570 } else { 1571 rtw_write32_mask(rtwdev, 1572 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1573 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1574 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); 1575 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1576 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 1577 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011); 1578 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3); 1579 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3); 1580 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 1581 rtw_write_rf(rtwdev, path, 1582 RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2); 1583 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12); 1584 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 1585 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 1586 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); 1587 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5); 1588 1589 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); 1590 1591 if (channel >= 36 && channel <= 64) 1592 rtw_write32_mask(rtwdev, 1593 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); 1594 else if (channel >= 100 && channel <= 144) 1595 rtw_write32_mask(rtwdev, 1596 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); 1597 else if (channel >= 149 && channel <= 177) 1598 rtw_write32_mask(rtwdev, 1599 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); 1600 1601 rtw8822c_txgapk_read_offset(rtwdev, path); 1602 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n"); 1603 } 1604 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg, 1605 reg_backup, ARRAY_SIZE(bb_reg)); 1606 } 1607 1608 static void rtw8822c_txgapk_rf_restore(struct rtw_dev *rtwdev, u8 path) 1609 { 1610 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1611 1612 if (path >= rtwdev->hal.rf_path_num) 1613 return; 1614 1615 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3); 1616 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0); 1617 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0); 1618 } 1619 1620 static u32 rtw8822c_txgapk_cal_gain(struct rtw_dev *rtwdev, u32 gain, s8 offset) 1621 { 1622 u32 gain_x2, new_gain; 1623 1624 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1625 1626 if (_rtw8822c_txgapk_gain_valid(rtwdev, gain)) { 1627 new_gain = gain; 1628 rtw_dbg(rtwdev, RTW_DBG_RFK, 1629 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n", 1630 gain, offset, new_gain); 1631 return new_gain; 1632 } 1633 1634 gain_x2 = (gain << 1) + offset; 1635 new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0); 1636 1637 rtw_dbg(rtwdev, RTW_DBG_RFK, 1638 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n", 1639 gain, offset, new_gain); 1640 1641 return new_gain; 1642 } 1643 1644 static void rtw8822c_txgapk_write_tx_gain(struct rtw_dev *rtwdev) 1645 { 1646 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1647 u32 i, j, tmp = 0x20, tmp_3f, v; 1648 s8 offset_tmp[RF_GAIN_NUM] = {0}; 1649 u8 path, band = RF_BAND_2G_OFDM, channel = txgapk->channel; 1650 1651 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1652 1653 if (channel >= 1 && channel <= 14) { 1654 tmp = 0x20; 1655 band = RF_BAND_2G_OFDM; 1656 } else if (channel >= 36 && channel <= 64) { 1657 tmp = 0x200; 1658 band = RF_BAND_5G_L; 1659 } else if (channel >= 100 && channel <= 144) { 1660 tmp = 0x280; 1661 band = RF_BAND_5G_M; 1662 } else if (channel >= 149 && channel <= 177) { 1663 tmp = 0x300; 1664 band = RF_BAND_5G_H; 1665 } else { 1666 rtw_err(rtwdev, "[TXGAPK] unknown channel %d!!\n", channel); 1667 return; 1668 } 1669 1670 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1671 for (i = 0; i < RF_GAIN_NUM; i++) { 1672 offset_tmp[i] = 0; 1673 for (j = i; j < RF_GAIN_NUM; j++) { 1674 v = txgapk->rf3f_bp[band][j][path]; 1675 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) 1676 continue; 1677 1678 offset_tmp[i] += txgapk->offset[j][path]; 1679 txgapk->fianl_offset[i][path] = offset_tmp[i]; 1680 } 1681 1682 v = txgapk->rf3f_bp[band][i][path]; 1683 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) { 1684 rtw_dbg(rtwdev, RTW_DBG_RFK, 1685 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", 1686 txgapk->rf3f_bp[band][i][path]); 1687 } else { 1688 txgapk->rf3f_fs[path][i] = offset_tmp[i]; 1689 rtw_dbg(rtwdev, RTW_DBG_RFK, 1690 "[TXGAPK] offset %d %d\n", 1691 offset_tmp[i], i); 1692 } 1693 } 1694 1695 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000); 1696 for (i = 0; i < RF_GAIN_NUM; i++) { 1697 rtw_write_rf(rtwdev, path, 1698 RF_LUTWA, RFREG_MASK, tmp + i); 1699 1700 tmp_3f = rtw8822c_txgapk_cal_gain(rtwdev, 1701 txgapk->rf3f_bp[band][i][path], 1702 offset_tmp[i]); 1703 rtw_write_rf(rtwdev, path, RF_LUTWD0, 1704 BIT_GAIN_EXT | BIT_DATA_L, tmp_3f); 1705 1706 rtw_dbg(rtwdev, RTW_DBG_RFK, 1707 "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n", 1708 tmp + i, tmp_3f); 1709 } 1710 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0); 1711 } 1712 } 1713 1714 static void rtw8822c_txgapk_save_all_tx_gain_table(struct rtw_dev *rtwdev) 1715 { 1716 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1717 static const u32 three_wire[2] = {REG_3WIRE, REG_3WIRE2}; 1718 static const u8 ch_num[RF_BAND_MAX] = {1, 1, 36, 100, 149}; 1719 static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5}; 1720 static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0}; 1721 u8 path, band, gain, rf0_idx; 1722 u32 rf18, v; 1723 1724 if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK)) 1725 return; 1726 1727 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1728 1729 if (txgapk->read_txgain == 1) { 1730 rtw_dbg(rtwdev, RTW_DBG_RFK, 1731 "[TXGAPK] Already Read txgapk->read_txgain return!!!\n"); 1732 rtw8822c_txgapk_write_gain_bb_table(rtwdev); 1733 return; 1734 } 1735 1736 for (band = 0; band < RF_BAND_MAX; band++) { 1737 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1738 rf18 = rtw_read_rf(rtwdev, path, RF_CFGCH, RFREG_MASK); 1739 1740 rtw_write32_mask(rtwdev, 1741 three_wire[path], BIT_3WIRE_EN, 0x0); 1742 rtw_write_rf(rtwdev, path, 1743 RF_CFGCH, MASKBYTE0, ch_num[band]); 1744 rtw_write_rf(rtwdev, path, 1745 RF_CFGCH, BIT_BAND, band_num[band]); 1746 rtw_write_rf(rtwdev, path, 1747 RF_BW_TRXBB, BIT_DBG_CCK_CCA, cck[band]); 1748 rtw_write_rf(rtwdev, path, 1749 RF_BW_TRXBB, BIT_TX_CCK_IND, cck[band]); 1750 gain = 0; 1751 for (rf0_idx = 1; rf0_idx < 32; rf0_idx += 3) { 1752 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, 1753 MASKBYTE0, rf0_idx); 1754 v = rtw_read_rf(rtwdev, path, 1755 RF_TX_RESULT, RFREG_MASK); 1756 txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L; 1757 1758 rtw_dbg(rtwdev, RTW_DBG_RFK, 1759 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n", 1760 txgapk->rf3f_bp[band][gain][path], 1761 band, path); 1762 gain++; 1763 } 1764 rtw_write_rf(rtwdev, path, RF_CFGCH, RFREG_MASK, rf18); 1765 rtw_write32_mask(rtwdev, 1766 three_wire[path], BIT_3WIRE_EN, 0x3); 1767 } 1768 } 1769 rtw8822c_txgapk_write_gain_bb_table(rtwdev); 1770 txgapk->read_txgain = 1; 1771 } 1772 1773 static void rtw8822c_txgapk(struct rtw_dev *rtwdev) 1774 { 1775 static const u32 bb_reg[2] = {REG_TX_PTCL_CTRL, REG_TX_FIFO}; 1776 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1777 u32 bb_reg_backup[2]; 1778 u8 path; 1779 1780 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1781 1782 rtw8822c_txgapk_save_all_tx_gain_table(rtwdev); 1783 1784 if (txgapk->read_txgain == 0) { 1785 rtw_dbg(rtwdev, RTW_DBG_RFK, 1786 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n"); 1787 return; 1788 } 1789 1790 if (rtwdev->efuse.power_track_type >= 4 && 1791 rtwdev->efuse.power_track_type <= 7) { 1792 rtw_dbg(rtwdev, RTW_DBG_RFK, 1793 "[TXGAPK] Normal Mode in TSSI mode. return!!!\n"); 1794 return; 1795 } 1796 1797 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg, 1798 bb_reg_backup, ARRAY_SIZE(bb_reg)); 1799 rtw8822c_txgapk_tx_pause(rtwdev); 1800 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1801 txgapk->channel = rtw_read_rf(rtwdev, path, 1802 RF_CFGCH, RFREG_MASK) & MASKBYTE0; 1803 rtw8822c_txgapk_bb_dpk(rtwdev, path); 1804 rtw8822c_txgapk_afe_dpk(rtwdev, path); 1805 rtw8822c_txgapk_calculate_offset(rtwdev, path); 1806 rtw8822c_txgapk_rf_restore(rtwdev, path); 1807 rtw8822c_txgapk_afe_dpk_restore(rtwdev, path); 1808 rtw8822c_txgapk_bb_dpk_restore(rtwdev, path); 1809 } 1810 rtw8822c_txgapk_write_tx_gain(rtwdev); 1811 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg, 1812 bb_reg_backup, ARRAY_SIZE(bb_reg)); 1813 } 1814 1815 static void rtw8822c_do_gapk(struct rtw_dev *rtwdev) 1816 { 1817 struct rtw_dm_info *dm = &rtwdev->dm_info; 1818 1819 if (dm->dm_flags & BIT(RTW_DM_CAP_TXGAPK)) { 1820 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] feature disable!!!\n"); 1821 return; 1822 } 1823 rtw8822c_rfk_handshake(rtwdev, true); 1824 rtw8822c_txgapk(rtwdev); 1825 rtw8822c_rfk_handshake(rtwdev, false); 1826 } 1827 1828 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1829 { 1830 rtw8822c_rf_dac_cal(rtwdev); 1831 rtw8822c_rf_x2_check(rtwdev); 1832 rtw8822c_thermal_trim(rtwdev); 1833 rtw8822c_power_trim(rtwdev); 1834 rtw8822c_pa_bias(rtwdev); 1835 } 1836 1837 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1838 { 1839 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1840 u8 path; 1841 1842 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1843 dm_info->delta_power_index[path] = 0; 1844 ewma_thermal_init(&dm_info->avg_thermal[path]); 1845 dm_info->thermal_avg[path] = 0xff; 1846 } 1847 1848 dm_info->pwr_trk_triggered = false; 1849 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1850 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k; 1851 } 1852 1853 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1854 { 1855 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1856 struct rtw_hal *hal = &rtwdev->hal; 1857 u8 crystal_cap; 1858 u8 cck_gi_u_bnd_msb = 0; 1859 u8 cck_gi_u_bnd_lsb = 0; 1860 u8 cck_gi_l_bnd_msb = 0; 1861 u8 cck_gi_l_bnd_lsb = 0; 1862 bool is_tx2_path; 1863 1864 /* power on BB/RF domain */ 1865 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1866 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1867 rtw_write8_set(rtwdev, REG_RF_CTRL, 1868 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1869 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1870 1871 /* disable low rate DPD */ 1872 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1873 1874 /* pre init before header files config */ 1875 rtw8822c_header_file_init(rtwdev, true); 1876 1877 rtw_phy_load_tables(rtwdev); 1878 1879 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1880 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1881 crystal_cap | (crystal_cap << 7)); 1882 1883 /* post init after header files config */ 1884 rtw8822c_header_file_init(rtwdev, false); 1885 1886 is_tx2_path = false; 1887 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1888 is_tx2_path); 1889 rtw_phy_init(rtwdev); 1890 1891 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1892 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1893 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1894 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1895 1896 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1897 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1898 1899 rtw8822c_rf_init(rtwdev); 1900 rtw8822c_pwrtrack_init(rtwdev); 1901 1902 rtw_bf_phy_init(rtwdev); 1903 } 1904 1905 #define WLAN_TXQ_RPT_EN 0x1F 1906 #define WLAN_SLOT_TIME 0x09 1907 #define WLAN_PIFS_TIME 0x1C 1908 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1909 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1910 #define WLAN_SIFS_CCK_TRX 0x0A 1911 #define WLAN_SIFS_OFDM_TRX 0x10 1912 #define WLAN_NAV_MAX 0xC8 1913 #define WLAN_RDG_NAV 0x05 1914 #define WLAN_TXOP_NAV 0x1B 1915 #define WLAN_CCK_RX_TSF 0x30 1916 #define WLAN_OFDM_RX_TSF 0x30 1917 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1918 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1919 #define WLAN_DRV_EARLY_INT 0x04 1920 #define WLAN_BCN_CTRL_CLT0 0x10 1921 #define WLAN_BCN_DMA_TIME 0x02 1922 #define WLAN_BCN_MAX_ERR 0xFF 1923 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1924 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1925 #define WLAN_SIFS_CCK_CTX 0x0A 1926 #define WLAN_SIFS_CCK_IRX 0x0A 1927 #define WLAN_SIFS_OFDM_CTX 0x0E 1928 #define WLAN_SIFS_OFDM_IRX 0x0E 1929 #define WLAN_EIFS_DUR_TUNE 0x40 1930 #define WLAN_EDCA_VO_PARAM 0x002FA226 1931 #define WLAN_EDCA_VI_PARAM 0x005EA328 1932 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1933 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1934 1935 #define WLAN_RX_FILTER0 0xFFFFFFFF 1936 #define WLAN_RX_FILTER2 0xFFFF 1937 #define WLAN_RCR_CFG 0xE400220E 1938 #define WLAN_RXPKT_MAX_SZ 12288 1939 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1940 1941 #define WLAN_AMPDU_MAX_TIME 0x70 1942 #define WLAN_RTS_LEN_TH 0xFF 1943 #define WLAN_RTS_TX_TIME_TH 0x08 1944 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1945 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1946 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1947 #define FAST_EDCA_VO_TH 0x06 1948 #define FAST_EDCA_VI_TH 0x06 1949 #define FAST_EDCA_BE_TH 0x06 1950 #define FAST_EDCA_BK_TH 0x06 1951 #define WLAN_BAR_RETRY_LIMIT 0x01 1952 #define WLAN_BAR_ACK_TYPE 0x05 1953 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1954 #define WLAN_RESP_TXRATE 0x84 1955 #define WLAN_ACK_TO 0x21 1956 #define WLAN_ACK_TO_CCK 0x6A 1957 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1958 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1959 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1960 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1961 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1962 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1963 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1964 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1965 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1966 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1967 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1968 #define WLAN_MULTI_ADDR 0xFFFFFFFF 1969 1970 #define WLAN_TX_FUNC_CFG1 0x30 1971 #define WLAN_TX_FUNC_CFG2 0x30 1972 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1973 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1974 #define WLAN_MAC_OPT_FUNC2 0xb0810041 1975 #define WLAN_MAC_INT_MIG_CFG 0x33330000 1976 1977 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1978 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1979 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1980 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1981 1982 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1983 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1984 1985 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1986 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1987 1988 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1989 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1990 1991 #define MAC_CLK_SPEED 80 /* 80M */ 1992 #define EFUSE_PCB_INFO_OFFSET 0xCA 1993 1994 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1995 { 1996 u8 value8; 1997 u16 value16; 1998 u32 value32; 1999 u16 pre_txcnt; 2000 2001 /* txq control */ 2002 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 2003 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 2004 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 2005 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 2006 /* sifs control */ 2007 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 2008 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 2009 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 2010 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 2011 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 2012 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 2013 /* rate fallback control */ 2014 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 2015 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 2016 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 2017 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 2018 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 2019 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 2020 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 2021 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 2022 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 2023 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 2024 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 2025 /* protocol configuration */ 2026 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 2027 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 2028 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 2029 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 2030 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 2031 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 2032 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 2033 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 2034 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 2035 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 2036 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 2037 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 2038 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 2039 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 2040 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 2041 /* close BA parser */ 2042 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 2043 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 2044 2045 /* EDCA configuration */ 2046 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 2047 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 2048 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 2049 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 2050 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 2051 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 2052 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 2053 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 2054 BIT_DIS_STBC_CFE) >> 8); 2055 2056 /* MAC clock configuration */ 2057 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 2058 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 2059 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 2060 2061 rtw_write8_set(rtwdev, REG_MISC_CTRL, 2062 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 2063 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 2064 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 2065 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 2066 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 2067 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 2068 /* Set beacon cotnrol - enable TSF and other related functions */ 2069 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2070 /* Set send beacon related registers */ 2071 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 2072 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 2073 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 2074 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 2075 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 2076 2077 /* WMAC configuration */ 2078 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 2079 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 2080 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 2081 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 2082 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 2083 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 2084 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 2085 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 2086 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 2087 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 2088 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 2089 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 2090 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 2091 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 2092 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 2093 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 2094 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 2095 2096 /* init low power */ 2097 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 2098 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 2099 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 2100 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 2101 value16 = 0; 2102 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 2103 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 2104 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 2105 | BIT_RXPSF_OFDMRST; 2106 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 2107 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 2108 /* rx ignore configuration */ 2109 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 2110 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 2111 BIT_RXPSF_CONT_ERRCHKEN); 2112 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 2113 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 2114 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 2115 BIT_DIS_CHK_VHTSIGB_CRC); 2116 2117 /* Interrupt migration configuration */ 2118 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 2119 2120 return 0; 2121 } 2122 2123 #define FWCD_SIZE_REG_8822C 0x2000 2124 #define FWCD_SIZE_DMEM_8822C 0x10000 2125 #define FWCD_SIZE_IMEM_8822C 0x10000 2126 #define FWCD_SIZE_EMEM_8822C 0x20000 2127 #define FWCD_SIZE_ROM_8822C 0x10000 2128 2129 static const u32 __fwcd_segs_8822c[] = { 2130 FWCD_SIZE_REG_8822C, 2131 FWCD_SIZE_DMEM_8822C, 2132 FWCD_SIZE_IMEM_8822C, 2133 FWCD_SIZE_EMEM_8822C, 2134 FWCD_SIZE_ROM_8822C, 2135 }; 2136 2137 static const struct rtw_fwcd_segs rtw8822c_fwcd_segs = { 2138 .segs = __fwcd_segs_8822c, 2139 .num = ARRAY_SIZE(__fwcd_segs_8822c), 2140 }; 2141 2142 static int rtw8822c_dump_fw_crash(struct rtw_dev *rtwdev) 2143 { 2144 #define __dump_fw_8822c(_dev, _mem) \ 2145 rtw_dump_fw(_dev, OCPBASE_ ## _mem ## _88XX, \ 2146 FWCD_SIZE_ ## _mem ## _8822C, RTW_FWCD_ ## _mem) 2147 int ret; 2148 2149 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C); 2150 if (ret) 2151 return ret; 2152 ret = __dump_fw_8822c(rtwdev, DMEM); 2153 if (ret) 2154 return ret; 2155 ret = __dump_fw_8822c(rtwdev, IMEM); 2156 if (ret) 2157 return ret; 2158 ret = __dump_fw_8822c(rtwdev, EMEM); 2159 if (ret) 2160 return ret; 2161 ret = __dump_fw_8822c(rtwdev, ROM); 2162 if (ret) 2163 return ret; 2164 2165 return 0; 2166 2167 #undef __dump_fw_8822c 2168 } 2169 2170 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 2171 { 2172 if (enable) { 2173 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 2174 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 2175 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 2176 } else { 2177 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 2178 } 2179 } 2180 2181 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 2182 { 2183 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 2184 #define RF18_BAND_2G (0) 2185 #define RF18_BAND_5G (BIT(16) | BIT(8)) 2186 #define RF18_CHANNEL_MASK (MASKBYTE0) 2187 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 2188 #define RF18_RFSI_GE_CH80 (BIT(17)) 2189 #define RF18_RFSI_GT_CH140 (BIT(18)) 2190 #define RF18_BW_MASK (BIT(13) | BIT(12)) 2191 #define RF18_BW_20M (BIT(13) | BIT(12)) 2192 #define RF18_BW_40M (BIT(13)) 2193 #define RF18_BW_80M (BIT(12)) 2194 2195 u32 rf_reg18 = 0; 2196 u32 rf_rxbb = 0; 2197 2198 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2199 2200 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 2201 RF18_BW_MASK); 2202 2203 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 2204 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 2205 if (IS_CH_5G_BAND_4(channel)) 2206 rf_reg18 |= RF18_RFSI_GT_CH140; 2207 else if (IS_CH_5G_BAND_3(channel)) 2208 rf_reg18 |= RF18_RFSI_GE_CH80; 2209 2210 switch (bw) { 2211 case RTW_CHANNEL_WIDTH_5: 2212 case RTW_CHANNEL_WIDTH_10: 2213 case RTW_CHANNEL_WIDTH_20: 2214 default: 2215 rf_reg18 |= RF18_BW_20M; 2216 rf_rxbb = 0x18; 2217 break; 2218 case RTW_CHANNEL_WIDTH_40: 2219 /* RF bandwidth */ 2220 rf_reg18 |= RF18_BW_40M; 2221 rf_rxbb = 0x10; 2222 break; 2223 case RTW_CHANNEL_WIDTH_80: 2224 rf_reg18 |= RF18_BW_80M; 2225 rf_rxbb = 0x8; 2226 break; 2227 } 2228 2229 rtw8822c_rstb_3wire(rtwdev, false); 2230 2231 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 2232 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 2233 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 2234 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 2235 2236 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 2237 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 2238 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 2239 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 2240 2241 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 2242 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 2243 2244 rtw8822c_rstb_3wire(rtwdev, true); 2245 } 2246 2247 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 2248 { 2249 u32 igi; 2250 2251 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 2252 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 2253 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 2254 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 2255 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 2256 } 2257 2258 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 2259 u8 primary_ch_idx) 2260 { 2261 if (IS_CH_2G_BAND(channel)) { 2262 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 2263 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 2264 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 2265 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 2266 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 2267 2268 switch (bw) { 2269 case RTW_CHANNEL_WIDTH_20: 2270 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 2271 0x5); 2272 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 2273 0x5); 2274 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2275 0x6); 2276 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2277 0x6); 2278 break; 2279 case RTW_CHANNEL_WIDTH_40: 2280 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 2281 0x4); 2282 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 2283 0x4); 2284 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2285 0x0); 2286 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2287 0x0); 2288 break; 2289 } 2290 if (channel == 13 || channel == 14) 2291 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 2292 else if (channel == 11 || channel == 12) 2293 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 2294 else 2295 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 2296 if (channel == 14) { 2297 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 2298 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 2299 0x4962c931); 2300 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 2301 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 2302 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 2303 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 2304 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 2305 0xff012455); 2306 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 2307 } else { 2308 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 2309 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 2310 0x3e18fec8); 2311 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 2312 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 2313 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 2314 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 2315 0x00faf0de); 2316 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 2317 0x00122344); 2318 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 2319 0x0fffffff); 2320 } 2321 if (channel == 13) 2322 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 2323 else 2324 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 2325 } else if (IS_CH_5G_BAND(channel)) { 2326 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 2327 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 2328 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 2329 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 2330 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 2331 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 2332 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 2333 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2334 0x1); 2335 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2336 0x1); 2337 } else if (IS_CH_5G_BAND_3(channel)) { 2338 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2339 0x2); 2340 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2341 0x2); 2342 } else if (IS_CH_5G_BAND_4(channel)) { 2343 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2344 0x3); 2345 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2346 0x3); 2347 } 2348 2349 if (channel >= 36 && channel <= 51) 2350 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 2351 else if (channel >= 52 && channel <= 55) 2352 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 2353 else if (channel >= 56 && channel <= 111) 2354 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 2355 else if (channel >= 112 && channel <= 119) 2356 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 2357 else if (channel >= 120 && channel <= 172) 2358 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 2359 else if (channel >= 173 && channel <= 177) 2360 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 2361 } 2362 2363 switch (bw) { 2364 case RTW_CHANNEL_WIDTH_20: 2365 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 2366 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2367 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 2368 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 2369 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 2370 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2371 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2372 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2373 break; 2374 case RTW_CHANNEL_WIDTH_40: 2375 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 2376 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 2377 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 2378 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 2379 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 2380 (primary_ch_idx | (primary_ch_idx << 4))); 2381 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 2382 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2383 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 2384 break; 2385 case RTW_CHANNEL_WIDTH_80: 2386 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 2387 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 2388 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 2389 (primary_ch_idx | (primary_ch_idx << 4))); 2390 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 2391 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 2392 break; 2393 case RTW_CHANNEL_WIDTH_5: 2394 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 2395 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2396 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 2397 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 2398 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 2399 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2400 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2401 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2402 break; 2403 case RTW_CHANNEL_WIDTH_10: 2404 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 2405 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2406 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 2407 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 2408 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 2409 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2410 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2411 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2412 break; 2413 } 2414 } 2415 2416 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 2417 u8 primary_chan_idx) 2418 { 2419 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 2420 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 2421 rtw8822c_set_channel_rf(rtwdev, channel, bw); 2422 rtw8822c_toggle_igi(rtwdev); 2423 } 2424 2425 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2426 { 2427 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 2428 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 2429 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 2430 } else if (rx_path == BB_PATH_AB) { 2431 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 2432 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 2433 } 2434 2435 if (rx_path == BB_PATH_A) 2436 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 2437 else if (rx_path == BB_PATH_B) 2438 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 2439 else if (rx_path == BB_PATH_AB) 2440 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 2441 } 2442 2443 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2444 { 2445 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 2446 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 2447 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 2448 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 2449 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 2450 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 2451 } else if (rx_path == BB_PATH_AB) { 2452 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 2453 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 2454 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 2455 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 2456 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 2457 } 2458 2459 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 2460 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 2461 } 2462 2463 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2464 { 2465 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 2466 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 2467 } 2468 2469 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2470 bool is_tx2_path) 2471 { 2472 if (tx_path == BB_PATH_A) { 2473 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 2474 } else if (tx_path == BB_PATH_B) { 2475 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 2476 } else { 2477 if (is_tx2_path) 2478 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 2479 else 2480 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 2481 } 2482 rtw8822c_bb_reset(rtwdev); 2483 } 2484 2485 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2486 enum rtw_bb_path tx_path_sel_1ss) 2487 { 2488 if (tx_path == BB_PATH_A) { 2489 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 2490 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 2491 } else if (tx_path == BB_PATH_B) { 2492 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 2493 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 2494 } else { 2495 if (tx_path_sel_1ss == BB_PATH_AB) { 2496 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 2497 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 2498 } else if (tx_path_sel_1ss == BB_PATH_B) { 2499 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32); 2500 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 2501 } else if (tx_path_sel_1ss == BB_PATH_A) { 2502 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 2503 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 2504 } 2505 } 2506 rtw8822c_bb_reset(rtwdev); 2507 } 2508 2509 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2510 enum rtw_bb_path tx_path_sel_1ss, 2511 enum rtw_bb_path tx_path_cck, 2512 bool is_tx2_path) 2513 { 2514 rtw8822c_config_cck_tx_path(rtwdev, tx_path_cck, is_tx2_path); 2515 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, tx_path_sel_1ss); 2516 rtw8822c_bb_reset(rtwdev); 2517 } 2518 2519 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 2520 u8 rx_path, bool is_tx2_path) 2521 { 2522 if ((tx_path | rx_path) & BB_PATH_A) 2523 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 2524 else 2525 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 2526 if ((tx_path | rx_path) & BB_PATH_B) 2527 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 2528 else 2529 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 2530 2531 rtw8822c_config_rx_path(rtwdev, rx_path); 2532 rtw8822c_config_tx_path(rtwdev, tx_path, BB_PATH_A, BB_PATH_A, 2533 is_tx2_path); 2534 2535 rtw8822c_toggle_igi(rtwdev); 2536 } 2537 2538 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 2539 struct rtw_rx_pkt_stat *pkt_stat) 2540 { 2541 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2542 u8 l_bnd, u_bnd; 2543 u8 gain_a, gain_b; 2544 s8 rx_power[RTW_RF_PATH_MAX]; 2545 s8 min_rx_power = -120; 2546 u8 rssi; 2547 u8 channel; 2548 int path; 2549 2550 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 2551 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 2552 l_bnd = dm_info->cck_gi_l_bnd; 2553 u_bnd = dm_info->cck_gi_u_bnd; 2554 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 2555 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 2556 if (gain_a < l_bnd) 2557 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 2558 else if (gain_a > u_bnd) 2559 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 2560 if (gain_b < l_bnd) 2561 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 2562 else if (gain_b > u_bnd) 2563 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 2564 2565 rx_power[RF_PATH_A] -= 110; 2566 rx_power[RF_PATH_B] -= 110; 2567 2568 channel = GET_PHY_STAT_P0_CHANNEL(phy_status); 2569 if (channel == 0) 2570 channel = rtwdev->hal.current_channel; 2571 rtw_set_rx_freq_band(pkt_stat, channel); 2572 2573 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 2574 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 2575 2576 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 2577 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 2578 dm_info->rssi[path] = rssi; 2579 } 2580 2581 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 2582 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 2583 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 2584 min_rx_power); 2585 } 2586 2587 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 2588 struct rtw_rx_pkt_stat *pkt_stat) 2589 { 2590 struct rtw_path_div *p_div = &rtwdev->dm_path_div; 2591 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2592 u8 rxsc, bw; 2593 s8 min_rx_power = -120; 2594 s8 rx_evm; 2595 u8 evm_dbm = 0; 2596 u8 rssi; 2597 int path; 2598 u8 channel; 2599 2600 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 2601 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 2602 else 2603 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 2604 2605 if (rxsc >= 9 && rxsc <= 12) 2606 bw = RTW_CHANNEL_WIDTH_40; 2607 else if (rxsc >= 13) 2608 bw = RTW_CHANNEL_WIDTH_80; 2609 else 2610 bw = RTW_CHANNEL_WIDTH_20; 2611 2612 channel = GET_PHY_STAT_P1_CHANNEL(phy_status); 2613 rtw_set_rx_freq_band(pkt_stat, channel); 2614 2615 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 2616 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 2617 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 2618 pkt_stat->bw = bw; 2619 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 2620 pkt_stat->rx_power[RF_PATH_B], 2621 min_rx_power); 2622 2623 dm_info->curr_rx_rate = pkt_stat->rate; 2624 2625 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 2626 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 2627 2628 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 2629 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 2630 2631 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 2632 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 2633 2634 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 2635 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 2636 dm_info->rssi[path] = rssi; 2637 if (path == RF_PATH_A) { 2638 p_div->path_a_sum += rssi; 2639 p_div->path_a_cnt++; 2640 } else if (path == RF_PATH_B) { 2641 p_div->path_b_sum += rssi; 2642 p_div->path_b_cnt++; 2643 } 2644 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 2645 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 2646 2647 rx_evm = pkt_stat->rx_evm[path]; 2648 2649 if (rx_evm < 0) { 2650 if (rx_evm == S8_MIN) 2651 evm_dbm = 0; 2652 else 2653 evm_dbm = ((u8)-rx_evm >> 1); 2654 } 2655 dm_info->rx_evm_dbm[path] = evm_dbm; 2656 } 2657 rtw_phy_parsing_cfo(rtwdev, pkt_stat); 2658 } 2659 2660 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 2661 struct rtw_rx_pkt_stat *pkt_stat) 2662 { 2663 u8 page; 2664 2665 page = *phy_status & 0xf; 2666 2667 switch (page) { 2668 case 0: 2669 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 2670 break; 2671 case 1: 2672 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 2673 break; 2674 default: 2675 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 2676 return; 2677 } 2678 } 2679 2680 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 2681 struct rtw_rx_pkt_stat *pkt_stat, 2682 struct ieee80211_rx_status *rx_status) 2683 { 2684 struct ieee80211_hdr *hdr; 2685 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 2686 u8 *phy_status = NULL; 2687 2688 memset(pkt_stat, 0, sizeof(*pkt_stat)); 2689 2690 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 2691 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 2692 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 2693 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 2694 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 2695 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 2696 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 2697 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 2698 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 2699 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 2700 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 2701 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 2702 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 2703 2704 /* drv_info_sz is in unit of 8-bytes */ 2705 pkt_stat->drv_info_sz *= 8; 2706 2707 /* c2h cmd pkt's rx/phy status is not interested */ 2708 if (pkt_stat->is_c2h) 2709 return; 2710 2711 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 2712 pkt_stat->drv_info_sz); 2713 pkt_stat->hdr = hdr; 2714 if (pkt_stat->phy_status) { 2715 phy_status = rx_desc + desc_sz + pkt_stat->shift; 2716 query_phy_status(rtwdev, phy_status, pkt_stat); 2717 } 2718 2719 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 2720 } 2721 2722 static void 2723 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 2724 u8 *tx_pwr_ref_ofdm) 2725 { 2726 struct rtw_hal *hal = &rtwdev->hal; 2727 u32 txref_cck[2] = {0x18a0, 0x41a0}; 2728 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 2729 u8 path; 2730 2731 for (path = 0; path < hal->rf_path_num; path++) { 2732 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 2733 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 2734 tx_pwr_ref_cck[path]); 2735 } 2736 for (path = 0; path < hal->rf_path_num; path++) { 2737 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 2738 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 2739 tx_pwr_ref_ofdm[path]); 2740 } 2741 } 2742 2743 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 2744 s8 *diff_idx) 2745 { 2746 u32 offset_txagc = 0x3a00; 2747 u8 rate_idx = rate & 0xfc; 2748 u8 pwr_idx[4]; 2749 u32 phy_pwr_idx; 2750 int i; 2751 2752 for (i = 0; i < 4; i++) 2753 pwr_idx[i] = diff_idx[i] & 0x7f; 2754 2755 phy_pwr_idx = pwr_idx[0] | 2756 (pwr_idx[1] << 8) | 2757 (pwr_idx[2] << 16) | 2758 (pwr_idx[3] << 24); 2759 2760 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 2761 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 2762 phy_pwr_idx); 2763 } 2764 2765 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 2766 { 2767 struct rtw_hal *hal = &rtwdev->hal; 2768 u8 rs, rate, j; 2769 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 2770 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 2771 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 2772 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 2773 s8 diff_a, diff_b; 2774 u8 pwr_a, pwr_b; 2775 s8 diff_idx[4]; 2776 2777 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 2778 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 2779 for (j = 0; j < rtw_rate_size[rs]; j++) { 2780 rate = rtw_rate_section[rs][j]; 2781 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 2782 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 2783 if (rs == 0) { 2784 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 2785 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 2786 } else { 2787 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 2788 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 2789 } 2790 diff_idx[rate % 4] = min(diff_a, diff_b); 2791 if (rate % 4 == 3) 2792 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 2793 diff_idx); 2794 } 2795 } 2796 } 2797 2798 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev, 2799 u32 antenna_tx, 2800 u32 antenna_rx) 2801 { 2802 struct rtw_hal *hal = &rtwdev->hal; 2803 2804 switch (antenna_tx) { 2805 case BB_PATH_A: 2806 case BB_PATH_B: 2807 case BB_PATH_AB: 2808 break; 2809 default: 2810 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 2811 return -EINVAL; 2812 } 2813 2814 /* path B only is not available for RX */ 2815 switch (antenna_rx) { 2816 case BB_PATH_A: 2817 case BB_PATH_AB: 2818 break; 2819 default: 2820 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 2821 return -EINVAL; 2822 } 2823 2824 hal->antenna_tx = antenna_tx; 2825 hal->antenna_rx = antenna_rx; 2826 2827 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 2828 2829 return 0; 2830 } 2831 2832 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 2833 { 2834 u8 ldo_pwr; 2835 2836 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 2837 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 2838 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 2839 } 2840 2841 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 2842 { 2843 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2844 u32 cck_enable; 2845 u32 cck_fa_cnt; 2846 u32 crc32_cnt; 2847 u32 cca32_cnt; 2848 u32 ofdm_fa_cnt; 2849 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 2850 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 2851 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 2852 2853 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 2854 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 2855 2856 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 2857 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 2858 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 2859 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 2860 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 2861 2862 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 2863 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 2864 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 2865 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 2866 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 2867 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 2868 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 2869 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 2870 2871 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 2872 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 2873 2874 dm_info->cck_fa_cnt = cck_fa_cnt; 2875 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 2876 dm_info->total_fa_cnt = ofdm_fa_cnt; 2877 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 2878 2879 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 2880 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 2881 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2882 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 2883 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 2884 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2885 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 2886 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 2887 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2888 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 2889 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 2890 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2891 2892 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 2893 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 2894 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 2895 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 2896 if (cck_enable) 2897 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 2898 2899 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 2900 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 2901 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 2902 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 2903 2904 /* disable rx clk gating to reset counters */ 2905 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2906 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2907 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2908 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2909 } 2910 2911 static void rtw8822c_do_lck(struct rtw_dev *rtwdev) 2912 { 2913 u32 val; 2914 2915 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2916 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA); 2917 fsleep(1); 2918 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000); 2919 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001); 2920 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000, 2921 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000); 2922 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8); 2923 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2924 2925 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2926 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000); 2927 fsleep(1); 2928 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2929 } 2930 2931 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 2932 { 2933 struct rtw_iqk_para para = {0}; 2934 u8 iqk_chk; 2935 int ret; 2936 2937 para.clear = 1; 2938 rtw_fw_do_iqk(rtwdev, ¶); 2939 2940 ret = read_poll_timeout(rtw_read8, iqk_chk, iqk_chk == IQK_DONE_8822C, 2941 20000, 300000, false, rtwdev, REG_RPT_CIP); 2942 if (ret) 2943 rtw_warn(rtwdev, "failed to poll iqk status bit\n"); 2944 2945 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 2946 } 2947 2948 /* for coex */ 2949 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 2950 { 2951 /* enable TBTT nterrupt */ 2952 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2953 2954 /* BT report packet sample rate */ 2955 /* 0x790[5:0]=0x5 */ 2956 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 2957 2958 /* enable BT counter statistics */ 2959 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2960 2961 /* enable PTA (3-wire function form BT side) */ 2962 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2963 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 2964 2965 /* enable PTA (tx/rx signal form WiFi side) */ 2966 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2967 /* wl tx signal to PTA not case EDCCA */ 2968 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2969 /* GNT_BT=1 while select both */ 2970 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2971 /* BT_CCA = ~GNT_WL_BB, not or GNT_BT_BB, LTE_Rx */ 2972 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2973 2974 /* to avoid RF parameter error */ 2975 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000); 2976 } 2977 2978 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2979 { 2980 struct rtw_coex *coex = &rtwdev->coex; 2981 struct rtw_coex_stat *coex_stat = &coex->stat; 2982 struct rtw_efuse *efuse = &rtwdev->efuse; 2983 u32 rf_0x1; 2984 2985 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2986 return; 2987 2988 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 2989 2990 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 2991 rf_0x1 = 0x40021; 2992 else 2993 rf_0x1 = 0x40000; 2994 2995 /* BT at S1 for Shared-Ant */ 2996 if (efuse->share_ant) 2997 rf_0x1 |= BIT(13); 2998 2999 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 3000 3001 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 3002 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 3003 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 3004 * 3005 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 3006 * disable 0x1c30[22] = 0, 3007 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 3008 */ 3009 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) { 3010 rtw_write8_mask(rtwdev, REG_ANAPAR + 2, 3011 BIT_ANAPAR_BTPS >> 16, 0); 3012 } else { 3013 rtw_write8_mask(rtwdev, REG_ANAPAR + 2, 3014 BIT_ANAPAR_BTPS >> 16, 1); 3015 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1, 3016 BIT_DAC_OFF_ENABLE, 0); 3017 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3, 3018 BIT_DAC_OFF_ENABLE, 1); 3019 } 3020 3021 /* disable WL-S1 BB chage RF mode if GNT_BT 3022 * since RF TRx mask can do it 3023 */ 3024 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4, 3025 BIT_PI_IGNORE_GNT_BT, 1); 3026 3027 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 3028 * or antenna path is separated 3029 */ 3030 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) { 3031 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3032 BIT_PI_IGNORE_GNT_BT, 1); 3033 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 3034 BIT_NOMASK_TXBT_ENABLE, 1); 3035 } else if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 3036 coex->under_5g || !efuse->share_ant) { 3037 if (coex_stat->kt_ver >= 3) { 3038 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3039 BIT_PI_IGNORE_GNT_BT, 0); 3040 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 3041 BIT_NOMASK_TXBT_ENABLE, 1); 3042 } else { 3043 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3044 BIT_PI_IGNORE_GNT_BT, 1); 3045 } 3046 } else { 3047 /* shared-antenna */ 3048 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3049 BIT_PI_IGNORE_GNT_BT, 0); 3050 if (coex_stat->kt_ver >= 3) { 3051 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 3052 BIT_NOMASK_TXBT_ENABLE, 0); 3053 } 3054 } 3055 } 3056 3057 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 3058 { 3059 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 3060 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 3061 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 3062 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 3063 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 3064 } 3065 3066 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 3067 { 3068 struct rtw_coex *coex = &rtwdev->coex; 3069 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 3070 struct rtw_efuse *efuse = &rtwdev->efuse; 3071 3072 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 3073 coex_rfe->ant_switch_polarity = 0; 3074 coex_rfe->ant_switch_exist = false; 3075 coex_rfe->ant_switch_with_bt = false; 3076 coex_rfe->ant_switch_diversity = false; 3077 3078 if (efuse->share_ant) 3079 coex_rfe->wlg_at_btg = true; 3080 else 3081 coex_rfe->wlg_at_btg = false; 3082 3083 /* disable LTE coex in wifi side */ 3084 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 3085 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 3086 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 3087 } 3088 3089 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 3090 { 3091 struct rtw_coex *coex = &rtwdev->coex; 3092 struct rtw_coex_dm *coex_dm = &coex->dm; 3093 3094 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 3095 return; 3096 3097 coex_dm->cur_wl_pwr_lvl = wl_pwr; 3098 } 3099 3100 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 3101 { 3102 struct rtw_coex *coex = &rtwdev->coex; 3103 struct rtw_coex_dm *coex_dm = &coex->dm; 3104 3105 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 3106 return; 3107 3108 coex_dm->cur_wl_rx_low_gain_en = low_gain; 3109 3110 if (coex_dm->cur_wl_rx_low_gain_en) { 3111 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); 3112 3113 /* set Rx filter corner RCK offset */ 3114 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22); 3115 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36); 3116 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22); 3117 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36); 3118 3119 } else { 3120 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); 3121 3122 /* set Rx filter corner RCK offset */ 3123 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20); 3124 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0); 3125 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20); 3126 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0); 3127 } 3128 } 3129 3130 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 3131 struct rtw_vif *vif, 3132 struct rtw_bfee *bfee) 3133 { 3134 u8 csi_rsc = 0; 3135 u32 tmp6dc; 3136 3137 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 3138 3139 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 3140 BIT_WMAC_USE_NDPARATE | 3141 (csi_rsc << 13); 3142 if (vif->net_type == RTW_NET_AP_MODE) 3143 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 3144 else 3145 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 3146 3147 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 3148 } 3149 3150 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 3151 struct rtw_vif *vif, 3152 struct rtw_bfee *bfee, bool enable) 3153 { 3154 if (enable) 3155 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 3156 else 3157 rtw_bf_remove_bfee_su(rtwdev, bfee); 3158 } 3159 3160 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 3161 struct rtw_vif *vif, 3162 struct rtw_bfee *bfee, bool enable) 3163 { 3164 if (enable) 3165 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 3166 else 3167 rtw_bf_remove_bfee_mu(rtwdev, bfee); 3168 } 3169 3170 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 3171 struct rtw_bfee *bfee, bool enable) 3172 { 3173 if (bfee->role == RTW_BFEE_SU) 3174 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 3175 else if (bfee->role == RTW_BFEE_MU) 3176 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 3177 else 3178 rtw_warn(rtwdev, "wrong bfee role\n"); 3179 } 3180 3181 struct dpk_cfg_pair { 3182 u32 addr; 3183 u32 bitmask; 3184 u32 data; 3185 }; 3186 3187 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 3188 const struct rtw_table *tbl) 3189 { 3190 const struct dpk_cfg_pair *p = tbl->data; 3191 const struct dpk_cfg_pair *end = p + tbl->size / 3; 3192 3193 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 3194 3195 for (; p < end; p++) 3196 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 3197 } 3198 3199 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 3200 { 3201 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3202 3203 if (is_before_k) { 3204 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 3205 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 3206 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 3207 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 3208 } else { 3209 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 3210 dpk_info->gnt_value); 3211 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 3212 } 3213 } 3214 3215 static void 3216 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 3217 struct rtw_backup_info *bckp) 3218 { 3219 rtw_restore_reg(rtwdev, bckp, reg_num); 3220 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3221 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 3222 } 3223 3224 static void 3225 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 3226 u32 reg_num, struct rtw_backup_info *bckp) 3227 { 3228 u32 i; 3229 3230 for (i = 0; i < reg_num; i++) { 3231 bckp[i].len = 4; 3232 bckp[i].reg = reg[i]; 3233 bckp[i].val = rtw_read32(rtwdev, reg[i]); 3234 } 3235 } 3236 3237 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 3238 u32 *rf_reg, 3239 u32 rf_reg_bak[][2]) 3240 { 3241 u32 i; 3242 3243 for (i = 0; i < DPK_RF_REG_NUM; i++) { 3244 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 3245 rf_reg[i], RFREG_MASK); 3246 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 3247 rf_reg[i], RFREG_MASK); 3248 } 3249 } 3250 3251 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 3252 u32 *rf_reg, 3253 u32 rf_reg_bak[][2]) 3254 { 3255 u32 i; 3256 3257 for (i = 0; i < DPK_RF_REG_NUM; i++) { 3258 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 3259 rf_reg_bak[i][RF_PATH_A]); 3260 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 3261 rf_reg_bak[i][RF_PATH_B]); 3262 } 3263 } 3264 3265 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 3266 { 3267 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3268 u32 reg; 3269 u8 band_shift; 3270 3271 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 3272 3273 band_shift = FIELD_GET(BIT(16), reg); 3274 dpk_info->dpk_band = 1 << band_shift; 3275 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 3276 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 3277 } 3278 3279 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 3280 { 3281 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 3282 udelay(5); 3283 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 3284 usleep_range(600, 610); 3285 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 3286 } 3287 3288 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 3289 { 3290 u16 dc_i, dc_q; 3291 u8 corr_idx; 3292 3293 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 3294 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 3295 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 3296 3297 if (dc_i & BIT(11)) 3298 dc_i = 0x1000 - dc_i; 3299 if (dc_q & BIT(11)) 3300 dc_q = 0x1000 - dc_q; 3301 3302 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3303 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 3304 rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 3305 3306 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 3307 return 1; 3308 else 3309 return 0; 3310 3311 } 3312 3313 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 3314 { 3315 u8 reg_a, reg_b; 3316 u16 count = 0; 3317 3318 rtw_write8(rtwdev, 0x522, 0xff); 3319 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 3320 3321 do { 3322 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 3323 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 3324 udelay(2); 3325 count++; 3326 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 3327 } 3328 3329 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 3330 { 3331 rtw8822c_dpk_tx_pause(rtwdev); 3332 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 3333 } 3334 3335 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 3336 { 3337 if (is_do_dpk) 3338 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 3339 else 3340 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 3341 } 3342 3343 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 3344 { 3345 u8 path; 3346 3347 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3348 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 3349 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 3350 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 3351 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); 3352 else 3353 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); 3354 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 3355 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 3356 } 3357 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3358 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 3359 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 3360 } 3361 3362 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 3363 { 3364 u32 ori_txbb; 3365 3366 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 3367 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 3368 3369 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 3370 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 3371 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0); 3372 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 3373 3374 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 3375 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1); 3376 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 3377 } else { 3378 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 3379 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 3380 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 3381 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 3382 } 3383 3384 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 3385 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 3386 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 3387 3388 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 3389 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 3390 else 3391 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 3392 3393 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 3394 3395 usleep_range(100, 110); 3396 3397 return ori_txbb & 0x1f; 3398 } 3399 3400 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 3401 { 3402 u16 cmd; 3403 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 3404 3405 switch (action) { 3406 case RTW_DPK_GAIN_LOSS: 3407 cmd = 0x14 + path; 3408 break; 3409 case RTW_DPK_DO_DPK: 3410 cmd = 0x16 + path + bw; 3411 break; 3412 case RTW_DPK_DPK_ON: 3413 cmd = 0x1a + path; 3414 break; 3415 case RTW_DPK_DAGC: 3416 cmd = 0x1c + path + bw; 3417 break; 3418 default: 3419 return 0; 3420 } 3421 3422 return (cmd << 8) | 0x48; 3423 } 3424 3425 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 3426 { 3427 u16 dpk_cmd; 3428 u8 result = 0; 3429 3430 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 3431 3432 if (action == RTW_DPK_CAL_PWR) { 3433 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 3434 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 3435 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3436 msleep(10); 3437 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 3438 result = 1; 3439 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 3440 } 3441 } else { 3442 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3443 0x8 | (path << 1)); 3444 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3445 3446 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 3447 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 3448 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 3449 msleep(10); 3450 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 3451 result = 1; 3452 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 3453 } 3454 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3455 0x8 | (path << 1)); 3456 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3457 } 3458 3459 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 3460 3461 rtw_write8(rtwdev, 0x1b10, 0x0); 3462 3463 return result; 3464 } 3465 3466 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 3467 { 3468 u16 dgain; 3469 3470 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3471 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 3472 3473 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 3474 3475 return dgain; 3476 } 3477 3478 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 3479 { 3480 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 3481 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 3482 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 3483 udelay(15); 3484 3485 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 3486 } 3487 3488 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 3489 { 3490 u32 i_val, q_val; 3491 3492 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 3493 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 3494 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 3495 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 3496 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 3497 3498 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 3499 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 3500 3501 if (i_val & BIT(15)) 3502 i_val = 0x10000 - i_val; 3503 if (q_val & BIT(15)) 3504 q_val = 0x10000 - q_val; 3505 3506 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 3507 3508 return i_val * i_val + q_val * q_val; 3509 } 3510 3511 static u32 rtw8822c_psd_log2base(u32 val) 3512 { 3513 u32 tmp, val_integerd_b, tindex; 3514 u32 result, val_fractiond_b; 3515 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 3516 151, 132, 115, 100, 86, 74, 62, 51, 3517 42, 32, 23, 15, 7, 0}; 3518 3519 if (val == 0) 3520 return 0; 3521 3522 val_integerd_b = __fls(val) + 1; 3523 3524 tmp = (val * 100) / (1 << val_integerd_b); 3525 tindex = tmp / 5; 3526 3527 if (tindex >= ARRAY_SIZE(table_fraction)) 3528 tindex = ARRAY_SIZE(table_fraction) - 1; 3529 3530 val_fractiond_b = table_fraction[tindex]; 3531 3532 result = val_integerd_b * 100 - val_fractiond_b; 3533 3534 return result; 3535 } 3536 3537 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 3538 { 3539 u8 result; 3540 3541 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3542 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 3543 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 3544 3545 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 3546 3547 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 3548 3549 return result; 3550 } 3551 3552 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 3553 u8 limited_pga) 3554 { 3555 u8 result = 0; 3556 u16 dgain; 3557 3558 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3559 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 3560 3561 if (dgain > 1535 && !limited_pga) 3562 return RTW_DPK_GAIN_LESS; 3563 else if (dgain < 768 && !limited_pga) 3564 return RTW_DPK_GAIN_LARGE; 3565 else 3566 return result; 3567 } 3568 3569 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 3570 { 3571 u32 loss, loss_db; 3572 3573 loss = rtw8822c_dpk_pas_read(rtwdev, path); 3574 if (loss < 0x4000000) 3575 return RTW_DPK_GL_LESS; 3576 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 3577 3578 if (loss_db > 1000) 3579 return RTW_DPK_GL_LARGE; 3580 else if (loss_db < 250) 3581 return RTW_DPK_GL_LESS; 3582 else 3583 return RTW_DPK_AGC_OUT; 3584 } 3585 3586 struct rtw8822c_dpk_data { 3587 u8 txbb; 3588 u8 pga; 3589 u8 limited_pga; 3590 u8 agc_cnt; 3591 bool loss_only; 3592 bool gain_only; 3593 u8 path; 3594 }; 3595 3596 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 3597 struct rtw8822c_dpk_data *data) 3598 { 3599 u8 state; 3600 3601 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 3602 BIT_GAIN_TXBB); 3603 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 3604 BIT_RXAGC); 3605 3606 if (data->loss_only) { 3607 state = RTW_DPK_LOSS_CHECK; 3608 goto check_end; 3609 } 3610 3611 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 3612 data->limited_pga); 3613 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 3614 state = RTW_DPK_AGC_OUT; 3615 else if (state == RTW_DPK_GAIN_CHECK) 3616 state = RTW_DPK_LOSS_CHECK; 3617 3618 check_end: 3619 data->agc_cnt++; 3620 if (data->agc_cnt >= 6) 3621 state = RTW_DPK_AGC_OUT; 3622 3623 return state; 3624 } 3625 3626 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 3627 struct rtw8822c_dpk_data *data) 3628 { 3629 u8 pga = data->pga; 3630 3631 if (pga > 0xe) 3632 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 3633 else if (pga > 0xb && pga < 0xf) 3634 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 3635 else if (pga < 0xc) 3636 data->limited_pga = 1; 3637 3638 return RTW_DPK_GAIN_CHECK; 3639 } 3640 3641 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 3642 struct rtw8822c_dpk_data *data) 3643 { 3644 u8 pga = data->pga; 3645 3646 if (pga < 0xc) 3647 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 3648 else if (pga > 0xb && pga < 0xf) 3649 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 3650 else if (pga > 0xe) 3651 data->limited_pga = 1; 3652 3653 return RTW_DPK_GAIN_CHECK; 3654 } 3655 3656 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 3657 struct rtw8822c_dpk_data *data, u8 is_large) 3658 { 3659 u8 txbb_bound[] = {0x1f, 0}; 3660 3661 if (data->txbb == txbb_bound[is_large]) 3662 return RTW_DPK_AGC_OUT; 3663 3664 if (is_large == 1) 3665 data->txbb -= 2; 3666 else 3667 data->txbb += 3; 3668 3669 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 3670 data->limited_pga = 0; 3671 3672 return RTW_DPK_GAIN_CHECK; 3673 } 3674 3675 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 3676 struct rtw8822c_dpk_data *data) 3677 { 3678 return rtw8822c_gl_state(rtwdev, data, 1); 3679 } 3680 3681 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 3682 struct rtw8822c_dpk_data *data) 3683 { 3684 return rtw8822c_gl_state(rtwdev, data, 0); 3685 } 3686 3687 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 3688 struct rtw8822c_dpk_data *data) 3689 { 3690 u8 path = data->path; 3691 u8 state; 3692 3693 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 3694 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 3695 3696 return state; 3697 } 3698 3699 static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 3700 struct rtw8822c_dpk_data *data) = { 3701 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 3702 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 3703 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 3704 3705 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 3706 bool gain_only, bool loss_only) 3707 { 3708 struct rtw8822c_dpk_data data = {0}; 3709 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 3710 u8 state = RTW_DPK_GAIN_CHECK; 3711 3712 data.loss_only = loss_only; 3713 data.gain_only = gain_only; 3714 data.path = path; 3715 3716 for (;;) { 3717 func = dpk_state[state]; 3718 state = func(rtwdev, &data); 3719 if (state == RTW_DPK_AGC_OUT) 3720 break; 3721 } 3722 3723 return data.txbb; 3724 } 3725 3726 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 3727 u16 coef_i, u16 coef_q) 3728 { 3729 if (coef_i == 0x1000 || coef_i == 0x0fff || 3730 coef_q == 0x1000 || coef_q == 0x0fff) 3731 return true; 3732 3733 return false; 3734 } 3735 3736 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 3737 { 3738 u32 reg = 0; 3739 u16 coef_i = 0, coef_q = 0; 3740 3741 reg = rtw_read32(rtwdev, REG_STAT_RPT); 3742 3743 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 3744 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 3745 3746 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 3747 3748 reg = (coef_i << 16) | coef_q; 3749 3750 return reg; 3751 } 3752 3753 static const u32 rtw8822c_dpk_get_coef_tbl[] = { 3754 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 3755 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 3756 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 3757 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 3758 }; 3759 3760 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 3761 { 3762 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3763 int i; 3764 3765 for (i = 0; i < 20; i++) { 3766 rtw_write32(rtwdev, REG_RXSRAM_CTL, 3767 rtw8822c_dpk_get_coef_tbl[i]); 3768 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 3769 } 3770 } 3771 3772 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 3773 { 3774 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 3775 3776 if (path == RF_PATH_A) { 3777 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 3778 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 3779 } else if (path == RF_PATH_B) { 3780 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 3781 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 3782 } 3783 3784 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 3785 } 3786 3787 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 3788 { 3789 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3790 u8 addr, result = 1; 3791 u16 coef_i, coef_q; 3792 3793 for (addr = 0; addr < 20; addr++) { 3794 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 3795 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 3796 3797 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 3798 result = 0; 3799 break; 3800 } 3801 } 3802 return result; 3803 } 3804 3805 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 3806 { 3807 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3808 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 3809 u32 coef; 3810 u8 addr; 3811 3812 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 3813 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3814 3815 for (addr = 0; addr < 20; addr++) { 3816 if (result == 0) { 3817 if (addr == 3) 3818 coef = 0x04001fff; 3819 else 3820 coef = 0x00001fff; 3821 } else { 3822 coef = dpk_info->coef[path][addr]; 3823 } 3824 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 3825 } 3826 } 3827 3828 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 3829 u8 path, u8 result) 3830 { 3831 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3832 3833 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3834 3835 if (result) 3836 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 3837 else 3838 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 3839 3840 dpk_info->result[path] = result; 3841 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 3842 3843 rtw8822c_dpk_coef_write(rtwdev, path, result); 3844 } 3845 3846 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 3847 { 3848 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3849 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 3850 3851 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 3852 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 3853 3854 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3855 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3856 rtw8822c_dpk_dgain_read(rtwdev, path); 3857 3858 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 3859 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3860 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3861 rtw8822c_dpk_dc_corr_check(rtwdev, path); 3862 } 3863 3864 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 3865 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 3866 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 3867 3868 if (tx_bb < tx_agc_search) 3869 tx_bb = 0; 3870 else 3871 tx_bb = tx_bb - tx_agc_search; 3872 3873 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 3874 3875 tx_agc = ori_txagc - (ori_txbb - tx_bb); 3876 3877 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 3878 3879 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 3880 3881 return tx_agc; 3882 } 3883 3884 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 3885 { 3886 u8 result; 3887 3888 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 3889 3890 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3891 3892 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 3893 3894 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 3895 3896 rtw8822c_dpk_get_coef(rtwdev, path); 3897 3898 return result; 3899 } 3900 3901 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 3902 { 3903 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3904 u32 tmp_gs = 0; 3905 3906 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3907 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 3908 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3909 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3910 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 3911 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3912 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 3913 3914 if (path == RF_PATH_A) { 3915 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3916 0x1066680); 3917 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 3918 } else { 3919 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3920 0x1066680); 3921 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 3922 } 3923 3924 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 3925 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 3926 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 3927 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 3928 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 3929 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3930 rtw_write32(rtwdev, REG_DPD_CTL15, 3931 0x05020000 | (BIT(path) << 28)); 3932 } else { 3933 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 3934 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 3935 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 3936 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 3937 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3938 rtw_write32(rtwdev, REG_DPD_CTL15, 3939 0x05020008 | (BIT(path) << 28)); 3940 } 3941 3942 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 3943 3944 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 3945 3946 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 3947 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3948 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3949 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 3950 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3951 3952 if (path == RF_PATH_A) 3953 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 3954 else 3955 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 3956 3957 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3958 3959 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 3960 tmp_gs = (tmp_gs * 910) >> 10; 3961 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 3962 3963 if (path == RF_PATH_A) 3964 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 3965 else 3966 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 3967 3968 dpk_info->dpk_gs[path] = tmp_gs; 3969 } 3970 3971 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 3972 { 3973 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3974 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 3975 u32 i_scaling; 3976 u8 path; 3977 3978 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3979 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3980 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 3981 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 3982 3983 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 3984 3985 rtw_write8(rtwdev, 0x1b10, 0x0); 3986 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3987 3988 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3989 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 3990 3991 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 3992 i_scaling); 3993 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3994 GENMASK(31, 28), 0x9); 3995 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3996 GENMASK(31, 28), 0x1); 3997 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3998 GENMASK(31, 28), 0x0); 3999 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 4000 BIT(14), 0x0); 4001 } 4002 } 4003 4004 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 4005 { 4006 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4007 4008 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 4009 4010 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 4011 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 4012 4013 if (test_bit(path, dpk_info->dpk_path_ok)) 4014 rtw8822c_dpk_cal_gs(rtwdev, path); 4015 } 4016 4017 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 4018 u32 dpk_txagc, u8 path) 4019 { 4020 bool result; 4021 4022 if (!is_fail) { 4023 if (rtw8822c_dpk_coef_read(rtwdev, path)) 4024 result = true; 4025 else 4026 result = false; 4027 } else { 4028 result = false; 4029 } 4030 4031 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 4032 4033 return result; 4034 } 4035 4036 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 4037 { 4038 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4039 u8 path; 4040 4041 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 4042 clear_bit(path, dpk_info->dpk_path_ok); 4043 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4044 0x8 | (path << 1)); 4045 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 4046 4047 dpk_info->dpk_txagc[path] = 0; 4048 dpk_info->result[path] = 0; 4049 dpk_info->dpk_gs[path] = 0x5b; 4050 dpk_info->pre_pwsf[path] = 0; 4051 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 4052 path); 4053 } 4054 } 4055 4056 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 4057 { 4058 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4059 u32 dpk_txagc; 4060 u8 dpk_fail; 4061 4062 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 4063 4064 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 4065 4066 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 4067 4068 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 4069 rtw_err(rtwdev, "failed to do dpk calibration\n"); 4070 4071 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 4072 4073 if (dpk_info->result[path]) 4074 set_bit(path, dpk_info->dpk_path_ok); 4075 } 4076 4077 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 4078 { 4079 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 4080 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 4081 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 4082 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 4083 rtw8822c_dpk_cal_coef1(rtwdev); 4084 } 4085 4086 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 4087 { 4088 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4089 u32 mask = BIT(15) | BIT(14); 4090 4091 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 4092 4093 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 4094 dpk_info->is_dpk_pwr_on); 4095 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 4096 dpk_info->is_dpk_pwr_on); 4097 4098 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 4099 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 4100 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 4101 } 4102 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 4103 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 4104 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 4105 } 4106 } 4107 4108 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 4109 { 4110 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4111 u8 path; 4112 4113 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 4114 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 4115 dpk_info->dpk_ch == 0) 4116 return; 4117 4118 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 4119 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4120 0x8 | (path << 1)); 4121 if (dpk_info->dpk_band == RTW_BAND_2G) 4122 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); 4123 else 4124 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); 4125 4126 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 4127 4128 rtw8822c_dpk_coef_write(rtwdev, path, 4129 test_bit(path, dpk_info->dpk_path_ok)); 4130 4131 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 4132 4133 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 4134 4135 if (path == RF_PATH_A) 4136 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 4137 dpk_info->dpk_gs[path]); 4138 else 4139 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 4140 dpk_info->dpk_gs[path]); 4141 } 4142 rtw8822c_dpk_cal_coef1(rtwdev); 4143 } 4144 4145 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 4146 { 4147 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4148 u8 channel; 4149 4150 dpk_info->is_reload = false; 4151 4152 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 4153 4154 if (channel == dpk_info->dpk_ch) { 4155 rtw_dbg(rtwdev, RTW_DBG_RFK, 4156 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 4157 rtw8822c_dpk_reload_data(rtwdev); 4158 dpk_info->is_reload = true; 4159 } 4160 4161 return dpk_info->is_reload; 4162 } 4163 4164 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 4165 { 4166 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4167 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 4168 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 4169 u32 bb_reg[DPK_BB_REG_NUM] = { 4170 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 4171 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 4172 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 4173 u32 rf_reg[DPK_RF_REG_NUM] = { 4174 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 4175 u8 path; 4176 4177 if (!dpk_info->is_dpk_pwr_on) { 4178 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 4179 return; 4180 } else if (rtw8822c_dpk_reload(rtwdev)) { 4181 return; 4182 } 4183 4184 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 4185 ewma_thermal_init(&dpk_info->avg_thermal[path]); 4186 4187 rtw8822c_dpk_information(rtwdev); 4188 4189 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 4190 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 4191 4192 rtw8822c_dpk_mac_bb_setting(rtwdev); 4193 rtw8822c_dpk_afe_setting(rtwdev, true); 4194 rtw8822c_dpk_pre_setting(rtwdev); 4195 rtw8822c_dpk_result_reset(rtwdev); 4196 rtw8822c_dpk_path_select(rtwdev); 4197 rtw8822c_dpk_afe_setting(rtwdev, false); 4198 rtw8822c_dpk_enable_disable(rtwdev); 4199 4200 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 4201 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 4202 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 4203 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 4204 } 4205 4206 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 4207 { 4208 rtw8822c_rfk_power_save(rtwdev, false); 4209 rtw8822c_do_gapk(rtwdev); 4210 rtw8822c_do_iqk(rtwdev); 4211 rtw8822c_do_dpk(rtwdev); 4212 rtw8822c_rfk_power_save(rtwdev, true); 4213 } 4214 4215 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 4216 { 4217 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4218 u8 path; 4219 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 4220 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 4221 4222 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 4223 return; 4224 4225 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 4226 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 4227 ewma_thermal_add(&dpk_info->avg_thermal[path], 4228 thermal_value[path]); 4229 thermal_value[path] = 4230 ewma_thermal_read(&dpk_info->avg_thermal[path]); 4231 delta_dpk[path] = dpk_info->thermal_dpk[path] - 4232 thermal_value[path]; 4233 offset[path] = delta_dpk[path] - 4234 dpk_info->thermal_dpk_delta[path]; 4235 offset[path] &= 0x7f; 4236 4237 if (offset[path] != dpk_info->pre_pwsf[path]) { 4238 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4239 0x8 | (path << 1)); 4240 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 4241 offset[path]); 4242 dpk_info->pre_pwsf[path] = offset[path]; 4243 } 4244 } 4245 } 4246 4247 #define XCAP_EXTEND(val) ({typeof(val) _v = (val); _v | _v << 7; }) 4248 static void rtw8822c_set_crystal_cap_reg(struct rtw_dev *rtwdev, u8 crystal_cap) 4249 { 4250 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4251 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4252 u32 val = 0; 4253 4254 val = XCAP_EXTEND(crystal_cap); 4255 cfo->crystal_cap = crystal_cap; 4256 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, BIT_XCAP_0, val); 4257 } 4258 4259 static void rtw8822c_set_crystal_cap(struct rtw_dev *rtwdev, u8 crystal_cap) 4260 { 4261 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4262 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4263 4264 if (cfo->crystal_cap == crystal_cap) 4265 return; 4266 4267 rtw8822c_set_crystal_cap_reg(rtwdev, crystal_cap); 4268 } 4269 4270 static void rtw8822c_cfo_tracking_reset(struct rtw_dev *rtwdev) 4271 { 4272 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4273 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4274 4275 cfo->is_adjust = true; 4276 4277 if (cfo->crystal_cap > rtwdev->efuse.crystal_cap) 4278 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap - 1); 4279 else if (cfo->crystal_cap < rtwdev->efuse.crystal_cap) 4280 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap + 1); 4281 } 4282 4283 static void rtw8822c_cfo_init(struct rtw_dev *rtwdev) 4284 { 4285 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4286 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4287 4288 cfo->crystal_cap = rtwdev->efuse.crystal_cap; 4289 cfo->is_adjust = true; 4290 } 4291 4292 #define REPORT_TO_KHZ(val) ({typeof(val) _v = (val); (_v << 1) + (_v >> 1); }) 4293 static s32 rtw8822c_cfo_calc_avg(struct rtw_dev *rtwdev, u8 path_num) 4294 { 4295 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4296 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4297 s32 cfo_avg, cfo_path_sum = 0, cfo_rpt_sum; 4298 u8 i; 4299 4300 for (i = 0; i < path_num; i++) { 4301 cfo_rpt_sum = REPORT_TO_KHZ(cfo->cfo_tail[i]); 4302 4303 if (cfo->cfo_cnt[i]) 4304 cfo_avg = cfo_rpt_sum / cfo->cfo_cnt[i]; 4305 else 4306 cfo_avg = 0; 4307 4308 cfo_path_sum += cfo_avg; 4309 } 4310 4311 for (i = 0; i < path_num; i++) { 4312 cfo->cfo_tail[i] = 0; 4313 cfo->cfo_cnt[i] = 0; 4314 } 4315 4316 return cfo_path_sum / path_num; 4317 } 4318 4319 static void rtw8822c_cfo_need_adjust(struct rtw_dev *rtwdev, s32 cfo_avg) 4320 { 4321 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4322 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4323 4324 if (!cfo->is_adjust) { 4325 if (abs(cfo_avg) > CFO_TRK_ENABLE_TH) 4326 cfo->is_adjust = true; 4327 } else { 4328 if (abs(cfo_avg) <= CFO_TRK_STOP_TH) 4329 cfo->is_adjust = false; 4330 } 4331 4332 if (!rtw_coex_disabled(rtwdev)) { 4333 cfo->is_adjust = false; 4334 rtw8822c_set_crystal_cap(rtwdev, rtwdev->efuse.crystal_cap); 4335 } 4336 } 4337 4338 static void rtw8822c_cfo_track(struct rtw_dev *rtwdev) 4339 { 4340 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4341 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4342 u8 path_num = rtwdev->hal.rf_path_num; 4343 s8 crystal_cap = cfo->crystal_cap; 4344 s32 cfo_avg = 0; 4345 4346 if (rtwdev->sta_cnt != 1) { 4347 rtw8822c_cfo_tracking_reset(rtwdev); 4348 return; 4349 } 4350 4351 if (cfo->packet_count == cfo->packet_count_pre) 4352 return; 4353 4354 cfo->packet_count_pre = cfo->packet_count; 4355 cfo_avg = rtw8822c_cfo_calc_avg(rtwdev, path_num); 4356 rtw8822c_cfo_need_adjust(rtwdev, cfo_avg); 4357 4358 if (cfo->is_adjust) { 4359 if (cfo_avg > CFO_TRK_ADJ_TH) 4360 crystal_cap++; 4361 else if (cfo_avg < -CFO_TRK_ADJ_TH) 4362 crystal_cap--; 4363 4364 crystal_cap = clamp_t(s8, crystal_cap, 0, XCAP_MASK); 4365 rtw8822c_set_crystal_cap(rtwdev, (u8)crystal_cap); 4366 } 4367 } 4368 4369 static const struct rtw_phy_cck_pd_reg 4370 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 4371 { 4372 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 4373 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 4374 }, 4375 { 4376 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 4377 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 4378 }, 4379 }; 4380 4381 #define RTW_CCK_PD_MAX 255 4382 #define RTW_CCK_CS_MAX 31 4383 #define RTW_CCK_CS_ERR1 27 4384 #define RTW_CCK_CS_ERR2 29 4385 static void 4386 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 4387 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 4388 { 4389 u32 pd, cs; 4390 4391 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 4392 return; 4393 4394 pd = rtw_read32_mask(rtwdev, 4395 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 4396 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 4397 cs = rtw_read32_mask(rtwdev, 4398 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 4399 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 4400 pd += pd_diff; 4401 cs += cs_diff; 4402 if (pd > RTW_CCK_PD_MAX) 4403 pd = RTW_CCK_PD_MAX; 4404 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 4405 cs++; 4406 else if (cs > RTW_CCK_CS_MAX) 4407 cs = RTW_CCK_CS_MAX; 4408 rtw_write32_mask(rtwdev, 4409 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 4410 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 4411 pd); 4412 rtw_write32_mask(rtwdev, 4413 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 4414 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 4415 cs); 4416 4417 rtw_dbg(rtwdev, RTW_DBG_PHY, 4418 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n", 4419 rtw_is_assoc(rtwdev), bw, nrx, cs, pd); 4420 } 4421 4422 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 4423 { 4424 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4425 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 4426 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 4427 u8 cur_lvl; 4428 u8 nrx, bw; 4429 4430 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 4431 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 4432 4433 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n", 4434 dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx, 4435 dm_info->cck_fa_avg); 4436 4437 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 4438 return; 4439 4440 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 4441 4442 /* update cck pd info */ 4443 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 4444 4445 rtw8822c_phy_cck_pd_set_reg(rtwdev, 4446 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 4447 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 4448 bw, nrx); 4449 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 4450 } 4451 4452 #define PWR_TRACK_MASK 0x7f 4453 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 4454 { 4455 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4456 4457 switch (rf_path) { 4458 case RF_PATH_A: 4459 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 4460 dm_info->delta_power_index[rf_path]); 4461 break; 4462 case RF_PATH_B: 4463 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 4464 dm_info->delta_power_index[rf_path]); 4465 break; 4466 default: 4467 break; 4468 } 4469 } 4470 4471 static void rtw8822c_pwr_track_stats(struct rtw_dev *rtwdev, u8 path) 4472 { 4473 u8 thermal_value; 4474 4475 if (rtwdev->efuse.thermal_meter[path] == 0xff) 4476 return; 4477 4478 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 4479 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 4480 } 4481 4482 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 4483 struct rtw_swing_table *swing_table, 4484 u8 path) 4485 { 4486 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4487 u8 delta; 4488 4489 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 4490 dm_info->delta_power_index[path] = 4491 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 4492 delta); 4493 rtw8822c_pwrtrack_set(rtwdev, path); 4494 } 4495 4496 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 4497 { 4498 struct rtw_swing_table swing_table; 4499 u8 i; 4500 4501 rtw_phy_config_swing_table(rtwdev, &swing_table); 4502 4503 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 4504 rtw8822c_pwr_track_stats(rtwdev, i); 4505 if (rtw_phy_pwrtrack_need_lck(rtwdev)) 4506 rtw8822c_do_lck(rtwdev); 4507 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 4508 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 4509 } 4510 4511 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 4512 { 4513 struct rtw_efuse *efuse = &rtwdev->efuse; 4514 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4515 4516 if (efuse->power_track_type != 0) 4517 return; 4518 4519 if (!dm_info->pwr_trk_triggered) { 4520 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 4521 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 4522 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 4523 4524 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 4525 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 4526 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 4527 4528 dm_info->pwr_trk_triggered = true; 4529 return; 4530 } 4531 4532 __rtw8822c_pwr_track(rtwdev); 4533 dm_info->pwr_trk_triggered = false; 4534 } 4535 4536 static void rtw8822c_adaptivity_init(struct rtw_dev *rtwdev) 4537 { 4538 rtw_phy_set_edcca_th(rtwdev, RTW8822C_EDCCA_MAX, RTW8822C_EDCCA_MAX); 4539 4540 /* mac edcca state setting */ 4541 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA); 4542 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN); 4543 4544 /* edcca decistion opt */ 4545 rtw_write32_clr(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION); 4546 } 4547 4548 static void rtw8822c_adaptivity(struct rtw_dev *rtwdev) 4549 { 4550 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4551 s8 l2h, h2l; 4552 u8 igi; 4553 4554 igi = dm_info->igi_history[0]; 4555 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) { 4556 l2h = max_t(s8, igi + EDCCA_IGI_L2H_DIFF, EDCCA_TH_L2H_LB); 4557 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL; 4558 } else { 4559 if (igi < dm_info->l2h_th_ini - EDCCA_ADC_BACKOFF) 4560 l2h = igi + EDCCA_ADC_BACKOFF; 4561 else 4562 l2h = dm_info->l2h_th_ini; 4563 h2l = l2h - EDCCA_L2H_H2L_DIFF; 4564 } 4565 4566 rtw_phy_set_edcca_th(rtwdev, l2h, h2l); 4567 } 4568 4569 static void rtw8822c_fill_txdesc_checksum(struct rtw_dev *rtwdev, 4570 struct rtw_tx_pkt_info *pkt_info, 4571 u8 *txdesc) 4572 { 4573 const struct rtw_chip_info *chip = rtwdev->chip; 4574 size_t words; 4575 4576 words = (pkt_info->pkt_offset * 8 + chip->tx_pkt_desc_sz) / 2; 4577 4578 fill_txdesc_checksum_common(txdesc, words); 4579 } 4580 4581 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 4582 {0x0086, 4583 RTW_PWR_CUT_ALL_MSK, 4584 RTW_PWR_INTF_SDIO_MSK, 4585 RTW_PWR_ADDR_SDIO, 4586 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4587 {0x0086, 4588 RTW_PWR_CUT_ALL_MSK, 4589 RTW_PWR_INTF_SDIO_MSK, 4590 RTW_PWR_ADDR_SDIO, 4591 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 4592 {0x002E, 4593 RTW_PWR_CUT_ALL_MSK, 4594 RTW_PWR_INTF_ALL_MSK, 4595 RTW_PWR_ADDR_MAC, 4596 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4597 {0x002D, 4598 RTW_PWR_CUT_ALL_MSK, 4599 RTW_PWR_INTF_ALL_MSK, 4600 RTW_PWR_ADDR_MAC, 4601 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4602 {0x007F, 4603 RTW_PWR_CUT_ALL_MSK, 4604 RTW_PWR_INTF_ALL_MSK, 4605 RTW_PWR_ADDR_MAC, 4606 RTW_PWR_CMD_WRITE, BIT(7), 0}, 4607 {0x004A, 4608 RTW_PWR_CUT_ALL_MSK, 4609 RTW_PWR_INTF_USB_MSK, 4610 RTW_PWR_ADDR_MAC, 4611 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4612 {0x0005, 4613 RTW_PWR_CUT_ALL_MSK, 4614 RTW_PWR_INTF_ALL_MSK, 4615 RTW_PWR_ADDR_MAC, 4616 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 4617 {0xFFFF, 4618 RTW_PWR_CUT_ALL_MSK, 4619 RTW_PWR_INTF_ALL_MSK, 4620 0, 4621 RTW_PWR_CMD_END, 0, 0}, 4622 }; 4623 4624 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 4625 {0x0000, 4626 RTW_PWR_CUT_ALL_MSK, 4627 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4628 RTW_PWR_ADDR_MAC, 4629 RTW_PWR_CMD_WRITE, BIT(5), 0}, 4630 {0x0005, 4631 RTW_PWR_CUT_ALL_MSK, 4632 RTW_PWR_INTF_ALL_MSK, 4633 RTW_PWR_ADDR_MAC, 4634 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 4635 {0x0075, 4636 RTW_PWR_CUT_ALL_MSK, 4637 RTW_PWR_INTF_PCI_MSK, 4638 RTW_PWR_ADDR_MAC, 4639 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4640 {0x0006, 4641 RTW_PWR_CUT_ALL_MSK, 4642 RTW_PWR_INTF_ALL_MSK, 4643 RTW_PWR_ADDR_MAC, 4644 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 4645 {0x0075, 4646 RTW_PWR_CUT_ALL_MSK, 4647 RTW_PWR_INTF_PCI_MSK, 4648 RTW_PWR_ADDR_MAC, 4649 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4650 {0xFF1A, 4651 RTW_PWR_CUT_ALL_MSK, 4652 RTW_PWR_INTF_USB_MSK, 4653 RTW_PWR_ADDR_MAC, 4654 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4655 {0x002E, 4656 RTW_PWR_CUT_ALL_MSK, 4657 RTW_PWR_INTF_ALL_MSK, 4658 RTW_PWR_ADDR_MAC, 4659 RTW_PWR_CMD_WRITE, BIT(3), 0}, 4660 {0x0006, 4661 RTW_PWR_CUT_ALL_MSK, 4662 RTW_PWR_INTF_ALL_MSK, 4663 RTW_PWR_ADDR_MAC, 4664 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4665 {0x0005, 4666 RTW_PWR_CUT_ALL_MSK, 4667 RTW_PWR_INTF_ALL_MSK, 4668 RTW_PWR_ADDR_MAC, 4669 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 4670 {0x1018, 4671 RTW_PWR_CUT_ALL_MSK, 4672 RTW_PWR_INTF_ALL_MSK, 4673 RTW_PWR_ADDR_MAC, 4674 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4675 {0x0005, 4676 RTW_PWR_CUT_ALL_MSK, 4677 RTW_PWR_INTF_ALL_MSK, 4678 RTW_PWR_ADDR_MAC, 4679 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4680 {0x0005, 4681 RTW_PWR_CUT_ALL_MSK, 4682 RTW_PWR_INTF_ALL_MSK, 4683 RTW_PWR_ADDR_MAC, 4684 RTW_PWR_CMD_POLLING, BIT(0), 0}, 4685 {0x0074, 4686 RTW_PWR_CUT_ALL_MSK, 4687 RTW_PWR_INTF_PCI_MSK, 4688 RTW_PWR_ADDR_MAC, 4689 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 4690 {0x0071, 4691 RTW_PWR_CUT_ALL_MSK, 4692 RTW_PWR_INTF_PCI_MSK, 4693 RTW_PWR_ADDR_MAC, 4694 RTW_PWR_CMD_WRITE, BIT(4), 0}, 4695 {0x0062, 4696 RTW_PWR_CUT_ALL_MSK, 4697 RTW_PWR_INTF_PCI_MSK, 4698 RTW_PWR_ADDR_MAC, 4699 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 4700 (BIT(7) | BIT(6) | BIT(5))}, 4701 {0x0061, 4702 RTW_PWR_CUT_ALL_MSK, 4703 RTW_PWR_INTF_PCI_MSK, 4704 RTW_PWR_ADDR_MAC, 4705 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 4706 {0x001F, 4707 RTW_PWR_CUT_ALL_MSK, 4708 RTW_PWR_INTF_ALL_MSK, 4709 RTW_PWR_ADDR_MAC, 4710 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 4711 {0x00EF, 4712 RTW_PWR_CUT_ALL_MSK, 4713 RTW_PWR_INTF_ALL_MSK, 4714 RTW_PWR_ADDR_MAC, 4715 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 4716 {0x1045, 4717 RTW_PWR_CUT_ALL_MSK, 4718 RTW_PWR_INTF_ALL_MSK, 4719 RTW_PWR_ADDR_MAC, 4720 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 4721 {0x0010, 4722 RTW_PWR_CUT_ALL_MSK, 4723 RTW_PWR_INTF_ALL_MSK, 4724 RTW_PWR_ADDR_MAC, 4725 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4726 {0x1064, 4727 RTW_PWR_CUT_ALL_MSK, 4728 RTW_PWR_INTF_ALL_MSK, 4729 RTW_PWR_ADDR_MAC, 4730 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 4731 {0xFFFF, 4732 RTW_PWR_CUT_ALL_MSK, 4733 RTW_PWR_INTF_ALL_MSK, 4734 0, 4735 RTW_PWR_CMD_END, 0, 0}, 4736 }; 4737 4738 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 4739 {0x0093, 4740 RTW_PWR_CUT_ALL_MSK, 4741 RTW_PWR_INTF_ALL_MSK, 4742 RTW_PWR_ADDR_MAC, 4743 RTW_PWR_CMD_WRITE, BIT(3), 0}, 4744 {0x001F, 4745 RTW_PWR_CUT_ALL_MSK, 4746 RTW_PWR_INTF_ALL_MSK, 4747 RTW_PWR_ADDR_MAC, 4748 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4749 {0x00EF, 4750 RTW_PWR_CUT_ALL_MSK, 4751 RTW_PWR_INTF_ALL_MSK, 4752 RTW_PWR_ADDR_MAC, 4753 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4754 {0x1045, 4755 RTW_PWR_CUT_ALL_MSK, 4756 RTW_PWR_INTF_ALL_MSK, 4757 RTW_PWR_ADDR_MAC, 4758 RTW_PWR_CMD_WRITE, BIT(4), 0}, 4759 {0xFF1A, 4760 RTW_PWR_CUT_ALL_MSK, 4761 RTW_PWR_INTF_USB_MSK, 4762 RTW_PWR_ADDR_MAC, 4763 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 4764 {0x0049, 4765 RTW_PWR_CUT_ALL_MSK, 4766 RTW_PWR_INTF_ALL_MSK, 4767 RTW_PWR_ADDR_MAC, 4768 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4769 {0x0006, 4770 RTW_PWR_CUT_ALL_MSK, 4771 RTW_PWR_INTF_ALL_MSK, 4772 RTW_PWR_ADDR_MAC, 4773 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4774 {0x0002, 4775 RTW_PWR_CUT_ALL_MSK, 4776 RTW_PWR_INTF_ALL_MSK, 4777 RTW_PWR_ADDR_MAC, 4778 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4779 {0x0005, 4780 RTW_PWR_CUT_ALL_MSK, 4781 RTW_PWR_INTF_ALL_MSK, 4782 RTW_PWR_ADDR_MAC, 4783 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 4784 {0x0005, 4785 RTW_PWR_CUT_ALL_MSK, 4786 RTW_PWR_INTF_ALL_MSK, 4787 RTW_PWR_ADDR_MAC, 4788 RTW_PWR_CMD_POLLING, BIT(1), 0}, 4789 {0x0000, 4790 RTW_PWR_CUT_ALL_MSK, 4791 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4792 RTW_PWR_ADDR_MAC, 4793 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 4794 {0xFFFF, 4795 RTW_PWR_CUT_ALL_MSK, 4796 RTW_PWR_INTF_ALL_MSK, 4797 0, 4798 RTW_PWR_CMD_END, 0, 0}, 4799 }; 4800 4801 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 4802 {0x0005, 4803 RTW_PWR_CUT_ALL_MSK, 4804 RTW_PWR_INTF_SDIO_MSK, 4805 RTW_PWR_ADDR_MAC, 4806 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 4807 {0x0007, 4808 RTW_PWR_CUT_ALL_MSK, 4809 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4810 RTW_PWR_ADDR_MAC, 4811 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 4812 {0x0067, 4813 RTW_PWR_CUT_ALL_MSK, 4814 RTW_PWR_INTF_ALL_MSK, 4815 RTW_PWR_ADDR_MAC, 4816 RTW_PWR_CMD_WRITE, BIT(5), 0}, 4817 {0x004A, 4818 RTW_PWR_CUT_ALL_MSK, 4819 RTW_PWR_INTF_USB_MSK, 4820 RTW_PWR_ADDR_MAC, 4821 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4822 {0x0081, 4823 RTW_PWR_CUT_ALL_MSK, 4824 RTW_PWR_INTF_ALL_MSK, 4825 RTW_PWR_ADDR_MAC, 4826 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 4827 {0x0090, 4828 RTW_PWR_CUT_ALL_MSK, 4829 RTW_PWR_INTF_ALL_MSK, 4830 RTW_PWR_ADDR_MAC, 4831 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4832 {0x0092, 4833 RTW_PWR_CUT_ALL_MSK, 4834 RTW_PWR_INTF_PCI_MSK, 4835 RTW_PWR_ADDR_MAC, 4836 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 4837 {0x0093, 4838 RTW_PWR_CUT_ALL_MSK, 4839 RTW_PWR_INTF_PCI_MSK, 4840 RTW_PWR_ADDR_MAC, 4841 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 4842 {0x0005, 4843 RTW_PWR_CUT_ALL_MSK, 4844 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4845 RTW_PWR_ADDR_MAC, 4846 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 4847 {0x0005, 4848 RTW_PWR_CUT_ALL_MSK, 4849 RTW_PWR_INTF_PCI_MSK, 4850 RTW_PWR_ADDR_MAC, 4851 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4852 {0x0086, 4853 RTW_PWR_CUT_ALL_MSK, 4854 RTW_PWR_INTF_SDIO_MSK, 4855 RTW_PWR_ADDR_SDIO, 4856 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4857 {0xFFFF, 4858 RTW_PWR_CUT_ALL_MSK, 4859 RTW_PWR_INTF_ALL_MSK, 4860 0, 4861 RTW_PWR_CMD_END, 0, 0}, 4862 }; 4863 4864 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 4865 trans_carddis_to_cardemu_8822c, 4866 trans_cardemu_to_act_8822c, 4867 NULL 4868 }; 4869 4870 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 4871 trans_act_to_cardemu_8822c, 4872 trans_cardemu_to_carddis_8822c, 4873 NULL 4874 }; 4875 4876 static const struct rtw_intf_phy_para usb2_param_8822c[] = { 4877 {0xFFFF, 0x00, 4878 RTW_IP_SEL_PHY, 4879 RTW_INTF_PHY_CUT_ALL, 4880 RTW_INTF_PHY_PLATFORM_ALL}, 4881 }; 4882 4883 static const struct rtw_intf_phy_para usb3_param_8822c[] = { 4884 {0xFFFF, 0x0000, 4885 RTW_IP_SEL_PHY, 4886 RTW_INTF_PHY_CUT_ALL, 4887 RTW_INTF_PHY_PLATFORM_ALL}, 4888 }; 4889 4890 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 4891 {0xFFFF, 0x0000, 4892 RTW_IP_SEL_PHY, 4893 RTW_INTF_PHY_CUT_ALL, 4894 RTW_INTF_PHY_PLATFORM_ALL}, 4895 }; 4896 4897 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 4898 {0xFFFF, 0x0000, 4899 RTW_IP_SEL_PHY, 4900 RTW_INTF_PHY_CUT_ALL, 4901 RTW_INTF_PHY_PLATFORM_ALL}, 4902 }; 4903 4904 static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 4905 .usb2_para = usb2_param_8822c, 4906 .usb3_para = usb3_param_8822c, 4907 .gen1_para = pcie_gen1_param_8822c, 4908 .gen2_para = pcie_gen2_param_8822c, 4909 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 4910 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 4911 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 4912 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 4913 }; 4914 4915 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 4916 [0] = RTW_DEF_RFE(8822c, 0, 0), 4917 [1] = RTW_DEF_RFE(8822c, 0, 0), 4918 [2] = RTW_DEF_RFE(8822c, 0, 0), 4919 [3] = RTW_DEF_RFE(8822c, 0, 0), 4920 [4] = RTW_DEF_RFE(8822c, 0, 0), 4921 [5] = RTW_DEF_RFE(8822c, 0, 5), 4922 [6] = RTW_DEF_RFE(8822c, 0, 0), 4923 }; 4924 4925 static const struct rtw_hw_reg rtw8822c_dig[] = { 4926 [0] = { .addr = 0x1d70, .mask = 0x7f }, 4927 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 4928 }; 4929 4930 static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = { 4931 .ctrl = LTECOEX_ACCESS_CTRL, 4932 .wdata = LTECOEX_WRITE_DATA, 4933 .rdata = LTECOEX_READ_DATA, 4934 }; 4935 4936 static const struct rtw_page_table page_table_8822c[] = { 4937 {64, 64, 64, 64, 1}, 4938 {64, 64, 64, 64, 1}, 4939 {64, 64, 0, 0, 1}, 4940 {64, 64, 64, 0, 1}, 4941 {64, 64, 64, 64, 1}, 4942 }; 4943 4944 static const struct rtw_rqpn rqpn_table_8822c[] = { 4945 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4946 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4947 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4948 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4949 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4950 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4951 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4952 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 4953 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 4954 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4955 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4956 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 4957 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4958 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4959 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4960 }; 4961 4962 static struct rtw_prioq_addrs prioq_addrs_8822c = { 4963 .prio[RTW_DMA_MAPPING_EXTRA] = { 4964 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 4965 }, 4966 .prio[RTW_DMA_MAPPING_LOW] = { 4967 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 4968 }, 4969 .prio[RTW_DMA_MAPPING_NORMAL] = { 4970 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 4971 }, 4972 .prio[RTW_DMA_MAPPING_HIGH] = { 4973 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 4974 }, 4975 .wsize = true, 4976 }; 4977 4978 static struct rtw_chip_ops rtw8822c_ops = { 4979 .phy_set_param = rtw8822c_phy_set_param, 4980 .read_efuse = rtw8822c_read_efuse, 4981 .query_rx_desc = rtw8822c_query_rx_desc, 4982 .set_channel = rtw8822c_set_channel, 4983 .mac_init = rtw8822c_mac_init, 4984 .dump_fw_crash = rtw8822c_dump_fw_crash, 4985 .read_rf = rtw_phy_read_rf, 4986 .write_rf = rtw_phy_write_rf_reg_mix, 4987 .set_tx_power_index = rtw8822c_set_tx_power_index, 4988 .set_antenna = rtw8822c_set_antenna, 4989 .cfg_ldo25 = rtw8822c_cfg_ldo25, 4990 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 4991 .dpk_track = rtw8822c_dpk_track, 4992 .phy_calibration = rtw8822c_phy_calibration, 4993 .cck_pd_set = rtw8822c_phy_cck_pd_set, 4994 .pwr_track = rtw8822c_pwr_track, 4995 .config_bfee = rtw8822c_bf_config_bfee, 4996 .set_gid_table = rtw_bf_set_gid_table, 4997 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 4998 .adaptivity_init = rtw8822c_adaptivity_init, 4999 .adaptivity = rtw8822c_adaptivity, 5000 .cfo_init = rtw8822c_cfo_init, 5001 .cfo_track = rtw8822c_cfo_track, 5002 .config_tx_path = rtw8822c_config_tx_path, 5003 .config_txrx_mode = rtw8822c_config_trx_mode, 5004 .fill_txdesc_checksum = rtw8822c_fill_txdesc_checksum, 5005 5006 .coex_set_init = rtw8822c_coex_cfg_init, 5007 .coex_set_ant_switch = NULL, 5008 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 5009 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 5010 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 5011 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 5012 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 5013 }; 5014 5015 /* Shared-Antenna Coex Table */ 5016 static const struct coex_table_para table_sant_8822c[] = { 5017 {0xffffffff, 0xffffffff}, /* case-0 */ 5018 {0x55555555, 0x55555555}, 5019 {0x66555555, 0x66555555}, 5020 {0xaaaaaaaa, 0xaaaaaaaa}, 5021 {0x5a5a5a5a, 0x5a5a5a5a}, 5022 {0xfafafafa, 0xfafafafa}, /* case-5 */ 5023 {0x6a5a5555, 0xaaaaaaaa}, 5024 {0x6a5a56aa, 0x6a5a56aa}, 5025 {0x6a5a5a5a, 0x6a5a5a5a}, 5026 {0x66555555, 0x5a5a5a5a}, 5027 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 5028 {0x66555555, 0x6a5a5aaa}, 5029 {0x66555555, 0x5a5a5aaa}, 5030 {0x66555555, 0x6aaa5aaa}, 5031 {0x66555555, 0xaaaa5aaa}, 5032 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 5033 {0xffff55ff, 0xfafafafa}, 5034 {0xffff55ff, 0x6afa5afa}, 5035 {0xaaffffaa, 0xfafafafa}, 5036 {0xaa5555aa, 0x5a5a5a5a}, 5037 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 5038 {0xaa5555aa, 0xaaaaaaaa}, 5039 {0xffffffff, 0x5a5a5a5a}, 5040 {0xffffffff, 0x5a5a5a5a}, 5041 {0xffffffff, 0x55555555}, 5042 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 5043 {0x55555555, 0x5a5a5a5a}, 5044 {0x55555555, 0xaaaaaaaa}, 5045 {0x55555555, 0x6a5a6a5a}, 5046 {0x66556655, 0x66556655}, 5047 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/ 5048 {0xffffffff, 0x5aaa5aaa}, 5049 {0x56555555, 0x5a5a5aaa}, 5050 {0xdaffdaff, 0xdaffdaff}, 5051 {0xddffddff, 0xddffddff}, 5052 }; 5053 5054 /* Non-Shared-Antenna Coex Table */ 5055 static const struct coex_table_para table_nsant_8822c[] = { 5056 {0xffffffff, 0xffffffff}, /* case-100 */ 5057 {0x55555555, 0x55555555}, 5058 {0x66555555, 0x66555555}, 5059 {0xaaaaaaaa, 0xaaaaaaaa}, 5060 {0x5a5a5a5a, 0x5a5a5a5a}, 5061 {0xfafafafa, 0xfafafafa}, /* case-105 */ 5062 {0x5afa5afa, 0x5afa5afa}, 5063 {0x55555555, 0xfafafafa}, 5064 {0x66555555, 0xfafafafa}, 5065 {0x66555555, 0x5a5a5a5a}, 5066 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 5067 {0x66555555, 0xaaaaaaaa}, 5068 {0xffff55ff, 0xfafafafa}, 5069 {0xffff55ff, 0x5afa5afa}, 5070 {0xffff55ff, 0xaaaaaaaa}, 5071 {0xffff55ff, 0xffff55ff}, /* case-115 */ 5072 {0xaaffffaa, 0x5afa5afa}, 5073 {0xaaffffaa, 0xaaaaaaaa}, 5074 {0xffffffff, 0xfafafafa}, 5075 {0xffffffff, 0x5afa5afa}, 5076 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 5077 {0x55ff55ff, 0x5afa5afa}, 5078 {0x55ff55ff, 0xaaaaaaaa}, 5079 {0x55ff55ff, 0x55ff55ff} 5080 }; 5081 5082 /* Shared-Antenna TDMA */ 5083 static const struct coex_tdma_para tdma_sant_8822c[] = { 5084 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 5085 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 5086 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 5087 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 5088 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 5089 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 5090 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 5091 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 5092 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 5093 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 5094 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 5095 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 5096 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 5097 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 5098 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 5099 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 5100 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 5101 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 5102 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 5103 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 5104 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 5105 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 5106 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 5107 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 5108 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 5109 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 5110 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 5111 { {0x61, 0x08, 0x03, 0x11, 0x11} } 5112 }; 5113 5114 /* Non-Shared-Antenna TDMA */ 5115 static const struct coex_tdma_para tdma_nsant_8822c[] = { 5116 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 5117 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 5118 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 5119 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 5120 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 5121 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 5122 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 5123 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 5124 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 5125 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 5126 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 5127 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 5128 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 5129 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 5130 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 5131 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 5132 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 5133 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 5134 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 5135 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 5136 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 5137 { {0x51, 0x08, 0x03, 0x10, 0x50} } 5138 }; 5139 5140 /* rssi in percentage % (dbm = % - 100) */ 5141 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 5142 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 5143 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 5144 5145 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 5146 static const struct coex_rf_para rf_para_tx_8822c[] = { 5147 {0, 0, false, 7}, /* for normal */ 5148 {0, 16, false, 7}, /* for WL-CPT */ 5149 {8, 17, true, 4}, 5150 {7, 18, true, 4}, 5151 {6, 19, true, 4}, 5152 {5, 20, true, 4}, 5153 {0, 21, true, 4} /* for gamg hid */ 5154 }; 5155 5156 static const struct coex_rf_para rf_para_rx_8822c[] = { 5157 {0, 0, false, 7}, /* for normal */ 5158 {0, 16, false, 7}, /* for WL-CPT */ 5159 {3, 24, true, 5}, 5160 {2, 26, true, 5}, 5161 {1, 27, true, 5}, 5162 {0, 28, true, 5}, 5163 {0, 28, true, 5} /* for gamg hid */ 5164 }; 5165 5166 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 5167 5168 static const u8 5169 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5170 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5171 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5172 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5173 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5174 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5175 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5176 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5177 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5178 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5179 }; 5180 5181 static const u8 5182 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5183 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5184 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5185 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5186 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5187 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5188 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5189 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5190 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5191 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5192 }; 5193 5194 static const u8 5195 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5196 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5197 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5198 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5199 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5200 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5201 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5202 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5203 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5204 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5205 }; 5206 5207 static const u8 5208 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5209 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5210 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5211 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5212 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5213 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5214 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5215 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5216 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5217 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5218 }; 5219 5220 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 5221 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 5222 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 5223 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 5224 }; 5225 5226 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 5227 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5228 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 5229 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 5230 }; 5231 5232 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 5233 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 5234 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 5235 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 5236 }; 5237 5238 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 5239 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5240 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 5241 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 5242 }; 5243 5244 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 5245 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 5246 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 5247 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 5248 }; 5249 5250 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 5251 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5252 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 5253 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 5254 }; 5255 5256 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 5257 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 5258 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 5259 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 5260 }; 5261 5262 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 5263 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 5264 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 5265 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 5266 }; 5267 5268 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 5269 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 5270 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 5271 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 5272 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 5273 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 5274 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 5275 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 5276 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 5277 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 5278 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 5279 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 5280 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 5281 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 5282 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 5283 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 5284 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 5285 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 5286 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 5287 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 5288 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 5289 }; 5290 5291 static struct rtw_hw_reg_offset rtw8822c_edcca_th[] = { 5292 [EDCCA_TH_L2H_IDX] = { 5293 {.addr = 0x84c, .mask = MASKBYTE2}, .offset = 0x80 5294 }, 5295 [EDCCA_TH_H2L_IDX] = { 5296 {.addr = 0x84c, .mask = MASKBYTE3}, .offset = 0x80 5297 }, 5298 }; 5299 5300 #ifdef CONFIG_PM 5301 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 5302 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 5303 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 5304 WIPHY_WOWLAN_NET_DETECT, 5305 .n_patterns = RTW_MAX_PATTERN_NUM, 5306 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 5307 .pattern_min_len = 1, 5308 .max_nd_match_sets = 4, 5309 }; 5310 #endif 5311 5312 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 5313 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 5314 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 5315 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 5316 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 5317 {0, 0, RTW_REG_DOMAIN_NL}, 5318 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5319 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5320 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 5321 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5322 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 5323 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 5324 {0, 0, RTW_REG_DOMAIN_NL}, 5325 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 5326 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 5327 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 5328 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 5329 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 5330 {0, 0, RTW_REG_DOMAIN_NL}, 5331 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5332 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5333 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 5334 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5335 }; 5336 5337 const struct rtw_chip_info rtw8822c_hw_spec = { 5338 .ops = &rtw8822c_ops, 5339 .id = RTW_CHIP_TYPE_8822C, 5340 .fw_name = "rtw88/rtw8822c_fw.bin", 5341 .wlan_cpu = RTW_WCPU_11AC, 5342 .tx_pkt_desc_sz = 48, 5343 .tx_buf_desc_sz = 16, 5344 .rx_pkt_desc_sz = 24, 5345 .rx_buf_desc_sz = 8, 5346 .phy_efuse_size = 512, 5347 .log_efuse_size = 768, 5348 .ptct_efuse_size = 124, 5349 .txff_size = 262144, 5350 .rxff_size = 24576, 5351 .fw_rxff_size = 12288, 5352 .txgi_factor = 2, 5353 .is_pwr_by_rate_dec = false, 5354 .max_power_index = 0x7f, 5355 .csi_buf_pg_num = 50, 5356 .band = RTW_BAND_2G | RTW_BAND_5G, 5357 .page_size = TX_PAGE_SIZE, 5358 .dig_min = 0x20, 5359 .default_1ss_tx_path = BB_PATH_A, 5360 .path_div_supported = true, 5361 .ht_supported = true, 5362 .vht_supported = true, 5363 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 5364 .sys_func_en = 0xD8, 5365 .pwr_on_seq = card_enable_flow_8822c, 5366 .pwr_off_seq = card_disable_flow_8822c, 5367 .page_table = page_table_8822c, 5368 .rqpn_table = rqpn_table_8822c, 5369 .prioq_addrs = &prioq_addrs_8822c, 5370 .intf_table = &phy_para_table_8822c, 5371 .dig = rtw8822c_dig, 5372 .dig_cck = NULL, 5373 .rf_base_addr = {0x3c00, 0x4c00}, 5374 .rf_sipi_addr = {0x1808, 0x4108}, 5375 .ltecoex_addr = &rtw8822c_ltecoex_addr, 5376 .mac_tbl = &rtw8822c_mac_tbl, 5377 .agc_tbl = &rtw8822c_agc_tbl, 5378 .bb_tbl = &rtw8822c_bb_tbl, 5379 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 5380 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 5381 .rfe_defs = rtw8822c_rfe_defs, 5382 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 5383 .en_dis_dpd = true, 5384 .dpd_ratemask = DIS_DPD_RATEALL, 5385 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 5386 .iqk_threshold = 8, 5387 .lck_threshold = 8, 5388 .bfer_su_max_num = 2, 5389 .bfer_mu_max_num = 1, 5390 .rx_ldpc = true, 5391 .tx_stbc = true, 5392 .edcca_th = rtw8822c_edcca_th, 5393 .l2h_th_ini_cs = 60, 5394 .l2h_th_ini_ad = 45, 5395 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 5396 5397 #ifdef CONFIG_PM 5398 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 5399 .wowlan_stub = &rtw_wowlan_stub_8822c, 5400 .max_sched_scan_ssids = 4, 5401 #endif 5402 .max_scan_ie_len = (RTW_PROBE_PG_CNT - 1) * TX_PAGE_SIZE, 5403 .coex_para_ver = 0x22020720, 5404 .bt_desired_ver = 0x20, 5405 .scbd_support = true, 5406 .new_scbd10_def = true, 5407 .ble_hid_profile_support = true, 5408 .wl_mimo_ps_support = true, 5409 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 5410 .bt_rssi_type = COEX_BTRSSI_DBM, 5411 .ant_isolation = 15, 5412 .rssi_tolerance = 2, 5413 .wl_rssi_step = wl_rssi_step_8822c, 5414 .bt_rssi_step = bt_rssi_step_8822c, 5415 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 5416 .table_sant = table_sant_8822c, 5417 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 5418 .table_nsant = table_nsant_8822c, 5419 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 5420 .tdma_sant = tdma_sant_8822c, 5421 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 5422 .tdma_nsant = tdma_nsant_8822c, 5423 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 5424 .wl_rf_para_tx = rf_para_tx_8822c, 5425 .wl_rf_para_rx = rf_para_rx_8822c, 5426 .bt_afh_span_bw20 = 0x24, 5427 .bt_afh_span_bw40 = 0x36, 5428 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 5429 .afh_5g = afh_5g_8822c, 5430 5431 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 5432 .coex_info_hw_regs = coex_info_hw_regs_8822c, 5433 5434 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 5435 .fwcd_segs = &rtw8822c_fwcd_segs, 5436 }; 5437 EXPORT_SYMBOL(rtw8822c_hw_spec); 5438 5439 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 5440 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 5441 5442 MODULE_AUTHOR("Realtek Corporation"); 5443 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver"); 5444 MODULE_LICENSE("Dual BSD/GPL"); 5445