1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822c.h" 13 #include "rtw8822c_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "util.h" 18 #include "bf.h" 19 #include "efuse.h" 20 21 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 22 u8 rx_path, bool is_tx2_path); 23 24 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 25 struct rtw8822c_efuse *map) 26 { 27 ether_addr_copy(efuse->addr, map->e.mac_addr); 28 } 29 30 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 31 { 32 struct rtw_efuse *efuse = &rtwdev->efuse; 33 struct rtw8822c_efuse *map; 34 int i; 35 36 map = (struct rtw8822c_efuse *)log_map; 37 38 efuse->rfe_option = map->rfe_option; 39 efuse->rf_board_option = map->rf_board_option; 40 efuse->crystal_cap = map->xtal_k; 41 efuse->channel_plan = map->channel_plan; 42 efuse->country_code[0] = map->country_code[0]; 43 efuse->country_code[1] = map->country_code[1]; 44 efuse->bt_setting = map->rf_bt_setting; 45 efuse->regd = map->rf_board_option & 0x7; 46 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 47 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 48 efuse->thermal_meter_k = 49 (map->path_a_thermal + map->path_b_thermal) >> 1; 50 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 51 52 for (i = 0; i < 4; i++) 53 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 54 55 switch (rtw_hci_type(rtwdev)) { 56 case RTW_HCI_TYPE_PCIE: 57 rtw8822ce_efuse_parsing(efuse, map); 58 break; 59 default: 60 /* unsupported now */ 61 return -ENOTSUPP; 62 } 63 64 return 0; 65 } 66 67 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 68 { 69 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 70 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 71 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 72 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 73 74 if (pre) 75 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 76 else 77 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 78 } 79 80 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 81 struct rtw_backup_info *backup, 82 struct rtw_backup_info *backup_rf) 83 { 84 u32 path, i; 85 u32 val; 86 u32 reg; 87 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 88 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 89 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 90 0x1a00, 0x1a14, 0x1d58, 0x1c38, 91 0x1e24, 0x1e28, 0x1860, 0x4160}; 92 93 for (i = 0; i < DACK_REG_8822C; i++) { 94 backup[i].len = 4; 95 backup[i].reg = addrs[i]; 96 backup[i].val = rtw_read32(rtwdev, addrs[i]); 97 } 98 99 for (path = 0; path < DACK_PATH_8822C; path++) { 100 for (i = 0; i < DACK_RF_8822C; i++) { 101 reg = rf_addr[i]; 102 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 103 backup_rf[path * i + i].reg = reg; 104 backup_rf[path * i + i].val = val; 105 } 106 } 107 } 108 109 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 110 struct rtw_backup_info *backup, 111 struct rtw_backup_info *backup_rf) 112 { 113 u32 path, i; 114 u32 val; 115 u32 reg; 116 117 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 118 119 for (path = 0; path < DACK_PATH_8822C; path++) { 120 for (i = 0; i < DACK_RF_8822C; i++) { 121 val = backup_rf[path * i + i].val; 122 reg = backup_rf[path * i + i].reg; 123 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 124 } 125 } 126 } 127 128 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 129 u32 *min, u32 *max) 130 { 131 if (value >= 0x200) { 132 if (*min >= 0x200) { 133 if (*min > value) 134 *min = value; 135 } else { 136 *min = value; 137 } 138 if (*max >= 0x200) { 139 if (*max < value) 140 *max = value; 141 } 142 } else { 143 if (*min < 0x200) { 144 if (*min > value) 145 *min = value; 146 } 147 148 if (*max >= 0x200) { 149 *max = value; 150 } else { 151 if (*max < value) 152 *max = value; 153 } 154 } 155 } 156 157 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 158 { 159 if (*v1 >= 0x200 && *v2 >= 0x200) { 160 if (*v1 > *v2) 161 swap(*v1, *v2); 162 } else if (*v1 < 0x200 && *v2 < 0x200) { 163 if (*v1 > *v2) 164 swap(*v1, *v2); 165 } else if (*v1 < 0x200 && *v2 >= 0x200) { 166 swap(*v1, *v2); 167 } 168 } 169 170 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 171 { 172 u32 i, j; 173 174 for (i = 0; i < DACK_SN_8822C - 1; i++) { 175 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 176 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 177 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 178 } 179 } 180 } 181 182 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 183 { 184 u32 p, m, t, i; 185 186 m = 0; 187 p = 0; 188 for (i = 10; i < DACK_SN_8822C - 10; i++) { 189 if (vec[i] > 0x200) 190 m = (0x400 - vec[i]) + m; 191 else 192 p = vec[i] + p; 193 } 194 195 if (p > m) { 196 t = p - m; 197 t = t / (DACK_SN_8822C - 20); 198 } else { 199 t = m - p; 200 t = t / (DACK_SN_8822C - 20); 201 if (t != 0x0) 202 t = 0x400 - t; 203 } 204 205 *val = t; 206 } 207 208 static u32 rtw8822c_get_path_write_addr(u8 path) 209 { 210 u32 base_addr; 211 212 switch (path) { 213 case RF_PATH_A: 214 base_addr = 0x1800; 215 break; 216 case RF_PATH_B: 217 base_addr = 0x4100; 218 break; 219 default: 220 WARN_ON(1); 221 return -1; 222 } 223 224 return base_addr; 225 } 226 227 static u32 rtw8822c_get_path_read_addr(u8 path) 228 { 229 u32 base_addr; 230 231 switch (path) { 232 case RF_PATH_A: 233 base_addr = 0x2800; 234 break; 235 case RF_PATH_B: 236 base_addr = 0x4500; 237 break; 238 default: 239 WARN_ON(1); 240 return -1; 241 } 242 243 return base_addr; 244 } 245 246 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 247 { 248 bool ret = true; 249 250 if ((value >= 0x200 && (0x400 - value) > 0x64) || 251 (value < 0x200 && value > 0x64)) { 252 ret = false; 253 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 254 } 255 256 return ret; 257 } 258 259 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 260 { 261 u32 temp; 262 int i = 0, cnt = 0; 263 264 while (i < DACK_SN_8822C && cnt < 10000) { 265 cnt++; 266 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 267 iv[i] = (temp & 0x3ff000) >> 12; 268 qv[i] = temp & 0x3ff; 269 270 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 271 rtw8822c_dac_iq_check(rtwdev, qv[i])) 272 i++; 273 } 274 } 275 276 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 277 u32 *iv, u32 *qv, 278 u32 *i_value, u32 *q_value) 279 { 280 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 281 u32 i_delta, q_delta; 282 u32 temp; 283 int i, cnt = 0; 284 285 do { 286 i_min = iv[0]; 287 i_max = iv[0]; 288 q_min = qv[0]; 289 q_max = qv[0]; 290 for (i = 0; i < DACK_SN_8822C; i++) { 291 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 292 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 293 } 294 295 if (i_max < 0x200 && i_min < 0x200) 296 i_delta = i_max - i_min; 297 else if (i_max >= 0x200 && i_min >= 0x200) 298 i_delta = i_max - i_min; 299 else 300 i_delta = i_max + (0x400 - i_min); 301 302 if (q_max < 0x200 && q_min < 0x200) 303 q_delta = q_max - q_min; 304 else if (q_max >= 0x200 && q_min >= 0x200) 305 q_delta = q_max - q_min; 306 else 307 q_delta = q_max + (0x400 - q_min); 308 309 rtw_dbg(rtwdev, RTW_DBG_RFK, 310 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 311 i_min, i_max, i_delta); 312 rtw_dbg(rtwdev, RTW_DBG_RFK, 313 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 314 q_min, q_max, q_delta); 315 316 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 317 318 if (i_delta > 5 || q_delta > 5) { 319 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 320 iv[0] = (temp & 0x3ff000) >> 12; 321 qv[0] = temp & 0x3ff; 322 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 323 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 324 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 325 } else { 326 break; 327 } 328 } while (cnt++ < 100); 329 330 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 331 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 332 } 333 334 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 335 u32 *i_value, u32 *q_value) 336 { 337 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 338 u32 rf_a, rf_b; 339 340 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 341 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 342 343 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 344 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 345 346 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 347 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 348 } 349 350 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 351 { 352 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 353 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 354 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 355 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 356 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 357 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 358 rtw_write32(rtwdev, 0x1b00, 0x00000008); 359 rtw_write8(rtwdev, 0x1bcc, 0x3f); 360 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 361 rtw_write8(rtwdev, 0x1bcc, 0x3f); 362 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 363 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 364 } 365 366 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 367 u8 path, u32 *adc_ic, u32 *adc_qc) 368 { 369 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 370 u32 ic = 0, qc = 0, temp = 0; 371 u32 base_addr; 372 u32 path_sel; 373 int i; 374 375 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 376 377 base_addr = rtw8822c_get_path_write_addr(path); 378 switch (path) { 379 case RF_PATH_A: 380 path_sel = 0xa0000; 381 break; 382 case RF_PATH_B: 383 path_sel = 0x80000; 384 break; 385 default: 386 WARN_ON(1); 387 return; 388 } 389 390 /* ADCK step1 */ 391 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 392 if (path == RF_PATH_B) 393 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 394 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 395 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 396 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 397 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 398 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 399 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 400 for (i = 0; i < 10; i++) { 401 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 402 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 403 rtw_write32(rtwdev, 0x1c24, 0x00010002); 404 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 405 rtw_dbg(rtwdev, RTW_DBG_RFK, 406 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 407 408 /* compensation value */ 409 if (ic != 0x0) { 410 ic = 0x400 - ic; 411 *adc_ic = ic; 412 } 413 if (qc != 0x0) { 414 qc = 0x400 - qc; 415 *adc_qc = qc; 416 } 417 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 418 rtw_write32(rtwdev, base_addr + 0x68, temp); 419 dm_info->dack_adck[path] = temp; 420 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 421 base_addr + 0x68, temp); 422 /* check ADC DC offset */ 423 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 424 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 425 rtw_dbg(rtwdev, RTW_DBG_RFK, 426 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 427 if (ic >= 0x200) 428 ic = 0x400 - ic; 429 if (qc >= 0x200) 430 qc = 0x400 - qc; 431 if (ic < 5 && qc < 5) 432 break; 433 } 434 435 /* ADCK step2 */ 436 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 437 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 438 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 439 440 /* release pull low switch on IQ path */ 441 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 442 } 443 444 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 445 { 446 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 447 u32 base_addr; 448 u32 read_addr; 449 450 base_addr = rtw8822c_get_path_write_addr(path); 451 read_addr = rtw8822c_get_path_read_addr(path); 452 453 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 454 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 455 if (path == RF_PATH_A) { 456 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 457 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 458 } 459 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 460 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 461 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 462 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 463 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 464 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 465 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 466 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 467 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 468 mdelay(2); 469 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 470 mdelay(2); 471 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 472 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 473 mdelay(1); 474 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 475 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 476 mdelay(20); 477 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 478 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 479 rtw_err(rtwdev, "failed to wait for dack ready\n"); 480 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 481 mdelay(1); 482 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 483 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 484 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 485 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 486 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 487 } 488 489 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 490 u8 path, u32 *ic_out, u32 *qc_out) 491 { 492 u32 base_addr; 493 u32 ic, qc, ic_in, qc_in; 494 495 base_addr = rtw8822c_get_path_write_addr(path); 496 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 497 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 498 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 499 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 500 501 rtw_write32(rtwdev, 0x1b00, 0x00000008); 502 rtw_write8(rtwdev, 0x1bcc, 0x03f); 503 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 504 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 505 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 506 507 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 508 ic = ic_in; 509 qc = qc_in; 510 511 /* compensation value */ 512 if (ic != 0x0) 513 ic = 0x400 - ic; 514 if (qc != 0x0) 515 qc = 0x400 - qc; 516 if (ic < 0x300) { 517 ic = ic * 2 * 6 / 5; 518 ic = ic + 0x80; 519 } else { 520 ic = (0x400 - ic) * 2 * 6 / 5; 521 ic = 0x7f - ic; 522 } 523 if (qc < 0x300) { 524 qc = qc * 2 * 6 / 5; 525 qc = qc + 0x80; 526 } else { 527 qc = (0x400 - qc) * 2 * 6 / 5; 528 qc = 0x7f - qc; 529 } 530 531 *ic_out = ic; 532 *qc_out = qc; 533 534 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 535 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 536 } 537 538 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 539 u32 adc_ic, u32 adc_qc, 540 u32 *ic_in, u32 *qc_in, 541 u32 *i_out, u32 *q_out) 542 { 543 u32 base_addr; 544 u32 read_addr; 545 u32 ic, qc; 546 u32 temp; 547 548 base_addr = rtw8822c_get_path_write_addr(path); 549 read_addr = rtw8822c_get_path_read_addr(path); 550 ic = *ic_in; 551 qc = *qc_in; 552 553 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 554 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 555 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 556 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 557 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 558 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 559 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 560 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 561 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 562 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 563 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 564 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 565 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 566 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 567 mdelay(2); 568 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 569 mdelay(2); 570 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 571 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 572 mdelay(1); 573 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 574 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 575 mdelay(20); 576 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 577 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 578 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 579 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 580 mdelay(1); 581 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 582 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 583 584 /* check DAC DC offset */ 585 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 586 rtw_write32(rtwdev, base_addr + 0x68, temp); 587 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 588 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 589 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 590 if (ic >= 0x10) 591 ic = ic - 0x10; 592 else 593 ic = 0x400 - (0x10 - ic); 594 595 if (qc >= 0x10) 596 qc = qc - 0x10; 597 else 598 qc = 0x400 - (0x10 - qc); 599 600 *i_out = ic; 601 *q_out = qc; 602 603 if (ic >= 0x200) 604 ic = 0x400 - ic; 605 if (qc >= 0x200) 606 qc = 0x400 - qc; 607 608 *ic_in = ic; 609 *qc_in = qc; 610 611 rtw_dbg(rtwdev, RTW_DBG_RFK, 612 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 613 } 614 615 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 616 { 617 u32 base_addr = rtw8822c_get_path_write_addr(path); 618 619 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 620 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 621 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 622 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 623 } 624 625 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 626 u8 path, u8 vec, u32 w_addr, u32 r_addr) 627 { 628 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 629 u16 val; 630 u32 i; 631 632 if (WARN_ON(vec >= 2)) 633 return; 634 635 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 636 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 637 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 638 dm_info->dack_msbk[path][vec][i] = val; 639 } 640 } 641 642 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 643 { 644 u32 w_off = 0x1c; 645 u32 r_off = 0x2c; 646 u32 w_addr, r_addr; 647 648 if (WARN_ON(path >= 2)) 649 return; 650 651 /* backup I vector */ 652 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 653 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 654 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 655 656 /* backup Q vector */ 657 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 658 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 659 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 660 } 661 662 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 663 { 664 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 665 u8 val; 666 667 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 668 dm_info->dack_dck[RF_PATH_A][0][0] = val; 669 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 670 dm_info->dack_dck[RF_PATH_A][0][1] = val; 671 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 672 dm_info->dack_dck[RF_PATH_A][1][0] = val; 673 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 674 dm_info->dack_dck[RF_PATH_A][1][1] = val; 675 676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 677 dm_info->dack_dck[RF_PATH_B][0][0] = val; 678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 679 dm_info->dack_dck[RF_PATH_B][1][0] = val; 680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 681 dm_info->dack_dck[RF_PATH_B][0][1] = val; 682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 683 dm_info->dack_dck[RF_PATH_B][1][1] = val; 684 } 685 686 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 687 { 688 u32 temp[3]; 689 690 temp[0] = rtw_read32(rtwdev, 0x1860); 691 temp[1] = rtw_read32(rtwdev, 0x4160); 692 temp[2] = rtw_read32(rtwdev, 0x9b4); 693 694 /* set clock */ 695 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 696 697 /* backup path-A I/Q */ 698 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 699 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 700 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 701 702 /* backup path-B I/Q */ 703 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 704 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 705 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 706 707 rtw8822c_dac_cal_backup_dck(rtwdev); 708 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 709 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 710 711 rtw_write32(rtwdev, 0x1860, temp[0]); 712 rtw_write32(rtwdev, 0x4160, temp[1]); 713 rtw_write32(rtwdev, 0x9b4, temp[2]); 714 } 715 716 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 717 { 718 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 719 u8 val; 720 721 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 722 val = dm_info->dack_dck[RF_PATH_A][0][0]; 723 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 724 val = dm_info->dack_dck[RF_PATH_A][0][1]; 725 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 726 727 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 728 val = dm_info->dack_dck[RF_PATH_A][1][0]; 729 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 730 val = dm_info->dack_dck[RF_PATH_A][1][1]; 731 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 732 733 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 734 val = dm_info->dack_dck[RF_PATH_B][0][0]; 735 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 736 val = dm_info->dack_dck[RF_PATH_B][0][1]; 737 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 738 739 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 740 val = dm_info->dack_dck[RF_PATH_B][1][0]; 741 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 742 val = dm_info->dack_dck[RF_PATH_B][1][1]; 743 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 744 } 745 746 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 747 { 748 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 749 750 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 751 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 752 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 753 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 754 755 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 756 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 757 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 758 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 759 760 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 761 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 762 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 763 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 764 765 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 766 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 767 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 768 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 769 770 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 771 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 772 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 773 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 774 775 rtw8822c_dac_cal_restore_dck(rtwdev); 776 777 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 778 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 779 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 780 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 781 782 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 783 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 784 785 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 786 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 787 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 788 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 789 790 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 791 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 792 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 793 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 794 795 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 796 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 797 } 798 799 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 800 u32 target_addr, u32 toggle_addr) 801 { 802 u32 cnt = 0; 803 804 do { 805 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 806 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 807 808 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 809 return true; 810 811 } while (cnt++ < 100); 812 813 return false; 814 } 815 816 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 817 { 818 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 819 u32 w_off = 0x1c; 820 u32 r_off = 0x2c; 821 u32 w_i, r_i, w_q, r_q; 822 u32 value; 823 u32 i; 824 825 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 826 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 827 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 828 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 829 830 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 831 return false; 832 833 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 834 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 835 value = dm_info->dack_msbk[path][0][i]; 836 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 837 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 838 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 839 } 840 841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 842 843 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 844 return false; 845 846 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 847 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 848 value = dm_info->dack_msbk[path][1][i]; 849 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 850 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 851 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 852 } 853 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 854 855 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 856 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 857 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 858 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 859 860 return true; 861 } 862 863 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 864 { 865 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 866 return false; 867 868 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 869 return false; 870 871 return true; 872 } 873 874 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 875 { 876 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 877 u32 temp[3]; 878 879 /* sample the first element for both path's IQ vector */ 880 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 881 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 882 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 883 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 884 return false; 885 886 temp[0] = rtw_read32(rtwdev, 0x1860); 887 temp[1] = rtw_read32(rtwdev, 0x4160); 888 temp[2] = rtw_read32(rtwdev, 0x9b4); 889 890 rtw8822c_dac_cal_restore_prepare(rtwdev); 891 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 892 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 893 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 894 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 895 return false; 896 897 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 898 rtw_err(rtwdev, "failed to restore dack vectors\n"); 899 return false; 900 } 901 902 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 903 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 904 rtw_write32(rtwdev, 0x1860, temp[0]); 905 rtw_write32(rtwdev, 0x4160, temp[1]); 906 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 907 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 908 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 909 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 910 rtw_write32(rtwdev, 0x9b4, temp[2]); 911 912 return true; 913 } 914 915 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 916 { 917 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 918 struct rtw_backup_info backup[DACK_REG_8822C]; 919 u32 ic = 0, qc = 0, i; 920 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 921 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 922 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 923 924 if (rtw8822c_dac_cal_restore(rtwdev)) 925 return; 926 927 /* not able to restore, do it */ 928 929 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 930 931 rtw8822c_dac_bb_setting(rtwdev); 932 933 /* path-A */ 934 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 935 for (i = 0; i < 10; i++) { 936 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 937 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 938 ic_a = ic; 939 qc_a = qc; 940 941 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 942 &ic, &qc, &i_a, &q_a); 943 944 if (ic < 5 && qc < 5) 945 break; 946 } 947 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 948 949 /* path-B */ 950 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 951 for (i = 0; i < 10; i++) { 952 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 953 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 954 ic_b = ic; 955 qc_b = qc; 956 957 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 958 &ic, &qc, &i_b, &q_b); 959 960 if (ic < 5 && qc < 5) 961 break; 962 } 963 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 964 965 rtw_write32(rtwdev, 0x1b00, 0x00000008); 966 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 967 rtw_write8(rtwdev, 0x1bcc, 0x0); 968 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 969 rtw_write8(rtwdev, 0x1bcc, 0x0); 970 971 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 972 973 /* backup results to restore, saving a lot of time */ 974 rtw8822c_dac_cal_backup(rtwdev); 975 976 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 977 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 978 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 980 } 981 982 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 983 { 984 u8 x2k_busy; 985 986 mdelay(1); 987 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 988 if (x2k_busy == 1) { 989 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 990 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 991 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 992 mdelay(1); 993 } 994 } 995 996 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8]) 997 { 998 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \ 999 do { \ 1000 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ 1001 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ 1002 bb_gain[_path][_idx]); \ 1003 } while (0) 1004 u8 path; 1005 1006 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1007 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); 1008 RF_SET_POWER_TRIM(path, 0x0, 0); 1009 RF_SET_POWER_TRIM(path, 0x1, 1); 1010 RF_SET_POWER_TRIM(path, 0x2, 2); 1011 RF_SET_POWER_TRIM(path, 0x3, 2); 1012 RF_SET_POWER_TRIM(path, 0x4, 3); 1013 RF_SET_POWER_TRIM(path, 0x5, 4); 1014 RF_SET_POWER_TRIM(path, 0x6, 5); 1015 RF_SET_POWER_TRIM(path, 0x7, 6); 1016 RF_SET_POWER_TRIM(path, 0x8, 7); 1017 RF_SET_POWER_TRIM(path, 0x9, 3); 1018 RF_SET_POWER_TRIM(path, 0xa, 4); 1019 RF_SET_POWER_TRIM(path, 0xb, 5); 1020 RF_SET_POWER_TRIM(path, 0xc, 6); 1021 RF_SET_POWER_TRIM(path, 0xd, 7); 1022 RF_SET_POWER_TRIM(path, 0xe, 7); 1023 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); 1024 } 1025 #undef RF_SET_POWER_TRIM 1026 } 1027 1028 static void rtw8822c_power_trim(struct rtw_dev *rtwdev) 1029 { 1030 u8 pg_pwr = 0xff, i, path, idx; 1031 s8 bb_gain[2][8] = {}; 1032 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB}; 1033 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA, 1034 PPG_5GM2_TXA, PPG_5GH1_TXA}, 1035 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB, 1036 PPG_5GM2_TXB, PPG_5GH1_TXB} }; 1037 bool set = false; 1038 1039 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { 1040 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr); 1041 if (pg_pwr == EFUSE_READ_FAIL) 1042 continue; 1043 set = true; 1044 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr); 1045 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr); 1046 } 1047 1048 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { 1049 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1050 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i], 1051 &pg_pwr); 1052 if (pg_pwr == EFUSE_READ_FAIL) 1053 continue; 1054 set = true; 1055 idx = i + ARRAY_SIZE(rf_efuse_2g); 1056 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr); 1057 } 1058 } 1059 if (set) 1060 rtw8822c_set_power_trim(rtwdev, bb_gain); 1061 1062 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1063 } 1064 1065 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev) 1066 { 1067 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B}; 1068 u8 pg_therm = 0xff, thermal[2] = {0}, path; 1069 1070 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1071 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm); 1072 if (pg_therm == EFUSE_READ_FAIL) 1073 return; 1074 /* Efuse value of BIT(0) shall be move to BIT(3), and the value 1075 * of BIT(1) to BIT(3) should be right shifted 1 bit. 1076 */ 1077 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm); 1078 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); 1079 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); 1080 } 1081 } 1082 1083 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 1084 { 1085 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB}; 1086 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB}; 1087 u8 pg_pa_bias = 0xff, path; 1088 1089 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1090 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path], 1091 &pg_pa_bias); 1092 if (pg_pa_bias == EFUSE_READ_FAIL) 1093 return; 1094 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1095 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias); 1096 } 1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1098 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path], 1099 &pg_pa_bias); 1100 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1101 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias); 1102 } 1103 } 1104 1105 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1106 { 1107 rtw8822c_rf_dac_cal(rtwdev); 1108 rtw8822c_rf_x2_check(rtwdev); 1109 rtw8822c_thermal_trim(rtwdev); 1110 rtw8822c_power_trim(rtwdev); 1111 rtw8822c_pa_bias(rtwdev); 1112 } 1113 1114 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1115 { 1116 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1117 u8 path; 1118 1119 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1120 dm_info->delta_power_index[path] = 0; 1121 ewma_thermal_init(&dm_info->avg_thermal[path]); 1122 dm_info->thermal_avg[path] = 0xff; 1123 } 1124 1125 dm_info->pwr_trk_triggered = false; 1126 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1127 } 1128 1129 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1130 { 1131 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1132 struct rtw_hal *hal = &rtwdev->hal; 1133 u8 crystal_cap; 1134 u8 cck_gi_u_bnd_msb = 0; 1135 u8 cck_gi_u_bnd_lsb = 0; 1136 u8 cck_gi_l_bnd_msb = 0; 1137 u8 cck_gi_l_bnd_lsb = 0; 1138 bool is_tx2_path; 1139 1140 /* power on BB/RF domain */ 1141 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1142 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1143 rtw_write8_set(rtwdev, REG_RF_CTRL, 1144 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1145 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1146 1147 /* disable low rate DPD */ 1148 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1149 1150 /* pre init before header files config */ 1151 rtw8822c_header_file_init(rtwdev, true); 1152 1153 rtw_phy_load_tables(rtwdev); 1154 1155 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1156 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1157 crystal_cap | (crystal_cap << 7)); 1158 1159 /* post init after header files config */ 1160 rtw8822c_header_file_init(rtwdev, false); 1161 1162 is_tx2_path = false; 1163 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1164 is_tx2_path); 1165 rtw_phy_init(rtwdev); 1166 1167 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1168 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1169 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1170 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1171 1172 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1173 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1174 1175 rtw8822c_rf_init(rtwdev); 1176 rtw8822c_pwrtrack_init(rtwdev); 1177 1178 rtw_bf_phy_init(rtwdev); 1179 } 1180 1181 #define WLAN_TXQ_RPT_EN 0x1F 1182 #define WLAN_SLOT_TIME 0x09 1183 #define WLAN_PIFS_TIME 0x1C 1184 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1185 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1186 #define WLAN_SIFS_CCK_TRX 0x0A 1187 #define WLAN_SIFS_OFDM_TRX 0x10 1188 #define WLAN_NAV_MAX 0xC8 1189 #define WLAN_RDG_NAV 0x05 1190 #define WLAN_TXOP_NAV 0x1B 1191 #define WLAN_CCK_RX_TSF 0x30 1192 #define WLAN_OFDM_RX_TSF 0x30 1193 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1194 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1195 #define WLAN_DRV_EARLY_INT 0x04 1196 #define WLAN_BCN_CTRL_CLT0 0x10 1197 #define WLAN_BCN_DMA_TIME 0x02 1198 #define WLAN_BCN_MAX_ERR 0xFF 1199 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1200 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1201 #define WLAN_SIFS_CCK_CTX 0x0A 1202 #define WLAN_SIFS_CCK_IRX 0x0A 1203 #define WLAN_SIFS_OFDM_CTX 0x0E 1204 #define WLAN_SIFS_OFDM_IRX 0x0E 1205 #define WLAN_EIFS_DUR_TUNE 0x40 1206 #define WLAN_EDCA_VO_PARAM 0x002FA226 1207 #define WLAN_EDCA_VI_PARAM 0x005EA328 1208 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1209 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1210 1211 #define WLAN_RX_FILTER0 0xFFFFFFFF 1212 #define WLAN_RX_FILTER2 0xFFFF 1213 #define WLAN_RCR_CFG 0xE400220E 1214 #define WLAN_RXPKT_MAX_SZ 12288 1215 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1216 1217 #define WLAN_AMPDU_MAX_TIME 0x70 1218 #define WLAN_RTS_LEN_TH 0xFF 1219 #define WLAN_RTS_TX_TIME_TH 0x08 1220 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1221 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1222 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1223 #define FAST_EDCA_VO_TH 0x06 1224 #define FAST_EDCA_VI_TH 0x06 1225 #define FAST_EDCA_BE_TH 0x06 1226 #define FAST_EDCA_BK_TH 0x06 1227 #define WLAN_BAR_RETRY_LIMIT 0x01 1228 #define WLAN_BAR_ACK_TYPE 0x05 1229 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1230 #define WLAN_RESP_TXRATE 0x84 1231 #define WLAN_ACK_TO 0x21 1232 #define WLAN_ACK_TO_CCK 0x6A 1233 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1234 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1235 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1236 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1237 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1238 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1239 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1240 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1241 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1242 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1243 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1244 #define WLAN_MULTI_ADDR 0xFFFFFFFF 1245 1246 #define WLAN_TX_FUNC_CFG1 0x30 1247 #define WLAN_TX_FUNC_CFG2 0x30 1248 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1249 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1250 #define WLAN_MAC_OPT_FUNC2 0x30810041 1251 #define WLAN_MAC_INT_MIG_CFG 0x33330000 1252 1253 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1254 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1255 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1256 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1257 1258 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1259 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1260 1261 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1262 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1263 1264 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1265 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1266 1267 #define MAC_CLK_SPEED 80 /* 80M */ 1268 #define EFUSE_PCB_INFO_OFFSET 0xCA 1269 1270 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1271 { 1272 u8 value8; 1273 u16 value16; 1274 u32 value32; 1275 u16 pre_txcnt; 1276 1277 /* txq control */ 1278 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1279 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1280 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1281 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1282 /* sifs control */ 1283 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1284 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1285 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1286 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1287 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1288 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1289 /* rate fallback control */ 1290 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 1291 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 1292 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 1293 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 1294 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 1295 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 1296 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 1297 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 1298 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 1299 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 1300 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 1301 /* protocol configuration */ 1302 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 1303 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 1304 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 1305 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 1306 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 1307 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 1308 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 1309 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 1310 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 1311 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 1312 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 1313 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 1314 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 1315 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 1316 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 1317 /* close BA parser */ 1318 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 1319 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 1320 1321 /* EDCA configuration */ 1322 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 1323 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 1324 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 1325 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 1326 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 1327 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 1328 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 1329 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 1330 BIT_DIS_STBC_CFE) >> 8); 1331 1332 /* MAC clock configuration */ 1333 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 1334 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 1335 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 1336 1337 rtw_write8_set(rtwdev, REG_MISC_CTRL, 1338 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 1339 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 1340 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 1341 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 1342 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 1343 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 1344 /* Set beacon cotnrol - enable TSF and other related functions */ 1345 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1346 /* Set send beacon related registers */ 1347 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 1348 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 1349 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 1350 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 1351 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 1352 1353 /* WMAC configuration */ 1354 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 1355 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 1356 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 1357 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 1358 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 1359 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 1360 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 1361 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 1362 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 1363 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 1364 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 1365 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 1366 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 1367 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 1368 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 1369 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 1370 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 1371 1372 /* init low power */ 1373 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 1374 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 1375 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 1376 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 1377 value16 = 0; 1378 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 1379 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 1380 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 1381 | BIT_RXPSF_OFDMRST; 1382 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1383 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 1384 /* rx ignore configuration */ 1385 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 1386 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 1387 BIT_RXPSF_CONT_ERRCHKEN); 1388 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 1389 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1390 1391 /* Interrupt migration configuration */ 1392 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 1393 1394 return 0; 1395 } 1396 1397 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 1398 { 1399 if (enable) { 1400 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 1401 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 1402 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 1403 } else { 1404 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 1405 } 1406 } 1407 1408 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 1409 { 1410 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 1411 #define RF18_BAND_2G (0) 1412 #define RF18_BAND_5G (BIT(16) | BIT(8)) 1413 #define RF18_CHANNEL_MASK (MASKBYTE0) 1414 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 1415 #define RF18_RFSI_GE_CH80 (BIT(17)) 1416 #define RF18_RFSI_GT_CH140 (BIT(18)) 1417 #define RF18_BW_MASK (BIT(13) | BIT(12)) 1418 #define RF18_BW_20M (BIT(13) | BIT(12)) 1419 #define RF18_BW_40M (BIT(13)) 1420 #define RF18_BW_80M (BIT(12)) 1421 1422 u32 rf_reg18 = 0; 1423 u32 rf_rxbb = 0; 1424 1425 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 1426 1427 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 1428 RF18_BW_MASK); 1429 1430 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 1431 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 1432 if (IS_CH_5G_BAND_4(channel)) 1433 rf_reg18 |= RF18_RFSI_GT_CH140; 1434 else if (IS_CH_5G_BAND_3(channel)) 1435 rf_reg18 |= RF18_RFSI_GE_CH80; 1436 1437 switch (bw) { 1438 case RTW_CHANNEL_WIDTH_5: 1439 case RTW_CHANNEL_WIDTH_10: 1440 case RTW_CHANNEL_WIDTH_20: 1441 default: 1442 rf_reg18 |= RF18_BW_20M; 1443 rf_rxbb = 0x18; 1444 break; 1445 case RTW_CHANNEL_WIDTH_40: 1446 /* RF bandwidth */ 1447 rf_reg18 |= RF18_BW_40M; 1448 rf_rxbb = 0x10; 1449 break; 1450 case RTW_CHANNEL_WIDTH_80: 1451 rf_reg18 |= RF18_BW_80M; 1452 rf_rxbb = 0x8; 1453 break; 1454 } 1455 1456 rtw8822c_rstb_3wire(rtwdev, false); 1457 1458 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 1459 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 1460 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 1461 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 1462 1463 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 1464 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 1465 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 1466 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 1467 1468 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 1469 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 1470 1471 rtw8822c_rstb_3wire(rtwdev, true); 1472 } 1473 1474 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 1475 { 1476 u32 igi; 1477 1478 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 1479 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 1480 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 1481 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 1482 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 1483 } 1484 1485 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1486 u8 primary_ch_idx) 1487 { 1488 if (IS_CH_2G_BAND(channel)) { 1489 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1490 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 1491 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1492 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1493 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 1494 1495 switch (bw) { 1496 case RTW_CHANNEL_WIDTH_20: 1497 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1498 0x5); 1499 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1500 0x5); 1501 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1502 0x6); 1503 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1504 0x6); 1505 break; 1506 case RTW_CHANNEL_WIDTH_40: 1507 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1508 0x4); 1509 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1510 0x4); 1511 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1512 0x0); 1513 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1514 0x0); 1515 break; 1516 } 1517 if (channel == 13 || channel == 14) 1518 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 1519 else if (channel == 11 || channel == 12) 1520 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 1521 else 1522 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 1523 if (channel == 14) { 1524 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 1525 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1526 0x4962c931); 1527 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 1528 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 1529 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 1530 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 1531 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1532 0xff012455); 1533 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 1534 } else { 1535 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 1536 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1537 0x3e18fec8); 1538 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 1539 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 1540 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 1541 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 1542 0x00faf0de); 1543 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1544 0x00122344); 1545 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 1546 0x0fffffff); 1547 } 1548 if (channel == 13) 1549 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1550 else 1551 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 1552 } else if (IS_CH_5G_BAND(channel)) { 1553 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1554 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1555 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1556 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 1557 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 1558 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1559 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 1560 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1561 0x1); 1562 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1563 0x1); 1564 } else if (IS_CH_5G_BAND_3(channel)) { 1565 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1566 0x2); 1567 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1568 0x2); 1569 } else if (IS_CH_5G_BAND_4(channel)) { 1570 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1571 0x3); 1572 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1573 0x3); 1574 } 1575 1576 if (channel >= 36 && channel <= 51) 1577 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 1578 else if (channel >= 52 && channel <= 55) 1579 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 1580 else if (channel >= 56 && channel <= 111) 1581 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 1582 else if (channel >= 112 && channel <= 119) 1583 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 1584 else if (channel >= 120 && channel <= 172) 1585 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 1586 else if (channel >= 173 && channel <= 177) 1587 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 1588 } 1589 1590 switch (bw) { 1591 case RTW_CHANNEL_WIDTH_20: 1592 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 1593 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1594 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 1595 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 1596 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 1597 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1598 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1599 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1600 break; 1601 case RTW_CHANNEL_WIDTH_40: 1602 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 1603 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 1604 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 1605 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1606 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1607 (primary_ch_idx | (primary_ch_idx << 4))); 1608 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 1609 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1610 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1611 break; 1612 case RTW_CHANNEL_WIDTH_80: 1613 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 1614 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1615 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1616 (primary_ch_idx | (primary_ch_idx << 4))); 1617 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 1618 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1619 break; 1620 case RTW_CHANNEL_WIDTH_5: 1621 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1622 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1623 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 1624 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 1625 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 1626 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1627 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1628 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1629 break; 1630 case RTW_CHANNEL_WIDTH_10: 1631 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1632 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1633 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 1634 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 1635 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 1636 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1637 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1638 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1639 break; 1640 } 1641 } 1642 1643 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1644 u8 primary_chan_idx) 1645 { 1646 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 1647 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 1648 rtw8822c_set_channel_rf(rtwdev, channel, bw); 1649 rtw8822c_toggle_igi(rtwdev); 1650 } 1651 1652 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1653 { 1654 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1655 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 1656 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 1657 } else if (rx_path == BB_PATH_AB) { 1658 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 1659 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 1660 } 1661 1662 if (rx_path == BB_PATH_A) 1663 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 1664 else if (rx_path == BB_PATH_B) 1665 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 1666 else if (rx_path == BB_PATH_AB) 1667 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 1668 } 1669 1670 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1671 { 1672 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1673 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 1674 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 1675 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 1676 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 1677 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 1678 } else if (rx_path == BB_PATH_AB) { 1679 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 1680 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 1681 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 1682 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 1683 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 1684 } 1685 1686 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 1687 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 1688 } 1689 1690 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1691 { 1692 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 1693 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 1694 } 1695 1696 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1697 bool is_tx2_path) 1698 { 1699 if (tx_path == BB_PATH_A) { 1700 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1701 } else if (tx_path == BB_PATH_B) { 1702 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 1703 } else { 1704 if (is_tx2_path) 1705 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 1706 else 1707 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1708 } 1709 } 1710 1711 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1712 bool is_tx2_path) 1713 { 1714 if (tx_path == BB_PATH_A) { 1715 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 1716 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1717 } else if (tx_path == BB_PATH_B) { 1718 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 1719 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1720 } else { 1721 if (is_tx2_path) { 1722 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 1723 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 1724 } else { 1725 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 1726 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 1727 } 1728 } 1729 } 1730 1731 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1732 bool is_tx2_path) 1733 { 1734 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 1735 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 1736 } 1737 1738 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 1739 u8 rx_path, bool is_tx2_path) 1740 { 1741 if ((tx_path | rx_path) & BB_PATH_A) 1742 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 1743 else 1744 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 1745 if ((tx_path | rx_path) & BB_PATH_B) 1746 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 1747 else 1748 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 1749 1750 rtw8822c_config_rx_path(rtwdev, rx_path); 1751 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 1752 1753 rtw8822c_toggle_igi(rtwdev); 1754 } 1755 1756 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 1757 struct rtw_rx_pkt_stat *pkt_stat) 1758 { 1759 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1760 u8 l_bnd, u_bnd; 1761 u8 gain_a, gain_b; 1762 s8 rx_power[RTW_RF_PATH_MAX]; 1763 s8 min_rx_power = -120; 1764 u8 rssi; 1765 int path; 1766 1767 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 1768 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 1769 l_bnd = dm_info->cck_gi_l_bnd; 1770 u_bnd = dm_info->cck_gi_u_bnd; 1771 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 1772 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 1773 if (gain_a < l_bnd) 1774 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 1775 else if (gain_a > u_bnd) 1776 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 1777 if (gain_b < l_bnd) 1778 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 1779 else if (gain_b > u_bnd) 1780 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 1781 1782 rx_power[RF_PATH_A] -= 110; 1783 rx_power[RF_PATH_B] -= 110; 1784 1785 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 1786 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 1787 1788 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1789 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1790 dm_info->rssi[path] = rssi; 1791 } 1792 1793 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1794 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1795 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 1796 min_rx_power); 1797 } 1798 1799 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 1800 struct rtw_rx_pkt_stat *pkt_stat) 1801 { 1802 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1803 u8 rxsc, bw; 1804 s8 min_rx_power = -120; 1805 s8 rx_evm; 1806 u8 evm_dbm = 0; 1807 u8 rssi; 1808 int path; 1809 1810 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 1811 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 1812 else 1813 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 1814 1815 if (rxsc >= 9 && rxsc <= 12) 1816 bw = RTW_CHANNEL_WIDTH_40; 1817 else if (rxsc >= 13) 1818 bw = RTW_CHANNEL_WIDTH_80; 1819 else 1820 bw = RTW_CHANNEL_WIDTH_20; 1821 1822 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 1823 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 1824 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 1825 pkt_stat->bw = bw; 1826 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 1827 pkt_stat->rx_power[RF_PATH_B], 1828 min_rx_power); 1829 1830 dm_info->curr_rx_rate = pkt_stat->rate; 1831 1832 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 1833 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 1834 1835 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 1836 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 1837 1838 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 1839 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 1840 1841 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1842 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1843 dm_info->rssi[path] = rssi; 1844 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 1845 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 1846 1847 rx_evm = pkt_stat->rx_evm[path]; 1848 1849 if (rx_evm < 0) { 1850 if (rx_evm == S8_MIN) 1851 evm_dbm = 0; 1852 else 1853 evm_dbm = ((u8)-rx_evm >> 1); 1854 } 1855 dm_info->rx_evm_dbm[path] = evm_dbm; 1856 } 1857 } 1858 1859 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1860 struct rtw_rx_pkt_stat *pkt_stat) 1861 { 1862 u8 page; 1863 1864 page = *phy_status & 0xf; 1865 1866 switch (page) { 1867 case 0: 1868 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 1869 break; 1870 case 1: 1871 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 1872 break; 1873 default: 1874 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 1875 return; 1876 } 1877 } 1878 1879 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1880 struct rtw_rx_pkt_stat *pkt_stat, 1881 struct ieee80211_rx_status *rx_status) 1882 { 1883 struct ieee80211_hdr *hdr; 1884 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1885 u8 *phy_status = NULL; 1886 1887 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1888 1889 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1890 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1891 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1892 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 1893 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 1894 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1895 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1896 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1897 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1898 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1899 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1900 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 1901 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1902 1903 /* drv_info_sz is in unit of 8-bytes */ 1904 pkt_stat->drv_info_sz *= 8; 1905 1906 /* c2h cmd pkt's rx/phy status is not interested */ 1907 if (pkt_stat->is_c2h) 1908 return; 1909 1910 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1911 pkt_stat->drv_info_sz); 1912 if (pkt_stat->phy_status) { 1913 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1914 query_phy_status(rtwdev, phy_status, pkt_stat); 1915 } 1916 1917 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1918 } 1919 1920 static void 1921 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 1922 u8 *tx_pwr_ref_ofdm) 1923 { 1924 struct rtw_hal *hal = &rtwdev->hal; 1925 u32 txref_cck[2] = {0x18a0, 0x41a0}; 1926 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 1927 u8 path; 1928 1929 for (path = 0; path < hal->rf_path_num; path++) { 1930 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1931 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 1932 tx_pwr_ref_cck[path]); 1933 } 1934 for (path = 0; path < hal->rf_path_num; path++) { 1935 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1936 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 1937 tx_pwr_ref_ofdm[path]); 1938 } 1939 } 1940 1941 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 1942 s8 *diff_idx) 1943 { 1944 u32 offset_txagc = 0x3a00; 1945 u8 rate_idx = rate & 0xfc; 1946 u8 pwr_idx[4]; 1947 u32 phy_pwr_idx; 1948 int i; 1949 1950 for (i = 0; i < 4; i++) 1951 pwr_idx[i] = diff_idx[i] & 0x7f; 1952 1953 phy_pwr_idx = pwr_idx[0] | 1954 (pwr_idx[1] << 8) | 1955 (pwr_idx[2] << 16) | 1956 (pwr_idx[3] << 24); 1957 1958 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 1959 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 1960 phy_pwr_idx); 1961 } 1962 1963 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 1964 { 1965 struct rtw_hal *hal = &rtwdev->hal; 1966 u8 rs, rate, j; 1967 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 1968 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 1969 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 1970 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 1971 s8 diff_a, diff_b; 1972 u8 pwr_a, pwr_b; 1973 s8 diff_idx[4]; 1974 1975 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 1976 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 1977 for (j = 0; j < rtw_rate_size[rs]; j++) { 1978 rate = rtw_rate_section[rs][j]; 1979 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 1980 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 1981 if (rs == 0) { 1982 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 1983 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 1984 } else { 1985 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 1986 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 1987 } 1988 diff_idx[rate % 4] = min(diff_a, diff_b); 1989 if (rate % 4 == 3) 1990 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 1991 diff_idx); 1992 } 1993 } 1994 } 1995 1996 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev, 1997 u32 antenna_tx, 1998 u32 antenna_rx) 1999 { 2000 struct rtw_hal *hal = &rtwdev->hal; 2001 2002 switch (antenna_tx) { 2003 case BB_PATH_A: 2004 case BB_PATH_B: 2005 case BB_PATH_AB: 2006 break; 2007 default: 2008 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 2009 return -EINVAL; 2010 } 2011 2012 /* path B only is not available for RX */ 2013 switch (antenna_rx) { 2014 case BB_PATH_A: 2015 case BB_PATH_AB: 2016 break; 2017 default: 2018 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 2019 return -EINVAL; 2020 } 2021 2022 hal->antenna_tx = antenna_tx; 2023 hal->antenna_rx = antenna_rx; 2024 2025 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 2026 2027 return 0; 2028 } 2029 2030 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 2031 { 2032 u8 ldo_pwr; 2033 2034 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 2035 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 2036 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 2037 } 2038 2039 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 2040 { 2041 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2042 u32 cck_enable; 2043 u32 cck_fa_cnt; 2044 u32 crc32_cnt; 2045 u32 cca32_cnt; 2046 u32 ofdm_fa_cnt; 2047 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 2048 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 2049 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 2050 2051 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 2052 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 2053 2054 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 2055 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 2056 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 2057 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 2058 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 2059 2060 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 2061 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 2062 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 2063 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 2064 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 2065 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 2066 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 2067 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 2068 2069 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 2070 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 2071 2072 dm_info->cck_fa_cnt = cck_fa_cnt; 2073 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 2074 dm_info->total_fa_cnt = ofdm_fa_cnt; 2075 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 2076 2077 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 2078 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 2079 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2080 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 2081 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 2082 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2083 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 2084 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 2085 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2086 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 2087 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 2088 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2089 2090 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 2091 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 2092 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 2093 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 2094 if (cck_enable) 2095 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 2096 2097 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 2098 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 2099 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 2100 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 2101 2102 /* disable rx clk gating to reset counters */ 2103 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2104 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2105 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2106 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2107 } 2108 2109 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 2110 { 2111 struct rtw_iqk_para para = {0}; 2112 u8 iqk_chk; 2113 int counter; 2114 2115 para.clear = 1; 2116 rtw_fw_do_iqk(rtwdev, ¶); 2117 2118 for (counter = 0; counter < 300; counter++) { 2119 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP); 2120 if (iqk_chk == 0xaa) 2121 break; 2122 msleep(20); 2123 } 2124 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 2125 2126 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter); 2127 } 2128 2129 /* for coex */ 2130 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 2131 { 2132 /* enable TBTT nterrupt */ 2133 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2134 2135 /* BT report packet sample rate */ 2136 /* 0x790[5:0]=0x5 */ 2137 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 2138 2139 /* enable BT counter statistics */ 2140 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2141 2142 /* enable PTA (3-wire function form BT side) */ 2143 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2144 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 2145 2146 /* enable PTA (tx/rx signal form WiFi side) */ 2147 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2148 /* wl tx signal to PTA not case EDCCA */ 2149 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2150 /* GNT_BT=1 while select both */ 2151 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2152 /* BT_CCA = ~GNT_WL_BB, not or GNT_BT_BB, LTE_Rx */ 2153 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2154 2155 /* to avoid RF parameter error */ 2156 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000); 2157 } 2158 2159 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2160 { 2161 struct rtw_coex *coex = &rtwdev->coex; 2162 struct rtw_coex_stat *coex_stat = &coex->stat; 2163 struct rtw_efuse *efuse = &rtwdev->efuse; 2164 u32 rf_0x1; 2165 2166 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2167 return; 2168 2169 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 2170 2171 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 2172 rf_0x1 = 0x40021; 2173 else 2174 rf_0x1 = 0x40000; 2175 2176 /* BT at S1 for Shared-Ant */ 2177 if (efuse->share_ant) 2178 rf_0x1 |= BIT(13); 2179 2180 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 2181 2182 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 2183 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 2184 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 2185 * 2186 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 2187 * disable 0x1c30[22] = 0, 2188 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 2189 * 2190 * disable WL-S1 BB chage RF mode if GNT_BT 2191 * since RF TRx mask can do it 2192 */ 2193 rtw_write8_mask(rtwdev, REG_ANAPAR + 2, BIT_ANAPAR_BTPS >> 16, 1); 2194 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1, BIT_DAC_OFF_ENABLE, 0); 2195 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3, BIT_DAC_OFF_ENABLE, 1); 2196 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4, BIT_PI_IGNORE_GNT_BT, 1); 2197 2198 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 2199 * or antenna path is separated 2200 */ 2201 if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 2202 coex->under_5g || !efuse->share_ant) { 2203 if (coex_stat->kt_ver >= 3) { 2204 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 2205 BIT_PI_IGNORE_GNT_BT, 0); 2206 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 2207 BIT_NOMASK_TXBT_ENABLE, 1); 2208 } else { 2209 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 2210 BIT_PI_IGNORE_GNT_BT, 1); 2211 } 2212 } else { 2213 /* shared-antenna */ 2214 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 2215 BIT_PI_IGNORE_GNT_BT, 0); 2216 if (coex_stat->kt_ver >= 3) { 2217 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 2218 BIT_NOMASK_TXBT_ENABLE, 0); 2219 } 2220 } 2221 } 2222 2223 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 2224 { 2225 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 2226 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 2227 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 2228 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 2229 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 2230 } 2231 2232 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 2233 { 2234 struct rtw_coex *coex = &rtwdev->coex; 2235 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 2236 struct rtw_efuse *efuse = &rtwdev->efuse; 2237 2238 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 2239 coex_rfe->ant_switch_polarity = 0; 2240 coex_rfe->ant_switch_exist = false; 2241 coex_rfe->ant_switch_with_bt = false; 2242 coex_rfe->ant_switch_diversity = false; 2243 2244 if (efuse->share_ant) 2245 coex_rfe->wlg_at_btg = true; 2246 else 2247 coex_rfe->wlg_at_btg = false; 2248 2249 /* disable LTE coex in wifi side */ 2250 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 2251 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 2252 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 2253 } 2254 2255 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 2256 { 2257 struct rtw_coex *coex = &rtwdev->coex; 2258 struct rtw_coex_dm *coex_dm = &coex->dm; 2259 2260 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 2261 return; 2262 2263 coex_dm->cur_wl_pwr_lvl = wl_pwr; 2264 } 2265 2266 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 2267 { 2268 struct rtw_coex *coex = &rtwdev->coex; 2269 struct rtw_coex_dm *coex_dm = &coex->dm; 2270 2271 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 2272 return; 2273 2274 coex_dm->cur_wl_rx_low_gain_en = low_gain; 2275 2276 if (coex_dm->cur_wl_rx_low_gain_en) { 2277 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); 2278 2279 /* set Rx filter corner RCK offset */ 2280 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22); 2281 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36); 2282 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22); 2283 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36); 2284 2285 } else { 2286 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); 2287 2288 /* set Rx filter corner RCK offset */ 2289 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20); 2290 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0); 2291 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20); 2292 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0); 2293 } 2294 } 2295 2296 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 2297 struct rtw_vif *vif, 2298 struct rtw_bfee *bfee) 2299 { 2300 u8 csi_rsc = 0; 2301 u32 tmp6dc; 2302 2303 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 2304 2305 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 2306 BIT_WMAC_USE_NDPARATE | 2307 (csi_rsc << 13); 2308 if (vif->net_type == RTW_NET_AP_MODE) 2309 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 2310 else 2311 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 2312 2313 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 2314 } 2315 2316 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 2317 struct rtw_vif *vif, 2318 struct rtw_bfee *bfee, bool enable) 2319 { 2320 if (enable) 2321 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 2322 else 2323 rtw_bf_remove_bfee_su(rtwdev, bfee); 2324 } 2325 2326 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 2327 struct rtw_vif *vif, 2328 struct rtw_bfee *bfee, bool enable) 2329 { 2330 if (enable) 2331 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 2332 else 2333 rtw_bf_remove_bfee_mu(rtwdev, bfee); 2334 } 2335 2336 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 2337 struct rtw_bfee *bfee, bool enable) 2338 { 2339 if (bfee->role == RTW_BFEE_SU) 2340 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 2341 else if (bfee->role == RTW_BFEE_MU) 2342 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 2343 else 2344 rtw_warn(rtwdev, "wrong bfee role\n"); 2345 } 2346 2347 struct dpk_cfg_pair { 2348 u32 addr; 2349 u32 bitmask; 2350 u32 data; 2351 }; 2352 2353 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 2354 const struct rtw_table *tbl) 2355 { 2356 const struct dpk_cfg_pair *p = tbl->data; 2357 const struct dpk_cfg_pair *end = p + tbl->size / 3; 2358 2359 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 2360 2361 for (; p < end; p++) 2362 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 2363 } 2364 2365 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 2366 { 2367 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2368 2369 if (is_before_k) { 2370 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 2371 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 2372 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 2373 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 2374 } else { 2375 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 2376 dpk_info->gnt_value); 2377 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 2378 } 2379 } 2380 2381 static void 2382 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 2383 struct rtw_backup_info *bckp) 2384 { 2385 rtw_restore_reg(rtwdev, bckp, reg_num); 2386 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2387 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 2388 } 2389 2390 static void 2391 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 2392 u32 reg_num, struct rtw_backup_info *bckp) 2393 { 2394 u32 i; 2395 2396 for (i = 0; i < reg_num; i++) { 2397 bckp[i].len = 4; 2398 bckp[i].reg = reg[i]; 2399 bckp[i].val = rtw_read32(rtwdev, reg[i]); 2400 } 2401 } 2402 2403 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 2404 u32 *rf_reg, 2405 u32 rf_reg_bak[][2]) 2406 { 2407 u32 i; 2408 2409 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2410 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 2411 rf_reg[i], RFREG_MASK); 2412 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 2413 rf_reg[i], RFREG_MASK); 2414 } 2415 } 2416 2417 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 2418 u32 *rf_reg, 2419 u32 rf_reg_bak[][2]) 2420 { 2421 u32 i; 2422 2423 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2424 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 2425 rf_reg_bak[i][RF_PATH_A]); 2426 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 2427 rf_reg_bak[i][RF_PATH_B]); 2428 } 2429 } 2430 2431 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 2432 { 2433 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2434 u32 reg; 2435 u8 band_shift; 2436 2437 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2438 2439 band_shift = FIELD_GET(BIT(16), reg); 2440 dpk_info->dpk_band = 1 << band_shift; 2441 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 2442 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 2443 } 2444 2445 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 2446 { 2447 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2448 udelay(5); 2449 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 2450 usleep_range(600, 610); 2451 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2452 } 2453 2454 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 2455 { 2456 u16 dc_i, dc_q; 2457 u8 corr_idx; 2458 2459 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 2460 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2461 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 2462 2463 if (dc_i & BIT(11)) 2464 dc_i = 0x1000 - dc_i; 2465 if (dc_q & BIT(11)) 2466 dc_q = 0x1000 - dc_q; 2467 2468 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2469 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 2470 rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 2471 2472 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 2473 return 1; 2474 else 2475 return 0; 2476 2477 } 2478 2479 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 2480 { 2481 u8 reg_a, reg_b; 2482 u16 count = 0; 2483 2484 rtw_write8(rtwdev, 0x522, 0xff); 2485 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 2486 2487 do { 2488 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 2489 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 2490 udelay(2); 2491 count++; 2492 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 2493 } 2494 2495 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 2496 { 2497 rtw8822c_dpk_tx_pause(rtwdev); 2498 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 2499 } 2500 2501 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 2502 { 2503 if (is_do_dpk) 2504 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 2505 else 2506 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 2507 } 2508 2509 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 2510 { 2511 u8 path; 2512 2513 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 2514 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 2515 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2516 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 2517 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 2518 else 2519 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 2520 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 2521 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 2522 } 2523 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2524 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 2525 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 2526 } 2527 2528 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 2529 { 2530 u32 ori_txbb; 2531 2532 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 2533 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 2534 2535 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 2536 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 2537 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0); 2538 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 2539 2540 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 2541 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1); 2542 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 2543 } else { 2544 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 2545 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 2546 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 2547 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 2548 } 2549 2550 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2551 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 2552 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 2553 2554 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 2555 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 2556 else 2557 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 2558 2559 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 2560 2561 usleep_range(100, 110); 2562 2563 return ori_txbb & 0x1f; 2564 } 2565 2566 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 2567 { 2568 u16 cmd; 2569 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 2570 2571 switch (action) { 2572 case RTW_DPK_GAIN_LOSS: 2573 cmd = 0x14 + path; 2574 break; 2575 case RTW_DPK_DO_DPK: 2576 cmd = 0x16 + path + bw; 2577 break; 2578 case RTW_DPK_DPK_ON: 2579 cmd = 0x1a + path; 2580 break; 2581 case RTW_DPK_DAGC: 2582 cmd = 0x1c + path + bw; 2583 break; 2584 default: 2585 return 0; 2586 } 2587 2588 return (cmd << 8) | 0x48; 2589 } 2590 2591 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 2592 { 2593 u16 dpk_cmd; 2594 u8 result = 0; 2595 2596 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 2597 2598 if (action == RTW_DPK_CAL_PWR) { 2599 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 2600 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 2601 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 2602 msleep(10); 2603 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 2604 result = 1; 2605 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2606 } 2607 } else { 2608 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2609 0x8 | (path << 1)); 2610 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 2611 2612 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 2613 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 2614 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 2615 msleep(10); 2616 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 2617 result = 1; 2618 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2619 } 2620 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2621 0x8 | (path << 1)); 2622 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 2623 } 2624 2625 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 2626 2627 rtw_write8(rtwdev, 0x1b10, 0x0); 2628 2629 return result; 2630 } 2631 2632 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 2633 { 2634 u16 dgain; 2635 2636 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2637 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 2638 2639 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2640 2641 return dgain; 2642 } 2643 2644 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 2645 { 2646 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2647 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 2648 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2649 udelay(15); 2650 2651 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 2652 } 2653 2654 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 2655 { 2656 u32 i_val, q_val; 2657 2658 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2659 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2660 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 2661 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2662 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 2663 2664 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 2665 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 2666 2667 if (i_val & BIT(15)) 2668 i_val = 0x10000 - i_val; 2669 if (q_val & BIT(15)) 2670 q_val = 0x10000 - q_val; 2671 2672 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2673 2674 return i_val * i_val + q_val * q_val; 2675 } 2676 2677 static u32 rtw8822c_psd_log2base(u32 val) 2678 { 2679 u32 tmp, val_integerd_b, tindex; 2680 u32 result, val_fractiond_b; 2681 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 2682 151, 132, 115, 100, 86, 74, 62, 51, 2683 42, 32, 23, 15, 7, 0}; 2684 2685 if (val == 0) 2686 return 0; 2687 2688 val_integerd_b = __fls(val) + 1; 2689 2690 tmp = (val * 100) / (1 << val_integerd_b); 2691 tindex = tmp / 5; 2692 2693 if (tindex >= ARRAY_SIZE(table_fraction)) 2694 tindex = ARRAY_SIZE(table_fraction) - 1; 2695 2696 val_fractiond_b = table_fraction[tindex]; 2697 2698 result = val_integerd_b * 100 - val_fractiond_b; 2699 2700 return result; 2701 } 2702 2703 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 2704 { 2705 u8 result; 2706 2707 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2708 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 2709 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 2710 2711 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 2712 2713 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2714 2715 return result; 2716 } 2717 2718 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 2719 u8 limited_pga) 2720 { 2721 u8 result = 0; 2722 u16 dgain; 2723 2724 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 2725 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 2726 2727 if (dgain > 1535 && !limited_pga) 2728 return RTW_DPK_GAIN_LESS; 2729 else if (dgain < 768 && !limited_pga) 2730 return RTW_DPK_GAIN_LARGE; 2731 else 2732 return result; 2733 } 2734 2735 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 2736 { 2737 u32 loss, loss_db; 2738 2739 loss = rtw8822c_dpk_pas_read(rtwdev, path); 2740 if (loss < 0x4000000) 2741 return RTW_DPK_GL_LESS; 2742 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 2743 2744 if (loss_db > 1000) 2745 return RTW_DPK_GL_LARGE; 2746 else if (loss_db < 250) 2747 return RTW_DPK_GL_LESS; 2748 else 2749 return RTW_DPK_AGC_OUT; 2750 } 2751 2752 struct rtw8822c_dpk_data { 2753 u8 txbb; 2754 u8 pga; 2755 u8 limited_pga; 2756 u8 agc_cnt; 2757 bool loss_only; 2758 bool gain_only; 2759 u8 path; 2760 }; 2761 2762 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 2763 struct rtw8822c_dpk_data *data) 2764 { 2765 u8 state; 2766 2767 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 2768 BIT_GAIN_TXBB); 2769 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 2770 BIT_RXAGC); 2771 2772 if (data->loss_only) { 2773 state = RTW_DPK_LOSS_CHECK; 2774 goto check_end; 2775 } 2776 2777 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 2778 data->limited_pga); 2779 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 2780 state = RTW_DPK_AGC_OUT; 2781 else if (state == RTW_DPK_GAIN_CHECK) 2782 state = RTW_DPK_LOSS_CHECK; 2783 2784 check_end: 2785 data->agc_cnt++; 2786 if (data->agc_cnt >= 6) 2787 state = RTW_DPK_AGC_OUT; 2788 2789 return state; 2790 } 2791 2792 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 2793 struct rtw8822c_dpk_data *data) 2794 { 2795 u8 pga = data->pga; 2796 2797 if (pga > 0xe) 2798 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2799 else if (pga > 0xb && pga < 0xf) 2800 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 2801 else if (pga < 0xc) 2802 data->limited_pga = 1; 2803 2804 return RTW_DPK_GAIN_CHECK; 2805 } 2806 2807 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 2808 struct rtw8822c_dpk_data *data) 2809 { 2810 u8 pga = data->pga; 2811 2812 if (pga < 0xc) 2813 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2814 else if (pga > 0xb && pga < 0xf) 2815 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2816 else if (pga > 0xe) 2817 data->limited_pga = 1; 2818 2819 return RTW_DPK_GAIN_CHECK; 2820 } 2821 2822 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 2823 struct rtw8822c_dpk_data *data, u8 is_large) 2824 { 2825 u8 txbb_bound[] = {0x1f, 0}; 2826 2827 if (data->txbb == txbb_bound[is_large]) 2828 return RTW_DPK_AGC_OUT; 2829 2830 if (is_large == 1) 2831 data->txbb -= 2; 2832 else 2833 data->txbb += 3; 2834 2835 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 2836 data->limited_pga = 0; 2837 2838 return RTW_DPK_GAIN_CHECK; 2839 } 2840 2841 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 2842 struct rtw8822c_dpk_data *data) 2843 { 2844 return rtw8822c_gl_state(rtwdev, data, 1); 2845 } 2846 2847 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 2848 struct rtw8822c_dpk_data *data) 2849 { 2850 return rtw8822c_gl_state(rtwdev, data, 0); 2851 } 2852 2853 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 2854 struct rtw8822c_dpk_data *data) 2855 { 2856 u8 path = data->path; 2857 u8 state; 2858 2859 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 2860 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 2861 2862 return state; 2863 } 2864 2865 static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 2866 struct rtw8822c_dpk_data *data) = { 2867 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 2868 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 2869 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 2870 2871 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 2872 bool gain_only, bool loss_only) 2873 { 2874 struct rtw8822c_dpk_data data = {0}; 2875 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 2876 u8 state = RTW_DPK_GAIN_CHECK; 2877 2878 data.loss_only = loss_only; 2879 data.gain_only = gain_only; 2880 data.path = path; 2881 2882 for (;;) { 2883 func = dpk_state[state]; 2884 state = func(rtwdev, &data); 2885 if (state == RTW_DPK_AGC_OUT) 2886 break; 2887 } 2888 2889 return data.txbb; 2890 } 2891 2892 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 2893 u16 coef_i, u16 coef_q) 2894 { 2895 if (coef_i == 0x1000 || coef_i == 0x0fff || 2896 coef_q == 0x1000 || coef_q == 0x0fff) 2897 return true; 2898 2899 return false; 2900 } 2901 2902 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 2903 { 2904 u32 reg = 0; 2905 u16 coef_i = 0, coef_q = 0; 2906 2907 reg = rtw_read32(rtwdev, REG_STAT_RPT); 2908 2909 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 2910 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 2911 2912 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 2913 2914 reg = (coef_i << 16) | coef_q; 2915 2916 return reg; 2917 } 2918 2919 static const u32 rtw8822c_dpk_get_coef_tbl[] = { 2920 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 2921 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 2922 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 2923 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 2924 }; 2925 2926 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 2927 { 2928 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2929 int i; 2930 2931 for (i = 0; i < 20; i++) { 2932 rtw_write32(rtwdev, REG_RXSRAM_CTL, 2933 rtw8822c_dpk_get_coef_tbl[i]); 2934 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 2935 } 2936 } 2937 2938 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 2939 { 2940 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2941 2942 if (path == RF_PATH_A) { 2943 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 2944 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 2945 } else if (path == RF_PATH_B) { 2946 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 2947 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 2948 } 2949 2950 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 2951 } 2952 2953 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 2954 { 2955 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2956 u8 addr, result = 1; 2957 u16 coef_i, coef_q; 2958 2959 for (addr = 0; addr < 20; addr++) { 2960 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 2961 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 2962 2963 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 2964 result = 0; 2965 break; 2966 } 2967 } 2968 return result; 2969 } 2970 2971 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 2972 { 2973 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2974 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 2975 u32 coef; 2976 u8 addr; 2977 2978 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2979 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2980 2981 for (addr = 0; addr < 20; addr++) { 2982 if (result == 0) { 2983 if (addr == 3) 2984 coef = 0x04001fff; 2985 else 2986 coef = 0x00001fff; 2987 } else { 2988 coef = dpk_info->coef[path][addr]; 2989 } 2990 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 2991 } 2992 } 2993 2994 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 2995 u8 path, u8 result) 2996 { 2997 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2998 2999 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3000 3001 if (result) 3002 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 3003 else 3004 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 3005 3006 dpk_info->result[path] = result; 3007 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 3008 3009 rtw8822c_dpk_coef_write(rtwdev, path, result); 3010 } 3011 3012 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 3013 { 3014 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3015 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 3016 3017 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 3018 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 3019 3020 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3021 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3022 rtw8822c_dpk_dgain_read(rtwdev, path); 3023 3024 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 3025 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3026 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3027 rtw8822c_dpk_dc_corr_check(rtwdev, path); 3028 } 3029 3030 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 3031 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 3032 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 3033 3034 if (tx_bb < tx_agc_search) 3035 tx_bb = 0; 3036 else 3037 tx_bb = tx_bb - tx_agc_search; 3038 3039 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 3040 3041 tx_agc = ori_txagc - (ori_txbb - tx_bb); 3042 3043 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 3044 3045 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 3046 3047 return tx_agc; 3048 } 3049 3050 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 3051 { 3052 u8 result; 3053 3054 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 3055 3056 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3057 3058 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 3059 3060 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 3061 3062 rtw8822c_dpk_get_coef(rtwdev, path); 3063 3064 return result; 3065 } 3066 3067 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 3068 { 3069 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3070 u32 tmp_gs = 0; 3071 3072 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3073 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 3074 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3075 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3076 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 3077 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3078 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 3079 3080 if (path == RF_PATH_A) { 3081 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3082 0x1066680); 3083 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 3084 } else { 3085 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3086 0x1066680); 3087 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 3088 } 3089 3090 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 3091 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 3092 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 3093 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 3094 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 3095 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3096 rtw_write32(rtwdev, REG_DPD_CTL15, 3097 0x05020000 | (BIT(path) << 28)); 3098 } else { 3099 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 3100 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 3101 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 3102 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 3103 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3104 rtw_write32(rtwdev, REG_DPD_CTL15, 3105 0x05020008 | (BIT(path) << 28)); 3106 } 3107 3108 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 3109 3110 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 3111 3112 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 3113 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3114 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3115 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 3116 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3117 3118 if (path == RF_PATH_A) 3119 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 3120 else 3121 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 3122 3123 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3124 3125 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 3126 tmp_gs = (tmp_gs * 910) >> 10; 3127 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 3128 3129 if (path == RF_PATH_A) 3130 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 3131 else 3132 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 3133 3134 dpk_info->dpk_gs[path] = tmp_gs; 3135 } 3136 3137 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 3138 { 3139 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3140 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 3141 u32 i_scaling; 3142 u8 path; 3143 3144 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3145 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3146 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 3147 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 3148 3149 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 3150 3151 rtw_write8(rtwdev, 0x1b10, 0x0); 3152 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3153 3154 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3155 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 3156 3157 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 3158 i_scaling); 3159 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3160 GENMASK(31, 28), 0x9); 3161 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3162 GENMASK(31, 28), 0x1); 3163 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3164 GENMASK(31, 28), 0x0); 3165 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 3166 BIT(14), 0x0); 3167 } 3168 } 3169 3170 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 3171 { 3172 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3173 3174 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3175 3176 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3177 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3178 3179 if (test_bit(path, dpk_info->dpk_path_ok)) 3180 rtw8822c_dpk_cal_gs(rtwdev, path); 3181 } 3182 3183 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 3184 u32 dpk_txagc, u8 path) 3185 { 3186 bool result; 3187 3188 if (!is_fail) { 3189 if (rtw8822c_dpk_coef_read(rtwdev, path)) 3190 result = true; 3191 else 3192 result = false; 3193 } else { 3194 result = false; 3195 } 3196 3197 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 3198 3199 return result; 3200 } 3201 3202 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 3203 { 3204 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3205 u8 path; 3206 3207 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3208 clear_bit(path, dpk_info->dpk_path_ok); 3209 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3210 0x8 | (path << 1)); 3211 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 3212 3213 dpk_info->dpk_txagc[path] = 0; 3214 dpk_info->result[path] = 0; 3215 dpk_info->dpk_gs[path] = 0x5b; 3216 dpk_info->pre_pwsf[path] = 0; 3217 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 3218 path); 3219 } 3220 } 3221 3222 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 3223 { 3224 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3225 u32 dpk_txagc; 3226 u8 dpk_fail; 3227 3228 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 3229 3230 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 3231 3232 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 3233 3234 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 3235 rtw_err(rtwdev, "failed to do dpk calibration\n"); 3236 3237 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 3238 3239 if (dpk_info->result[path]) 3240 set_bit(path, dpk_info->dpk_path_ok); 3241 } 3242 3243 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 3244 { 3245 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 3246 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 3247 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 3248 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 3249 rtw8822c_dpk_cal_coef1(rtwdev); 3250 } 3251 3252 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 3253 { 3254 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3255 u32 mask = BIT(15) | BIT(14); 3256 3257 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3258 3259 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 3260 dpk_info->is_dpk_pwr_on); 3261 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 3262 dpk_info->is_dpk_pwr_on); 3263 3264 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 3265 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 3266 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 3267 } 3268 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 3269 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 3270 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 3271 } 3272 } 3273 3274 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 3275 { 3276 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3277 u8 path; 3278 3279 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 3280 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 3281 dpk_info->dpk_ch == 0) 3282 return; 3283 3284 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3285 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3286 0x8 | (path << 1)); 3287 if (dpk_info->dpk_band == RTW_BAND_2G) 3288 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 3289 else 3290 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 3291 3292 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 3293 3294 rtw8822c_dpk_coef_write(rtwdev, path, 3295 test_bit(path, dpk_info->dpk_path_ok)); 3296 3297 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3298 3299 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3300 3301 if (path == RF_PATH_A) 3302 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3303 dpk_info->dpk_gs[path]); 3304 else 3305 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3306 dpk_info->dpk_gs[path]); 3307 } 3308 rtw8822c_dpk_cal_coef1(rtwdev); 3309 } 3310 3311 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 3312 { 3313 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3314 u8 channel; 3315 3316 dpk_info->is_reload = false; 3317 3318 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 3319 3320 if (channel == dpk_info->dpk_ch) { 3321 rtw_dbg(rtwdev, RTW_DBG_RFK, 3322 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 3323 rtw8822c_dpk_reload_data(rtwdev); 3324 dpk_info->is_reload = true; 3325 } 3326 3327 return dpk_info->is_reload; 3328 } 3329 3330 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 3331 { 3332 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3333 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 3334 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 3335 u32 bb_reg[DPK_BB_REG_NUM] = { 3336 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 3337 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 3338 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 3339 u32 rf_reg[DPK_RF_REG_NUM] = { 3340 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 3341 u8 path; 3342 3343 if (!dpk_info->is_dpk_pwr_on) { 3344 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 3345 return; 3346 } else if (rtw8822c_dpk_reload(rtwdev)) { 3347 return; 3348 } 3349 3350 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 3351 ewma_thermal_init(&dpk_info->avg_thermal[path]); 3352 3353 rtw8822c_dpk_information(rtwdev); 3354 3355 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 3356 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3357 3358 rtw8822c_dpk_mac_bb_setting(rtwdev); 3359 rtw8822c_dpk_afe_setting(rtwdev, true); 3360 rtw8822c_dpk_pre_setting(rtwdev); 3361 rtw8822c_dpk_result_reset(rtwdev); 3362 rtw8822c_dpk_path_select(rtwdev); 3363 rtw8822c_dpk_afe_setting(rtwdev, false); 3364 rtw8822c_dpk_enable_disable(rtwdev); 3365 3366 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3367 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 3368 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3369 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 3370 } 3371 3372 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 3373 { 3374 rtw8822c_do_iqk(rtwdev); 3375 rtw8822c_do_dpk(rtwdev); 3376 } 3377 3378 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 3379 { 3380 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3381 u8 path; 3382 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 3383 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 3384 3385 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 3386 return; 3387 3388 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 3389 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 3390 ewma_thermal_add(&dpk_info->avg_thermal[path], 3391 thermal_value[path]); 3392 thermal_value[path] = 3393 ewma_thermal_read(&dpk_info->avg_thermal[path]); 3394 delta_dpk[path] = dpk_info->thermal_dpk[path] - 3395 thermal_value[path]; 3396 offset[path] = delta_dpk[path] - 3397 dpk_info->thermal_dpk_delta[path]; 3398 offset[path] &= 0x7f; 3399 3400 if (offset[path] != dpk_info->pre_pwsf[path]) { 3401 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3402 0x8 | (path << 1)); 3403 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 3404 offset[path]); 3405 dpk_info->pre_pwsf[path] = offset[path]; 3406 } 3407 } 3408 } 3409 3410 static const struct rtw_phy_cck_pd_reg 3411 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 3412 { 3413 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 3414 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 3415 }, 3416 { 3417 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 3418 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 3419 }, 3420 }; 3421 3422 #define RTW_CCK_PD_MAX 255 3423 #define RTW_CCK_CS_MAX 31 3424 #define RTW_CCK_CS_ERR1 27 3425 #define RTW_CCK_CS_ERR2 29 3426 static void 3427 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 3428 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 3429 { 3430 u32 pd, cs; 3431 3432 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 3433 return; 3434 3435 pd = rtw_read32_mask(rtwdev, 3436 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3437 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 3438 cs = rtw_read32_mask(rtwdev, 3439 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3440 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 3441 pd += pd_diff; 3442 cs += cs_diff; 3443 if (pd > RTW_CCK_PD_MAX) 3444 pd = RTW_CCK_PD_MAX; 3445 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 3446 cs++; 3447 else if (cs > RTW_CCK_CS_MAX) 3448 cs = RTW_CCK_CS_MAX; 3449 rtw_write32_mask(rtwdev, 3450 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3451 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 3452 pd); 3453 rtw_write32_mask(rtwdev, 3454 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3455 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 3456 cs); 3457 3458 rtw_dbg(rtwdev, RTW_DBG_PHY, 3459 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n", 3460 rtw_is_assoc(rtwdev), bw, nrx, cs, pd); 3461 } 3462 3463 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 3464 { 3465 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3466 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 3467 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 3468 u8 cur_lvl; 3469 u8 nrx, bw; 3470 3471 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 3472 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 3473 3474 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n", 3475 dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx, 3476 dm_info->cck_fa_avg); 3477 3478 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 3479 return; 3480 3481 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 3482 3483 /* update cck pd info */ 3484 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 3485 3486 rtw8822c_phy_cck_pd_set_reg(rtwdev, 3487 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 3488 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 3489 bw, nrx); 3490 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 3491 } 3492 3493 #define PWR_TRACK_MASK 0x7f 3494 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 3495 { 3496 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3497 3498 switch (rf_path) { 3499 case RF_PATH_A: 3500 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 3501 dm_info->delta_power_index[rf_path]); 3502 break; 3503 case RF_PATH_B: 3504 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 3505 dm_info->delta_power_index[rf_path]); 3506 break; 3507 default: 3508 break; 3509 } 3510 } 3511 3512 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 3513 struct rtw_swing_table *swing_table, 3514 u8 path) 3515 { 3516 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3517 u8 thermal_value, delta; 3518 3519 if (rtwdev->efuse.thermal_meter[path] == 0xff) 3520 return; 3521 3522 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 3523 3524 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 3525 3526 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 3527 3528 dm_info->delta_power_index[path] = 3529 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 3530 delta); 3531 3532 rtw8822c_pwrtrack_set(rtwdev, path); 3533 } 3534 3535 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3536 { 3537 struct rtw_swing_table swing_table; 3538 u8 i; 3539 3540 rtw_phy_config_swing_table(rtwdev, &swing_table); 3541 3542 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 3543 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 3544 3545 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 3546 rtw8822c_do_iqk(rtwdev); 3547 } 3548 3549 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3550 { 3551 struct rtw_efuse *efuse = &rtwdev->efuse; 3552 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3553 3554 if (efuse->power_track_type != 0) 3555 return; 3556 3557 if (!dm_info->pwr_trk_triggered) { 3558 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3559 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 3560 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3561 3562 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3563 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 3564 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3565 3566 dm_info->pwr_trk_triggered = true; 3567 return; 3568 } 3569 3570 __rtw8822c_pwr_track(rtwdev); 3571 dm_info->pwr_trk_triggered = false; 3572 } 3573 3574 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 3575 {0x0086, 3576 RTW_PWR_CUT_ALL_MSK, 3577 RTW_PWR_INTF_SDIO_MSK, 3578 RTW_PWR_ADDR_SDIO, 3579 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3580 {0x0086, 3581 RTW_PWR_CUT_ALL_MSK, 3582 RTW_PWR_INTF_SDIO_MSK, 3583 RTW_PWR_ADDR_SDIO, 3584 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3585 {0x002E, 3586 RTW_PWR_CUT_ALL_MSK, 3587 RTW_PWR_INTF_ALL_MSK, 3588 RTW_PWR_ADDR_MAC, 3589 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3590 {0x002D, 3591 RTW_PWR_CUT_ALL_MSK, 3592 RTW_PWR_INTF_ALL_MSK, 3593 RTW_PWR_ADDR_MAC, 3594 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3595 {0x007F, 3596 RTW_PWR_CUT_ALL_MSK, 3597 RTW_PWR_INTF_ALL_MSK, 3598 RTW_PWR_ADDR_MAC, 3599 RTW_PWR_CMD_WRITE, BIT(7), 0}, 3600 {0x004A, 3601 RTW_PWR_CUT_ALL_MSK, 3602 RTW_PWR_INTF_USB_MSK, 3603 RTW_PWR_ADDR_MAC, 3604 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3605 {0x0005, 3606 RTW_PWR_CUT_ALL_MSK, 3607 RTW_PWR_INTF_ALL_MSK, 3608 RTW_PWR_ADDR_MAC, 3609 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 3610 {0xFFFF, 3611 RTW_PWR_CUT_ALL_MSK, 3612 RTW_PWR_INTF_ALL_MSK, 3613 0, 3614 RTW_PWR_CMD_END, 0, 0}, 3615 }; 3616 3617 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 3618 {0x0000, 3619 RTW_PWR_CUT_ALL_MSK, 3620 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3621 RTW_PWR_ADDR_MAC, 3622 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3623 {0x0005, 3624 RTW_PWR_CUT_ALL_MSK, 3625 RTW_PWR_INTF_ALL_MSK, 3626 RTW_PWR_ADDR_MAC, 3627 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 3628 {0x0075, 3629 RTW_PWR_CUT_ALL_MSK, 3630 RTW_PWR_INTF_PCI_MSK, 3631 RTW_PWR_ADDR_MAC, 3632 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3633 {0x0006, 3634 RTW_PWR_CUT_ALL_MSK, 3635 RTW_PWR_INTF_ALL_MSK, 3636 RTW_PWR_ADDR_MAC, 3637 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3638 {0x0075, 3639 RTW_PWR_CUT_ALL_MSK, 3640 RTW_PWR_INTF_PCI_MSK, 3641 RTW_PWR_ADDR_MAC, 3642 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3643 {0xFF1A, 3644 RTW_PWR_CUT_ALL_MSK, 3645 RTW_PWR_INTF_USB_MSK, 3646 RTW_PWR_ADDR_MAC, 3647 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3648 {0x002E, 3649 RTW_PWR_CUT_ALL_MSK, 3650 RTW_PWR_INTF_ALL_MSK, 3651 RTW_PWR_ADDR_MAC, 3652 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3653 {0x0006, 3654 RTW_PWR_CUT_ALL_MSK, 3655 RTW_PWR_INTF_ALL_MSK, 3656 RTW_PWR_ADDR_MAC, 3657 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3658 {0x0005, 3659 RTW_PWR_CUT_ALL_MSK, 3660 RTW_PWR_INTF_ALL_MSK, 3661 RTW_PWR_ADDR_MAC, 3662 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 3663 {0x1018, 3664 RTW_PWR_CUT_ALL_MSK, 3665 RTW_PWR_INTF_ALL_MSK, 3666 RTW_PWR_ADDR_MAC, 3667 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3668 {0x0005, 3669 RTW_PWR_CUT_ALL_MSK, 3670 RTW_PWR_INTF_ALL_MSK, 3671 RTW_PWR_ADDR_MAC, 3672 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3673 {0x0005, 3674 RTW_PWR_CUT_ALL_MSK, 3675 RTW_PWR_INTF_ALL_MSK, 3676 RTW_PWR_ADDR_MAC, 3677 RTW_PWR_CMD_POLLING, BIT(0), 0}, 3678 {0x0074, 3679 RTW_PWR_CUT_ALL_MSK, 3680 RTW_PWR_INTF_PCI_MSK, 3681 RTW_PWR_ADDR_MAC, 3682 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3683 {0x0071, 3684 RTW_PWR_CUT_ALL_MSK, 3685 RTW_PWR_INTF_PCI_MSK, 3686 RTW_PWR_ADDR_MAC, 3687 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3688 {0x0062, 3689 RTW_PWR_CUT_ALL_MSK, 3690 RTW_PWR_INTF_PCI_MSK, 3691 RTW_PWR_ADDR_MAC, 3692 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 3693 (BIT(7) | BIT(6) | BIT(5))}, 3694 {0x0061, 3695 RTW_PWR_CUT_ALL_MSK, 3696 RTW_PWR_INTF_PCI_MSK, 3697 RTW_PWR_ADDR_MAC, 3698 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 3699 {0x001F, 3700 RTW_PWR_CUT_ALL_MSK, 3701 RTW_PWR_INTF_ALL_MSK, 3702 RTW_PWR_ADDR_MAC, 3703 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3704 {0x00EF, 3705 RTW_PWR_CUT_ALL_MSK, 3706 RTW_PWR_INTF_ALL_MSK, 3707 RTW_PWR_ADDR_MAC, 3708 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3709 {0x1045, 3710 RTW_PWR_CUT_ALL_MSK, 3711 RTW_PWR_INTF_ALL_MSK, 3712 RTW_PWR_ADDR_MAC, 3713 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 3714 {0x0010, 3715 RTW_PWR_CUT_ALL_MSK, 3716 RTW_PWR_INTF_ALL_MSK, 3717 RTW_PWR_ADDR_MAC, 3718 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3719 {0x1064, 3720 RTW_PWR_CUT_ALL_MSK, 3721 RTW_PWR_INTF_ALL_MSK, 3722 RTW_PWR_ADDR_MAC, 3723 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3724 {0xFFFF, 3725 RTW_PWR_CUT_ALL_MSK, 3726 RTW_PWR_INTF_ALL_MSK, 3727 0, 3728 RTW_PWR_CMD_END, 0, 0}, 3729 }; 3730 3731 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 3732 {0x0093, 3733 RTW_PWR_CUT_ALL_MSK, 3734 RTW_PWR_INTF_ALL_MSK, 3735 RTW_PWR_ADDR_MAC, 3736 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3737 {0x001F, 3738 RTW_PWR_CUT_ALL_MSK, 3739 RTW_PWR_INTF_ALL_MSK, 3740 RTW_PWR_ADDR_MAC, 3741 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3742 {0x00EF, 3743 RTW_PWR_CUT_ALL_MSK, 3744 RTW_PWR_INTF_ALL_MSK, 3745 RTW_PWR_ADDR_MAC, 3746 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3747 {0x1045, 3748 RTW_PWR_CUT_ALL_MSK, 3749 RTW_PWR_INTF_ALL_MSK, 3750 RTW_PWR_ADDR_MAC, 3751 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3752 {0xFF1A, 3753 RTW_PWR_CUT_ALL_MSK, 3754 RTW_PWR_INTF_USB_MSK, 3755 RTW_PWR_ADDR_MAC, 3756 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 3757 {0x0049, 3758 RTW_PWR_CUT_ALL_MSK, 3759 RTW_PWR_INTF_ALL_MSK, 3760 RTW_PWR_ADDR_MAC, 3761 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3762 {0x0006, 3763 RTW_PWR_CUT_ALL_MSK, 3764 RTW_PWR_INTF_ALL_MSK, 3765 RTW_PWR_ADDR_MAC, 3766 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3767 {0x0002, 3768 RTW_PWR_CUT_ALL_MSK, 3769 RTW_PWR_INTF_ALL_MSK, 3770 RTW_PWR_ADDR_MAC, 3771 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3772 {0x0005, 3773 RTW_PWR_CUT_ALL_MSK, 3774 RTW_PWR_INTF_ALL_MSK, 3775 RTW_PWR_ADDR_MAC, 3776 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3777 {0x0005, 3778 RTW_PWR_CUT_ALL_MSK, 3779 RTW_PWR_INTF_ALL_MSK, 3780 RTW_PWR_ADDR_MAC, 3781 RTW_PWR_CMD_POLLING, BIT(1), 0}, 3782 {0x0000, 3783 RTW_PWR_CUT_ALL_MSK, 3784 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3785 RTW_PWR_ADDR_MAC, 3786 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3787 {0xFFFF, 3788 RTW_PWR_CUT_ALL_MSK, 3789 RTW_PWR_INTF_ALL_MSK, 3790 0, 3791 RTW_PWR_CMD_END, 0, 0}, 3792 }; 3793 3794 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 3795 {0x0005, 3796 RTW_PWR_CUT_ALL_MSK, 3797 RTW_PWR_INTF_SDIO_MSK, 3798 RTW_PWR_ADDR_MAC, 3799 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 3800 {0x0007, 3801 RTW_PWR_CUT_ALL_MSK, 3802 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3803 RTW_PWR_ADDR_MAC, 3804 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 3805 {0x0067, 3806 RTW_PWR_CUT_ALL_MSK, 3807 RTW_PWR_INTF_ALL_MSK, 3808 RTW_PWR_ADDR_MAC, 3809 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3810 {0x004A, 3811 RTW_PWR_CUT_ALL_MSK, 3812 RTW_PWR_INTF_USB_MSK, 3813 RTW_PWR_ADDR_MAC, 3814 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3815 {0x0081, 3816 RTW_PWR_CUT_ALL_MSK, 3817 RTW_PWR_INTF_ALL_MSK, 3818 RTW_PWR_ADDR_MAC, 3819 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 3820 {0x0090, 3821 RTW_PWR_CUT_ALL_MSK, 3822 RTW_PWR_INTF_ALL_MSK, 3823 RTW_PWR_ADDR_MAC, 3824 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3825 {0x0092, 3826 RTW_PWR_CUT_ALL_MSK, 3827 RTW_PWR_INTF_PCI_MSK, 3828 RTW_PWR_ADDR_MAC, 3829 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 3830 {0x0093, 3831 RTW_PWR_CUT_ALL_MSK, 3832 RTW_PWR_INTF_PCI_MSK, 3833 RTW_PWR_ADDR_MAC, 3834 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 3835 {0x0005, 3836 RTW_PWR_CUT_ALL_MSK, 3837 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3838 RTW_PWR_ADDR_MAC, 3839 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 3840 {0x0005, 3841 RTW_PWR_CUT_ALL_MSK, 3842 RTW_PWR_INTF_PCI_MSK, 3843 RTW_PWR_ADDR_MAC, 3844 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3845 {0x0086, 3846 RTW_PWR_CUT_ALL_MSK, 3847 RTW_PWR_INTF_SDIO_MSK, 3848 RTW_PWR_ADDR_SDIO, 3849 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3850 {0xFFFF, 3851 RTW_PWR_CUT_ALL_MSK, 3852 RTW_PWR_INTF_ALL_MSK, 3853 0, 3854 RTW_PWR_CMD_END, 0, 0}, 3855 }; 3856 3857 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 3858 trans_carddis_to_cardemu_8822c, 3859 trans_cardemu_to_act_8822c, 3860 NULL 3861 }; 3862 3863 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 3864 trans_act_to_cardemu_8822c, 3865 trans_cardemu_to_carddis_8822c, 3866 NULL 3867 }; 3868 3869 static const struct rtw_intf_phy_para usb2_param_8822c[] = { 3870 {0xFFFF, 0x00, 3871 RTW_IP_SEL_PHY, 3872 RTW_INTF_PHY_CUT_ALL, 3873 RTW_INTF_PHY_PLATFORM_ALL}, 3874 }; 3875 3876 static const struct rtw_intf_phy_para usb3_param_8822c[] = { 3877 {0xFFFF, 0x0000, 3878 RTW_IP_SEL_PHY, 3879 RTW_INTF_PHY_CUT_ALL, 3880 RTW_INTF_PHY_PLATFORM_ALL}, 3881 }; 3882 3883 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 3884 {0xFFFF, 0x0000, 3885 RTW_IP_SEL_PHY, 3886 RTW_INTF_PHY_CUT_ALL, 3887 RTW_INTF_PHY_PLATFORM_ALL}, 3888 }; 3889 3890 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 3891 {0xFFFF, 0x0000, 3892 RTW_IP_SEL_PHY, 3893 RTW_INTF_PHY_CUT_ALL, 3894 RTW_INTF_PHY_PLATFORM_ALL}, 3895 }; 3896 3897 static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 3898 .usb2_para = usb2_param_8822c, 3899 .usb3_para = usb3_param_8822c, 3900 .gen1_para = pcie_gen1_param_8822c, 3901 .gen2_para = pcie_gen2_param_8822c, 3902 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 3903 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 3904 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 3905 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 3906 }; 3907 3908 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 3909 [0] = RTW_DEF_RFE(8822c, 0, 0), 3910 [1] = RTW_DEF_RFE(8822c, 0, 0), 3911 [2] = RTW_DEF_RFE(8822c, 0, 0), 3912 [5] = RTW_DEF_RFE(8822c, 0, 5), 3913 [6] = RTW_DEF_RFE(8822c, 0, 0), 3914 }; 3915 3916 static const struct rtw_hw_reg rtw8822c_dig[] = { 3917 [0] = { .addr = 0x1d70, .mask = 0x7f }, 3918 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 3919 }; 3920 3921 static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = { 3922 .ctrl = LTECOEX_ACCESS_CTRL, 3923 .wdata = LTECOEX_WRITE_DATA, 3924 .rdata = LTECOEX_READ_DATA, 3925 }; 3926 3927 static const struct rtw_page_table page_table_8822c[] = { 3928 {64, 64, 64, 64, 1}, 3929 {64, 64, 64, 64, 1}, 3930 {64, 64, 0, 0, 1}, 3931 {64, 64, 64, 0, 1}, 3932 {64, 64, 64, 64, 1}, 3933 }; 3934 3935 static const struct rtw_rqpn rqpn_table_8822c[] = { 3936 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3937 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3938 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3939 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3940 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3941 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3942 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3943 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 3944 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3945 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3946 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3947 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3948 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3949 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3950 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3951 }; 3952 3953 static struct rtw_prioq_addrs prioq_addrs_8822c = { 3954 .prio[RTW_DMA_MAPPING_EXTRA] = { 3955 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 3956 }, 3957 .prio[RTW_DMA_MAPPING_LOW] = { 3958 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 3959 }, 3960 .prio[RTW_DMA_MAPPING_NORMAL] = { 3961 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 3962 }, 3963 .prio[RTW_DMA_MAPPING_HIGH] = { 3964 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 3965 }, 3966 .wsize = true, 3967 }; 3968 3969 static struct rtw_chip_ops rtw8822c_ops = { 3970 .phy_set_param = rtw8822c_phy_set_param, 3971 .read_efuse = rtw8822c_read_efuse, 3972 .query_rx_desc = rtw8822c_query_rx_desc, 3973 .set_channel = rtw8822c_set_channel, 3974 .mac_init = rtw8822c_mac_init, 3975 .read_rf = rtw_phy_read_rf, 3976 .write_rf = rtw_phy_write_rf_reg_mix, 3977 .set_tx_power_index = rtw8822c_set_tx_power_index, 3978 .set_antenna = rtw8822c_set_antenna, 3979 .cfg_ldo25 = rtw8822c_cfg_ldo25, 3980 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 3981 .dpk_track = rtw8822c_dpk_track, 3982 .phy_calibration = rtw8822c_phy_calibration, 3983 .cck_pd_set = rtw8822c_phy_cck_pd_set, 3984 .pwr_track = rtw8822c_pwr_track, 3985 .config_bfee = rtw8822c_bf_config_bfee, 3986 .set_gid_table = rtw_bf_set_gid_table, 3987 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 3988 3989 .coex_set_init = rtw8822c_coex_cfg_init, 3990 .coex_set_ant_switch = NULL, 3991 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 3992 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 3993 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 3994 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 3995 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 3996 }; 3997 3998 /* Shared-Antenna Coex Table */ 3999 static const struct coex_table_para table_sant_8822c[] = { 4000 {0xffffffff, 0xffffffff}, /* case-0 */ 4001 {0x55555555, 0x55555555}, 4002 {0x66555555, 0x66555555}, 4003 {0xaaaaaaaa, 0xaaaaaaaa}, 4004 {0x5a5a5a5a, 0x5a5a5a5a}, 4005 {0xfafafafa, 0xfafafafa}, /* case-5 */ 4006 {0x6a5a5555, 0xaaaaaaaa}, 4007 {0x6a5a56aa, 0x6a5a56aa}, 4008 {0x6a5a5a5a, 0x6a5a5a5a}, 4009 {0x66555555, 0x5a5a5a5a}, 4010 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 4011 {0x66555555, 0x6a5a5aaa}, 4012 {0x66555555, 0x5a5a5aaa}, 4013 {0x66555555, 0x6aaa5aaa}, 4014 {0x66555555, 0xaaaa5aaa}, 4015 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 4016 {0xffff55ff, 0xfafafafa}, 4017 {0xffff55ff, 0x6afa5afa}, 4018 {0xaaffffaa, 0xfafafafa}, 4019 {0xaa5555aa, 0x5a5a5a5a}, 4020 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 4021 {0xaa5555aa, 0xaaaaaaaa}, 4022 {0xffffffff, 0x5a5a5a5a}, 4023 {0xffffffff, 0x5a5a5a5a}, 4024 {0xffffffff, 0x55555555}, 4025 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 4026 {0x55555555, 0x5a5a5a5a}, 4027 {0x55555555, 0xaaaaaaaa}, 4028 {0x55555555, 0x6a5a6a5a}, 4029 {0x66556655, 0x66556655}, 4030 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/ 4031 {0xffffffff, 0x5aaa5aaa}, 4032 {0x56555555, 0x5a5a5aaa}, 4033 }; 4034 4035 /* Non-Shared-Antenna Coex Table */ 4036 static const struct coex_table_para table_nsant_8822c[] = { 4037 {0xffffffff, 0xffffffff}, /* case-100 */ 4038 {0x55555555, 0x55555555}, 4039 {0x66555555, 0x66555555}, 4040 {0xaaaaaaaa, 0xaaaaaaaa}, 4041 {0x5a5a5a5a, 0x5a5a5a5a}, 4042 {0xfafafafa, 0xfafafafa}, /* case-105 */ 4043 {0x5afa5afa, 0x5afa5afa}, 4044 {0x55555555, 0xfafafafa}, 4045 {0x66555555, 0xfafafafa}, 4046 {0x66555555, 0x5a5a5a5a}, 4047 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 4048 {0x66555555, 0xaaaaaaaa}, 4049 {0xffff55ff, 0xfafafafa}, 4050 {0xffff55ff, 0x5afa5afa}, 4051 {0xffff55ff, 0xaaaaaaaa}, 4052 {0xffff55ff, 0xffff55ff}, /* case-115 */ 4053 {0xaaffffaa, 0x5afa5afa}, 4054 {0xaaffffaa, 0xaaaaaaaa}, 4055 {0xffffffff, 0xfafafafa}, 4056 {0xffffffff, 0x5afa5afa}, 4057 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 4058 {0x55ff55ff, 0x5afa5afa}, 4059 {0x55ff55ff, 0xaaaaaaaa}, 4060 {0x55ff55ff, 0x55ff55ff} 4061 }; 4062 4063 /* Shared-Antenna TDMA */ 4064 static const struct coex_tdma_para tdma_sant_8822c[] = { 4065 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 4066 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 4067 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4068 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4069 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4070 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 4071 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4072 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4073 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4074 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4075 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 4076 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4077 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4078 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4079 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4080 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 4081 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 4082 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4083 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4084 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4085 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 4086 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 4087 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 4088 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 4089 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 4090 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 4091 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 4092 { {0x61, 0x08, 0x03, 0x11, 0x11} } 4093 }; 4094 4095 /* Non-Shared-Antenna TDMA */ 4096 static const struct coex_tdma_para tdma_nsant_8822c[] = { 4097 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 4098 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4099 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4100 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4101 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4102 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 4103 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4104 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4105 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4106 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4107 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 4108 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4109 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4110 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4111 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4112 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 4113 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 4114 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4115 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4116 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4117 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 4118 { {0x51, 0x08, 0x03, 0x10, 0x50} } 4119 }; 4120 4121 /* rssi in percentage % (dbm = % - 100) */ 4122 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 4123 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 4124 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 4125 4126 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 4127 static const struct coex_rf_para rf_para_tx_8822c[] = { 4128 {0, 0, false, 7}, /* for normal */ 4129 {0, 16, false, 7}, /* for WL-CPT */ 4130 {8, 17, true, 4}, 4131 {7, 18, true, 4}, 4132 {6, 19, true, 4}, 4133 {5, 20, true, 4} 4134 }; 4135 4136 static const struct coex_rf_para rf_para_rx_8822c[] = { 4137 {0, 0, false, 7}, /* for normal */ 4138 {0, 16, false, 7}, /* for WL-CPT */ 4139 {3, 24, true, 5}, 4140 {2, 26, true, 5}, 4141 {1, 27, true, 5}, 4142 {0, 28, true, 5} 4143 }; 4144 4145 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 4146 4147 static const u8 4148 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4149 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4150 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4151 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4152 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4153 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4154 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4155 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4156 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4157 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4158 }; 4159 4160 static const u8 4161 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4162 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4163 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4164 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4165 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4166 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4167 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4168 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4169 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4170 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4171 }; 4172 4173 static const u8 4174 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4175 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4176 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4177 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4178 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4179 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4180 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4181 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4182 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4183 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4184 }; 4185 4186 static const u8 4187 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4188 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4189 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4190 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4191 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4192 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4193 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4194 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4195 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4196 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4197 }; 4198 4199 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 4200 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 4201 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 4202 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 4203 }; 4204 4205 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 4206 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4207 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 4208 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 4209 }; 4210 4211 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 4212 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 4213 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 4214 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 4215 }; 4216 4217 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 4218 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4219 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 4220 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 4221 }; 4222 4223 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 4224 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4225 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4226 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 4227 }; 4228 4229 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 4230 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4231 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 4232 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 4233 }; 4234 4235 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 4236 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 4237 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 4238 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 4239 }; 4240 4241 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 4242 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4243 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4244 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 4245 }; 4246 4247 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 4248 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 4249 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 4250 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 4251 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 4252 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 4253 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 4254 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 4255 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 4256 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 4257 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 4258 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 4259 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 4260 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 4261 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 4262 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 4263 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 4264 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 4265 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 4266 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 4267 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 4268 }; 4269 4270 #ifdef CONFIG_PM 4271 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 4272 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 4273 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 4274 WIPHY_WOWLAN_NET_DETECT, 4275 .n_patterns = RTW_MAX_PATTERN_NUM, 4276 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 4277 .pattern_min_len = 1, 4278 .max_nd_match_sets = 4, 4279 }; 4280 #endif 4281 4282 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 4283 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 4284 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 4285 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 4286 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 4287 {0, 0, RTW_REG_DOMAIN_NL}, 4288 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4289 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4290 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4291 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4292 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 4293 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4294 {0, 0, RTW_REG_DOMAIN_NL}, 4295 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 4296 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 4297 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 4298 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 4299 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 4300 {0, 0, RTW_REG_DOMAIN_NL}, 4301 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4302 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4303 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 4304 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4305 }; 4306 4307 struct rtw_chip_info rtw8822c_hw_spec = { 4308 .ops = &rtw8822c_ops, 4309 .id = RTW_CHIP_TYPE_8822C, 4310 .fw_name = "rtw88/rtw8822c_fw.bin", 4311 .wlan_cpu = RTW_WCPU_11AC, 4312 .tx_pkt_desc_sz = 48, 4313 .tx_buf_desc_sz = 16, 4314 .rx_pkt_desc_sz = 24, 4315 .rx_buf_desc_sz = 8, 4316 .phy_efuse_size = 512, 4317 .log_efuse_size = 768, 4318 .ptct_efuse_size = 124, 4319 .txff_size = 262144, 4320 .rxff_size = 24576, 4321 .fw_rxff_size = 12288, 4322 .txgi_factor = 2, 4323 .is_pwr_by_rate_dec = false, 4324 .max_power_index = 0x7f, 4325 .csi_buf_pg_num = 50, 4326 .band = RTW_BAND_2G | RTW_BAND_5G, 4327 .page_size = 128, 4328 .dig_min = 0x20, 4329 .ht_supported = true, 4330 .vht_supported = true, 4331 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 4332 .sys_func_en = 0xD8, 4333 .pwr_on_seq = card_enable_flow_8822c, 4334 .pwr_off_seq = card_disable_flow_8822c, 4335 .page_table = page_table_8822c, 4336 .rqpn_table = rqpn_table_8822c, 4337 .prioq_addrs = &prioq_addrs_8822c, 4338 .intf_table = &phy_para_table_8822c, 4339 .dig = rtw8822c_dig, 4340 .dig_cck = NULL, 4341 .rf_base_addr = {0x3c00, 0x4c00}, 4342 .rf_sipi_addr = {0x1808, 0x4108}, 4343 .ltecoex_addr = &rtw8822c_ltecoex_addr, 4344 .mac_tbl = &rtw8822c_mac_tbl, 4345 .agc_tbl = &rtw8822c_agc_tbl, 4346 .bb_tbl = &rtw8822c_bb_tbl, 4347 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 4348 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 4349 .rfe_defs = rtw8822c_rfe_defs, 4350 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 4351 .en_dis_dpd = true, 4352 .dpd_ratemask = DIS_DPD_RATEALL, 4353 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 4354 .iqk_threshold = 8, 4355 .bfer_su_max_num = 2, 4356 .bfer_mu_max_num = 1, 4357 .rx_ldpc = true, 4358 4359 #ifdef CONFIG_PM 4360 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 4361 .wowlan_stub = &rtw_wowlan_stub_8822c, 4362 .max_sched_scan_ssids = 4, 4363 #endif 4364 .coex_para_ver = 0x201029, 4365 .bt_desired_ver = 0x1c, 4366 .scbd_support = true, 4367 .new_scbd10_def = true, 4368 .ble_hid_profile_support = true, 4369 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 4370 .bt_rssi_type = COEX_BTRSSI_DBM, 4371 .ant_isolation = 15, 4372 .rssi_tolerance = 2, 4373 .wl_rssi_step = wl_rssi_step_8822c, 4374 .bt_rssi_step = bt_rssi_step_8822c, 4375 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 4376 .table_sant = table_sant_8822c, 4377 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 4378 .table_nsant = table_nsant_8822c, 4379 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 4380 .tdma_sant = tdma_sant_8822c, 4381 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 4382 .tdma_nsant = tdma_nsant_8822c, 4383 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 4384 .wl_rf_para_tx = rf_para_tx_8822c, 4385 .wl_rf_para_rx = rf_para_rx_8822c, 4386 .bt_afh_span_bw20 = 0x24, 4387 .bt_afh_span_bw40 = 0x36, 4388 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 4389 .afh_5g = afh_5g_8822c, 4390 4391 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 4392 .coex_info_hw_regs = coex_info_hw_regs_8822c, 4393 4394 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 4395 }; 4396 EXPORT_SYMBOL(rtw8822c_hw_spec); 4397 4398 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 4399 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 4400 4401 MODULE_AUTHOR("Realtek Corporation"); 4402 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver"); 4403 MODULE_LICENSE("Dual BSD/GPL"); 4404