1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "fw.h" 7 #include "tx.h" 8 #include "rx.h" 9 #include "phy.h" 10 #include "rtw8822c.h" 11 #include "rtw8822c_table.h" 12 #include "mac.h" 13 #include "reg.h" 14 #include "debug.h" 15 16 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 17 u8 rx_path, bool is_tx2_path); 18 19 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 20 struct rtw8822c_efuse *map) 21 { 22 ether_addr_copy(efuse->addr, map->e.mac_addr); 23 } 24 25 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 26 { 27 struct rtw_efuse *efuse = &rtwdev->efuse; 28 struct rtw8822c_efuse *map; 29 int i; 30 31 map = (struct rtw8822c_efuse *)log_map; 32 33 efuse->rfe_option = map->rfe_option; 34 efuse->crystal_cap = map->xtal_k; 35 efuse->channel_plan = map->channel_plan; 36 efuse->country_code[0] = map->country_code[0]; 37 efuse->country_code[1] = map->country_code[1]; 38 efuse->bt_setting = map->rf_bt_setting; 39 efuse->regd = map->rf_board_option & 0x7; 40 41 for (i = 0; i < 4; i++) 42 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 43 44 switch (rtw_hci_type(rtwdev)) { 45 case RTW_HCI_TYPE_PCIE: 46 rtw8822ce_efuse_parsing(efuse, map); 47 break; 48 default: 49 /* unsupported now */ 50 return -ENOTSUPP; 51 } 52 53 return 0; 54 } 55 56 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 57 { 58 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 59 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 60 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 61 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 62 63 if (pre) 64 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 65 else 66 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 67 } 68 69 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 70 struct rtw_backup_info *backup, 71 struct rtw_backup_info *backup_rf) 72 { 73 u32 path, i; 74 u32 val; 75 u32 reg; 76 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 77 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 78 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 79 0x1a00, 0x1a14, 0x1d58, 0x1c38, 80 0x1e24, 0x1e28, 0x1860, 0x4160}; 81 82 for (i = 0; i < DACK_REG_8822C; i++) { 83 backup[i].len = 4; 84 backup[i].reg = addrs[i]; 85 backup[i].val = rtw_read32(rtwdev, addrs[i]); 86 } 87 88 for (path = 0; path < DACK_PATH_8822C; path++) { 89 for (i = 0; i < DACK_RF_8822C; i++) { 90 reg = rf_addr[i]; 91 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 92 backup_rf[path * i + i].reg = reg; 93 backup_rf[path * i + i].val = val; 94 } 95 } 96 } 97 98 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 99 struct rtw_backup_info *backup, 100 struct rtw_backup_info *backup_rf) 101 { 102 u32 path, i; 103 u32 val; 104 u32 reg; 105 106 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 107 108 for (path = 0; path < DACK_PATH_8822C; path++) { 109 for (i = 0; i < DACK_RF_8822C; i++) { 110 val = backup_rf[path * i + i].val; 111 reg = backup_rf[path * i + i].reg; 112 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 113 } 114 } 115 } 116 117 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 118 u32 *min, u32 *max) 119 { 120 if (value >= 0x200) { 121 if (*min >= 0x200) { 122 if (*min > value) 123 *min = value; 124 } else { 125 *min = value; 126 } 127 if (*max >= 0x200) { 128 if (*max < value) 129 *max = value; 130 } 131 } else { 132 if (*min < 0x200) { 133 if (*min > value) 134 *min = value; 135 } 136 137 if (*max >= 0x200) { 138 *max = value; 139 } else { 140 if (*max < value) 141 *max = value; 142 } 143 } 144 } 145 146 static void swap_u32(u32 *v1, u32 *v2) 147 { 148 u32 tmp; 149 150 tmp = *v1; 151 *v1 = *v2; 152 *v2 = tmp; 153 } 154 155 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 156 { 157 if (*v1 >= 0x200 && *v2 >= 0x200) { 158 if (*v1 > *v2) 159 swap_u32(v1, v2); 160 } else if (*v1 < 0x200 && *v2 < 0x200) { 161 if (*v1 > *v2) 162 swap_u32(v1, v2); 163 } else if (*v1 < 0x200 && *v2 >= 0x200) { 164 swap_u32(v1, v2); 165 } 166 } 167 168 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 169 { 170 u32 i, j; 171 172 for (i = 0; i < DACK_SN_8822C - 1; i++) { 173 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 174 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 175 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 176 } 177 } 178 } 179 180 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 181 { 182 u32 p, m, t, i; 183 184 m = 0; 185 p = 0; 186 for (i = 10; i < DACK_SN_8822C - 10; i++) { 187 if (vec[i] > 0x200) 188 m = (0x400 - vec[i]) + m; 189 else 190 p = vec[i] + p; 191 } 192 193 if (p > m) { 194 t = p - m; 195 t = t / (DACK_SN_8822C - 20); 196 } else { 197 t = m - p; 198 t = t / (DACK_SN_8822C - 20); 199 if (t != 0x0) 200 t = 0x400 - t; 201 } 202 203 *val = t; 204 } 205 206 static u32 rtw8822c_get_path_write_addr(u8 path) 207 { 208 u32 base_addr; 209 210 switch (path) { 211 case RF_PATH_A: 212 base_addr = 0x1800; 213 break; 214 case RF_PATH_B: 215 base_addr = 0x4100; 216 break; 217 default: 218 WARN_ON(1); 219 return -1; 220 } 221 222 return base_addr; 223 } 224 225 static u32 rtw8822c_get_path_read_addr(u8 path) 226 { 227 u32 base_addr; 228 229 switch (path) { 230 case RF_PATH_A: 231 base_addr = 0x2800; 232 break; 233 case RF_PATH_B: 234 base_addr = 0x4500; 235 break; 236 default: 237 WARN_ON(1); 238 return -1; 239 } 240 241 return base_addr; 242 } 243 244 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 245 { 246 bool ret = true; 247 248 if ((value >= 0x200 && (0x400 - value) > 0x64) || 249 (value < 0x200 && value > 0x64)) { 250 ret = false; 251 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 252 } 253 254 return ret; 255 } 256 257 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 258 { 259 u32 temp; 260 int i = 0, cnt = 0; 261 262 while (i < DACK_SN_8822C && cnt < 10000) { 263 cnt++; 264 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 265 iv[i] = (temp & 0x3ff000) >> 12; 266 qv[i] = temp & 0x3ff; 267 268 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 269 rtw8822c_dac_iq_check(rtwdev, qv[i])) 270 i++; 271 } 272 } 273 274 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 275 u32 *iv, u32 *qv, 276 u32 *i_value, u32 *q_value) 277 { 278 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 279 u32 i_delta, q_delta; 280 u32 temp; 281 int i, cnt = 0; 282 283 do { 284 i_min = iv[0]; 285 i_max = iv[0]; 286 q_min = qv[0]; 287 q_max = qv[0]; 288 for (i = 0; i < DACK_SN_8822C; i++) { 289 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 290 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 291 } 292 293 if (i_max < 0x200 && i_min < 0x200) 294 i_delta = i_max - i_min; 295 else if (i_max >= 0x200 && i_min >= 0x200) 296 i_delta = i_max - i_min; 297 else 298 i_delta = i_max + (0x400 - i_min); 299 300 if (q_max < 0x200 && q_min < 0x200) 301 q_delta = q_max - q_min; 302 else if (q_max >= 0x200 && q_min >= 0x200) 303 q_delta = q_max - q_min; 304 else 305 q_delta = q_max + (0x400 - q_min); 306 307 rtw_dbg(rtwdev, RTW_DBG_RFK, 308 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 309 i_min, i_max, i_delta); 310 rtw_dbg(rtwdev, RTW_DBG_RFK, 311 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 312 q_min, q_max, q_delta); 313 314 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 315 316 if (i_delta > 5 || q_delta > 5) { 317 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 318 iv[0] = (temp & 0x3ff000) >> 12; 319 qv[0] = temp & 0x3ff; 320 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 321 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 322 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 323 } else { 324 break; 325 } 326 } while (cnt++ < 100); 327 328 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 329 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 330 } 331 332 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 333 u32 *i_value, u32 *q_value) 334 { 335 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 336 u32 rf_a, rf_b; 337 338 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 339 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 340 341 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 342 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 343 344 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 345 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 346 } 347 348 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 349 { 350 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 351 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 352 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 353 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 354 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 355 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 356 rtw_write32(rtwdev, 0x1b00, 0x00000008); 357 rtw_write8(rtwdev, 0x1bcc, 0x3f); 358 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 359 rtw_write8(rtwdev, 0x1bcc, 0x3f); 360 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 361 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 362 } 363 364 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 365 u8 path, u32 *adc_ic, u32 *adc_qc) 366 { 367 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 368 u32 ic = 0, qc = 0, temp = 0; 369 u32 base_addr; 370 u32 path_sel; 371 int i; 372 373 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 374 375 base_addr = rtw8822c_get_path_write_addr(path); 376 switch (path) { 377 case RF_PATH_A: 378 path_sel = 0xa0000; 379 break; 380 case RF_PATH_B: 381 path_sel = 0x80000; 382 break; 383 default: 384 WARN_ON(1); 385 return; 386 } 387 388 /* ADCK step1 */ 389 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 390 if (path == RF_PATH_B) 391 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 392 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 393 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 394 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 395 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 396 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 397 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 398 for (i = 0; i < 10; i++) { 399 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 400 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 401 rtw_write32(rtwdev, 0x1c24, 0x00010002); 402 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 403 rtw_dbg(rtwdev, RTW_DBG_RFK, 404 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 405 406 /* compensation value */ 407 if (ic != 0x0) { 408 ic = 0x400 - ic; 409 *adc_ic = ic; 410 } 411 if (qc != 0x0) { 412 qc = 0x400 - qc; 413 *adc_qc = qc; 414 } 415 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 416 rtw_write32(rtwdev, base_addr + 0x68, temp); 417 dm_info->dack_adck[path] = temp; 418 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 419 base_addr + 0x68, temp); 420 /* check ADC DC offset */ 421 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 422 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 423 rtw_dbg(rtwdev, RTW_DBG_RFK, 424 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 425 if (ic >= 0x200) 426 ic = 0x400 - ic; 427 if (qc >= 0x200) 428 qc = 0x400 - qc; 429 if (ic < 5 && qc < 5) 430 break; 431 } 432 433 /* ADCK step2 */ 434 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 435 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 436 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 437 438 /* release pull low switch on IQ path */ 439 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 440 } 441 442 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 443 { 444 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 445 u32 base_addr; 446 u32 read_addr; 447 448 base_addr = rtw8822c_get_path_write_addr(path); 449 read_addr = rtw8822c_get_path_read_addr(path); 450 451 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 452 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 453 if (path == RF_PATH_A) { 454 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 455 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 456 } 457 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 458 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 459 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 460 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 461 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 462 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 463 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 464 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 465 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 466 mdelay(2); 467 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 468 mdelay(2); 469 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 470 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 471 mdelay(1); 472 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 473 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 474 mdelay(20); 475 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 476 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 477 rtw_err(rtwdev, "failed to wait for dack ready\n"); 478 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 479 mdelay(1); 480 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 481 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 482 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 483 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 484 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 485 } 486 487 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 488 u8 path, u32 *ic_out, u32 *qc_out) 489 { 490 u32 base_addr; 491 u32 ic, qc, ic_in, qc_in; 492 493 base_addr = rtw8822c_get_path_write_addr(path); 494 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 495 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 496 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 497 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 498 499 rtw_write32(rtwdev, 0x1b00, 0x00000008); 500 rtw_write8(rtwdev, 0x1bcc, 0x03f); 501 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 502 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 503 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 504 505 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 506 ic = ic_in; 507 qc = qc_in; 508 509 /* compensation value */ 510 if (ic != 0x0) 511 ic = 0x400 - ic; 512 if (qc != 0x0) 513 qc = 0x400 - qc; 514 if (ic < 0x300) { 515 ic = ic * 2 * 6 / 5; 516 ic = ic + 0x80; 517 } else { 518 ic = (0x400 - ic) * 2 * 6 / 5; 519 ic = 0x7f - ic; 520 } 521 if (qc < 0x300) { 522 qc = qc * 2 * 6 / 5; 523 qc = qc + 0x80; 524 } else { 525 qc = (0x400 - qc) * 2 * 6 / 5; 526 qc = 0x7f - qc; 527 } 528 529 *ic_out = ic; 530 *qc_out = qc; 531 532 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 533 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 534 } 535 536 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 537 u32 adc_ic, u32 adc_qc, 538 u32 *ic_in, u32 *qc_in, 539 u32 *i_out, u32 *q_out) 540 { 541 u32 base_addr; 542 u32 read_addr; 543 u32 ic, qc; 544 u32 temp; 545 546 base_addr = rtw8822c_get_path_write_addr(path); 547 read_addr = rtw8822c_get_path_read_addr(path); 548 ic = *ic_in; 549 qc = *qc_in; 550 551 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 552 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 553 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 554 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 555 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 556 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 557 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 558 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 559 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 560 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 561 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 562 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 563 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 564 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 565 mdelay(2); 566 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 567 mdelay(2); 568 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 569 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 570 mdelay(1); 571 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 572 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 573 mdelay(20); 574 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 575 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 576 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 577 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 578 mdelay(1); 579 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 580 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 581 582 /* check DAC DC offset */ 583 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 584 rtw_write32(rtwdev, base_addr + 0x68, temp); 585 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 586 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 587 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 588 if (ic >= 0x10) 589 ic = ic - 0x10; 590 else 591 ic = 0x400 - (0x10 - ic); 592 593 if (qc >= 0x10) 594 qc = qc - 0x10; 595 else 596 qc = 0x400 - (0x10 - qc); 597 598 *i_out = ic; 599 *q_out = qc; 600 601 if (ic >= 0x200) 602 ic = 0x400 - ic; 603 if (qc >= 0x200) 604 qc = 0x400 - qc; 605 606 *ic_in = ic; 607 *qc_in = qc; 608 609 rtw_dbg(rtwdev, RTW_DBG_RFK, 610 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 611 } 612 613 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 614 { 615 u32 base_addr = rtw8822c_get_path_write_addr(path); 616 617 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 618 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 619 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 620 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 621 } 622 623 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 624 u8 path, u8 vec, u32 w_addr, u32 r_addr) 625 { 626 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 627 u16 val; 628 u32 i; 629 630 if (WARN_ON(vec >= 2)) 631 return; 632 633 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 634 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 635 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 636 dm_info->dack_msbk[path][vec][i] = val; 637 } 638 } 639 640 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 641 { 642 u32 w_off = 0x1c; 643 u32 r_off = 0x2c; 644 u32 w_addr, r_addr; 645 646 if (WARN_ON(path >= 2)) 647 return; 648 649 /* backup I vector */ 650 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 651 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 652 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 653 654 /* backup Q vector */ 655 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 656 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 657 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 658 } 659 660 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 661 { 662 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 663 u8 val; 664 665 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 666 dm_info->dack_dck[RF_PATH_A][0][0] = val; 667 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 668 dm_info->dack_dck[RF_PATH_A][0][1] = val; 669 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 670 dm_info->dack_dck[RF_PATH_A][1][0] = val; 671 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 672 dm_info->dack_dck[RF_PATH_A][1][1] = val; 673 674 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 675 dm_info->dack_dck[RF_PATH_B][0][0] = val; 676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 677 dm_info->dack_dck[RF_PATH_B][1][0] = val; 678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 679 dm_info->dack_dck[RF_PATH_B][0][1] = val; 680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 681 dm_info->dack_dck[RF_PATH_B][1][1] = val; 682 } 683 684 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 685 { 686 u32 temp[3]; 687 688 temp[0] = rtw_read32(rtwdev, 0x1860); 689 temp[1] = rtw_read32(rtwdev, 0x4160); 690 temp[2] = rtw_read32(rtwdev, 0x9b4); 691 692 /* set clock */ 693 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 694 695 /* backup path-A I/Q */ 696 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 697 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 698 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 699 700 /* backup path-B I/Q */ 701 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 702 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 703 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 704 705 rtw8822c_dac_cal_backup_dck(rtwdev); 706 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 707 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 708 709 rtw_write32(rtwdev, 0x1860, temp[0]); 710 rtw_write32(rtwdev, 0x4160, temp[1]); 711 rtw_write32(rtwdev, 0x9b4, temp[2]); 712 } 713 714 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 715 { 716 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 717 u8 val; 718 719 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 720 val = dm_info->dack_dck[RF_PATH_A][0][0]; 721 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 722 val = dm_info->dack_dck[RF_PATH_A][0][1]; 723 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 724 725 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 726 val = dm_info->dack_dck[RF_PATH_A][1][0]; 727 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 728 val = dm_info->dack_dck[RF_PATH_A][1][1]; 729 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 730 731 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 732 val = dm_info->dack_dck[RF_PATH_B][0][0]; 733 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 734 val = dm_info->dack_dck[RF_PATH_B][0][1]; 735 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 736 737 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 738 val = dm_info->dack_dck[RF_PATH_B][1][0]; 739 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 740 val = dm_info->dack_dck[RF_PATH_B][1][1]; 741 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 742 } 743 744 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 745 { 746 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 747 748 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 749 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 750 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 751 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 752 753 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 754 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 755 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 756 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 757 758 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 759 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 760 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 761 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 762 763 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 764 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 765 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 766 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 767 768 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 769 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 770 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 771 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 772 773 rtw8822c_dac_cal_restore_dck(rtwdev); 774 775 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 776 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 777 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 778 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 779 780 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 781 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 782 783 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 784 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 785 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 786 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 787 788 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 789 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 790 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 791 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 792 793 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 794 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 795 } 796 797 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 798 u32 target_addr, u32 toggle_addr) 799 { 800 u32 cnt = 0; 801 802 do { 803 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 804 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 805 806 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 807 return true; 808 809 } while (cnt++ < 100); 810 811 return false; 812 } 813 814 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 815 { 816 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 817 u32 w_off = 0x1c; 818 u32 r_off = 0x2c; 819 u32 w_i, r_i, w_q, r_q; 820 u32 value; 821 u32 i; 822 823 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 824 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 825 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 826 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 827 828 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 829 return false; 830 831 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 832 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 833 value = dm_info->dack_msbk[path][0][i]; 834 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 835 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 836 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 837 } 838 839 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 840 841 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 842 return false; 843 844 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 845 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 846 value = dm_info->dack_msbk[path][1][i]; 847 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 848 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 849 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 850 } 851 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 852 853 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 854 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 855 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 856 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 857 858 return true; 859 } 860 861 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 862 { 863 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 864 return false; 865 866 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 867 return false; 868 869 return true; 870 } 871 872 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 873 { 874 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 875 u32 temp[3]; 876 877 /* sample the first element for both path's IQ vector */ 878 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 879 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 880 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 881 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 882 return false; 883 884 temp[0] = rtw_read32(rtwdev, 0x1860); 885 temp[1] = rtw_read32(rtwdev, 0x4160); 886 temp[2] = rtw_read32(rtwdev, 0x9b4); 887 888 rtw8822c_dac_cal_restore_prepare(rtwdev); 889 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 890 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 891 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 892 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 893 return false; 894 895 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 896 rtw_err(rtwdev, "failed to restore dack vectors\n"); 897 return false; 898 } 899 900 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 901 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 902 rtw_write32(rtwdev, 0x1860, temp[0]); 903 rtw_write32(rtwdev, 0x4160, temp[1]); 904 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 905 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 906 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 907 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 908 rtw_write32(rtwdev, 0x9b4, temp[2]); 909 910 return true; 911 } 912 913 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 914 { 915 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 916 struct rtw_backup_info backup[DACK_REG_8822C]; 917 u32 ic = 0, qc = 0, i; 918 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 919 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 920 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 921 922 if (rtw8822c_dac_cal_restore(rtwdev)) 923 return; 924 925 /* not able to restore, do it */ 926 927 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 928 929 rtw8822c_dac_bb_setting(rtwdev); 930 931 /* path-A */ 932 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 933 for (i = 0; i < 10; i++) { 934 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 935 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 936 ic_a = ic; 937 qc_a = qc; 938 939 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 940 &ic, &qc, &i_a, &q_a); 941 942 if (ic < 5 && qc < 5) 943 break; 944 } 945 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 946 947 /* path-B */ 948 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 949 for (i = 0; i < 10; i++) { 950 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 951 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 952 ic_b = ic; 953 qc_b = qc; 954 955 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 956 &ic, &qc, &i_b, &q_b); 957 958 if (ic < 5 && qc < 5) 959 break; 960 } 961 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 962 963 rtw_write32(rtwdev, 0x1b00, 0x00000008); 964 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 965 rtw_write8(rtwdev, 0x1bcc, 0x0); 966 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 967 rtw_write8(rtwdev, 0x1bcc, 0x0); 968 969 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 970 971 /* backup results to restore, saving a lot of time */ 972 rtw8822c_dac_cal_backup(rtwdev); 973 974 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 975 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 976 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 977 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 978 } 979 980 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 981 { 982 u8 x2k_busy; 983 984 mdelay(1); 985 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 986 if (x2k_busy == 1) { 987 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 988 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 989 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 990 mdelay(1); 991 } 992 } 993 994 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 995 { 996 rtw8822c_rf_dac_cal(rtwdev); 997 rtw8822c_rf_x2_check(rtwdev); 998 } 999 1000 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1001 { 1002 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1003 struct rtw_hal *hal = &rtwdev->hal; 1004 u8 crystal_cap; 1005 u8 cck_gi_u_bnd_msb = 0; 1006 u8 cck_gi_u_bnd_lsb = 0; 1007 u8 cck_gi_l_bnd_msb = 0; 1008 u8 cck_gi_l_bnd_lsb = 0; 1009 bool is_tx2_path; 1010 1011 /* power on BB/RF domain */ 1012 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1013 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1014 rtw_write8_set(rtwdev, REG_RF_CTRL, 1015 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1016 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1017 1018 /* pre init before header files config */ 1019 rtw8822c_header_file_init(rtwdev, true); 1020 1021 rtw_phy_load_tables(rtwdev); 1022 1023 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1024 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1025 crystal_cap | (crystal_cap << 7)); 1026 1027 /* post init after header files config */ 1028 rtw8822c_header_file_init(rtwdev, false); 1029 1030 is_tx2_path = false; 1031 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1032 is_tx2_path); 1033 rtw_phy_init(rtwdev); 1034 1035 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1036 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1037 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1038 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1039 1040 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1041 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1042 1043 rtw8822c_rf_init(rtwdev); 1044 /* wifi path controller */ 1045 rtw_write32_mask(rtwdev, 0x70, 0xff000000, 0x0e); 1046 rtw_write32_mask(rtwdev, 0x1704, 0xffffffff, 0x7700); 1047 rtw_write32_mask(rtwdev, 0x1700, 0xffffffff, 0xc00f0038); 1048 rtw_write32_mask(rtwdev, 0x6c0, 0xffffffff, 0xaaaaaaaa); 1049 rtw_write32_mask(rtwdev, 0x6c4, 0xffffffff, 0xaaaaaaaa); 1050 } 1051 1052 #define WLAN_TXQ_RPT_EN 0x1F 1053 #define WLAN_SLOT_TIME 0x09 1054 #define WLAN_PIFS_TIME 0x1C 1055 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1056 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1057 #define WLAN_SIFS_CCK_TRX 0x0A 1058 #define WLAN_SIFS_OFDM_TRX 0x10 1059 #define WLAN_NAV_MAX 0xC8 1060 #define WLAN_RDG_NAV 0x05 1061 #define WLAN_TXOP_NAV 0x1B 1062 #define WLAN_CCK_RX_TSF 0x30 1063 #define WLAN_OFDM_RX_TSF 0x30 1064 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1065 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1066 #define WLAN_DRV_EARLY_INT 0x04 1067 #define WLAN_BCN_CTRL_CLT0 0x10 1068 #define WLAN_BCN_DMA_TIME 0x02 1069 #define WLAN_BCN_MAX_ERR 0xFF 1070 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1071 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1072 #define WLAN_SIFS_CCK_CTX 0x0A 1073 #define WLAN_SIFS_CCK_IRX 0x0A 1074 #define WLAN_SIFS_OFDM_CTX 0x0E 1075 #define WLAN_SIFS_OFDM_IRX 0x0E 1076 #define WLAN_EIFS_DUR_TUNE 0x40 1077 #define WLAN_EDCA_VO_PARAM 0x002FA226 1078 #define WLAN_EDCA_VI_PARAM 0x005EA328 1079 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1080 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1081 1082 #define WLAN_RX_FILTER0 0xFFFFFFFF 1083 #define WLAN_RX_FILTER2 0xFFFF 1084 #define WLAN_RCR_CFG 0xE400220E 1085 #define WLAN_RXPKT_MAX_SZ 12288 1086 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1087 1088 #define WLAN_AMPDU_MAX_TIME 0x70 1089 #define WLAN_RTS_LEN_TH 0xFF 1090 #define WLAN_RTS_TX_TIME_TH 0x08 1091 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 1092 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 1093 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1094 #define FAST_EDCA_VO_TH 0x06 1095 #define FAST_EDCA_VI_TH 0x06 1096 #define FAST_EDCA_BE_TH 0x06 1097 #define FAST_EDCA_BK_TH 0x06 1098 #define WLAN_BAR_RETRY_LIMIT 0x01 1099 #define WLAN_BAR_ACK_TYPE 0x05 1100 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1101 #define WLAN_RESP_TXRATE 0x84 1102 #define WLAN_ACK_TO 0x21 1103 #define WLAN_ACK_TO_CCK 0x6A 1104 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1105 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1106 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1107 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1108 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1109 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1110 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1111 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1112 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1113 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1114 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1115 1116 #define WLAN_TX_FUNC_CFG1 0x30 1117 #define WLAN_TX_FUNC_CFG2 0x30 1118 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1119 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1120 #define WLAN_MAC_OPT_FUNC2 0x30810041 1121 1122 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1123 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1124 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1125 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1126 1127 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1128 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1129 1130 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1131 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1132 1133 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1134 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1135 1136 #define MAC_CLK_SPEED 80 /* 80M */ 1137 #define EFUSE_PCB_INFO_OFFSET 0xCA 1138 1139 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1140 { 1141 u8 value8; 1142 u16 value16; 1143 u32 value32; 1144 u16 pre_txcnt; 1145 1146 /* txq control */ 1147 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1148 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1149 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1150 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1151 /* sifs control */ 1152 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1153 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1154 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1155 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1156 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1157 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1158 /* rate fallback control */ 1159 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 1160 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 1161 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 1162 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 1163 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 1164 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 1165 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 1166 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 1167 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 1168 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 1169 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 1170 /* protocol configuration */ 1171 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 1172 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 1173 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 1174 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 1175 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 1176 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 1177 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 1178 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 1179 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 1180 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 1181 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 1182 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 1183 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 1184 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 1185 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 1186 /* close BA parser */ 1187 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 1188 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 1189 1190 /* EDCA configuration */ 1191 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 1192 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 1193 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 1194 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 1195 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 1196 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 1197 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 1198 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 1199 BIT_DIS_STBC_CFE) >> 8); 1200 1201 /* MAC clock configuration */ 1202 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 1203 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 1204 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 1205 1206 rtw_write8_set(rtwdev, REG_MISC_CTRL, 1207 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 1208 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 1209 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 1210 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 1211 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 1212 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 1213 /* Set beacon cotnrol - enable TSF and other related functions */ 1214 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1215 /* Set send beacon related registers */ 1216 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 1217 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 1218 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 1219 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 1220 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 1221 1222 /* WMAC configuration */ 1223 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 1224 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 1225 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 1226 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 1227 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 1228 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 1229 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 1230 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 1231 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 1232 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 1233 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 1234 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 1235 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 1236 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 1237 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 1238 1239 /* init low power */ 1240 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 1241 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 1242 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 1243 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 1244 value16 = 0; 1245 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 1246 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 1247 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 1248 | BIT_RXPSF_OFDMRST; 1249 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1250 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 1251 /* rx ignore configuration */ 1252 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 1253 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 1254 BIT_RXPSF_CONT_ERRCHKEN); 1255 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 1256 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1257 1258 return 0; 1259 } 1260 1261 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 1262 { 1263 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 1264 #define RF18_BAND_2G (0) 1265 #define RF18_BAND_5G (BIT(16) | BIT(8)) 1266 #define RF18_CHANNEL_MASK (MASKBYTE0) 1267 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 1268 #define RF18_RFSI_GE_CH80 (BIT(17)) 1269 #define RF18_RFSI_GT_CH140 (BIT(18)) 1270 #define RF18_BW_MASK (BIT(13) | BIT(12)) 1271 #define RF18_BW_20M (BIT(13) | BIT(12)) 1272 #define RF18_BW_40M (BIT(13)) 1273 #define RF18_BW_80M (BIT(12)) 1274 1275 u32 rf_reg18 = 0; 1276 u32 rf_rxbb = 0; 1277 1278 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 1279 1280 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 1281 RF18_BW_MASK); 1282 1283 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 1284 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 1285 if (channel > 144) 1286 rf_reg18 |= RF18_RFSI_GT_CH140; 1287 else if (channel >= 80) 1288 rf_reg18 |= RF18_RFSI_GE_CH80; 1289 1290 switch (bw) { 1291 case RTW_CHANNEL_WIDTH_5: 1292 case RTW_CHANNEL_WIDTH_10: 1293 case RTW_CHANNEL_WIDTH_20: 1294 default: 1295 rf_reg18 |= RF18_BW_20M; 1296 rf_rxbb = 0x18; 1297 break; 1298 case RTW_CHANNEL_WIDTH_40: 1299 /* RF bandwidth */ 1300 rf_reg18 |= RF18_BW_40M; 1301 rf_rxbb = 0x10; 1302 break; 1303 case RTW_CHANNEL_WIDTH_80: 1304 rf_reg18 |= RF18_BW_80M; 1305 rf_rxbb = 0x8; 1306 break; 1307 } 1308 1309 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 1310 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 1311 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 1312 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 1313 1314 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 1315 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 1316 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 1317 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 1318 1319 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 1320 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 1321 } 1322 1323 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 1324 { 1325 u32 igi; 1326 1327 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 1328 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 1329 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 1330 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 1331 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 1332 } 1333 1334 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1335 u8 primary_ch_idx) 1336 { 1337 if (channel <= 14) { 1338 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1339 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1340 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 1341 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1342 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1343 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 1344 1345 switch (bw) { 1346 case RTW_CHANNEL_WIDTH_20: 1347 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1348 0x5); 1349 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1350 0x5); 1351 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1352 0x6); 1353 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1354 0x6); 1355 break; 1356 case RTW_CHANNEL_WIDTH_40: 1357 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1358 0x4); 1359 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1360 0x4); 1361 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1362 0x0); 1363 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1364 0x0); 1365 break; 1366 } 1367 if (channel == 13 || channel == 14) 1368 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 1369 else if (channel == 11 || channel == 12) 1370 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 1371 else 1372 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 1373 if (channel == 14) { 1374 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 1375 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1376 0x4962c931); 1377 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 1378 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 1379 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 1380 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 1381 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1382 0xff012455); 1383 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 1384 } else { 1385 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 1386 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1387 0x3e18fec8); 1388 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 1389 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 1390 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 1391 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 1392 0x00faf0de); 1393 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1394 0x00122344); 1395 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 1396 0x0fffffff); 1397 } 1398 if (channel == 13) 1399 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1400 else 1401 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 1402 } else if (channel > 35) { 1403 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1404 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1405 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1406 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 1407 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x0); 1408 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 1409 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1410 if (channel >= 36 && channel <= 64) { 1411 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1412 0x1); 1413 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1414 0x1); 1415 } else if (channel >= 100 && channel <= 144) { 1416 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1417 0x2); 1418 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1419 0x2); 1420 } else if (channel >= 149) { 1421 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1422 0x3); 1423 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1424 0x3); 1425 } 1426 1427 if (channel >= 36 && channel <= 51) 1428 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 1429 else if (channel >= 52 && channel <= 55) 1430 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 1431 else if (channel >= 56 && channel <= 111) 1432 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 1433 else if (channel >= 112 && channel <= 119) 1434 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 1435 else if (channel >= 120 && channel <= 172) 1436 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 1437 else if (channel >= 173 && channel <= 177) 1438 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 1439 } 1440 1441 switch (bw) { 1442 case RTW_CHANNEL_WIDTH_20: 1443 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 1444 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1445 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 1446 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 1447 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 1448 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1449 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1450 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1451 break; 1452 case RTW_CHANNEL_WIDTH_40: 1453 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 1454 (primary_ch_idx == 1 ? 1 : 0)); 1455 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 1456 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1457 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1458 (primary_ch_idx | (primary_ch_idx << 4))); 1459 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 1460 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1461 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1462 break; 1463 case RTW_CHANNEL_WIDTH_80: 1464 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 1465 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1466 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1467 (primary_ch_idx | (primary_ch_idx << 4))); 1468 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 1469 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1470 break; 1471 case RTW_CHANNEL_WIDTH_5: 1472 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1473 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1474 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 1475 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 1476 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 1477 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1478 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1479 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1480 break; 1481 case RTW_CHANNEL_WIDTH_10: 1482 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1483 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1484 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 1485 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 1486 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 1487 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1488 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1489 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1490 break; 1491 } 1492 } 1493 1494 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1495 u8 primary_chan_idx) 1496 { 1497 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 1498 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 1499 rtw8822c_set_channel_rf(rtwdev, channel, bw); 1500 rtw8822c_toggle_igi(rtwdev); 1501 } 1502 1503 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1504 { 1505 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1506 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 1507 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 1508 } else if (rx_path == BB_PATH_AB) { 1509 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 1510 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 1511 } 1512 1513 if (rx_path == BB_PATH_A) 1514 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 1515 else if (rx_path == BB_PATH_B) 1516 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 1517 else if (rx_path == BB_PATH_AB) 1518 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 1519 } 1520 1521 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1522 { 1523 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1524 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 1525 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 1526 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 1527 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 1528 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 1529 } else if (rx_path == BB_PATH_AB) { 1530 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 1531 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 1532 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 1533 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 1534 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 1535 } 1536 1537 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 1538 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 1539 } 1540 1541 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1542 { 1543 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 1544 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 1545 } 1546 1547 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1548 bool is_tx2_path) 1549 { 1550 if (tx_path == BB_PATH_A) { 1551 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1552 } else if (tx_path == BB_PATH_B) { 1553 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 1554 } else { 1555 if (is_tx2_path) 1556 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 1557 else 1558 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1559 } 1560 } 1561 1562 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1563 bool is_tx2_path) 1564 { 1565 if (tx_path == BB_PATH_A) { 1566 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 1567 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1568 } else if (tx_path == BB_PATH_B) { 1569 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 1570 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1571 } else { 1572 if (is_tx2_path) { 1573 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 1574 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 1575 } else { 1576 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 1577 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 1578 } 1579 } 1580 } 1581 1582 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1583 bool is_tx2_path) 1584 { 1585 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 1586 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 1587 } 1588 1589 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 1590 u8 rx_path, bool is_tx2_path) 1591 { 1592 if ((tx_path | rx_path) & BB_PATH_A) 1593 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 1594 else 1595 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 1596 if ((tx_path | rx_path) & BB_PATH_B) 1597 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 1598 else 1599 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 1600 1601 rtw8822c_config_rx_path(rtwdev, rx_path); 1602 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 1603 1604 rtw8822c_toggle_igi(rtwdev); 1605 } 1606 1607 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 1608 struct rtw_rx_pkt_stat *pkt_stat) 1609 { 1610 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1611 u8 l_bnd, u_bnd; 1612 u8 gain_a, gain_b; 1613 s8 rx_power[RTW_RF_PATH_MAX]; 1614 s8 min_rx_power = -120; 1615 1616 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 1617 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 1618 l_bnd = dm_info->cck_gi_l_bnd; 1619 u_bnd = dm_info->cck_gi_u_bnd; 1620 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 1621 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 1622 if (gain_a < l_bnd) 1623 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 1624 else if (gain_a > u_bnd) 1625 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 1626 if (gain_b < l_bnd) 1627 rx_power[RF_PATH_A] += (l_bnd - gain_b) << 1; 1628 else if (gain_b > u_bnd) 1629 rx_power[RF_PATH_A] -= (gain_b - u_bnd) << 1; 1630 1631 rx_power[RF_PATH_A] -= 110; 1632 rx_power[RF_PATH_B] -= 110; 1633 1634 pkt_stat->rx_power[RF_PATH_A] = max3(rx_power[RF_PATH_A], 1635 rx_power[RF_PATH_B], 1636 min_rx_power); 1637 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1638 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1639 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 1640 min_rx_power); 1641 } 1642 1643 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 1644 struct rtw_rx_pkt_stat *pkt_stat) 1645 { 1646 u8 rxsc, bw; 1647 s8 min_rx_power = -120; 1648 1649 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 1650 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 1651 else 1652 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 1653 1654 if (rxsc >= 9 && rxsc <= 12) 1655 bw = RTW_CHANNEL_WIDTH_40; 1656 else if (rxsc >= 13) 1657 bw = RTW_CHANNEL_WIDTH_80; 1658 else 1659 bw = RTW_CHANNEL_WIDTH_20; 1660 1661 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 1662 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 1663 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 1664 pkt_stat->bw = bw; 1665 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 1666 pkt_stat->rx_power[RF_PATH_B], 1667 min_rx_power); 1668 } 1669 1670 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1671 struct rtw_rx_pkt_stat *pkt_stat) 1672 { 1673 u8 page; 1674 1675 page = *phy_status & 0xf; 1676 1677 switch (page) { 1678 case 0: 1679 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 1680 break; 1681 case 1: 1682 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 1683 break; 1684 default: 1685 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 1686 return; 1687 } 1688 } 1689 1690 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1691 struct rtw_rx_pkt_stat *pkt_stat, 1692 struct ieee80211_rx_status *rx_status) 1693 { 1694 struct ieee80211_hdr *hdr; 1695 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1696 u8 *phy_status = NULL; 1697 1698 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1699 1700 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1701 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1702 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1703 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc); 1704 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1705 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1706 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1707 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1708 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1709 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1710 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 1711 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1712 1713 /* drv_info_sz is in unit of 8-bytes */ 1714 pkt_stat->drv_info_sz *= 8; 1715 1716 /* c2h cmd pkt's rx/phy status is not interested */ 1717 if (pkt_stat->is_c2h) 1718 return; 1719 1720 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1721 pkt_stat->drv_info_sz); 1722 if (pkt_stat->phy_status) { 1723 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1724 query_phy_status(rtwdev, phy_status, pkt_stat); 1725 } 1726 1727 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1728 } 1729 1730 static void 1731 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 1732 u8 *tx_pwr_ref_ofdm) 1733 { 1734 struct rtw_hal *hal = &rtwdev->hal; 1735 u32 txref_cck[2] = {0x18a0, 0x41a0}; 1736 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 1737 u8 path; 1738 1739 for (path = 0; path < hal->rf_path_num; path++) { 1740 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1741 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 1742 tx_pwr_ref_cck[path]); 1743 } 1744 for (path = 0; path < hal->rf_path_num; path++) { 1745 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1746 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 1747 tx_pwr_ref_ofdm[path]); 1748 } 1749 } 1750 1751 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 1752 s8 *diff_idx) 1753 { 1754 u32 offset_txagc = 0x3a00; 1755 u8 rate_idx = rate & 0xfc; 1756 u8 pwr_idx[4]; 1757 u32 phy_pwr_idx; 1758 int i; 1759 1760 for (i = 0; i < 4; i++) 1761 pwr_idx[i] = diff_idx[i] & 0x7f; 1762 1763 phy_pwr_idx = pwr_idx[0] | 1764 (pwr_idx[1] << 8) | 1765 (pwr_idx[2] << 16) | 1766 (pwr_idx[3] << 24); 1767 1768 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 1769 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 1770 phy_pwr_idx); 1771 } 1772 1773 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 1774 { 1775 struct rtw_hal *hal = &rtwdev->hal; 1776 u8 rs, rate, j; 1777 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 1778 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 1779 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 1780 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 1781 s8 diff_a, diff_b; 1782 u8 pwr_a, pwr_b; 1783 s8 diff_idx[4]; 1784 1785 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 1786 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 1787 for (j = 0; j < rtw_rate_size[rs]; j++) { 1788 rate = rtw_rate_section[rs][j]; 1789 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 1790 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 1791 if (rs == 0) { 1792 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 1793 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 1794 } else { 1795 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 1796 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 1797 } 1798 diff_idx[rate % 4] = min(diff_a, diff_b); 1799 if (rate % 4 == 3) 1800 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 1801 diff_idx); 1802 } 1803 } 1804 } 1805 1806 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1807 { 1808 u8 ldo_pwr; 1809 1810 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 1811 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 1812 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 1813 } 1814 1815 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 1816 { 1817 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1818 u32 cck_enable; 1819 u32 cck_fa_cnt; 1820 u32 ofdm_fa_cnt; 1821 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 1822 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 1823 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 1824 1825 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 1826 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 1827 1828 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 1829 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 1830 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 1831 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 1832 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 1833 1834 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 1835 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 1836 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 1837 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 1838 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 1839 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 1840 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 1841 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 1842 1843 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 1844 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 1845 1846 dm_info->cck_fa_cnt = cck_fa_cnt; 1847 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1848 dm_info->total_fa_cnt = ofdm_fa_cnt; 1849 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 1850 1851 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 1852 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 1853 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 1854 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 1855 1856 /* disable rx clk gating to reset counters */ 1857 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 1858 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 1859 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 1860 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 1861 } 1862 1863 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 1864 { 1865 } 1866 1867 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 1868 {0x0086, 1869 RTW_PWR_CUT_ALL_MSK, 1870 RTW_PWR_INTF_SDIO_MSK, 1871 RTW_PWR_ADDR_SDIO, 1872 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1873 {0x0086, 1874 RTW_PWR_CUT_ALL_MSK, 1875 RTW_PWR_INTF_SDIO_MSK, 1876 RTW_PWR_ADDR_SDIO, 1877 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1878 {0x002E, 1879 RTW_PWR_CUT_ALL_MSK, 1880 RTW_PWR_INTF_ALL_MSK, 1881 RTW_PWR_ADDR_MAC, 1882 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1883 {0x002D, 1884 RTW_PWR_CUT_ALL_MSK, 1885 RTW_PWR_INTF_ALL_MSK, 1886 RTW_PWR_ADDR_MAC, 1887 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1888 {0x007F, 1889 RTW_PWR_CUT_ALL_MSK, 1890 RTW_PWR_INTF_ALL_MSK, 1891 RTW_PWR_ADDR_MAC, 1892 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1893 {0x004A, 1894 RTW_PWR_CUT_ALL_MSK, 1895 RTW_PWR_INTF_USB_MSK, 1896 RTW_PWR_ADDR_MAC, 1897 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1898 {0x0005, 1899 RTW_PWR_CUT_ALL_MSK, 1900 RTW_PWR_INTF_ALL_MSK, 1901 RTW_PWR_ADDR_MAC, 1902 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1903 {0xFFFF, 1904 RTW_PWR_CUT_ALL_MSK, 1905 RTW_PWR_INTF_ALL_MSK, 1906 0, 1907 RTW_PWR_CMD_END, 0, 0}, 1908 }; 1909 1910 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 1911 {0x0000, 1912 RTW_PWR_CUT_ALL_MSK, 1913 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1914 RTW_PWR_ADDR_MAC, 1915 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1916 {0x0005, 1917 RTW_PWR_CUT_ALL_MSK, 1918 RTW_PWR_INTF_ALL_MSK, 1919 RTW_PWR_ADDR_MAC, 1920 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1921 {0x0075, 1922 RTW_PWR_CUT_ALL_MSK, 1923 RTW_PWR_INTF_PCI_MSK, 1924 RTW_PWR_ADDR_MAC, 1925 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1926 {0x0006, 1927 RTW_PWR_CUT_ALL_MSK, 1928 RTW_PWR_INTF_ALL_MSK, 1929 RTW_PWR_ADDR_MAC, 1930 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1931 {0x0075, 1932 RTW_PWR_CUT_ALL_MSK, 1933 RTW_PWR_INTF_PCI_MSK, 1934 RTW_PWR_ADDR_MAC, 1935 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1936 {0xFF1A, 1937 RTW_PWR_CUT_ALL_MSK, 1938 RTW_PWR_INTF_USB_MSK, 1939 RTW_PWR_ADDR_MAC, 1940 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1941 {0x002E, 1942 RTW_PWR_CUT_ALL_MSK, 1943 RTW_PWR_INTF_ALL_MSK, 1944 RTW_PWR_ADDR_MAC, 1945 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1946 {0x0006, 1947 RTW_PWR_CUT_ALL_MSK, 1948 RTW_PWR_INTF_ALL_MSK, 1949 RTW_PWR_ADDR_MAC, 1950 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1951 {0x0005, 1952 RTW_PWR_CUT_ALL_MSK, 1953 RTW_PWR_INTF_ALL_MSK, 1954 RTW_PWR_ADDR_MAC, 1955 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1956 {0x0005, 1957 RTW_PWR_CUT_ALL_MSK, 1958 RTW_PWR_INTF_ALL_MSK, 1959 RTW_PWR_ADDR_MAC, 1960 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1961 {0x0005, 1962 RTW_PWR_CUT_ALL_MSK, 1963 RTW_PWR_INTF_ALL_MSK, 1964 RTW_PWR_ADDR_MAC, 1965 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1966 {0x0005, 1967 RTW_PWR_CUT_ALL_MSK, 1968 RTW_PWR_INTF_ALL_MSK, 1969 RTW_PWR_ADDR_MAC, 1970 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1971 {0x0074, 1972 RTW_PWR_CUT_ALL_MSK, 1973 RTW_PWR_INTF_PCI_MSK, 1974 RTW_PWR_ADDR_MAC, 1975 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1976 {0x0071, 1977 RTW_PWR_CUT_ALL_MSK, 1978 RTW_PWR_INTF_PCI_MSK, 1979 RTW_PWR_ADDR_MAC, 1980 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1981 {0x0062, 1982 RTW_PWR_CUT_ALL_MSK, 1983 RTW_PWR_INTF_PCI_MSK, 1984 RTW_PWR_ADDR_MAC, 1985 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1986 (BIT(7) | BIT(6) | BIT(5))}, 1987 {0x0061, 1988 RTW_PWR_CUT_ALL_MSK, 1989 RTW_PWR_INTF_PCI_MSK, 1990 RTW_PWR_ADDR_MAC, 1991 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1992 {0x001F, 1993 RTW_PWR_CUT_ALL_MSK, 1994 RTW_PWR_INTF_ALL_MSK, 1995 RTW_PWR_ADDR_MAC, 1996 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 1997 {0x00EF, 1998 RTW_PWR_CUT_ALL_MSK, 1999 RTW_PWR_INTF_ALL_MSK, 2000 RTW_PWR_ADDR_MAC, 2001 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 2002 {0x1045, 2003 RTW_PWR_CUT_ALL_MSK, 2004 RTW_PWR_INTF_ALL_MSK, 2005 RTW_PWR_ADDR_MAC, 2006 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 2007 {0x0010, 2008 RTW_PWR_CUT_ALL_MSK, 2009 RTW_PWR_INTF_ALL_MSK, 2010 RTW_PWR_ADDR_MAC, 2011 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2012 {0xFFFF, 2013 RTW_PWR_CUT_ALL_MSK, 2014 RTW_PWR_INTF_ALL_MSK, 2015 0, 2016 RTW_PWR_CMD_END, 0, 0}, 2017 }; 2018 2019 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 2020 {0x0093, 2021 RTW_PWR_CUT_ALL_MSK, 2022 RTW_PWR_INTF_ALL_MSK, 2023 RTW_PWR_ADDR_MAC, 2024 RTW_PWR_CMD_WRITE, BIT(3), 0}, 2025 {0x001F, 2026 RTW_PWR_CUT_ALL_MSK, 2027 RTW_PWR_INTF_ALL_MSK, 2028 RTW_PWR_ADDR_MAC, 2029 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2030 {0x00EF, 2031 RTW_PWR_CUT_ALL_MSK, 2032 RTW_PWR_INTF_ALL_MSK, 2033 RTW_PWR_ADDR_MAC, 2034 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2035 {0x1045, 2036 RTW_PWR_CUT_ALL_MSK, 2037 RTW_PWR_INTF_ALL_MSK, 2038 RTW_PWR_ADDR_MAC, 2039 RTW_PWR_CMD_WRITE, BIT(4), 0}, 2040 {0xFF1A, 2041 RTW_PWR_CUT_ALL_MSK, 2042 RTW_PWR_INTF_USB_MSK, 2043 RTW_PWR_ADDR_MAC, 2044 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 2045 {0x0049, 2046 RTW_PWR_CUT_ALL_MSK, 2047 RTW_PWR_INTF_ALL_MSK, 2048 RTW_PWR_ADDR_MAC, 2049 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2050 {0x0006, 2051 RTW_PWR_CUT_ALL_MSK, 2052 RTW_PWR_INTF_ALL_MSK, 2053 RTW_PWR_ADDR_MAC, 2054 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2055 {0x0002, 2056 RTW_PWR_CUT_ALL_MSK, 2057 RTW_PWR_INTF_ALL_MSK, 2058 RTW_PWR_ADDR_MAC, 2059 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2060 {0x0005, 2061 RTW_PWR_CUT_ALL_MSK, 2062 RTW_PWR_INTF_ALL_MSK, 2063 RTW_PWR_ADDR_MAC, 2064 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2065 {0x0005, 2066 RTW_PWR_CUT_ALL_MSK, 2067 RTW_PWR_INTF_ALL_MSK, 2068 RTW_PWR_ADDR_MAC, 2069 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2070 {0x0000, 2071 RTW_PWR_CUT_ALL_MSK, 2072 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2073 RTW_PWR_ADDR_MAC, 2074 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2075 {0xFFFF, 2076 RTW_PWR_CUT_ALL_MSK, 2077 RTW_PWR_INTF_ALL_MSK, 2078 0, 2079 RTW_PWR_CMD_END, 0, 0}, 2080 }; 2081 2082 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 2083 {0x0005, 2084 RTW_PWR_CUT_ALL_MSK, 2085 RTW_PWR_INTF_SDIO_MSK, 2086 RTW_PWR_ADDR_MAC, 2087 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 2088 {0x0007, 2089 RTW_PWR_CUT_ALL_MSK, 2090 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2091 RTW_PWR_ADDR_MAC, 2092 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2093 {0x0067, 2094 RTW_PWR_CUT_ALL_MSK, 2095 RTW_PWR_INTF_ALL_MSK, 2096 RTW_PWR_ADDR_MAC, 2097 RTW_PWR_CMD_WRITE, BIT(5), 0}, 2098 {0x004A, 2099 RTW_PWR_CUT_ALL_MSK, 2100 RTW_PWR_INTF_USB_MSK, 2101 RTW_PWR_ADDR_MAC, 2102 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2103 {0x0081, 2104 RTW_PWR_CUT_ALL_MSK, 2105 RTW_PWR_INTF_ALL_MSK, 2106 RTW_PWR_ADDR_MAC, 2107 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 2108 {0x0090, 2109 RTW_PWR_CUT_ALL_MSK, 2110 RTW_PWR_INTF_ALL_MSK, 2111 RTW_PWR_ADDR_MAC, 2112 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2113 {0x0005, 2114 RTW_PWR_CUT_ALL_MSK, 2115 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2116 RTW_PWR_ADDR_MAC, 2117 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 2118 {0x0005, 2119 RTW_PWR_CUT_ALL_MSK, 2120 RTW_PWR_INTF_PCI_MSK, 2121 RTW_PWR_ADDR_MAC, 2122 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2123 {0x0086, 2124 RTW_PWR_CUT_ALL_MSK, 2125 RTW_PWR_INTF_SDIO_MSK, 2126 RTW_PWR_ADDR_SDIO, 2127 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2128 {0xFFFF, 2129 RTW_PWR_CUT_ALL_MSK, 2130 RTW_PWR_INTF_ALL_MSK, 2131 0, 2132 RTW_PWR_CMD_END, 0, 0}, 2133 }; 2134 2135 static struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 2136 trans_carddis_to_cardemu_8822c, 2137 trans_cardemu_to_act_8822c, 2138 NULL 2139 }; 2140 2141 static struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 2142 trans_act_to_cardemu_8822c, 2143 trans_cardemu_to_carddis_8822c, 2144 NULL 2145 }; 2146 2147 static struct rtw_intf_phy_para usb2_param_8822c[] = { 2148 {0xFFFF, 0x00, 2149 RTW_IP_SEL_PHY, 2150 RTW_INTF_PHY_CUT_ALL, 2151 RTW_INTF_PHY_PLATFORM_ALL}, 2152 }; 2153 2154 static struct rtw_intf_phy_para usb3_param_8822c[] = { 2155 {0xFFFF, 0x0000, 2156 RTW_IP_SEL_PHY, 2157 RTW_INTF_PHY_CUT_ALL, 2158 RTW_INTF_PHY_PLATFORM_ALL}, 2159 }; 2160 2161 static struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 2162 {0xFFFF, 0x0000, 2163 RTW_IP_SEL_PHY, 2164 RTW_INTF_PHY_CUT_ALL, 2165 RTW_INTF_PHY_PLATFORM_ALL}, 2166 }; 2167 2168 static struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 2169 {0xFFFF, 0x0000, 2170 RTW_IP_SEL_PHY, 2171 RTW_INTF_PHY_CUT_ALL, 2172 RTW_INTF_PHY_PLATFORM_ALL}, 2173 }; 2174 2175 static struct rtw_intf_phy_para_table phy_para_table_8822c = { 2176 .usb2_para = usb2_param_8822c, 2177 .usb3_para = usb3_param_8822c, 2178 .gen1_para = pcie_gen1_param_8822c, 2179 .gen2_para = pcie_gen2_param_8822c, 2180 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 2181 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 2182 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 2183 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 2184 }; 2185 2186 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 2187 [0] = RTW_DEF_RFE(8822c, 0, 0), 2188 [1] = RTW_DEF_RFE(8822c, 0, 0), 2189 [2] = RTW_DEF_RFE(8822c, 0, 0), 2190 }; 2191 2192 static struct rtw_hw_reg rtw8822c_dig[] = { 2193 [0] = { .addr = 0x1d70, .mask = 0x7f }, 2194 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 2195 }; 2196 2197 static struct rtw_page_table page_table_8822c[] = { 2198 {64, 64, 64, 64, 1}, 2199 {64, 64, 64, 64, 1}, 2200 {64, 64, 0, 0, 1}, 2201 {64, 64, 64, 0, 1}, 2202 {64, 64, 64, 64, 1}, 2203 }; 2204 2205 static struct rtw_rqpn rqpn_table_8822c[] = { 2206 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2207 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2208 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2209 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2210 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2211 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2212 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2213 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2214 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2215 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2216 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2217 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2218 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2219 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2220 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2221 }; 2222 2223 static struct rtw_chip_ops rtw8822c_ops = { 2224 .phy_set_param = rtw8822c_phy_set_param, 2225 .read_efuse = rtw8822c_read_efuse, 2226 .query_rx_desc = rtw8822c_query_rx_desc, 2227 .set_channel = rtw8822c_set_channel, 2228 .mac_init = rtw8822c_mac_init, 2229 .read_rf = rtw_phy_read_rf, 2230 .write_rf = rtw_phy_write_rf_reg_mix, 2231 .set_tx_power_index = rtw8822c_set_tx_power_index, 2232 .cfg_ldo25 = rtw8822c_cfg_ldo25, 2233 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 2234 .do_iqk = rtw8822c_do_iqk, 2235 }; 2236 2237 struct rtw_chip_info rtw8822c_hw_spec = { 2238 .ops = &rtw8822c_ops, 2239 .id = RTW_CHIP_TYPE_8822C, 2240 .fw_name = "rtw88/rtw8822c_fw.bin", 2241 .tx_pkt_desc_sz = 48, 2242 .tx_buf_desc_sz = 16, 2243 .rx_pkt_desc_sz = 24, 2244 .rx_buf_desc_sz = 8, 2245 .phy_efuse_size = 512, 2246 .log_efuse_size = 768, 2247 .ptct_efuse_size = 124, 2248 .txff_size = 262144, 2249 .rxff_size = 24576, 2250 .txgi_factor = 2, 2251 .is_pwr_by_rate_dec = false, 2252 .max_power_index = 0x7f, 2253 .csi_buf_pg_num = 50, 2254 .band = RTW_BAND_2G | RTW_BAND_5G, 2255 .page_size = 128, 2256 .dig_min = 0x20, 2257 .ht_supported = true, 2258 .vht_supported = true, 2259 .sys_func_en = 0xD8, 2260 .pwr_on_seq = card_enable_flow_8822c, 2261 .pwr_off_seq = card_disable_flow_8822c, 2262 .page_table = page_table_8822c, 2263 .rqpn_table = rqpn_table_8822c, 2264 .intf_table = &phy_para_table_8822c, 2265 .dig = rtw8822c_dig, 2266 .rf_base_addr = {0x3c00, 0x4c00}, 2267 .rf_sipi_addr = {0x1808, 0x4108}, 2268 .mac_tbl = &rtw8822c_mac_tbl, 2269 .agc_tbl = &rtw8822c_agc_tbl, 2270 .bb_tbl = &rtw8822c_bb_tbl, 2271 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 2272 .rf_tbl = {&rtw8822c_rf_a_tbl, &rtw8822c_rf_b_tbl}, 2273 .rfe_defs = rtw8822c_rfe_defs, 2274 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 2275 }; 2276 EXPORT_SYMBOL(rtw8822c_hw_spec); 2277 2278 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 2279