1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8822c.h" 12 #include "rtw8822c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "util.h" 17 #include "bf.h" 18 19 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 20 u8 rx_path, bool is_tx2_path); 21 22 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 23 struct rtw8822c_efuse *map) 24 { 25 ether_addr_copy(efuse->addr, map->e.mac_addr); 26 } 27 28 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 29 { 30 struct rtw_efuse *efuse = &rtwdev->efuse; 31 struct rtw8822c_efuse *map; 32 int i; 33 34 map = (struct rtw8822c_efuse *)log_map; 35 36 efuse->rfe_option = map->rfe_option; 37 efuse->rf_board_option = map->rf_board_option; 38 efuse->crystal_cap = map->xtal_k; 39 efuse->channel_plan = map->channel_plan; 40 efuse->country_code[0] = map->country_code[0]; 41 efuse->country_code[1] = map->country_code[1]; 42 efuse->bt_setting = map->rf_bt_setting; 43 efuse->regd = map->rf_board_option & 0x7; 44 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 45 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 46 efuse->thermal_meter_k = 47 (map->path_a_thermal + map->path_b_thermal) >> 1; 48 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 49 50 for (i = 0; i < 4; i++) 51 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 52 53 switch (rtw_hci_type(rtwdev)) { 54 case RTW_HCI_TYPE_PCIE: 55 rtw8822ce_efuse_parsing(efuse, map); 56 break; 57 default: 58 /* unsupported now */ 59 return -ENOTSUPP; 60 } 61 62 return 0; 63 } 64 65 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 66 { 67 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 68 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 69 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 70 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 71 72 if (pre) 73 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 74 else 75 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 76 } 77 78 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 79 struct rtw_backup_info *backup, 80 struct rtw_backup_info *backup_rf) 81 { 82 u32 path, i; 83 u32 val; 84 u32 reg; 85 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 86 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 87 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 88 0x1a00, 0x1a14, 0x1d58, 0x1c38, 89 0x1e24, 0x1e28, 0x1860, 0x4160}; 90 91 for (i = 0; i < DACK_REG_8822C; i++) { 92 backup[i].len = 4; 93 backup[i].reg = addrs[i]; 94 backup[i].val = rtw_read32(rtwdev, addrs[i]); 95 } 96 97 for (path = 0; path < DACK_PATH_8822C; path++) { 98 for (i = 0; i < DACK_RF_8822C; i++) { 99 reg = rf_addr[i]; 100 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 101 backup_rf[path * i + i].reg = reg; 102 backup_rf[path * i + i].val = val; 103 } 104 } 105 } 106 107 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 108 struct rtw_backup_info *backup, 109 struct rtw_backup_info *backup_rf) 110 { 111 u32 path, i; 112 u32 val; 113 u32 reg; 114 115 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 116 117 for (path = 0; path < DACK_PATH_8822C; path++) { 118 for (i = 0; i < DACK_RF_8822C; i++) { 119 val = backup_rf[path * i + i].val; 120 reg = backup_rf[path * i + i].reg; 121 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 122 } 123 } 124 } 125 126 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 127 u32 *min, u32 *max) 128 { 129 if (value >= 0x200) { 130 if (*min >= 0x200) { 131 if (*min > value) 132 *min = value; 133 } else { 134 *min = value; 135 } 136 if (*max >= 0x200) { 137 if (*max < value) 138 *max = value; 139 } 140 } else { 141 if (*min < 0x200) { 142 if (*min > value) 143 *min = value; 144 } 145 146 if (*max >= 0x200) { 147 *max = value; 148 } else { 149 if (*max < value) 150 *max = value; 151 } 152 } 153 } 154 155 static void swap_u32(u32 *v1, u32 *v2) 156 { 157 u32 tmp; 158 159 tmp = *v1; 160 *v1 = *v2; 161 *v2 = tmp; 162 } 163 164 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 165 { 166 if (*v1 >= 0x200 && *v2 >= 0x200) { 167 if (*v1 > *v2) 168 swap_u32(v1, v2); 169 } else if (*v1 < 0x200 && *v2 < 0x200) { 170 if (*v1 > *v2) 171 swap_u32(v1, v2); 172 } else if (*v1 < 0x200 && *v2 >= 0x200) { 173 swap_u32(v1, v2); 174 } 175 } 176 177 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 178 { 179 u32 i, j; 180 181 for (i = 0; i < DACK_SN_8822C - 1; i++) { 182 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 183 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 184 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 185 } 186 } 187 } 188 189 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 190 { 191 u32 p, m, t, i; 192 193 m = 0; 194 p = 0; 195 for (i = 10; i < DACK_SN_8822C - 10; i++) { 196 if (vec[i] > 0x200) 197 m = (0x400 - vec[i]) + m; 198 else 199 p = vec[i] + p; 200 } 201 202 if (p > m) { 203 t = p - m; 204 t = t / (DACK_SN_8822C - 20); 205 } else { 206 t = m - p; 207 t = t / (DACK_SN_8822C - 20); 208 if (t != 0x0) 209 t = 0x400 - t; 210 } 211 212 *val = t; 213 } 214 215 static u32 rtw8822c_get_path_write_addr(u8 path) 216 { 217 u32 base_addr; 218 219 switch (path) { 220 case RF_PATH_A: 221 base_addr = 0x1800; 222 break; 223 case RF_PATH_B: 224 base_addr = 0x4100; 225 break; 226 default: 227 WARN_ON(1); 228 return -1; 229 } 230 231 return base_addr; 232 } 233 234 static u32 rtw8822c_get_path_read_addr(u8 path) 235 { 236 u32 base_addr; 237 238 switch (path) { 239 case RF_PATH_A: 240 base_addr = 0x2800; 241 break; 242 case RF_PATH_B: 243 base_addr = 0x4500; 244 break; 245 default: 246 WARN_ON(1); 247 return -1; 248 } 249 250 return base_addr; 251 } 252 253 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 254 { 255 bool ret = true; 256 257 if ((value >= 0x200 && (0x400 - value) > 0x64) || 258 (value < 0x200 && value > 0x64)) { 259 ret = false; 260 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 261 } 262 263 return ret; 264 } 265 266 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 267 { 268 u32 temp; 269 int i = 0, cnt = 0; 270 271 while (i < DACK_SN_8822C && cnt < 10000) { 272 cnt++; 273 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 274 iv[i] = (temp & 0x3ff000) >> 12; 275 qv[i] = temp & 0x3ff; 276 277 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 278 rtw8822c_dac_iq_check(rtwdev, qv[i])) 279 i++; 280 } 281 } 282 283 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 284 u32 *iv, u32 *qv, 285 u32 *i_value, u32 *q_value) 286 { 287 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 288 u32 i_delta, q_delta; 289 u32 temp; 290 int i, cnt = 0; 291 292 do { 293 i_min = iv[0]; 294 i_max = iv[0]; 295 q_min = qv[0]; 296 q_max = qv[0]; 297 for (i = 0; i < DACK_SN_8822C; i++) { 298 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 299 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 300 } 301 302 if (i_max < 0x200 && i_min < 0x200) 303 i_delta = i_max - i_min; 304 else if (i_max >= 0x200 && i_min >= 0x200) 305 i_delta = i_max - i_min; 306 else 307 i_delta = i_max + (0x400 - i_min); 308 309 if (q_max < 0x200 && q_min < 0x200) 310 q_delta = q_max - q_min; 311 else if (q_max >= 0x200 && q_min >= 0x200) 312 q_delta = q_max - q_min; 313 else 314 q_delta = q_max + (0x400 - q_min); 315 316 rtw_dbg(rtwdev, RTW_DBG_RFK, 317 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 318 i_min, i_max, i_delta); 319 rtw_dbg(rtwdev, RTW_DBG_RFK, 320 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 321 q_min, q_max, q_delta); 322 323 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 324 325 if (i_delta > 5 || q_delta > 5) { 326 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 327 iv[0] = (temp & 0x3ff000) >> 12; 328 qv[0] = temp & 0x3ff; 329 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 330 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 331 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 332 } else { 333 break; 334 } 335 } while (cnt++ < 100); 336 337 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 338 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 339 } 340 341 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 342 u32 *i_value, u32 *q_value) 343 { 344 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 345 u32 rf_a, rf_b; 346 347 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 348 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 349 350 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 351 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 352 353 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 354 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 355 } 356 357 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 358 { 359 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 360 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 361 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 362 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 363 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 364 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 365 rtw_write32(rtwdev, 0x1b00, 0x00000008); 366 rtw_write8(rtwdev, 0x1bcc, 0x3f); 367 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 368 rtw_write8(rtwdev, 0x1bcc, 0x3f); 369 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 370 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 371 } 372 373 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 374 u8 path, u32 *adc_ic, u32 *adc_qc) 375 { 376 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 377 u32 ic = 0, qc = 0, temp = 0; 378 u32 base_addr; 379 u32 path_sel; 380 int i; 381 382 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 383 384 base_addr = rtw8822c_get_path_write_addr(path); 385 switch (path) { 386 case RF_PATH_A: 387 path_sel = 0xa0000; 388 break; 389 case RF_PATH_B: 390 path_sel = 0x80000; 391 break; 392 default: 393 WARN_ON(1); 394 return; 395 } 396 397 /* ADCK step1 */ 398 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 399 if (path == RF_PATH_B) 400 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 401 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 402 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 403 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 404 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 405 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 406 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 407 for (i = 0; i < 10; i++) { 408 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 409 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 410 rtw_write32(rtwdev, 0x1c24, 0x00010002); 411 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 412 rtw_dbg(rtwdev, RTW_DBG_RFK, 413 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 414 415 /* compensation value */ 416 if (ic != 0x0) { 417 ic = 0x400 - ic; 418 *adc_ic = ic; 419 } 420 if (qc != 0x0) { 421 qc = 0x400 - qc; 422 *adc_qc = qc; 423 } 424 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 425 rtw_write32(rtwdev, base_addr + 0x68, temp); 426 dm_info->dack_adck[path] = temp; 427 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 428 base_addr + 0x68, temp); 429 /* check ADC DC offset */ 430 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 431 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 432 rtw_dbg(rtwdev, RTW_DBG_RFK, 433 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 434 if (ic >= 0x200) 435 ic = 0x400 - ic; 436 if (qc >= 0x200) 437 qc = 0x400 - qc; 438 if (ic < 5 && qc < 5) 439 break; 440 } 441 442 /* ADCK step2 */ 443 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 444 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 445 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 446 447 /* release pull low switch on IQ path */ 448 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 449 } 450 451 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 452 { 453 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 454 u32 base_addr; 455 u32 read_addr; 456 457 base_addr = rtw8822c_get_path_write_addr(path); 458 read_addr = rtw8822c_get_path_read_addr(path); 459 460 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 461 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 462 if (path == RF_PATH_A) { 463 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 464 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 465 } 466 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 467 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 468 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 469 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 470 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 471 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 472 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 473 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 474 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 475 mdelay(2); 476 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 477 mdelay(2); 478 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 479 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 480 mdelay(1); 481 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 482 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 483 mdelay(20); 484 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 485 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 486 rtw_err(rtwdev, "failed to wait for dack ready\n"); 487 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 488 mdelay(1); 489 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 490 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 491 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 492 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 493 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 494 } 495 496 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 497 u8 path, u32 *ic_out, u32 *qc_out) 498 { 499 u32 base_addr; 500 u32 ic, qc, ic_in, qc_in; 501 502 base_addr = rtw8822c_get_path_write_addr(path); 503 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 504 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 505 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 506 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 507 508 rtw_write32(rtwdev, 0x1b00, 0x00000008); 509 rtw_write8(rtwdev, 0x1bcc, 0x03f); 510 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 511 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 512 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 513 514 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 515 ic = ic_in; 516 qc = qc_in; 517 518 /* compensation value */ 519 if (ic != 0x0) 520 ic = 0x400 - ic; 521 if (qc != 0x0) 522 qc = 0x400 - qc; 523 if (ic < 0x300) { 524 ic = ic * 2 * 6 / 5; 525 ic = ic + 0x80; 526 } else { 527 ic = (0x400 - ic) * 2 * 6 / 5; 528 ic = 0x7f - ic; 529 } 530 if (qc < 0x300) { 531 qc = qc * 2 * 6 / 5; 532 qc = qc + 0x80; 533 } else { 534 qc = (0x400 - qc) * 2 * 6 / 5; 535 qc = 0x7f - qc; 536 } 537 538 *ic_out = ic; 539 *qc_out = qc; 540 541 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 542 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 543 } 544 545 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 546 u32 adc_ic, u32 adc_qc, 547 u32 *ic_in, u32 *qc_in, 548 u32 *i_out, u32 *q_out) 549 { 550 u32 base_addr; 551 u32 read_addr; 552 u32 ic, qc; 553 u32 temp; 554 555 base_addr = rtw8822c_get_path_write_addr(path); 556 read_addr = rtw8822c_get_path_read_addr(path); 557 ic = *ic_in; 558 qc = *qc_in; 559 560 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 561 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 562 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 563 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 564 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 565 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 566 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 567 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 568 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 569 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 570 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 571 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 572 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 573 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 574 mdelay(2); 575 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 576 mdelay(2); 577 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 578 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 579 mdelay(1); 580 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 581 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 582 mdelay(20); 583 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 584 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 585 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 586 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 587 mdelay(1); 588 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 589 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 590 591 /* check DAC DC offset */ 592 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 593 rtw_write32(rtwdev, base_addr + 0x68, temp); 594 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 595 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 596 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 597 if (ic >= 0x10) 598 ic = ic - 0x10; 599 else 600 ic = 0x400 - (0x10 - ic); 601 602 if (qc >= 0x10) 603 qc = qc - 0x10; 604 else 605 qc = 0x400 - (0x10 - qc); 606 607 *i_out = ic; 608 *q_out = qc; 609 610 if (ic >= 0x200) 611 ic = 0x400 - ic; 612 if (qc >= 0x200) 613 qc = 0x400 - qc; 614 615 *ic_in = ic; 616 *qc_in = qc; 617 618 rtw_dbg(rtwdev, RTW_DBG_RFK, 619 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 620 } 621 622 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 623 { 624 u32 base_addr = rtw8822c_get_path_write_addr(path); 625 626 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 627 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 628 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 629 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 630 } 631 632 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 633 u8 path, u8 vec, u32 w_addr, u32 r_addr) 634 { 635 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 636 u16 val; 637 u32 i; 638 639 if (WARN_ON(vec >= 2)) 640 return; 641 642 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 643 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 644 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 645 dm_info->dack_msbk[path][vec][i] = val; 646 } 647 } 648 649 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 650 { 651 u32 w_off = 0x1c; 652 u32 r_off = 0x2c; 653 u32 w_addr, r_addr; 654 655 if (WARN_ON(path >= 2)) 656 return; 657 658 /* backup I vector */ 659 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 660 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 661 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 662 663 /* backup Q vector */ 664 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 665 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 666 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 667 } 668 669 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 670 { 671 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 672 u8 val; 673 674 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 675 dm_info->dack_dck[RF_PATH_A][0][0] = val; 676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 677 dm_info->dack_dck[RF_PATH_A][0][1] = val; 678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 679 dm_info->dack_dck[RF_PATH_A][1][0] = val; 680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 681 dm_info->dack_dck[RF_PATH_A][1][1] = val; 682 683 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 684 dm_info->dack_dck[RF_PATH_B][0][0] = val; 685 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 686 dm_info->dack_dck[RF_PATH_B][1][0] = val; 687 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 688 dm_info->dack_dck[RF_PATH_B][0][1] = val; 689 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 690 dm_info->dack_dck[RF_PATH_B][1][1] = val; 691 } 692 693 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 694 { 695 u32 temp[3]; 696 697 temp[0] = rtw_read32(rtwdev, 0x1860); 698 temp[1] = rtw_read32(rtwdev, 0x4160); 699 temp[2] = rtw_read32(rtwdev, 0x9b4); 700 701 /* set clock */ 702 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 703 704 /* backup path-A I/Q */ 705 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 706 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 707 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 708 709 /* backup path-B I/Q */ 710 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 711 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 712 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 713 714 rtw8822c_dac_cal_backup_dck(rtwdev); 715 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 716 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 717 718 rtw_write32(rtwdev, 0x1860, temp[0]); 719 rtw_write32(rtwdev, 0x4160, temp[1]); 720 rtw_write32(rtwdev, 0x9b4, temp[2]); 721 } 722 723 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 724 { 725 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 726 u8 val; 727 728 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 729 val = dm_info->dack_dck[RF_PATH_A][0][0]; 730 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 731 val = dm_info->dack_dck[RF_PATH_A][0][1]; 732 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 733 734 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 735 val = dm_info->dack_dck[RF_PATH_A][1][0]; 736 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 737 val = dm_info->dack_dck[RF_PATH_A][1][1]; 738 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 739 740 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 741 val = dm_info->dack_dck[RF_PATH_B][0][0]; 742 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 743 val = dm_info->dack_dck[RF_PATH_B][0][1]; 744 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 745 746 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 747 val = dm_info->dack_dck[RF_PATH_B][1][0]; 748 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 749 val = dm_info->dack_dck[RF_PATH_B][1][1]; 750 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 751 } 752 753 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 754 { 755 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 756 757 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 758 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 759 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 760 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 761 762 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 763 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 764 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 765 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 766 767 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 768 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 769 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 770 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 771 772 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 773 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 774 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 775 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 776 777 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 778 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 779 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 780 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 781 782 rtw8822c_dac_cal_restore_dck(rtwdev); 783 784 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 785 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 786 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 787 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 788 789 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 790 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 791 792 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 793 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 794 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 795 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 796 797 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 798 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 799 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 800 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 801 802 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 803 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 804 } 805 806 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 807 u32 target_addr, u32 toggle_addr) 808 { 809 u32 cnt = 0; 810 811 do { 812 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 813 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 814 815 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 816 return true; 817 818 } while (cnt++ < 100); 819 820 return false; 821 } 822 823 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 824 { 825 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 826 u32 w_off = 0x1c; 827 u32 r_off = 0x2c; 828 u32 w_i, r_i, w_q, r_q; 829 u32 value; 830 u32 i; 831 832 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 833 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 834 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 835 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 836 837 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 838 return false; 839 840 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 842 value = dm_info->dack_msbk[path][0][i]; 843 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 844 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 845 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 846 } 847 848 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 849 850 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 851 return false; 852 853 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 854 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 855 value = dm_info->dack_msbk[path][1][i]; 856 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 857 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 858 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 859 } 860 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 861 862 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 863 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 864 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 865 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 866 867 return true; 868 } 869 870 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 871 { 872 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 873 return false; 874 875 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 876 return false; 877 878 return true; 879 } 880 881 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 882 { 883 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 884 u32 temp[3]; 885 886 /* sample the first element for both path's IQ vector */ 887 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 888 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 889 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 890 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 891 return false; 892 893 temp[0] = rtw_read32(rtwdev, 0x1860); 894 temp[1] = rtw_read32(rtwdev, 0x4160); 895 temp[2] = rtw_read32(rtwdev, 0x9b4); 896 897 rtw8822c_dac_cal_restore_prepare(rtwdev); 898 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 899 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 900 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 901 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 902 return false; 903 904 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 905 rtw_err(rtwdev, "failed to restore dack vectors\n"); 906 return false; 907 } 908 909 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 910 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 911 rtw_write32(rtwdev, 0x1860, temp[0]); 912 rtw_write32(rtwdev, 0x4160, temp[1]); 913 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 914 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 915 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 916 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 917 rtw_write32(rtwdev, 0x9b4, temp[2]); 918 919 return true; 920 } 921 922 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 923 { 924 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 925 struct rtw_backup_info backup[DACK_REG_8822C]; 926 u32 ic = 0, qc = 0, i; 927 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 928 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 929 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 930 931 if (rtw8822c_dac_cal_restore(rtwdev)) 932 return; 933 934 /* not able to restore, do it */ 935 936 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 937 938 rtw8822c_dac_bb_setting(rtwdev); 939 940 /* path-A */ 941 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 942 for (i = 0; i < 10; i++) { 943 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 944 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 945 ic_a = ic; 946 qc_a = qc; 947 948 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 949 &ic, &qc, &i_a, &q_a); 950 951 if (ic < 5 && qc < 5) 952 break; 953 } 954 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 955 956 /* path-B */ 957 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 958 for (i = 0; i < 10; i++) { 959 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 960 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 961 ic_b = ic; 962 qc_b = qc; 963 964 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 965 &ic, &qc, &i_b, &q_b); 966 967 if (ic < 5 && qc < 5) 968 break; 969 } 970 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 971 972 rtw_write32(rtwdev, 0x1b00, 0x00000008); 973 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 974 rtw_write8(rtwdev, 0x1bcc, 0x0); 975 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 976 rtw_write8(rtwdev, 0x1bcc, 0x0); 977 978 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 979 980 /* backup results to restore, saving a lot of time */ 981 rtw8822c_dac_cal_backup(rtwdev); 982 983 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 984 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 985 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 986 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 987 } 988 989 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 990 { 991 u8 x2k_busy; 992 993 mdelay(1); 994 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 995 if (x2k_busy == 1) { 996 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 997 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 998 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 999 mdelay(1); 1000 } 1001 } 1002 1003 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1004 { 1005 rtw8822c_rf_dac_cal(rtwdev); 1006 rtw8822c_rf_x2_check(rtwdev); 1007 } 1008 1009 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1010 { 1011 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1012 u8 path; 1013 1014 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1015 dm_info->delta_power_index[path] = 0; 1016 ewma_thermal_init(&dm_info->avg_thermal[path]); 1017 dm_info->thermal_avg[path] = 0xff; 1018 } 1019 1020 dm_info->pwr_trk_triggered = false; 1021 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1022 } 1023 1024 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1025 { 1026 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1027 struct rtw_hal *hal = &rtwdev->hal; 1028 u8 crystal_cap; 1029 u8 cck_gi_u_bnd_msb = 0; 1030 u8 cck_gi_u_bnd_lsb = 0; 1031 u8 cck_gi_l_bnd_msb = 0; 1032 u8 cck_gi_l_bnd_lsb = 0; 1033 bool is_tx2_path; 1034 1035 /* power on BB/RF domain */ 1036 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1037 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1038 rtw_write8_set(rtwdev, REG_RF_CTRL, 1039 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1040 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1041 1042 /* disable low rate DPD */ 1043 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1044 1045 /* pre init before header files config */ 1046 rtw8822c_header_file_init(rtwdev, true); 1047 1048 rtw_phy_load_tables(rtwdev); 1049 1050 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1051 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1052 crystal_cap | (crystal_cap << 7)); 1053 1054 /* post init after header files config */ 1055 rtw8822c_header_file_init(rtwdev, false); 1056 1057 is_tx2_path = false; 1058 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1059 is_tx2_path); 1060 rtw_phy_init(rtwdev); 1061 1062 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1063 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1064 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1065 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1066 1067 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1068 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1069 1070 rtw8822c_rf_init(rtwdev); 1071 rtw8822c_pwrtrack_init(rtwdev); 1072 1073 rtw_bf_phy_init(rtwdev); 1074 } 1075 1076 #define WLAN_TXQ_RPT_EN 0x1F 1077 #define WLAN_SLOT_TIME 0x09 1078 #define WLAN_PIFS_TIME 0x1C 1079 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1080 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1081 #define WLAN_SIFS_CCK_TRX 0x0A 1082 #define WLAN_SIFS_OFDM_TRX 0x10 1083 #define WLAN_NAV_MAX 0xC8 1084 #define WLAN_RDG_NAV 0x05 1085 #define WLAN_TXOP_NAV 0x1B 1086 #define WLAN_CCK_RX_TSF 0x30 1087 #define WLAN_OFDM_RX_TSF 0x30 1088 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1089 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1090 #define WLAN_DRV_EARLY_INT 0x04 1091 #define WLAN_BCN_CTRL_CLT0 0x10 1092 #define WLAN_BCN_DMA_TIME 0x02 1093 #define WLAN_BCN_MAX_ERR 0xFF 1094 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1095 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1096 #define WLAN_SIFS_CCK_CTX 0x0A 1097 #define WLAN_SIFS_CCK_IRX 0x0A 1098 #define WLAN_SIFS_OFDM_CTX 0x0E 1099 #define WLAN_SIFS_OFDM_IRX 0x0E 1100 #define WLAN_EIFS_DUR_TUNE 0x40 1101 #define WLAN_EDCA_VO_PARAM 0x002FA226 1102 #define WLAN_EDCA_VI_PARAM 0x005EA328 1103 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1104 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1105 1106 #define WLAN_RX_FILTER0 0xFFFFFFFF 1107 #define WLAN_RX_FILTER2 0xFFFF 1108 #define WLAN_RCR_CFG 0xE400220E 1109 #define WLAN_RXPKT_MAX_SZ 12288 1110 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1111 1112 #define WLAN_AMPDU_MAX_TIME 0x70 1113 #define WLAN_RTS_LEN_TH 0xFF 1114 #define WLAN_RTS_TX_TIME_TH 0x08 1115 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1116 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1117 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1118 #define FAST_EDCA_VO_TH 0x06 1119 #define FAST_EDCA_VI_TH 0x06 1120 #define FAST_EDCA_BE_TH 0x06 1121 #define FAST_EDCA_BK_TH 0x06 1122 #define WLAN_BAR_RETRY_LIMIT 0x01 1123 #define WLAN_BAR_ACK_TYPE 0x05 1124 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1125 #define WLAN_RESP_TXRATE 0x84 1126 #define WLAN_ACK_TO 0x21 1127 #define WLAN_ACK_TO_CCK 0x6A 1128 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1129 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1130 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1131 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1132 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1133 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1134 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1135 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1136 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1137 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1138 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1139 #define WLAN_MULTI_ADDR 0xFFFFFFFF 1140 1141 #define WLAN_TX_FUNC_CFG1 0x30 1142 #define WLAN_TX_FUNC_CFG2 0x30 1143 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1144 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1145 #define WLAN_MAC_OPT_FUNC2 0x30810041 1146 #define WLAN_MAC_INT_MIG_CFG 0x33330000 1147 1148 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1149 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1150 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1151 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1152 1153 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1154 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1155 1156 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1157 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1158 1159 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1160 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1161 1162 #define MAC_CLK_SPEED 80 /* 80M */ 1163 #define EFUSE_PCB_INFO_OFFSET 0xCA 1164 1165 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1166 { 1167 u8 value8; 1168 u16 value16; 1169 u32 value32; 1170 u16 pre_txcnt; 1171 1172 /* txq control */ 1173 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1174 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1175 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1176 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1177 /* sifs control */ 1178 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1179 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1180 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1181 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1182 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1183 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1184 /* rate fallback control */ 1185 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 1186 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 1187 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 1188 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 1189 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 1190 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 1191 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 1192 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 1193 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 1194 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 1195 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 1196 /* protocol configuration */ 1197 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 1198 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 1199 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 1200 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 1201 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 1202 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 1203 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 1204 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 1205 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 1206 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 1207 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 1208 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 1209 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 1210 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 1211 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 1212 /* close BA parser */ 1213 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 1214 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 1215 1216 /* EDCA configuration */ 1217 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 1218 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 1219 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 1220 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 1221 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 1222 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 1223 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 1224 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 1225 BIT_DIS_STBC_CFE) >> 8); 1226 1227 /* MAC clock configuration */ 1228 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 1229 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 1230 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 1231 1232 rtw_write8_set(rtwdev, REG_MISC_CTRL, 1233 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 1234 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 1235 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 1236 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 1237 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 1238 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 1239 /* Set beacon cotnrol - enable TSF and other related functions */ 1240 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1241 /* Set send beacon related registers */ 1242 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 1243 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 1244 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 1245 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 1246 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 1247 1248 /* WMAC configuration */ 1249 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 1250 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 1251 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 1252 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 1253 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 1254 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 1255 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 1256 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 1257 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 1258 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 1259 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 1260 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 1261 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 1262 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 1263 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 1264 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 1265 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 1266 1267 /* init low power */ 1268 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 1269 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 1270 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 1271 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 1272 value16 = 0; 1273 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 1274 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 1275 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 1276 | BIT_RXPSF_OFDMRST; 1277 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1278 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 1279 /* rx ignore configuration */ 1280 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 1281 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 1282 BIT_RXPSF_CONT_ERRCHKEN); 1283 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 1284 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1285 1286 /* Interrupt migration configuration */ 1287 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 1288 1289 return 0; 1290 } 1291 1292 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 1293 { 1294 if (enable) { 1295 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 1296 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 1297 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 1298 } else { 1299 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 1300 } 1301 } 1302 1303 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 1304 { 1305 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 1306 #define RF18_BAND_2G (0) 1307 #define RF18_BAND_5G (BIT(16) | BIT(8)) 1308 #define RF18_CHANNEL_MASK (MASKBYTE0) 1309 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 1310 #define RF18_RFSI_GE_CH80 (BIT(17)) 1311 #define RF18_RFSI_GT_CH140 (BIT(18)) 1312 #define RF18_BW_MASK (BIT(13) | BIT(12)) 1313 #define RF18_BW_20M (BIT(13) | BIT(12)) 1314 #define RF18_BW_40M (BIT(13)) 1315 #define RF18_BW_80M (BIT(12)) 1316 1317 u32 rf_reg18 = 0; 1318 u32 rf_rxbb = 0; 1319 1320 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 1321 1322 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 1323 RF18_BW_MASK); 1324 1325 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 1326 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 1327 if (IS_CH_5G_BAND_4(channel)) 1328 rf_reg18 |= RF18_RFSI_GT_CH140; 1329 else if (IS_CH_5G_BAND_3(channel)) 1330 rf_reg18 |= RF18_RFSI_GE_CH80; 1331 1332 switch (bw) { 1333 case RTW_CHANNEL_WIDTH_5: 1334 case RTW_CHANNEL_WIDTH_10: 1335 case RTW_CHANNEL_WIDTH_20: 1336 default: 1337 rf_reg18 |= RF18_BW_20M; 1338 rf_rxbb = 0x18; 1339 break; 1340 case RTW_CHANNEL_WIDTH_40: 1341 /* RF bandwidth */ 1342 rf_reg18 |= RF18_BW_40M; 1343 rf_rxbb = 0x10; 1344 break; 1345 case RTW_CHANNEL_WIDTH_80: 1346 rf_reg18 |= RF18_BW_80M; 1347 rf_rxbb = 0x8; 1348 break; 1349 } 1350 1351 rtw8822c_rstb_3wire(rtwdev, false); 1352 1353 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 1354 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 1355 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 1356 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 1357 1358 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 1359 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 1360 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 1361 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 1362 1363 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 1364 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 1365 1366 rtw8822c_rstb_3wire(rtwdev, true); 1367 } 1368 1369 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 1370 { 1371 u32 igi; 1372 1373 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 1374 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 1375 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 1376 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 1377 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 1378 } 1379 1380 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1381 u8 primary_ch_idx) 1382 { 1383 if (IS_CH_2G_BAND(channel)) { 1384 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1385 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1386 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 1387 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1388 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1389 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 1390 1391 switch (bw) { 1392 case RTW_CHANNEL_WIDTH_20: 1393 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1394 0x5); 1395 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1396 0x5); 1397 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1398 0x6); 1399 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1400 0x6); 1401 break; 1402 case RTW_CHANNEL_WIDTH_40: 1403 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1404 0x4); 1405 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1406 0x4); 1407 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1408 0x0); 1409 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1410 0x0); 1411 break; 1412 } 1413 if (channel == 13 || channel == 14) 1414 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 1415 else if (channel == 11 || channel == 12) 1416 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 1417 else 1418 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 1419 if (channel == 14) { 1420 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 1421 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1422 0x4962c931); 1423 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 1424 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 1425 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 1426 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 1427 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1428 0xff012455); 1429 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 1430 } else { 1431 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 1432 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1433 0x3e18fec8); 1434 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 1435 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 1436 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 1437 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 1438 0x00faf0de); 1439 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1440 0x00122344); 1441 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 1442 0x0fffffff); 1443 } 1444 if (channel == 13) 1445 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1446 else 1447 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 1448 } else if (IS_CH_5G_BAND(channel)) { 1449 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1450 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1451 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1452 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 1453 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x0); 1454 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 1455 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1456 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 1457 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1458 0x1); 1459 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1460 0x1); 1461 } else if (IS_CH_5G_BAND_3(channel)) { 1462 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1463 0x2); 1464 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1465 0x2); 1466 } else if (IS_CH_5G_BAND_4(channel)) { 1467 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1468 0x3); 1469 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1470 0x3); 1471 } 1472 1473 if (channel >= 36 && channel <= 51) 1474 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 1475 else if (channel >= 52 && channel <= 55) 1476 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 1477 else if (channel >= 56 && channel <= 111) 1478 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 1479 else if (channel >= 112 && channel <= 119) 1480 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 1481 else if (channel >= 120 && channel <= 172) 1482 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 1483 else if (channel >= 173 && channel <= 177) 1484 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 1485 } 1486 1487 switch (bw) { 1488 case RTW_CHANNEL_WIDTH_20: 1489 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 1490 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1491 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 1492 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 1493 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 1494 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1495 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1496 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1497 break; 1498 case RTW_CHANNEL_WIDTH_40: 1499 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 1500 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 1501 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 1502 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1503 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1504 (primary_ch_idx | (primary_ch_idx << 4))); 1505 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 1506 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1507 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1508 break; 1509 case RTW_CHANNEL_WIDTH_80: 1510 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 1511 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1512 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1513 (primary_ch_idx | (primary_ch_idx << 4))); 1514 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 1515 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1516 break; 1517 case RTW_CHANNEL_WIDTH_5: 1518 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1519 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1520 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 1521 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 1522 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 1523 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1524 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1525 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1526 break; 1527 case RTW_CHANNEL_WIDTH_10: 1528 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1529 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1530 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 1531 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 1532 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 1533 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1534 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1535 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1536 break; 1537 } 1538 } 1539 1540 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1541 u8 primary_chan_idx) 1542 { 1543 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 1544 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 1545 rtw8822c_set_channel_rf(rtwdev, channel, bw); 1546 rtw8822c_toggle_igi(rtwdev); 1547 } 1548 1549 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1550 { 1551 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1552 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 1553 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 1554 } else if (rx_path == BB_PATH_AB) { 1555 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 1556 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 1557 } 1558 1559 if (rx_path == BB_PATH_A) 1560 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 1561 else if (rx_path == BB_PATH_B) 1562 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 1563 else if (rx_path == BB_PATH_AB) 1564 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 1565 } 1566 1567 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1568 { 1569 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1570 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 1571 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 1572 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 1573 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 1574 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 1575 } else if (rx_path == BB_PATH_AB) { 1576 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 1577 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 1578 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 1579 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 1580 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 1581 } 1582 1583 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 1584 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 1585 } 1586 1587 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1588 { 1589 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 1590 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 1591 } 1592 1593 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1594 bool is_tx2_path) 1595 { 1596 if (tx_path == BB_PATH_A) { 1597 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1598 } else if (tx_path == BB_PATH_B) { 1599 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 1600 } else { 1601 if (is_tx2_path) 1602 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 1603 else 1604 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1605 } 1606 } 1607 1608 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1609 bool is_tx2_path) 1610 { 1611 if (tx_path == BB_PATH_A) { 1612 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 1613 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1614 } else if (tx_path == BB_PATH_B) { 1615 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 1616 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1617 } else { 1618 if (is_tx2_path) { 1619 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 1620 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 1621 } else { 1622 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 1623 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 1624 } 1625 } 1626 } 1627 1628 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1629 bool is_tx2_path) 1630 { 1631 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 1632 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 1633 } 1634 1635 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 1636 u8 rx_path, bool is_tx2_path) 1637 { 1638 if ((tx_path | rx_path) & BB_PATH_A) 1639 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 1640 else 1641 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 1642 if ((tx_path | rx_path) & BB_PATH_B) 1643 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 1644 else 1645 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 1646 1647 rtw8822c_config_rx_path(rtwdev, rx_path); 1648 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 1649 1650 rtw8822c_toggle_igi(rtwdev); 1651 } 1652 1653 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 1654 struct rtw_rx_pkt_stat *pkt_stat) 1655 { 1656 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1657 u8 l_bnd, u_bnd; 1658 u8 gain_a, gain_b; 1659 s8 rx_power[RTW_RF_PATH_MAX]; 1660 s8 min_rx_power = -120; 1661 u8 rssi; 1662 int path; 1663 1664 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 1665 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 1666 l_bnd = dm_info->cck_gi_l_bnd; 1667 u_bnd = dm_info->cck_gi_u_bnd; 1668 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 1669 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 1670 if (gain_a < l_bnd) 1671 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 1672 else if (gain_a > u_bnd) 1673 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 1674 if (gain_b < l_bnd) 1675 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 1676 else if (gain_b > u_bnd) 1677 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 1678 1679 rx_power[RF_PATH_A] -= 110; 1680 rx_power[RF_PATH_B] -= 110; 1681 1682 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 1683 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 1684 1685 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1686 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1687 dm_info->rssi[path] = rssi; 1688 } 1689 1690 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1691 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1692 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 1693 min_rx_power); 1694 } 1695 1696 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 1697 struct rtw_rx_pkt_stat *pkt_stat) 1698 { 1699 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1700 u8 rxsc, bw; 1701 s8 min_rx_power = -120; 1702 s8 rx_evm; 1703 u8 evm_dbm = 0; 1704 u8 rssi; 1705 int path; 1706 1707 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 1708 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 1709 else 1710 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 1711 1712 if (rxsc >= 9 && rxsc <= 12) 1713 bw = RTW_CHANNEL_WIDTH_40; 1714 else if (rxsc >= 13) 1715 bw = RTW_CHANNEL_WIDTH_80; 1716 else 1717 bw = RTW_CHANNEL_WIDTH_20; 1718 1719 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 1720 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 1721 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 1722 pkt_stat->bw = bw; 1723 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 1724 pkt_stat->rx_power[RF_PATH_B], 1725 min_rx_power); 1726 1727 dm_info->curr_rx_rate = pkt_stat->rate; 1728 1729 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 1730 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 1731 1732 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 1733 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 1734 1735 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 1736 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 1737 1738 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1739 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1740 dm_info->rssi[path] = rssi; 1741 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 1742 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 1743 1744 rx_evm = pkt_stat->rx_evm[path]; 1745 1746 if (rx_evm < 0) { 1747 if (rx_evm == S8_MIN) 1748 evm_dbm = 0; 1749 else 1750 evm_dbm = ((u8)-rx_evm >> 1); 1751 } 1752 dm_info->rx_evm_dbm[path] = evm_dbm; 1753 } 1754 } 1755 1756 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1757 struct rtw_rx_pkt_stat *pkt_stat) 1758 { 1759 u8 page; 1760 1761 page = *phy_status & 0xf; 1762 1763 switch (page) { 1764 case 0: 1765 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 1766 break; 1767 case 1: 1768 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 1769 break; 1770 default: 1771 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 1772 return; 1773 } 1774 } 1775 1776 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1777 struct rtw_rx_pkt_stat *pkt_stat, 1778 struct ieee80211_rx_status *rx_status) 1779 { 1780 struct ieee80211_hdr *hdr; 1781 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1782 u8 *phy_status = NULL; 1783 1784 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1785 1786 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1787 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1788 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1789 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 1790 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 1791 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1792 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1793 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1794 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1795 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1796 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1797 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 1798 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1799 1800 /* drv_info_sz is in unit of 8-bytes */ 1801 pkt_stat->drv_info_sz *= 8; 1802 1803 /* c2h cmd pkt's rx/phy status is not interested */ 1804 if (pkt_stat->is_c2h) 1805 return; 1806 1807 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1808 pkt_stat->drv_info_sz); 1809 if (pkt_stat->phy_status) { 1810 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1811 query_phy_status(rtwdev, phy_status, pkt_stat); 1812 } 1813 1814 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1815 } 1816 1817 static void 1818 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 1819 u8 *tx_pwr_ref_ofdm) 1820 { 1821 struct rtw_hal *hal = &rtwdev->hal; 1822 u32 txref_cck[2] = {0x18a0, 0x41a0}; 1823 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 1824 u8 path; 1825 1826 for (path = 0; path < hal->rf_path_num; path++) { 1827 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1828 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 1829 tx_pwr_ref_cck[path]); 1830 } 1831 for (path = 0; path < hal->rf_path_num; path++) { 1832 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1833 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 1834 tx_pwr_ref_ofdm[path]); 1835 } 1836 } 1837 1838 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 1839 s8 *diff_idx) 1840 { 1841 u32 offset_txagc = 0x3a00; 1842 u8 rate_idx = rate & 0xfc; 1843 u8 pwr_idx[4]; 1844 u32 phy_pwr_idx; 1845 int i; 1846 1847 for (i = 0; i < 4; i++) 1848 pwr_idx[i] = diff_idx[i] & 0x7f; 1849 1850 phy_pwr_idx = pwr_idx[0] | 1851 (pwr_idx[1] << 8) | 1852 (pwr_idx[2] << 16) | 1853 (pwr_idx[3] << 24); 1854 1855 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 1856 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 1857 phy_pwr_idx); 1858 } 1859 1860 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 1861 { 1862 struct rtw_hal *hal = &rtwdev->hal; 1863 u8 rs, rate, j; 1864 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 1865 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 1866 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 1867 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 1868 s8 diff_a, diff_b; 1869 u8 pwr_a, pwr_b; 1870 s8 diff_idx[4]; 1871 1872 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 1873 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 1874 for (j = 0; j < rtw_rate_size[rs]; j++) { 1875 rate = rtw_rate_section[rs][j]; 1876 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 1877 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 1878 if (rs == 0) { 1879 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 1880 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 1881 } else { 1882 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 1883 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 1884 } 1885 diff_idx[rate % 4] = min(diff_a, diff_b); 1886 if (rate % 4 == 3) 1887 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 1888 diff_idx); 1889 } 1890 } 1891 } 1892 1893 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1894 { 1895 u8 ldo_pwr; 1896 1897 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 1898 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 1899 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 1900 } 1901 1902 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 1903 { 1904 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1905 u32 cck_enable; 1906 u32 cck_fa_cnt; 1907 u32 crc32_cnt; 1908 u32 cca32_cnt; 1909 u32 ofdm_fa_cnt; 1910 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 1911 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 1912 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 1913 1914 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 1915 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 1916 1917 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 1918 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 1919 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 1920 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 1921 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 1922 1923 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 1924 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 1925 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 1926 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 1927 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 1928 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 1929 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 1930 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 1931 1932 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 1933 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 1934 1935 dm_info->cck_fa_cnt = cck_fa_cnt; 1936 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1937 dm_info->total_fa_cnt = ofdm_fa_cnt; 1938 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 1939 1940 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 1941 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 1942 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1943 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 1944 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 1945 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1946 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 1947 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 1948 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1949 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 1950 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 1951 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1952 1953 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 1954 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 1955 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 1956 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 1957 if (cck_enable) 1958 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 1959 1960 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 1961 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 1962 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 1963 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 1964 1965 /* disable rx clk gating to reset counters */ 1966 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 1967 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 1968 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 1969 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 1970 } 1971 1972 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 1973 { 1974 struct rtw_iqk_para para = {0}; 1975 u8 iqk_chk; 1976 int counter; 1977 1978 para.clear = 1; 1979 rtw_fw_do_iqk(rtwdev, ¶); 1980 1981 for (counter = 0; counter < 300; counter++) { 1982 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP); 1983 if (iqk_chk == 0xaa) 1984 break; 1985 msleep(20); 1986 } 1987 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 1988 1989 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter); 1990 } 1991 1992 /* for coex */ 1993 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 1994 { 1995 /* enable TBTT nterrupt */ 1996 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1997 1998 /* BT report packet sample rate */ 1999 /* 0x790[5:0]=0x5 */ 2000 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 2001 2002 /* enable BT counter statistics */ 2003 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2004 2005 /* enable PTA (3-wire function form BT side) */ 2006 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2007 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 2008 2009 /* enable PTA (tx/rx signal form WiFi side) */ 2010 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2011 /* wl tx signal to PTA not case EDCCA */ 2012 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2013 /* GNT_BT=1 while select both */ 2014 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2015 /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */ 2016 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2017 2018 /* to avoid RF parameter error */ 2019 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000); 2020 } 2021 2022 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2023 { 2024 struct rtw_coex *coex = &rtwdev->coex; 2025 struct rtw_coex_stat *coex_stat = &coex->stat; 2026 struct rtw_efuse *efuse = &rtwdev->efuse; 2027 u32 rf_0x1; 2028 2029 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2030 return; 2031 2032 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 2033 2034 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 2035 rf_0x1 = 0x40021; 2036 else 2037 rf_0x1 = 0x40000; 2038 2039 /* BT at S1 for Shared-Ant */ 2040 if (efuse->share_ant) 2041 rf_0x1 |= BIT(13); 2042 2043 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 2044 2045 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 2046 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 2047 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 2048 * 2049 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 2050 * disable 0x1c30[22] = 0, 2051 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 2052 * 2053 * disable WL-S1 BB chage RF mode if GNT_BT 2054 * since RF TRx mask can do it 2055 */ 2056 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1); 2057 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0); 2058 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1); 2059 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1); 2060 2061 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 2062 * or antenna path is separated 2063 */ 2064 if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 2065 coex->under_5g || !efuse->share_ant) { 2066 if (coex_stat->kt_ver >= 3) { 2067 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2068 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1); 2069 } else { 2070 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1); 2071 } 2072 } else { 2073 /* shared-antenna */ 2074 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2075 if (coex_stat->kt_ver >= 3) 2076 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0); 2077 } 2078 } 2079 2080 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 2081 { 2082 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0); 2083 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0); 2084 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0); 2085 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0); 2086 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0); 2087 } 2088 2089 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 2090 { 2091 struct rtw_coex *coex = &rtwdev->coex; 2092 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 2093 struct rtw_efuse *efuse = &rtwdev->efuse; 2094 2095 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 2096 coex_rfe->ant_switch_polarity = 0; 2097 coex_rfe->ant_switch_exist = false; 2098 coex_rfe->ant_switch_with_bt = false; 2099 coex_rfe->ant_switch_diversity = false; 2100 2101 if (efuse->share_ant) 2102 coex_rfe->wlg_at_btg = true; 2103 else 2104 coex_rfe->wlg_at_btg = false; 2105 2106 /* disable LTE coex in wifi side */ 2107 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0); 2108 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff); 2109 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff); 2110 } 2111 2112 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 2113 { 2114 struct rtw_coex *coex = &rtwdev->coex; 2115 struct rtw_coex_dm *coex_dm = &coex->dm; 2116 2117 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 2118 return; 2119 2120 coex_dm->cur_wl_pwr_lvl = wl_pwr; 2121 } 2122 2123 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 2124 { 2125 struct rtw_coex *coex = &rtwdev->coex; 2126 struct rtw_coex_dm *coex_dm = &coex->dm; 2127 2128 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 2129 return; 2130 2131 coex_dm->cur_wl_rx_low_gain_en = low_gain; 2132 2133 if (coex_dm->cur_wl_rx_low_gain_en) { 2134 /* set Rx filter corner RCK offset */ 2135 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22); 2136 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36); 2137 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22); 2138 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36); 2139 } else { 2140 /* set Rx filter corner RCK offset */ 2141 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20); 2142 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0); 2143 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0); 2144 } 2145 } 2146 2147 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 2148 struct rtw_vif *vif, 2149 struct rtw_bfee *bfee) 2150 { 2151 u8 csi_rsc = 0; 2152 u32 tmp6dc; 2153 2154 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 2155 2156 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 2157 BIT_WMAC_USE_NDPARATE | 2158 (csi_rsc << 13); 2159 if (vif->net_type == RTW_NET_AP_MODE) 2160 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 2161 else 2162 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 2163 2164 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 2165 } 2166 2167 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 2168 struct rtw_vif *vif, 2169 struct rtw_bfee *bfee, bool enable) 2170 { 2171 if (enable) 2172 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 2173 else 2174 rtw_bf_remove_bfee_su(rtwdev, bfee); 2175 } 2176 2177 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 2178 struct rtw_vif *vif, 2179 struct rtw_bfee *bfee, bool enable) 2180 { 2181 if (enable) 2182 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 2183 else 2184 rtw_bf_remove_bfee_mu(rtwdev, bfee); 2185 } 2186 2187 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 2188 struct rtw_bfee *bfee, bool enable) 2189 { 2190 if (bfee->role == RTW_BFEE_SU) 2191 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 2192 else if (bfee->role == RTW_BFEE_MU) 2193 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 2194 else 2195 rtw_warn(rtwdev, "wrong bfee role\n"); 2196 } 2197 2198 struct dpk_cfg_pair { 2199 u32 addr; 2200 u32 bitmask; 2201 u32 data; 2202 }; 2203 2204 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 2205 const struct rtw_table *tbl) 2206 { 2207 const struct dpk_cfg_pair *p = tbl->data; 2208 const struct dpk_cfg_pair *end = p + tbl->size / 3; 2209 2210 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 2211 2212 for (; p < end; p++) 2213 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 2214 } 2215 2216 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 2217 { 2218 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2219 2220 if (is_before_k) { 2221 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 2222 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 2223 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 2224 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 2225 } else { 2226 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 2227 dpk_info->gnt_value); 2228 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 2229 } 2230 } 2231 2232 static void 2233 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 2234 struct rtw_backup_info *bckp) 2235 { 2236 rtw_restore_reg(rtwdev, bckp, reg_num); 2237 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2238 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 2239 } 2240 2241 static void 2242 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 2243 u32 reg_num, struct rtw_backup_info *bckp) 2244 { 2245 u32 i; 2246 2247 for (i = 0; i < reg_num; i++) { 2248 bckp[i].len = 4; 2249 bckp[i].reg = reg[i]; 2250 bckp[i].val = rtw_read32(rtwdev, reg[i]); 2251 } 2252 } 2253 2254 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 2255 u32 *rf_reg, 2256 u32 rf_reg_bak[][2]) 2257 { 2258 u32 i; 2259 2260 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2261 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 2262 rf_reg[i], RFREG_MASK); 2263 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 2264 rf_reg[i], RFREG_MASK); 2265 } 2266 } 2267 2268 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 2269 u32 *rf_reg, 2270 u32 rf_reg_bak[][2]) 2271 { 2272 u32 i; 2273 2274 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2275 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 2276 rf_reg_bak[i][RF_PATH_A]); 2277 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 2278 rf_reg_bak[i][RF_PATH_B]); 2279 } 2280 } 2281 2282 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 2283 { 2284 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2285 u32 reg; 2286 u8 band_shift; 2287 2288 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2289 2290 band_shift = FIELD_GET(BIT(16), reg); 2291 dpk_info->dpk_band = 1 << band_shift; 2292 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 2293 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 2294 } 2295 2296 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 2297 { 2298 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2299 udelay(5); 2300 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 2301 usleep_range(600, 610); 2302 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2303 } 2304 2305 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 2306 { 2307 u16 dc_i, dc_q; 2308 u8 corr_val, corr_idx; 2309 2310 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 2311 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2312 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 2313 2314 if (dc_i & BIT(11)) 2315 dc_i = 0x1000 - dc_i; 2316 if (dc_q & BIT(11)) 2317 dc_q = 0x1000 - dc_q; 2318 2319 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2320 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 2321 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 2322 2323 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 2324 return 1; 2325 else 2326 return 0; 2327 2328 } 2329 2330 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 2331 { 2332 u8 reg_a, reg_b; 2333 u16 count = 0; 2334 2335 rtw_write8(rtwdev, 0x522, 0xff); 2336 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 2337 2338 do { 2339 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 2340 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 2341 udelay(2); 2342 count++; 2343 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 2344 } 2345 2346 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 2347 { 2348 rtw8822c_dpk_tx_pause(rtwdev); 2349 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 2350 } 2351 2352 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 2353 { 2354 if (is_do_dpk) 2355 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 2356 else 2357 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 2358 } 2359 2360 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 2361 { 2362 u8 path; 2363 2364 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 2365 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 2366 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2367 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 2368 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 2369 else 2370 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 2371 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 2372 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 2373 } 2374 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2375 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 2376 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 2377 } 2378 2379 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 2380 { 2381 u32 ori_txbb; 2382 2383 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 2384 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 2385 2386 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 2387 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 2388 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0); 2389 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 2390 2391 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 2392 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1); 2393 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 2394 } else { 2395 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 2396 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 2397 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 2398 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 2399 } 2400 2401 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2402 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 2403 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 2404 2405 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 2406 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 2407 else 2408 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 2409 2410 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 2411 2412 usleep_range(100, 110); 2413 2414 return ori_txbb & 0x1f; 2415 } 2416 2417 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 2418 { 2419 u16 cmd; 2420 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 2421 2422 switch (action) { 2423 case RTW_DPK_GAIN_LOSS: 2424 cmd = 0x14 + path; 2425 break; 2426 case RTW_DPK_DO_DPK: 2427 cmd = 0x16 + path + bw; 2428 break; 2429 case RTW_DPK_DPK_ON: 2430 cmd = 0x1a + path; 2431 break; 2432 case RTW_DPK_DAGC: 2433 cmd = 0x1c + path + bw; 2434 break; 2435 default: 2436 return 0; 2437 } 2438 2439 return (cmd << 8) | 0x48; 2440 } 2441 2442 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 2443 { 2444 u16 dpk_cmd; 2445 u8 result = 0; 2446 2447 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 2448 2449 if (action == RTW_DPK_CAL_PWR) { 2450 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 2451 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 2452 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 2453 msleep(10); 2454 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 2455 result = 1; 2456 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2457 } 2458 } else { 2459 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2460 0x8 | (path << 1)); 2461 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 2462 2463 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 2464 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 2465 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 2466 msleep(10); 2467 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 2468 result = 1; 2469 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2470 } 2471 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2472 0x8 | (path << 1)); 2473 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 2474 } 2475 2476 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 2477 2478 rtw_write8(rtwdev, 0x1b10, 0x0); 2479 2480 return result; 2481 } 2482 2483 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 2484 { 2485 u16 dgain; 2486 2487 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2488 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 2489 2490 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2491 2492 return dgain; 2493 } 2494 2495 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 2496 { 2497 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2498 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 2499 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2500 udelay(15); 2501 2502 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 2503 } 2504 2505 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 2506 { 2507 u32 i_val, q_val; 2508 2509 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2510 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2511 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 2512 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2513 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 2514 2515 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 2516 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 2517 2518 if (i_val & BIT(15)) 2519 i_val = 0x10000 - i_val; 2520 if (q_val & BIT(15)) 2521 q_val = 0x10000 - q_val; 2522 2523 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2524 2525 return i_val * i_val + q_val * q_val; 2526 } 2527 2528 static u32 rtw8822c_psd_log2base(u32 val) 2529 { 2530 u32 tmp, val_integerd_b, tindex; 2531 u32 result, val_fractiond_b; 2532 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 2533 151, 132, 115, 100, 86, 74, 62, 51, 2534 42, 32, 23, 15, 7, 0}; 2535 2536 if (val == 0) 2537 return 0; 2538 2539 val_integerd_b = __fls(val) + 1; 2540 2541 tmp = (val * 100) / (1 << val_integerd_b); 2542 tindex = tmp / 5; 2543 2544 if (tindex >= ARRAY_SIZE(table_fraction)) 2545 tindex = ARRAY_SIZE(table_fraction) - 1; 2546 2547 val_fractiond_b = table_fraction[tindex]; 2548 2549 result = val_integerd_b * 100 - val_fractiond_b; 2550 2551 return result; 2552 } 2553 2554 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 2555 { 2556 u8 result; 2557 2558 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2559 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 2560 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 2561 2562 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 2563 2564 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2565 2566 return result; 2567 } 2568 2569 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 2570 u8 limited_pga) 2571 { 2572 u8 result = 0; 2573 u16 dgain; 2574 2575 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 2576 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 2577 2578 if (dgain > 1535 && !limited_pga) 2579 return RTW_DPK_GAIN_LESS; 2580 else if (dgain < 768 && !limited_pga) 2581 return RTW_DPK_GAIN_LARGE; 2582 else 2583 return result; 2584 } 2585 2586 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 2587 { 2588 u32 loss, loss_db; 2589 2590 loss = rtw8822c_dpk_pas_read(rtwdev, path); 2591 if (loss < 0x4000000) 2592 return RTW_DPK_GL_LESS; 2593 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 2594 2595 if (loss_db > 1000) 2596 return RTW_DPK_GL_LARGE; 2597 else if (loss_db < 250) 2598 return RTW_DPK_GL_LESS; 2599 else 2600 return RTW_DPK_AGC_OUT; 2601 } 2602 2603 struct rtw8822c_dpk_data { 2604 u8 txbb; 2605 u8 pga; 2606 u8 limited_pga; 2607 u8 agc_cnt; 2608 bool loss_only; 2609 bool gain_only; 2610 u8 path; 2611 }; 2612 2613 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 2614 struct rtw8822c_dpk_data *data) 2615 { 2616 u8 state; 2617 2618 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 2619 BIT_GAIN_TXBB); 2620 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 2621 BIT_RXAGC); 2622 2623 if (data->loss_only) { 2624 state = RTW_DPK_LOSS_CHECK; 2625 goto check_end; 2626 } 2627 2628 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 2629 data->limited_pga); 2630 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 2631 state = RTW_DPK_AGC_OUT; 2632 else if (state == RTW_DPK_GAIN_CHECK) 2633 state = RTW_DPK_LOSS_CHECK; 2634 2635 check_end: 2636 data->agc_cnt++; 2637 if (data->agc_cnt >= 6) 2638 state = RTW_DPK_AGC_OUT; 2639 2640 return state; 2641 } 2642 2643 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 2644 struct rtw8822c_dpk_data *data) 2645 { 2646 u8 pga = data->pga; 2647 2648 if (pga > 0xe) 2649 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2650 else if (pga > 0xb && pga < 0xf) 2651 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 2652 else if (pga < 0xc) 2653 data->limited_pga = 1; 2654 2655 return RTW_DPK_GAIN_CHECK; 2656 } 2657 2658 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 2659 struct rtw8822c_dpk_data *data) 2660 { 2661 u8 pga = data->pga; 2662 2663 if (pga < 0xc) 2664 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2665 else if (pga > 0xb && pga < 0xf) 2666 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2667 else if (pga > 0xe) 2668 data->limited_pga = 1; 2669 2670 return RTW_DPK_GAIN_CHECK; 2671 } 2672 2673 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 2674 struct rtw8822c_dpk_data *data, u8 is_large) 2675 { 2676 u8 txbb_bound[] = {0x1f, 0}; 2677 2678 if (data->txbb == txbb_bound[is_large]) 2679 return RTW_DPK_AGC_OUT; 2680 2681 if (is_large == 1) 2682 data->txbb -= 2; 2683 else 2684 data->txbb += 3; 2685 2686 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 2687 data->limited_pga = 0; 2688 2689 return RTW_DPK_GAIN_CHECK; 2690 } 2691 2692 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 2693 struct rtw8822c_dpk_data *data) 2694 { 2695 return rtw8822c_gl_state(rtwdev, data, 1); 2696 } 2697 2698 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 2699 struct rtw8822c_dpk_data *data) 2700 { 2701 return rtw8822c_gl_state(rtwdev, data, 0); 2702 } 2703 2704 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 2705 struct rtw8822c_dpk_data *data) 2706 { 2707 u8 path = data->path; 2708 u8 state; 2709 2710 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 2711 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 2712 2713 return state; 2714 } 2715 2716 static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 2717 struct rtw8822c_dpk_data *data) = { 2718 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 2719 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 2720 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 2721 2722 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 2723 bool gain_only, bool loss_only) 2724 { 2725 struct rtw8822c_dpk_data data = {0}; 2726 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 2727 u8 state = RTW_DPK_GAIN_CHECK; 2728 2729 data.loss_only = loss_only; 2730 data.gain_only = gain_only; 2731 data.path = path; 2732 2733 for (;;) { 2734 func = dpk_state[state]; 2735 state = func(rtwdev, &data); 2736 if (state == RTW_DPK_AGC_OUT) 2737 break; 2738 } 2739 2740 return data.txbb; 2741 } 2742 2743 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 2744 u16 coef_i, u16 coef_q) 2745 { 2746 if (coef_i == 0x1000 || coef_i == 0x0fff || 2747 coef_q == 0x1000 || coef_q == 0x0fff) 2748 return true; 2749 2750 return false; 2751 } 2752 2753 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 2754 { 2755 u32 reg = 0; 2756 u16 coef_i = 0, coef_q = 0; 2757 2758 reg = rtw_read32(rtwdev, REG_STAT_RPT); 2759 2760 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 2761 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 2762 2763 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 2764 2765 reg = (coef_i << 16) | coef_q; 2766 2767 return reg; 2768 } 2769 2770 static const u32 rtw8822c_dpk_get_coef_tbl[] = { 2771 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 2772 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 2773 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 2774 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 2775 }; 2776 2777 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 2778 { 2779 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2780 int i; 2781 2782 for (i = 0; i < 20; i++) { 2783 rtw_write32(rtwdev, REG_RXSRAM_CTL, 2784 rtw8822c_dpk_get_coef_tbl[i]); 2785 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 2786 } 2787 } 2788 2789 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 2790 { 2791 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2792 2793 if (path == RF_PATH_A) { 2794 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 2795 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 2796 } else if (path == RF_PATH_B) { 2797 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 2798 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 2799 } 2800 2801 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 2802 } 2803 2804 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 2805 { 2806 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2807 u8 addr, result = 1; 2808 u16 coef_i, coef_q; 2809 2810 for (addr = 0; addr < 20; addr++) { 2811 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 2812 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 2813 2814 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 2815 result = 0; 2816 break; 2817 } 2818 } 2819 return result; 2820 } 2821 2822 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 2823 { 2824 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2825 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 2826 u32 coef; 2827 u8 addr; 2828 2829 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2830 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2831 2832 for (addr = 0; addr < 20; addr++) { 2833 if (result == 0) { 2834 if (addr == 3) 2835 coef = 0x04001fff; 2836 else 2837 coef = 0x00001fff; 2838 } else { 2839 coef = dpk_info->coef[path][addr]; 2840 } 2841 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 2842 } 2843 } 2844 2845 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 2846 u8 path, u8 result) 2847 { 2848 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2849 2850 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2851 2852 if (result) 2853 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 2854 else 2855 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 2856 2857 dpk_info->result[path] = result; 2858 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 2859 2860 rtw8822c_dpk_coef_write(rtwdev, path, result); 2861 } 2862 2863 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 2864 { 2865 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2866 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 2867 2868 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 2869 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 2870 2871 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 2872 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 2873 rtw8822c_dpk_dgain_read(rtwdev, path); 2874 2875 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 2876 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 2877 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 2878 rtw8822c_dpk_dc_corr_check(rtwdev, path); 2879 } 2880 2881 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 2882 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 2883 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 2884 2885 if (tx_bb < tx_agc_search) 2886 tx_bb = 0; 2887 else 2888 tx_bb = tx_bb - tx_agc_search; 2889 2890 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 2891 2892 tx_agc = ori_txagc - (ori_txbb - tx_bb); 2893 2894 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 2895 2896 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 2897 2898 return tx_agc; 2899 } 2900 2901 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 2902 { 2903 u8 result; 2904 2905 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 2906 2907 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2908 2909 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 2910 2911 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 2912 2913 rtw8822c_dpk_get_coef(rtwdev, path); 2914 2915 return result; 2916 } 2917 2918 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 2919 { 2920 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2921 u32 tmp_gs = 0; 2922 2923 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2924 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 2925 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 2926 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 2927 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 2928 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2929 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 2930 2931 if (path == RF_PATH_A) { 2932 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 2933 0x1066680); 2934 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 2935 } else { 2936 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 2937 0x1066680); 2938 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 2939 } 2940 2941 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 2942 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 2943 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 2944 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 2945 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 2946 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 2947 rtw_write32(rtwdev, REG_DPD_CTL15, 2948 0x05020000 | (BIT(path) << 28)); 2949 } else { 2950 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 2951 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 2952 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 2953 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 2954 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 2955 rtw_write32(rtwdev, REG_DPD_CTL15, 2956 0x05020008 | (BIT(path) << 28)); 2957 } 2958 2959 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 2960 2961 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 2962 2963 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 2964 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2965 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 2966 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 2967 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2968 2969 if (path == RF_PATH_A) 2970 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 2971 else 2972 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 2973 2974 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 2975 2976 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 2977 tmp_gs = (tmp_gs * 910) >> 10; 2978 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 2979 2980 if (path == RF_PATH_A) 2981 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 2982 else 2983 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 2984 2985 dpk_info->dpk_gs[path] = tmp_gs; 2986 } 2987 2988 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 2989 { 2990 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2991 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 2992 u32 i_scaling; 2993 u8 path; 2994 2995 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 2996 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2997 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 2998 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 2999 3000 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 3001 3002 rtw_write8(rtwdev, 0x1b10, 0x0); 3003 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3004 3005 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3006 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 3007 3008 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 3009 i_scaling); 3010 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3011 GENMASK(31, 28), 0x9); 3012 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3013 GENMASK(31, 28), 0x1); 3014 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3015 GENMASK(31, 28), 0x0); 3016 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 3017 BIT(14), 0x0); 3018 } 3019 } 3020 3021 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 3022 { 3023 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3024 3025 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3026 3027 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3028 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3029 3030 if (test_bit(path, dpk_info->dpk_path_ok)) 3031 rtw8822c_dpk_cal_gs(rtwdev, path); 3032 } 3033 3034 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 3035 u32 dpk_txagc, u8 path) 3036 { 3037 bool result; 3038 3039 if (!is_fail) { 3040 if (rtw8822c_dpk_coef_read(rtwdev, path)) 3041 result = true; 3042 else 3043 result = false; 3044 } else { 3045 result = false; 3046 } 3047 3048 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 3049 3050 return result; 3051 } 3052 3053 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 3054 { 3055 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3056 u8 path; 3057 3058 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3059 clear_bit(path, dpk_info->dpk_path_ok); 3060 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3061 0x8 | (path << 1)); 3062 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 3063 3064 dpk_info->dpk_txagc[path] = 0; 3065 dpk_info->result[path] = 0; 3066 dpk_info->dpk_gs[path] = 0x5b; 3067 dpk_info->pre_pwsf[path] = 0; 3068 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 3069 path); 3070 } 3071 } 3072 3073 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 3074 { 3075 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3076 u32 dpk_txagc; 3077 u8 dpk_fail; 3078 3079 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 3080 3081 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 3082 3083 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 3084 3085 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 3086 rtw_err(rtwdev, "failed to do dpk calibration\n"); 3087 3088 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 3089 3090 if (dpk_info->result[path]) 3091 set_bit(path, dpk_info->dpk_path_ok); 3092 } 3093 3094 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 3095 { 3096 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 3097 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 3098 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 3099 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 3100 rtw8822c_dpk_cal_coef1(rtwdev); 3101 } 3102 3103 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 3104 { 3105 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3106 u32 mask = BIT(15) | BIT(14); 3107 3108 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3109 3110 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 3111 dpk_info->is_dpk_pwr_on); 3112 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 3113 dpk_info->is_dpk_pwr_on); 3114 3115 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 3116 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 3117 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 3118 } 3119 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 3120 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 3121 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 3122 } 3123 } 3124 3125 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 3126 { 3127 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3128 u8 path; 3129 3130 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 3131 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 3132 dpk_info->dpk_ch == 0) 3133 return; 3134 3135 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3136 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3137 0x8 | (path << 1)); 3138 if (dpk_info->dpk_band == RTW_BAND_2G) 3139 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 3140 else 3141 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 3142 3143 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 3144 3145 rtw8822c_dpk_coef_write(rtwdev, path, 3146 test_bit(path, dpk_info->dpk_path_ok)); 3147 3148 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3149 3150 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3151 3152 if (path == RF_PATH_A) 3153 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3154 dpk_info->dpk_gs[path]); 3155 else 3156 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3157 dpk_info->dpk_gs[path]); 3158 } 3159 rtw8822c_dpk_cal_coef1(rtwdev); 3160 } 3161 3162 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 3163 { 3164 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3165 u8 channel; 3166 3167 dpk_info->is_reload = false; 3168 3169 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 3170 3171 if (channel == dpk_info->dpk_ch) { 3172 rtw_dbg(rtwdev, RTW_DBG_RFK, 3173 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 3174 rtw8822c_dpk_reload_data(rtwdev); 3175 dpk_info->is_reload = true; 3176 } 3177 3178 return dpk_info->is_reload; 3179 } 3180 3181 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 3182 { 3183 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3184 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 3185 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 3186 u32 bb_reg[DPK_BB_REG_NUM] = { 3187 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 3188 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 3189 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 3190 u32 rf_reg[DPK_RF_REG_NUM] = { 3191 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 3192 u8 path; 3193 3194 if (!dpk_info->is_dpk_pwr_on) { 3195 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 3196 return; 3197 } else if (rtw8822c_dpk_reload(rtwdev)) { 3198 return; 3199 } 3200 3201 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 3202 ewma_thermal_init(&dpk_info->avg_thermal[path]); 3203 3204 rtw8822c_dpk_information(rtwdev); 3205 3206 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 3207 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3208 3209 rtw8822c_dpk_mac_bb_setting(rtwdev); 3210 rtw8822c_dpk_afe_setting(rtwdev, true); 3211 rtw8822c_dpk_pre_setting(rtwdev); 3212 rtw8822c_dpk_result_reset(rtwdev); 3213 rtw8822c_dpk_path_select(rtwdev); 3214 rtw8822c_dpk_afe_setting(rtwdev, false); 3215 rtw8822c_dpk_enable_disable(rtwdev); 3216 3217 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3218 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 3219 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3220 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 3221 } 3222 3223 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 3224 { 3225 rtw8822c_do_iqk(rtwdev); 3226 rtw8822c_do_dpk(rtwdev); 3227 } 3228 3229 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 3230 { 3231 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3232 u8 path; 3233 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 3234 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 3235 3236 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 3237 return; 3238 3239 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 3240 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 3241 ewma_thermal_add(&dpk_info->avg_thermal[path], 3242 thermal_value[path]); 3243 thermal_value[path] = 3244 ewma_thermal_read(&dpk_info->avg_thermal[path]); 3245 delta_dpk[path] = dpk_info->thermal_dpk[path] - 3246 thermal_value[path]; 3247 offset[path] = delta_dpk[path] - 3248 dpk_info->thermal_dpk_delta[path]; 3249 offset[path] &= 0x7f; 3250 3251 if (offset[path] != dpk_info->pre_pwsf[path]) { 3252 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3253 0x8 | (path << 1)); 3254 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 3255 offset[path]); 3256 dpk_info->pre_pwsf[path] = offset[path]; 3257 } 3258 } 3259 } 3260 3261 static const struct rtw_phy_cck_pd_reg 3262 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 3263 { 3264 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 3265 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 3266 }, 3267 { 3268 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 3269 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 3270 }, 3271 }; 3272 3273 #define RTW_CCK_PD_MAX 255 3274 #define RTW_CCK_CS_MAX 31 3275 #define RTW_CCK_CS_ERR1 27 3276 #define RTW_CCK_CS_ERR2 29 3277 static void 3278 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 3279 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 3280 { 3281 u32 pd, cs; 3282 3283 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 3284 return; 3285 3286 pd = rtw_read32_mask(rtwdev, 3287 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3288 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 3289 cs = rtw_read32_mask(rtwdev, 3290 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3291 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 3292 pd += pd_diff; 3293 cs += cs_diff; 3294 if (pd > RTW_CCK_PD_MAX) 3295 pd = RTW_CCK_PD_MAX; 3296 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 3297 cs++; 3298 else if (cs > RTW_CCK_CS_MAX) 3299 cs = RTW_CCK_CS_MAX; 3300 rtw_write32_mask(rtwdev, 3301 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3302 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 3303 pd); 3304 rtw_write32_mask(rtwdev, 3305 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3306 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 3307 cs); 3308 } 3309 3310 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 3311 { 3312 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3313 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 3314 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 3315 u8 cur_lvl; 3316 u8 nrx, bw; 3317 3318 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 3319 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 3320 3321 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 3322 return; 3323 3324 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 3325 3326 /* update cck pd info */ 3327 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 3328 3329 rtw8822c_phy_cck_pd_set_reg(rtwdev, 3330 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 3331 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 3332 bw, nrx); 3333 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 3334 } 3335 3336 #define PWR_TRACK_MASK 0x7f 3337 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 3338 { 3339 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3340 3341 switch (rf_path) { 3342 case RF_PATH_A: 3343 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 3344 dm_info->delta_power_index[rf_path]); 3345 break; 3346 case RF_PATH_B: 3347 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 3348 dm_info->delta_power_index[rf_path]); 3349 break; 3350 default: 3351 break; 3352 } 3353 } 3354 3355 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 3356 struct rtw_swing_table *swing_table, 3357 u8 path) 3358 { 3359 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3360 u8 thermal_value, delta; 3361 3362 if (rtwdev->efuse.thermal_meter[path] == 0xff) 3363 return; 3364 3365 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 3366 3367 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 3368 3369 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 3370 3371 dm_info->delta_power_index[path] = 3372 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 3373 delta); 3374 3375 rtw8822c_pwrtrack_set(rtwdev, path); 3376 } 3377 3378 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3379 { 3380 struct rtw_swing_table swing_table; 3381 u8 i; 3382 3383 rtw_phy_config_swing_table(rtwdev, &swing_table); 3384 3385 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 3386 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 3387 3388 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 3389 rtw8822c_do_iqk(rtwdev); 3390 } 3391 3392 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3393 { 3394 struct rtw_efuse *efuse = &rtwdev->efuse; 3395 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3396 3397 if (efuse->power_track_type != 0) 3398 return; 3399 3400 if (!dm_info->pwr_trk_triggered) { 3401 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3402 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 3403 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3404 3405 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3406 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 3407 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3408 3409 dm_info->pwr_trk_triggered = true; 3410 return; 3411 } 3412 3413 __rtw8822c_pwr_track(rtwdev); 3414 dm_info->pwr_trk_triggered = false; 3415 } 3416 3417 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 3418 {0x0086, 3419 RTW_PWR_CUT_ALL_MSK, 3420 RTW_PWR_INTF_SDIO_MSK, 3421 RTW_PWR_ADDR_SDIO, 3422 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3423 {0x0086, 3424 RTW_PWR_CUT_ALL_MSK, 3425 RTW_PWR_INTF_SDIO_MSK, 3426 RTW_PWR_ADDR_SDIO, 3427 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3428 {0x002E, 3429 RTW_PWR_CUT_ALL_MSK, 3430 RTW_PWR_INTF_ALL_MSK, 3431 RTW_PWR_ADDR_MAC, 3432 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3433 {0x002D, 3434 RTW_PWR_CUT_ALL_MSK, 3435 RTW_PWR_INTF_ALL_MSK, 3436 RTW_PWR_ADDR_MAC, 3437 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3438 {0x007F, 3439 RTW_PWR_CUT_ALL_MSK, 3440 RTW_PWR_INTF_ALL_MSK, 3441 RTW_PWR_ADDR_MAC, 3442 RTW_PWR_CMD_WRITE, BIT(7), 0}, 3443 {0x004A, 3444 RTW_PWR_CUT_ALL_MSK, 3445 RTW_PWR_INTF_USB_MSK, 3446 RTW_PWR_ADDR_MAC, 3447 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3448 {0x0005, 3449 RTW_PWR_CUT_ALL_MSK, 3450 RTW_PWR_INTF_ALL_MSK, 3451 RTW_PWR_ADDR_MAC, 3452 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 3453 {0xFFFF, 3454 RTW_PWR_CUT_ALL_MSK, 3455 RTW_PWR_INTF_ALL_MSK, 3456 0, 3457 RTW_PWR_CMD_END, 0, 0}, 3458 }; 3459 3460 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 3461 {0x0000, 3462 RTW_PWR_CUT_ALL_MSK, 3463 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3464 RTW_PWR_ADDR_MAC, 3465 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3466 {0x0005, 3467 RTW_PWR_CUT_ALL_MSK, 3468 RTW_PWR_INTF_ALL_MSK, 3469 RTW_PWR_ADDR_MAC, 3470 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 3471 {0x0075, 3472 RTW_PWR_CUT_ALL_MSK, 3473 RTW_PWR_INTF_PCI_MSK, 3474 RTW_PWR_ADDR_MAC, 3475 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3476 {0x0006, 3477 RTW_PWR_CUT_ALL_MSK, 3478 RTW_PWR_INTF_ALL_MSK, 3479 RTW_PWR_ADDR_MAC, 3480 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3481 {0x0075, 3482 RTW_PWR_CUT_ALL_MSK, 3483 RTW_PWR_INTF_PCI_MSK, 3484 RTW_PWR_ADDR_MAC, 3485 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3486 {0xFF1A, 3487 RTW_PWR_CUT_ALL_MSK, 3488 RTW_PWR_INTF_USB_MSK, 3489 RTW_PWR_ADDR_MAC, 3490 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3491 {0x002E, 3492 RTW_PWR_CUT_ALL_MSK, 3493 RTW_PWR_INTF_ALL_MSK, 3494 RTW_PWR_ADDR_MAC, 3495 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3496 {0x0006, 3497 RTW_PWR_CUT_ALL_MSK, 3498 RTW_PWR_INTF_ALL_MSK, 3499 RTW_PWR_ADDR_MAC, 3500 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3501 {0x0005, 3502 RTW_PWR_CUT_ALL_MSK, 3503 RTW_PWR_INTF_ALL_MSK, 3504 RTW_PWR_ADDR_MAC, 3505 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 3506 {0x1018, 3507 RTW_PWR_CUT_ALL_MSK, 3508 RTW_PWR_INTF_ALL_MSK, 3509 RTW_PWR_ADDR_MAC, 3510 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3511 {0x0005, 3512 RTW_PWR_CUT_ALL_MSK, 3513 RTW_PWR_INTF_ALL_MSK, 3514 RTW_PWR_ADDR_MAC, 3515 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3516 {0x0005, 3517 RTW_PWR_CUT_ALL_MSK, 3518 RTW_PWR_INTF_ALL_MSK, 3519 RTW_PWR_ADDR_MAC, 3520 RTW_PWR_CMD_POLLING, BIT(0), 0}, 3521 {0x0074, 3522 RTW_PWR_CUT_ALL_MSK, 3523 RTW_PWR_INTF_PCI_MSK, 3524 RTW_PWR_ADDR_MAC, 3525 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3526 {0x0071, 3527 RTW_PWR_CUT_ALL_MSK, 3528 RTW_PWR_INTF_PCI_MSK, 3529 RTW_PWR_ADDR_MAC, 3530 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3531 {0x0062, 3532 RTW_PWR_CUT_ALL_MSK, 3533 RTW_PWR_INTF_PCI_MSK, 3534 RTW_PWR_ADDR_MAC, 3535 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 3536 (BIT(7) | BIT(6) | BIT(5))}, 3537 {0x0061, 3538 RTW_PWR_CUT_ALL_MSK, 3539 RTW_PWR_INTF_PCI_MSK, 3540 RTW_PWR_ADDR_MAC, 3541 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 3542 {0x001F, 3543 RTW_PWR_CUT_ALL_MSK, 3544 RTW_PWR_INTF_ALL_MSK, 3545 RTW_PWR_ADDR_MAC, 3546 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3547 {0x00EF, 3548 RTW_PWR_CUT_ALL_MSK, 3549 RTW_PWR_INTF_ALL_MSK, 3550 RTW_PWR_ADDR_MAC, 3551 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3552 {0x1045, 3553 RTW_PWR_CUT_ALL_MSK, 3554 RTW_PWR_INTF_ALL_MSK, 3555 RTW_PWR_ADDR_MAC, 3556 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 3557 {0x0010, 3558 RTW_PWR_CUT_ALL_MSK, 3559 RTW_PWR_INTF_ALL_MSK, 3560 RTW_PWR_ADDR_MAC, 3561 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3562 {0x1064, 3563 RTW_PWR_CUT_ALL_MSK, 3564 RTW_PWR_INTF_ALL_MSK, 3565 RTW_PWR_ADDR_MAC, 3566 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3567 {0xFFFF, 3568 RTW_PWR_CUT_ALL_MSK, 3569 RTW_PWR_INTF_ALL_MSK, 3570 0, 3571 RTW_PWR_CMD_END, 0, 0}, 3572 }; 3573 3574 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 3575 {0x0093, 3576 RTW_PWR_CUT_ALL_MSK, 3577 RTW_PWR_INTF_ALL_MSK, 3578 RTW_PWR_ADDR_MAC, 3579 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3580 {0x001F, 3581 RTW_PWR_CUT_ALL_MSK, 3582 RTW_PWR_INTF_ALL_MSK, 3583 RTW_PWR_ADDR_MAC, 3584 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3585 {0x00EF, 3586 RTW_PWR_CUT_ALL_MSK, 3587 RTW_PWR_INTF_ALL_MSK, 3588 RTW_PWR_ADDR_MAC, 3589 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3590 {0x1045, 3591 RTW_PWR_CUT_ALL_MSK, 3592 RTW_PWR_INTF_ALL_MSK, 3593 RTW_PWR_ADDR_MAC, 3594 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3595 {0xFF1A, 3596 RTW_PWR_CUT_ALL_MSK, 3597 RTW_PWR_INTF_USB_MSK, 3598 RTW_PWR_ADDR_MAC, 3599 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 3600 {0x0049, 3601 RTW_PWR_CUT_ALL_MSK, 3602 RTW_PWR_INTF_ALL_MSK, 3603 RTW_PWR_ADDR_MAC, 3604 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3605 {0x0006, 3606 RTW_PWR_CUT_ALL_MSK, 3607 RTW_PWR_INTF_ALL_MSK, 3608 RTW_PWR_ADDR_MAC, 3609 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3610 {0x0002, 3611 RTW_PWR_CUT_ALL_MSK, 3612 RTW_PWR_INTF_ALL_MSK, 3613 RTW_PWR_ADDR_MAC, 3614 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3615 {0x0005, 3616 RTW_PWR_CUT_ALL_MSK, 3617 RTW_PWR_INTF_ALL_MSK, 3618 RTW_PWR_ADDR_MAC, 3619 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3620 {0x0005, 3621 RTW_PWR_CUT_ALL_MSK, 3622 RTW_PWR_INTF_ALL_MSK, 3623 RTW_PWR_ADDR_MAC, 3624 RTW_PWR_CMD_POLLING, BIT(1), 0}, 3625 {0x0000, 3626 RTW_PWR_CUT_ALL_MSK, 3627 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3628 RTW_PWR_ADDR_MAC, 3629 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3630 {0xFFFF, 3631 RTW_PWR_CUT_ALL_MSK, 3632 RTW_PWR_INTF_ALL_MSK, 3633 0, 3634 RTW_PWR_CMD_END, 0, 0}, 3635 }; 3636 3637 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 3638 {0x0005, 3639 RTW_PWR_CUT_ALL_MSK, 3640 RTW_PWR_INTF_SDIO_MSK, 3641 RTW_PWR_ADDR_MAC, 3642 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 3643 {0x0007, 3644 RTW_PWR_CUT_ALL_MSK, 3645 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3646 RTW_PWR_ADDR_MAC, 3647 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 3648 {0x0067, 3649 RTW_PWR_CUT_ALL_MSK, 3650 RTW_PWR_INTF_ALL_MSK, 3651 RTW_PWR_ADDR_MAC, 3652 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3653 {0x004A, 3654 RTW_PWR_CUT_ALL_MSK, 3655 RTW_PWR_INTF_USB_MSK, 3656 RTW_PWR_ADDR_MAC, 3657 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3658 {0x0081, 3659 RTW_PWR_CUT_ALL_MSK, 3660 RTW_PWR_INTF_ALL_MSK, 3661 RTW_PWR_ADDR_MAC, 3662 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 3663 {0x0090, 3664 RTW_PWR_CUT_ALL_MSK, 3665 RTW_PWR_INTF_ALL_MSK, 3666 RTW_PWR_ADDR_MAC, 3667 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3668 {0x0092, 3669 RTW_PWR_CUT_ALL_MSK, 3670 RTW_PWR_INTF_PCI_MSK, 3671 RTW_PWR_ADDR_MAC, 3672 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 3673 {0x0093, 3674 RTW_PWR_CUT_ALL_MSK, 3675 RTW_PWR_INTF_PCI_MSK, 3676 RTW_PWR_ADDR_MAC, 3677 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 3678 {0x0005, 3679 RTW_PWR_CUT_ALL_MSK, 3680 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3681 RTW_PWR_ADDR_MAC, 3682 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 3683 {0x0005, 3684 RTW_PWR_CUT_ALL_MSK, 3685 RTW_PWR_INTF_PCI_MSK, 3686 RTW_PWR_ADDR_MAC, 3687 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3688 {0x0086, 3689 RTW_PWR_CUT_ALL_MSK, 3690 RTW_PWR_INTF_SDIO_MSK, 3691 RTW_PWR_ADDR_SDIO, 3692 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3693 {0xFFFF, 3694 RTW_PWR_CUT_ALL_MSK, 3695 RTW_PWR_INTF_ALL_MSK, 3696 0, 3697 RTW_PWR_CMD_END, 0, 0}, 3698 }; 3699 3700 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 3701 trans_carddis_to_cardemu_8822c, 3702 trans_cardemu_to_act_8822c, 3703 NULL 3704 }; 3705 3706 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 3707 trans_act_to_cardemu_8822c, 3708 trans_cardemu_to_carddis_8822c, 3709 NULL 3710 }; 3711 3712 static const struct rtw_intf_phy_para usb2_param_8822c[] = { 3713 {0xFFFF, 0x00, 3714 RTW_IP_SEL_PHY, 3715 RTW_INTF_PHY_CUT_ALL, 3716 RTW_INTF_PHY_PLATFORM_ALL}, 3717 }; 3718 3719 static const struct rtw_intf_phy_para usb3_param_8822c[] = { 3720 {0xFFFF, 0x0000, 3721 RTW_IP_SEL_PHY, 3722 RTW_INTF_PHY_CUT_ALL, 3723 RTW_INTF_PHY_PLATFORM_ALL}, 3724 }; 3725 3726 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 3727 {0xFFFF, 0x0000, 3728 RTW_IP_SEL_PHY, 3729 RTW_INTF_PHY_CUT_ALL, 3730 RTW_INTF_PHY_PLATFORM_ALL}, 3731 }; 3732 3733 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 3734 {0xFFFF, 0x0000, 3735 RTW_IP_SEL_PHY, 3736 RTW_INTF_PHY_CUT_ALL, 3737 RTW_INTF_PHY_PLATFORM_ALL}, 3738 }; 3739 3740 static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 3741 .usb2_para = usb2_param_8822c, 3742 .usb3_para = usb3_param_8822c, 3743 .gen1_para = pcie_gen1_param_8822c, 3744 .gen2_para = pcie_gen2_param_8822c, 3745 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 3746 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 3747 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 3748 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 3749 }; 3750 3751 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 3752 [0] = RTW_DEF_RFE(8822c, 0, 0), 3753 [1] = RTW_DEF_RFE(8822c, 0, 0), 3754 [2] = RTW_DEF_RFE(8822c, 0, 0), 3755 }; 3756 3757 static const struct rtw_hw_reg rtw8822c_dig[] = { 3758 [0] = { .addr = 0x1d70, .mask = 0x7f }, 3759 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 3760 }; 3761 3762 static const struct rtw_page_table page_table_8822c[] = { 3763 {64, 64, 64, 64, 1}, 3764 {64, 64, 64, 64, 1}, 3765 {64, 64, 0, 0, 1}, 3766 {64, 64, 64, 0, 1}, 3767 {64, 64, 64, 64, 1}, 3768 }; 3769 3770 static const struct rtw_rqpn rqpn_table_8822c[] = { 3771 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3772 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3773 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3774 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3775 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3776 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3777 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3778 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 3779 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3780 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3781 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3782 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3783 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3784 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3785 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3786 }; 3787 3788 static struct rtw_chip_ops rtw8822c_ops = { 3789 .phy_set_param = rtw8822c_phy_set_param, 3790 .read_efuse = rtw8822c_read_efuse, 3791 .query_rx_desc = rtw8822c_query_rx_desc, 3792 .set_channel = rtw8822c_set_channel, 3793 .mac_init = rtw8822c_mac_init, 3794 .read_rf = rtw_phy_read_rf, 3795 .write_rf = rtw_phy_write_rf_reg_mix, 3796 .set_tx_power_index = rtw8822c_set_tx_power_index, 3797 .cfg_ldo25 = rtw8822c_cfg_ldo25, 3798 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 3799 .dpk_track = rtw8822c_dpk_track, 3800 .phy_calibration = rtw8822c_phy_calibration, 3801 .cck_pd_set = rtw8822c_phy_cck_pd_set, 3802 .pwr_track = rtw8822c_pwr_track, 3803 .config_bfee = rtw8822c_bf_config_bfee, 3804 .set_gid_table = rtw_bf_set_gid_table, 3805 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 3806 3807 .coex_set_init = rtw8822c_coex_cfg_init, 3808 .coex_set_ant_switch = NULL, 3809 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 3810 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 3811 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 3812 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 3813 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 3814 }; 3815 3816 /* Shared-Antenna Coex Table */ 3817 static const struct coex_table_para table_sant_8822c[] = { 3818 {0xffffffff, 0xffffffff}, /* case-0 */ 3819 {0x55555555, 0x55555555}, 3820 {0x66555555, 0x66555555}, 3821 {0xaaaaaaaa, 0xaaaaaaaa}, 3822 {0x5a5a5a5a, 0x5a5a5a5a}, 3823 {0xfafafafa, 0xfafafafa}, /* case-5 */ 3824 {0x6a5a6a5a, 0xaaaaaaaa}, 3825 {0x6a5a56aa, 0x6a5a56aa}, 3826 {0x6a5a5a5a, 0x6a5a5a5a}, 3827 {0x66555555, 0x5a5a5a5a}, 3828 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 3829 {0x66555555, 0xfafafafa}, 3830 {0x66555555, 0x6a5a5aaa}, 3831 {0x66555555, 0x5aaa5aaa}, 3832 {0x66555555, 0xaaaa5aaa}, 3833 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 3834 {0xffff55ff, 0xfafafafa}, 3835 {0xffff55ff, 0x6afa5afa}, 3836 {0xaaffffaa, 0xfafafafa}, 3837 {0xaa5555aa, 0x5a5a5a5a}, 3838 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 3839 {0xaa5555aa, 0xaaaaaaaa}, 3840 {0xffffffff, 0x5a5a5a5a}, 3841 {0xffffffff, 0x6a5a5a5a}, 3842 {0xffffffff, 0x55555555}, 3843 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 3844 {0x55555555, 0x5a5a5a5a}, 3845 {0x55555555, 0xaaaaaaaa}, 3846 {0x55555555, 0x6a5a6a5a}, 3847 {0x66556655, 0x66556655} 3848 }; 3849 3850 /* Non-Shared-Antenna Coex Table */ 3851 static const struct coex_table_para table_nsant_8822c[] = { 3852 {0xffffffff, 0xffffffff}, /* case-100 */ 3853 {0x55555555, 0x55555555}, 3854 {0x66555555, 0x66555555}, 3855 {0xaaaaaaaa, 0xaaaaaaaa}, 3856 {0x5a5a5a5a, 0x5a5a5a5a}, 3857 {0xfafafafa, 0xfafafafa}, /* case-105 */ 3858 {0x5afa5afa, 0x5afa5afa}, 3859 {0x55555555, 0xfafafafa}, 3860 {0x66555555, 0xfafafafa}, 3861 {0x66555555, 0x5a5a5a5a}, 3862 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 3863 {0x66555555, 0xaaaaaaaa}, 3864 {0xffff55ff, 0xfafafafa}, 3865 {0xffff55ff, 0x5afa5afa}, 3866 {0xffff55ff, 0xaaaaaaaa}, 3867 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 3868 {0xaaffffaa, 0x5afa5afa}, 3869 {0xaaffffaa, 0xaaaaaaaa}, 3870 {0xffffffff, 0xfafafafa}, 3871 {0xffffffff, 0x5afa5afa}, 3872 {0xffffffff, 0xaaaaaaaa},/* case-120 */ 3873 {0x55ff55ff, 0x5afa5afa}, 3874 {0x55ff55ff, 0xaaaaaaaa}, 3875 {0x55ff55ff, 0x55ff55ff} 3876 }; 3877 3878 /* Shared-Antenna TDMA */ 3879 static const struct coex_tdma_para tdma_sant_8822c[] = { 3880 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 3881 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 3882 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 3883 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 3884 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 3885 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 3886 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 3887 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 3888 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 3889 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 3890 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 3891 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 3892 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 3893 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 3894 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 3895 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 3896 { {0x51, 0x45, 0x03, 0x10, 0x10} }, 3897 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 3898 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 3899 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 3900 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 3901 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 3902 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 3903 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 3904 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 3905 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 3906 { {0x51, 0x08, 0x03, 0x10, 0x50} } 3907 }; 3908 3909 /* Non-Shared-Antenna TDMA */ 3910 static const struct coex_tdma_para tdma_nsant_8822c[] = { 3911 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 3912 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 3913 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 3914 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 3915 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 3916 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 3917 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 3918 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 3919 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 3920 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 3921 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 3922 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 3923 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 3924 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 3925 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 3926 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 3927 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 3928 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 3929 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 3930 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 3931 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ 3932 }; 3933 3934 /* rssi in percentage % (dbm = % - 100) */ 3935 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 3936 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 3937 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 3938 3939 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 3940 static const struct coex_rf_para rf_para_tx_8822c[] = { 3941 {0, 0, false, 7}, /* for normal */ 3942 {0, 16, false, 7}, /* for WL-CPT */ 3943 {8, 17, true, 4}, 3944 {7, 18, true, 4}, 3945 {6, 19, true, 4}, 3946 {5, 20, true, 4} 3947 }; 3948 3949 static const struct coex_rf_para rf_para_rx_8822c[] = { 3950 {0, 0, false, 7}, /* for normal */ 3951 {0, 16, false, 7}, /* for WL-CPT */ 3952 {3, 24, true, 5}, 3953 {2, 26, true, 5}, 3954 {1, 27, true, 5}, 3955 {0, 28, true, 5} 3956 }; 3957 3958 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 3959 3960 static const u8 3961 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 3962 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 3963 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 3964 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 3965 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 3966 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 3967 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 3968 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 3969 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 3970 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 3971 }; 3972 3973 static const u8 3974 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 3975 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 3976 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 3977 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 3978 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 3979 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 3980 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 3981 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 3982 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 3983 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 3984 }; 3985 3986 static const u8 3987 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 3988 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 3989 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 3990 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 3991 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 3992 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 3993 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 3994 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 3995 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 3996 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 3997 }; 3998 3999 static const u8 4000 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4001 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4002 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4003 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4004 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4005 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4006 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4007 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4008 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4009 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4010 }; 4011 4012 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 4013 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 4014 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 4015 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 4016 }; 4017 4018 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 4019 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4020 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 4021 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 4022 }; 4023 4024 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 4025 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 4026 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 4027 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 4028 }; 4029 4030 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 4031 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4032 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 4033 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 4034 }; 4035 4036 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 4037 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4038 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4039 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 4040 }; 4041 4042 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 4043 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4044 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 4045 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 4046 }; 4047 4048 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 4049 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 4050 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 4051 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 4052 }; 4053 4054 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 4055 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4056 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4057 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 4058 }; 4059 4060 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 4061 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 4062 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 4063 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 4064 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 4065 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 4066 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 4067 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 4068 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 4069 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 4070 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 4071 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 4072 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 4073 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 4074 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 4075 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 4076 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 4077 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 4078 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 4079 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 4080 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 4081 }; 4082 4083 #ifdef CONFIG_PM 4084 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 4085 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 4086 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 4087 WIPHY_WOWLAN_NET_DETECT, 4088 .n_patterns = RTW_MAX_PATTERN_NUM, 4089 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 4090 .pattern_min_len = 1, 4091 .max_nd_match_sets = 4, 4092 }; 4093 #endif 4094 4095 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 4096 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 4097 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 4098 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 4099 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 4100 {0, 0, RTW_REG_DOMAIN_NL}, 4101 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4102 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4103 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4104 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4105 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 4106 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4107 {0, 0, RTW_REG_DOMAIN_NL}, 4108 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 4109 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 4110 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 4111 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 4112 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 4113 {0, 0, RTW_REG_DOMAIN_NL}, 4114 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4115 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4116 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 4117 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4118 }; 4119 4120 struct rtw_chip_info rtw8822c_hw_spec = { 4121 .ops = &rtw8822c_ops, 4122 .id = RTW_CHIP_TYPE_8822C, 4123 .fw_name = "rtw88/rtw8822c_fw.bin", 4124 .tx_pkt_desc_sz = 48, 4125 .tx_buf_desc_sz = 16, 4126 .rx_pkt_desc_sz = 24, 4127 .rx_buf_desc_sz = 8, 4128 .phy_efuse_size = 512, 4129 .log_efuse_size = 768, 4130 .ptct_efuse_size = 124, 4131 .txff_size = 262144, 4132 .rxff_size = 24576, 4133 .txgi_factor = 2, 4134 .is_pwr_by_rate_dec = false, 4135 .max_power_index = 0x7f, 4136 .csi_buf_pg_num = 50, 4137 .band = RTW_BAND_2G | RTW_BAND_5G, 4138 .page_size = 128, 4139 .dig_min = 0x20, 4140 .ht_supported = true, 4141 .vht_supported = true, 4142 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 4143 .sys_func_en = 0xD8, 4144 .pwr_on_seq = card_enable_flow_8822c, 4145 .pwr_off_seq = card_disable_flow_8822c, 4146 .page_table = page_table_8822c, 4147 .rqpn_table = rqpn_table_8822c, 4148 .intf_table = &phy_para_table_8822c, 4149 .dig = rtw8822c_dig, 4150 .rf_base_addr = {0x3c00, 0x4c00}, 4151 .rf_sipi_addr = {0x1808, 0x4108}, 4152 .mac_tbl = &rtw8822c_mac_tbl, 4153 .agc_tbl = &rtw8822c_agc_tbl, 4154 .bb_tbl = &rtw8822c_bb_tbl, 4155 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 4156 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 4157 .rfe_defs = rtw8822c_rfe_defs, 4158 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 4159 .en_dis_dpd = true, 4160 .dpd_ratemask = DIS_DPD_RATEALL, 4161 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 4162 .iqk_threshold = 8, 4163 .bfer_su_max_num = 2, 4164 .bfer_mu_max_num = 1, 4165 4166 #ifdef CONFIG_PM 4167 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 4168 .wowlan_stub = &rtw_wowlan_stub_8822c, 4169 .max_sched_scan_ssids = 4, 4170 #endif 4171 .coex_para_ver = 0x19062706, 4172 .bt_desired_ver = 0x6, 4173 .scbd_support = true, 4174 .new_scbd10_def = true, 4175 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 4176 .bt_rssi_type = COEX_BTRSSI_DBM, 4177 .ant_isolation = 15, 4178 .rssi_tolerance = 2, 4179 .wl_rssi_step = wl_rssi_step_8822c, 4180 .bt_rssi_step = bt_rssi_step_8822c, 4181 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 4182 .table_sant = table_sant_8822c, 4183 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 4184 .table_nsant = table_nsant_8822c, 4185 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 4186 .tdma_sant = tdma_sant_8822c, 4187 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 4188 .tdma_nsant = tdma_nsant_8822c, 4189 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 4190 .wl_rf_para_tx = rf_para_tx_8822c, 4191 .wl_rf_para_rx = rf_para_rx_8822c, 4192 .bt_afh_span_bw20 = 0x24, 4193 .bt_afh_span_bw40 = 0x36, 4194 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 4195 .afh_5g = afh_5g_8822c, 4196 4197 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 4198 .coex_info_hw_regs = coex_info_hw_regs_8822c, 4199 }; 4200 EXPORT_SYMBOL(rtw8822c_hw_spec); 4201 4202 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 4203 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 4204