1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8822c.h" 12 #include "rtw8822c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 17 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 18 u8 rx_path, bool is_tx2_path); 19 20 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 21 struct rtw8822c_efuse *map) 22 { 23 ether_addr_copy(efuse->addr, map->e.mac_addr); 24 } 25 26 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 27 { 28 struct rtw_efuse *efuse = &rtwdev->efuse; 29 struct rtw8822c_efuse *map; 30 int i; 31 32 map = (struct rtw8822c_efuse *)log_map; 33 34 efuse->rfe_option = map->rfe_option; 35 efuse->rf_board_option = map->rf_board_option; 36 efuse->crystal_cap = map->xtal_k; 37 efuse->channel_plan = map->channel_plan; 38 efuse->country_code[0] = map->country_code[0]; 39 efuse->country_code[1] = map->country_code[1]; 40 efuse->bt_setting = map->rf_bt_setting; 41 efuse->regd = map->rf_board_option & 0x7; 42 43 for (i = 0; i < 4; i++) 44 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 45 46 switch (rtw_hci_type(rtwdev)) { 47 case RTW_HCI_TYPE_PCIE: 48 rtw8822ce_efuse_parsing(efuse, map); 49 break; 50 default: 51 /* unsupported now */ 52 return -ENOTSUPP; 53 } 54 55 return 0; 56 } 57 58 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 59 { 60 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 61 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 62 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 63 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 64 65 if (pre) 66 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 67 else 68 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 69 } 70 71 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 72 struct rtw_backup_info *backup, 73 struct rtw_backup_info *backup_rf) 74 { 75 u32 path, i; 76 u32 val; 77 u32 reg; 78 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 79 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 80 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 81 0x1a00, 0x1a14, 0x1d58, 0x1c38, 82 0x1e24, 0x1e28, 0x1860, 0x4160}; 83 84 for (i = 0; i < DACK_REG_8822C; i++) { 85 backup[i].len = 4; 86 backup[i].reg = addrs[i]; 87 backup[i].val = rtw_read32(rtwdev, addrs[i]); 88 } 89 90 for (path = 0; path < DACK_PATH_8822C; path++) { 91 for (i = 0; i < DACK_RF_8822C; i++) { 92 reg = rf_addr[i]; 93 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 94 backup_rf[path * i + i].reg = reg; 95 backup_rf[path * i + i].val = val; 96 } 97 } 98 } 99 100 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 101 struct rtw_backup_info *backup, 102 struct rtw_backup_info *backup_rf) 103 { 104 u32 path, i; 105 u32 val; 106 u32 reg; 107 108 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 109 110 for (path = 0; path < DACK_PATH_8822C; path++) { 111 for (i = 0; i < DACK_RF_8822C; i++) { 112 val = backup_rf[path * i + i].val; 113 reg = backup_rf[path * i + i].reg; 114 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 115 } 116 } 117 } 118 119 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 120 u32 *min, u32 *max) 121 { 122 if (value >= 0x200) { 123 if (*min >= 0x200) { 124 if (*min > value) 125 *min = value; 126 } else { 127 *min = value; 128 } 129 if (*max >= 0x200) { 130 if (*max < value) 131 *max = value; 132 } 133 } else { 134 if (*min < 0x200) { 135 if (*min > value) 136 *min = value; 137 } 138 139 if (*max >= 0x200) { 140 *max = value; 141 } else { 142 if (*max < value) 143 *max = value; 144 } 145 } 146 } 147 148 static void swap_u32(u32 *v1, u32 *v2) 149 { 150 u32 tmp; 151 152 tmp = *v1; 153 *v1 = *v2; 154 *v2 = tmp; 155 } 156 157 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 158 { 159 if (*v1 >= 0x200 && *v2 >= 0x200) { 160 if (*v1 > *v2) 161 swap_u32(v1, v2); 162 } else if (*v1 < 0x200 && *v2 < 0x200) { 163 if (*v1 > *v2) 164 swap_u32(v1, v2); 165 } else if (*v1 < 0x200 && *v2 >= 0x200) { 166 swap_u32(v1, v2); 167 } 168 } 169 170 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 171 { 172 u32 i, j; 173 174 for (i = 0; i < DACK_SN_8822C - 1; i++) { 175 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 176 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 177 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 178 } 179 } 180 } 181 182 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 183 { 184 u32 p, m, t, i; 185 186 m = 0; 187 p = 0; 188 for (i = 10; i < DACK_SN_8822C - 10; i++) { 189 if (vec[i] > 0x200) 190 m = (0x400 - vec[i]) + m; 191 else 192 p = vec[i] + p; 193 } 194 195 if (p > m) { 196 t = p - m; 197 t = t / (DACK_SN_8822C - 20); 198 } else { 199 t = m - p; 200 t = t / (DACK_SN_8822C - 20); 201 if (t != 0x0) 202 t = 0x400 - t; 203 } 204 205 *val = t; 206 } 207 208 static u32 rtw8822c_get_path_write_addr(u8 path) 209 { 210 u32 base_addr; 211 212 switch (path) { 213 case RF_PATH_A: 214 base_addr = 0x1800; 215 break; 216 case RF_PATH_B: 217 base_addr = 0x4100; 218 break; 219 default: 220 WARN_ON(1); 221 return -1; 222 } 223 224 return base_addr; 225 } 226 227 static u32 rtw8822c_get_path_read_addr(u8 path) 228 { 229 u32 base_addr; 230 231 switch (path) { 232 case RF_PATH_A: 233 base_addr = 0x2800; 234 break; 235 case RF_PATH_B: 236 base_addr = 0x4500; 237 break; 238 default: 239 WARN_ON(1); 240 return -1; 241 } 242 243 return base_addr; 244 } 245 246 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 247 { 248 bool ret = true; 249 250 if ((value >= 0x200 && (0x400 - value) > 0x64) || 251 (value < 0x200 && value > 0x64)) { 252 ret = false; 253 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 254 } 255 256 return ret; 257 } 258 259 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 260 { 261 u32 temp; 262 int i = 0, cnt = 0; 263 264 while (i < DACK_SN_8822C && cnt < 10000) { 265 cnt++; 266 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 267 iv[i] = (temp & 0x3ff000) >> 12; 268 qv[i] = temp & 0x3ff; 269 270 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 271 rtw8822c_dac_iq_check(rtwdev, qv[i])) 272 i++; 273 } 274 } 275 276 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 277 u32 *iv, u32 *qv, 278 u32 *i_value, u32 *q_value) 279 { 280 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 281 u32 i_delta, q_delta; 282 u32 temp; 283 int i, cnt = 0; 284 285 do { 286 i_min = iv[0]; 287 i_max = iv[0]; 288 q_min = qv[0]; 289 q_max = qv[0]; 290 for (i = 0; i < DACK_SN_8822C; i++) { 291 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 292 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 293 } 294 295 if (i_max < 0x200 && i_min < 0x200) 296 i_delta = i_max - i_min; 297 else if (i_max >= 0x200 && i_min >= 0x200) 298 i_delta = i_max - i_min; 299 else 300 i_delta = i_max + (0x400 - i_min); 301 302 if (q_max < 0x200 && q_min < 0x200) 303 q_delta = q_max - q_min; 304 else if (q_max >= 0x200 && q_min >= 0x200) 305 q_delta = q_max - q_min; 306 else 307 q_delta = q_max + (0x400 - q_min); 308 309 rtw_dbg(rtwdev, RTW_DBG_RFK, 310 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 311 i_min, i_max, i_delta); 312 rtw_dbg(rtwdev, RTW_DBG_RFK, 313 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 314 q_min, q_max, q_delta); 315 316 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 317 318 if (i_delta > 5 || q_delta > 5) { 319 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 320 iv[0] = (temp & 0x3ff000) >> 12; 321 qv[0] = temp & 0x3ff; 322 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 323 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 324 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 325 } else { 326 break; 327 } 328 } while (cnt++ < 100); 329 330 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 331 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 332 } 333 334 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 335 u32 *i_value, u32 *q_value) 336 { 337 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 338 u32 rf_a, rf_b; 339 340 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 341 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 342 343 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 344 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 345 346 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 347 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 348 } 349 350 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 351 { 352 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 353 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 354 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 355 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 356 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 357 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 358 rtw_write32(rtwdev, 0x1b00, 0x00000008); 359 rtw_write8(rtwdev, 0x1bcc, 0x3f); 360 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 361 rtw_write8(rtwdev, 0x1bcc, 0x3f); 362 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 363 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 364 } 365 366 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 367 u8 path, u32 *adc_ic, u32 *adc_qc) 368 { 369 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 370 u32 ic = 0, qc = 0, temp = 0; 371 u32 base_addr; 372 u32 path_sel; 373 int i; 374 375 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 376 377 base_addr = rtw8822c_get_path_write_addr(path); 378 switch (path) { 379 case RF_PATH_A: 380 path_sel = 0xa0000; 381 break; 382 case RF_PATH_B: 383 path_sel = 0x80000; 384 break; 385 default: 386 WARN_ON(1); 387 return; 388 } 389 390 /* ADCK step1 */ 391 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 392 if (path == RF_PATH_B) 393 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 394 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 395 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 396 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 397 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 398 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 399 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 400 for (i = 0; i < 10; i++) { 401 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 402 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 403 rtw_write32(rtwdev, 0x1c24, 0x00010002); 404 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 405 rtw_dbg(rtwdev, RTW_DBG_RFK, 406 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 407 408 /* compensation value */ 409 if (ic != 0x0) { 410 ic = 0x400 - ic; 411 *adc_ic = ic; 412 } 413 if (qc != 0x0) { 414 qc = 0x400 - qc; 415 *adc_qc = qc; 416 } 417 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 418 rtw_write32(rtwdev, base_addr + 0x68, temp); 419 dm_info->dack_adck[path] = temp; 420 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 421 base_addr + 0x68, temp); 422 /* check ADC DC offset */ 423 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 424 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 425 rtw_dbg(rtwdev, RTW_DBG_RFK, 426 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 427 if (ic >= 0x200) 428 ic = 0x400 - ic; 429 if (qc >= 0x200) 430 qc = 0x400 - qc; 431 if (ic < 5 && qc < 5) 432 break; 433 } 434 435 /* ADCK step2 */ 436 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 437 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 438 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 439 440 /* release pull low switch on IQ path */ 441 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 442 } 443 444 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 445 { 446 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 447 u32 base_addr; 448 u32 read_addr; 449 450 base_addr = rtw8822c_get_path_write_addr(path); 451 read_addr = rtw8822c_get_path_read_addr(path); 452 453 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 454 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 455 if (path == RF_PATH_A) { 456 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 457 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 458 } 459 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 460 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 461 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 462 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 463 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 464 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 465 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 466 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 467 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 468 mdelay(2); 469 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 470 mdelay(2); 471 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 472 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 473 mdelay(1); 474 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 475 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 476 mdelay(20); 477 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 478 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 479 rtw_err(rtwdev, "failed to wait for dack ready\n"); 480 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 481 mdelay(1); 482 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 483 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 484 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 485 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 486 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 487 } 488 489 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 490 u8 path, u32 *ic_out, u32 *qc_out) 491 { 492 u32 base_addr; 493 u32 ic, qc, ic_in, qc_in; 494 495 base_addr = rtw8822c_get_path_write_addr(path); 496 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 497 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 498 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 499 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 500 501 rtw_write32(rtwdev, 0x1b00, 0x00000008); 502 rtw_write8(rtwdev, 0x1bcc, 0x03f); 503 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 504 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 505 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 506 507 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 508 ic = ic_in; 509 qc = qc_in; 510 511 /* compensation value */ 512 if (ic != 0x0) 513 ic = 0x400 - ic; 514 if (qc != 0x0) 515 qc = 0x400 - qc; 516 if (ic < 0x300) { 517 ic = ic * 2 * 6 / 5; 518 ic = ic + 0x80; 519 } else { 520 ic = (0x400 - ic) * 2 * 6 / 5; 521 ic = 0x7f - ic; 522 } 523 if (qc < 0x300) { 524 qc = qc * 2 * 6 / 5; 525 qc = qc + 0x80; 526 } else { 527 qc = (0x400 - qc) * 2 * 6 / 5; 528 qc = 0x7f - qc; 529 } 530 531 *ic_out = ic; 532 *qc_out = qc; 533 534 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 535 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 536 } 537 538 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 539 u32 adc_ic, u32 adc_qc, 540 u32 *ic_in, u32 *qc_in, 541 u32 *i_out, u32 *q_out) 542 { 543 u32 base_addr; 544 u32 read_addr; 545 u32 ic, qc; 546 u32 temp; 547 548 base_addr = rtw8822c_get_path_write_addr(path); 549 read_addr = rtw8822c_get_path_read_addr(path); 550 ic = *ic_in; 551 qc = *qc_in; 552 553 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 554 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 555 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 556 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 557 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 558 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 559 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 560 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 561 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 562 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 563 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 564 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 565 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 566 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 567 mdelay(2); 568 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 569 mdelay(2); 570 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 571 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 572 mdelay(1); 573 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 574 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 575 mdelay(20); 576 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 577 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 578 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 579 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 580 mdelay(1); 581 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 582 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 583 584 /* check DAC DC offset */ 585 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 586 rtw_write32(rtwdev, base_addr + 0x68, temp); 587 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 588 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 589 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 590 if (ic >= 0x10) 591 ic = ic - 0x10; 592 else 593 ic = 0x400 - (0x10 - ic); 594 595 if (qc >= 0x10) 596 qc = qc - 0x10; 597 else 598 qc = 0x400 - (0x10 - qc); 599 600 *i_out = ic; 601 *q_out = qc; 602 603 if (ic >= 0x200) 604 ic = 0x400 - ic; 605 if (qc >= 0x200) 606 qc = 0x400 - qc; 607 608 *ic_in = ic; 609 *qc_in = qc; 610 611 rtw_dbg(rtwdev, RTW_DBG_RFK, 612 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 613 } 614 615 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 616 { 617 u32 base_addr = rtw8822c_get_path_write_addr(path); 618 619 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 620 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 621 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 622 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 623 } 624 625 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 626 u8 path, u8 vec, u32 w_addr, u32 r_addr) 627 { 628 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 629 u16 val; 630 u32 i; 631 632 if (WARN_ON(vec >= 2)) 633 return; 634 635 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 636 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 637 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 638 dm_info->dack_msbk[path][vec][i] = val; 639 } 640 } 641 642 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 643 { 644 u32 w_off = 0x1c; 645 u32 r_off = 0x2c; 646 u32 w_addr, r_addr; 647 648 if (WARN_ON(path >= 2)) 649 return; 650 651 /* backup I vector */ 652 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 653 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 654 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 655 656 /* backup Q vector */ 657 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 658 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 659 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 660 } 661 662 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 663 { 664 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 665 u8 val; 666 667 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 668 dm_info->dack_dck[RF_PATH_A][0][0] = val; 669 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 670 dm_info->dack_dck[RF_PATH_A][0][1] = val; 671 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 672 dm_info->dack_dck[RF_PATH_A][1][0] = val; 673 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 674 dm_info->dack_dck[RF_PATH_A][1][1] = val; 675 676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 677 dm_info->dack_dck[RF_PATH_B][0][0] = val; 678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 679 dm_info->dack_dck[RF_PATH_B][1][0] = val; 680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 681 dm_info->dack_dck[RF_PATH_B][0][1] = val; 682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 683 dm_info->dack_dck[RF_PATH_B][1][1] = val; 684 } 685 686 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 687 { 688 u32 temp[3]; 689 690 temp[0] = rtw_read32(rtwdev, 0x1860); 691 temp[1] = rtw_read32(rtwdev, 0x4160); 692 temp[2] = rtw_read32(rtwdev, 0x9b4); 693 694 /* set clock */ 695 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 696 697 /* backup path-A I/Q */ 698 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 699 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 700 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 701 702 /* backup path-B I/Q */ 703 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 704 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 705 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 706 707 rtw8822c_dac_cal_backup_dck(rtwdev); 708 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 709 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 710 711 rtw_write32(rtwdev, 0x1860, temp[0]); 712 rtw_write32(rtwdev, 0x4160, temp[1]); 713 rtw_write32(rtwdev, 0x9b4, temp[2]); 714 } 715 716 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 717 { 718 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 719 u8 val; 720 721 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 722 val = dm_info->dack_dck[RF_PATH_A][0][0]; 723 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 724 val = dm_info->dack_dck[RF_PATH_A][0][1]; 725 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 726 727 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 728 val = dm_info->dack_dck[RF_PATH_A][1][0]; 729 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 730 val = dm_info->dack_dck[RF_PATH_A][1][1]; 731 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 732 733 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 734 val = dm_info->dack_dck[RF_PATH_B][0][0]; 735 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 736 val = dm_info->dack_dck[RF_PATH_B][0][1]; 737 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 738 739 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 740 val = dm_info->dack_dck[RF_PATH_B][1][0]; 741 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 742 val = dm_info->dack_dck[RF_PATH_B][1][1]; 743 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 744 } 745 746 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 747 { 748 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 749 750 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 751 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 752 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 753 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 754 755 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 756 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 757 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 758 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 759 760 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 761 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 762 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 763 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 764 765 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 766 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 767 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 768 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 769 770 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 771 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 772 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 773 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 774 775 rtw8822c_dac_cal_restore_dck(rtwdev); 776 777 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 778 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 779 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 780 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 781 782 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 783 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 784 785 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 786 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 787 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 788 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 789 790 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 791 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 792 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 793 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 794 795 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 796 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 797 } 798 799 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 800 u32 target_addr, u32 toggle_addr) 801 { 802 u32 cnt = 0; 803 804 do { 805 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 806 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 807 808 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 809 return true; 810 811 } while (cnt++ < 100); 812 813 return false; 814 } 815 816 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 817 { 818 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 819 u32 w_off = 0x1c; 820 u32 r_off = 0x2c; 821 u32 w_i, r_i, w_q, r_q; 822 u32 value; 823 u32 i; 824 825 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 826 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 827 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 828 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 829 830 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 831 return false; 832 833 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 834 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 835 value = dm_info->dack_msbk[path][0][i]; 836 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 837 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 838 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 839 } 840 841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 842 843 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 844 return false; 845 846 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 847 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 848 value = dm_info->dack_msbk[path][1][i]; 849 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 850 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 851 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 852 } 853 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 854 855 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 856 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 857 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 858 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 859 860 return true; 861 } 862 863 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 864 { 865 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 866 return false; 867 868 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 869 return false; 870 871 return true; 872 } 873 874 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 875 { 876 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 877 u32 temp[3]; 878 879 /* sample the first element for both path's IQ vector */ 880 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 881 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 882 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 883 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 884 return false; 885 886 temp[0] = rtw_read32(rtwdev, 0x1860); 887 temp[1] = rtw_read32(rtwdev, 0x4160); 888 temp[2] = rtw_read32(rtwdev, 0x9b4); 889 890 rtw8822c_dac_cal_restore_prepare(rtwdev); 891 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 892 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 893 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 894 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 895 return false; 896 897 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 898 rtw_err(rtwdev, "failed to restore dack vectors\n"); 899 return false; 900 } 901 902 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 903 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 904 rtw_write32(rtwdev, 0x1860, temp[0]); 905 rtw_write32(rtwdev, 0x4160, temp[1]); 906 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 907 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 908 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 909 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 910 rtw_write32(rtwdev, 0x9b4, temp[2]); 911 912 return true; 913 } 914 915 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 916 { 917 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 918 struct rtw_backup_info backup[DACK_REG_8822C]; 919 u32 ic = 0, qc = 0, i; 920 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 921 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 922 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 923 924 if (rtw8822c_dac_cal_restore(rtwdev)) 925 return; 926 927 /* not able to restore, do it */ 928 929 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 930 931 rtw8822c_dac_bb_setting(rtwdev); 932 933 /* path-A */ 934 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 935 for (i = 0; i < 10; i++) { 936 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 937 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 938 ic_a = ic; 939 qc_a = qc; 940 941 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 942 &ic, &qc, &i_a, &q_a); 943 944 if (ic < 5 && qc < 5) 945 break; 946 } 947 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 948 949 /* path-B */ 950 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 951 for (i = 0; i < 10; i++) { 952 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 953 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 954 ic_b = ic; 955 qc_b = qc; 956 957 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 958 &ic, &qc, &i_b, &q_b); 959 960 if (ic < 5 && qc < 5) 961 break; 962 } 963 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 964 965 rtw_write32(rtwdev, 0x1b00, 0x00000008); 966 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 967 rtw_write8(rtwdev, 0x1bcc, 0x0); 968 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 969 rtw_write8(rtwdev, 0x1bcc, 0x0); 970 971 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 972 973 /* backup results to restore, saving a lot of time */ 974 rtw8822c_dac_cal_backup(rtwdev); 975 976 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 977 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 978 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 980 } 981 982 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 983 { 984 u8 x2k_busy; 985 986 mdelay(1); 987 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 988 if (x2k_busy == 1) { 989 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 990 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 991 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 992 mdelay(1); 993 } 994 } 995 996 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 997 { 998 rtw8822c_rf_dac_cal(rtwdev); 999 rtw8822c_rf_x2_check(rtwdev); 1000 } 1001 1002 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1003 { 1004 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1005 struct rtw_hal *hal = &rtwdev->hal; 1006 u8 crystal_cap; 1007 u8 cck_gi_u_bnd_msb = 0; 1008 u8 cck_gi_u_bnd_lsb = 0; 1009 u8 cck_gi_l_bnd_msb = 0; 1010 u8 cck_gi_l_bnd_lsb = 0; 1011 bool is_tx2_path; 1012 1013 /* power on BB/RF domain */ 1014 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1015 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1016 rtw_write8_set(rtwdev, REG_RF_CTRL, 1017 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1018 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1019 1020 /* pre init before header files config */ 1021 rtw8822c_header_file_init(rtwdev, true); 1022 1023 rtw_phy_load_tables(rtwdev); 1024 1025 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1026 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1027 crystal_cap | (crystal_cap << 7)); 1028 1029 /* post init after header files config */ 1030 rtw8822c_header_file_init(rtwdev, false); 1031 1032 is_tx2_path = false; 1033 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1034 is_tx2_path); 1035 rtw_phy_init(rtwdev); 1036 1037 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1038 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1039 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1040 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1041 1042 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1043 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1044 1045 rtw8822c_rf_init(rtwdev); 1046 } 1047 1048 #define WLAN_TXQ_RPT_EN 0x1F 1049 #define WLAN_SLOT_TIME 0x09 1050 #define WLAN_PIFS_TIME 0x1C 1051 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1052 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1053 #define WLAN_SIFS_CCK_TRX 0x0A 1054 #define WLAN_SIFS_OFDM_TRX 0x10 1055 #define WLAN_NAV_MAX 0xC8 1056 #define WLAN_RDG_NAV 0x05 1057 #define WLAN_TXOP_NAV 0x1B 1058 #define WLAN_CCK_RX_TSF 0x30 1059 #define WLAN_OFDM_RX_TSF 0x30 1060 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1061 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1062 #define WLAN_DRV_EARLY_INT 0x04 1063 #define WLAN_BCN_CTRL_CLT0 0x10 1064 #define WLAN_BCN_DMA_TIME 0x02 1065 #define WLAN_BCN_MAX_ERR 0xFF 1066 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1067 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1068 #define WLAN_SIFS_CCK_CTX 0x0A 1069 #define WLAN_SIFS_CCK_IRX 0x0A 1070 #define WLAN_SIFS_OFDM_CTX 0x0E 1071 #define WLAN_SIFS_OFDM_IRX 0x0E 1072 #define WLAN_EIFS_DUR_TUNE 0x40 1073 #define WLAN_EDCA_VO_PARAM 0x002FA226 1074 #define WLAN_EDCA_VI_PARAM 0x005EA328 1075 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1076 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1077 1078 #define WLAN_RX_FILTER0 0xFFFFFFFF 1079 #define WLAN_RX_FILTER2 0xFFFF 1080 #define WLAN_RCR_CFG 0xE400220E 1081 #define WLAN_RXPKT_MAX_SZ 12288 1082 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1083 1084 #define WLAN_AMPDU_MAX_TIME 0x70 1085 #define WLAN_RTS_LEN_TH 0xFF 1086 #define WLAN_RTS_TX_TIME_TH 0x08 1087 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 1088 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 1089 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1090 #define FAST_EDCA_VO_TH 0x06 1091 #define FAST_EDCA_VI_TH 0x06 1092 #define FAST_EDCA_BE_TH 0x06 1093 #define FAST_EDCA_BK_TH 0x06 1094 #define WLAN_BAR_RETRY_LIMIT 0x01 1095 #define WLAN_BAR_ACK_TYPE 0x05 1096 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1097 #define WLAN_RESP_TXRATE 0x84 1098 #define WLAN_ACK_TO 0x21 1099 #define WLAN_ACK_TO_CCK 0x6A 1100 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1101 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1102 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1103 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1104 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1105 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1106 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1107 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1108 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1109 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1110 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1111 1112 #define WLAN_TX_FUNC_CFG1 0x30 1113 #define WLAN_TX_FUNC_CFG2 0x30 1114 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1115 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1116 #define WLAN_MAC_OPT_FUNC2 0x30810041 1117 1118 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1119 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1120 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1121 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1122 1123 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1124 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1125 1126 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1127 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1128 1129 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1130 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1131 1132 #define MAC_CLK_SPEED 80 /* 80M */ 1133 #define EFUSE_PCB_INFO_OFFSET 0xCA 1134 1135 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1136 { 1137 u8 value8; 1138 u16 value16; 1139 u32 value32; 1140 u16 pre_txcnt; 1141 1142 /* txq control */ 1143 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1144 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1145 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1146 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1147 /* sifs control */ 1148 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1149 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1150 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1151 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1152 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1153 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1154 /* rate fallback control */ 1155 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 1156 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 1157 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 1158 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 1159 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 1160 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 1161 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 1162 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 1163 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 1164 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 1165 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 1166 /* protocol configuration */ 1167 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 1168 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 1169 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 1170 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 1171 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 1172 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 1173 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 1174 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 1175 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 1176 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 1177 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 1178 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 1179 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 1180 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 1181 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 1182 /* close BA parser */ 1183 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 1184 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 1185 1186 /* EDCA configuration */ 1187 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 1188 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 1189 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 1190 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 1191 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 1192 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 1193 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 1194 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 1195 BIT_DIS_STBC_CFE) >> 8); 1196 1197 /* MAC clock configuration */ 1198 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 1199 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 1200 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 1201 1202 rtw_write8_set(rtwdev, REG_MISC_CTRL, 1203 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 1204 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 1205 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 1206 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 1207 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 1208 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 1209 /* Set beacon cotnrol - enable TSF and other related functions */ 1210 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1211 /* Set send beacon related registers */ 1212 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 1213 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 1214 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 1215 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 1216 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 1217 1218 /* WMAC configuration */ 1219 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 1220 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 1221 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 1222 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 1223 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 1224 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 1225 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 1226 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 1227 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 1228 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 1229 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 1230 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 1231 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 1232 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 1233 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 1234 1235 /* init low power */ 1236 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 1237 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 1238 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 1239 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 1240 value16 = 0; 1241 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 1242 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 1243 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 1244 | BIT_RXPSF_OFDMRST; 1245 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1246 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 1247 /* rx ignore configuration */ 1248 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 1249 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 1250 BIT_RXPSF_CONT_ERRCHKEN); 1251 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 1252 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1253 1254 return 0; 1255 } 1256 1257 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 1258 { 1259 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 1260 #define RF18_BAND_2G (0) 1261 #define RF18_BAND_5G (BIT(16) | BIT(8)) 1262 #define RF18_CHANNEL_MASK (MASKBYTE0) 1263 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 1264 #define RF18_RFSI_GE_CH80 (BIT(17)) 1265 #define RF18_RFSI_GT_CH140 (BIT(18)) 1266 #define RF18_BW_MASK (BIT(13) | BIT(12)) 1267 #define RF18_BW_20M (BIT(13) | BIT(12)) 1268 #define RF18_BW_40M (BIT(13)) 1269 #define RF18_BW_80M (BIT(12)) 1270 1271 u32 rf_reg18 = 0; 1272 u32 rf_rxbb = 0; 1273 1274 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 1275 1276 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 1277 RF18_BW_MASK); 1278 1279 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 1280 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 1281 if (channel > 144) 1282 rf_reg18 |= RF18_RFSI_GT_CH140; 1283 else if (channel >= 80) 1284 rf_reg18 |= RF18_RFSI_GE_CH80; 1285 1286 switch (bw) { 1287 case RTW_CHANNEL_WIDTH_5: 1288 case RTW_CHANNEL_WIDTH_10: 1289 case RTW_CHANNEL_WIDTH_20: 1290 default: 1291 rf_reg18 |= RF18_BW_20M; 1292 rf_rxbb = 0x18; 1293 break; 1294 case RTW_CHANNEL_WIDTH_40: 1295 /* RF bandwidth */ 1296 rf_reg18 |= RF18_BW_40M; 1297 rf_rxbb = 0x10; 1298 break; 1299 case RTW_CHANNEL_WIDTH_80: 1300 rf_reg18 |= RF18_BW_80M; 1301 rf_rxbb = 0x8; 1302 break; 1303 } 1304 1305 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 1306 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 1307 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 1308 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 1309 1310 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 1311 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 1312 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 1313 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 1314 1315 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 1316 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 1317 } 1318 1319 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 1320 { 1321 u32 igi; 1322 1323 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 1324 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 1325 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 1326 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 1327 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 1328 } 1329 1330 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1331 u8 primary_ch_idx) 1332 { 1333 if (channel <= 14) { 1334 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1335 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1336 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 1337 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1338 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1339 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 1340 1341 switch (bw) { 1342 case RTW_CHANNEL_WIDTH_20: 1343 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1344 0x5); 1345 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1346 0x5); 1347 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1348 0x6); 1349 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1350 0x6); 1351 break; 1352 case RTW_CHANNEL_WIDTH_40: 1353 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1354 0x4); 1355 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1356 0x4); 1357 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1358 0x0); 1359 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1360 0x0); 1361 break; 1362 } 1363 if (channel == 13 || channel == 14) 1364 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 1365 else if (channel == 11 || channel == 12) 1366 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 1367 else 1368 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 1369 if (channel == 14) { 1370 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 1371 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1372 0x4962c931); 1373 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 1374 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 1375 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 1376 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 1377 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1378 0xff012455); 1379 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 1380 } else { 1381 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 1382 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1383 0x3e18fec8); 1384 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 1385 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 1386 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 1387 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 1388 0x00faf0de); 1389 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1390 0x00122344); 1391 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 1392 0x0fffffff); 1393 } 1394 if (channel == 13) 1395 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1396 else 1397 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 1398 } else if (channel > 35) { 1399 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1400 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1401 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1402 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 1403 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x0); 1404 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 1405 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1406 if (channel >= 36 && channel <= 64) { 1407 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1408 0x1); 1409 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1410 0x1); 1411 } else if (channel >= 100 && channel <= 144) { 1412 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1413 0x2); 1414 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1415 0x2); 1416 } else if (channel >= 149) { 1417 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1418 0x3); 1419 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1420 0x3); 1421 } 1422 1423 if (channel >= 36 && channel <= 51) 1424 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 1425 else if (channel >= 52 && channel <= 55) 1426 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 1427 else if (channel >= 56 && channel <= 111) 1428 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 1429 else if (channel >= 112 && channel <= 119) 1430 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 1431 else if (channel >= 120 && channel <= 172) 1432 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 1433 else if (channel >= 173 && channel <= 177) 1434 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 1435 } 1436 1437 switch (bw) { 1438 case RTW_CHANNEL_WIDTH_20: 1439 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 1440 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1441 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 1442 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 1443 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 1444 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1445 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1446 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1447 break; 1448 case RTW_CHANNEL_WIDTH_40: 1449 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 1450 (primary_ch_idx == 1 ? 1 : 0)); 1451 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 1452 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1453 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1454 (primary_ch_idx | (primary_ch_idx << 4))); 1455 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 1456 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1457 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1458 break; 1459 case RTW_CHANNEL_WIDTH_80: 1460 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 1461 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1462 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1463 (primary_ch_idx | (primary_ch_idx << 4))); 1464 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 1465 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1466 break; 1467 case RTW_CHANNEL_WIDTH_5: 1468 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1469 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1470 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 1471 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 1472 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 1473 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1474 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1475 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1476 break; 1477 case RTW_CHANNEL_WIDTH_10: 1478 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1479 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1480 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 1481 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 1482 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 1483 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1484 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1485 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1486 break; 1487 } 1488 } 1489 1490 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1491 u8 primary_chan_idx) 1492 { 1493 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 1494 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 1495 rtw8822c_set_channel_rf(rtwdev, channel, bw); 1496 rtw8822c_toggle_igi(rtwdev); 1497 } 1498 1499 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1500 { 1501 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1502 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 1503 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 1504 } else if (rx_path == BB_PATH_AB) { 1505 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 1506 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 1507 } 1508 1509 if (rx_path == BB_PATH_A) 1510 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 1511 else if (rx_path == BB_PATH_B) 1512 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 1513 else if (rx_path == BB_PATH_AB) 1514 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 1515 } 1516 1517 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1518 { 1519 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1520 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 1521 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 1522 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 1523 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 1524 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 1525 } else if (rx_path == BB_PATH_AB) { 1526 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 1527 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 1528 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 1529 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 1530 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 1531 } 1532 1533 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 1534 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 1535 } 1536 1537 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1538 { 1539 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 1540 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 1541 } 1542 1543 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1544 bool is_tx2_path) 1545 { 1546 if (tx_path == BB_PATH_A) { 1547 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1548 } else if (tx_path == BB_PATH_B) { 1549 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 1550 } else { 1551 if (is_tx2_path) 1552 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 1553 else 1554 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1555 } 1556 } 1557 1558 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1559 bool is_tx2_path) 1560 { 1561 if (tx_path == BB_PATH_A) { 1562 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 1563 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1564 } else if (tx_path == BB_PATH_B) { 1565 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 1566 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1567 } else { 1568 if (is_tx2_path) { 1569 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 1570 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 1571 } else { 1572 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 1573 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 1574 } 1575 } 1576 } 1577 1578 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1579 bool is_tx2_path) 1580 { 1581 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 1582 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 1583 } 1584 1585 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 1586 u8 rx_path, bool is_tx2_path) 1587 { 1588 if ((tx_path | rx_path) & BB_PATH_A) 1589 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 1590 else 1591 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 1592 if ((tx_path | rx_path) & BB_PATH_B) 1593 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 1594 else 1595 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 1596 1597 rtw8822c_config_rx_path(rtwdev, rx_path); 1598 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 1599 1600 rtw8822c_toggle_igi(rtwdev); 1601 } 1602 1603 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 1604 struct rtw_rx_pkt_stat *pkt_stat) 1605 { 1606 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1607 u8 l_bnd, u_bnd; 1608 u8 gain_a, gain_b; 1609 s8 rx_power[RTW_RF_PATH_MAX]; 1610 s8 min_rx_power = -120; 1611 1612 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 1613 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 1614 l_bnd = dm_info->cck_gi_l_bnd; 1615 u_bnd = dm_info->cck_gi_u_bnd; 1616 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 1617 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 1618 if (gain_a < l_bnd) 1619 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 1620 else if (gain_a > u_bnd) 1621 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 1622 if (gain_b < l_bnd) 1623 rx_power[RF_PATH_A] += (l_bnd - gain_b) << 1; 1624 else if (gain_b > u_bnd) 1625 rx_power[RF_PATH_A] -= (gain_b - u_bnd) << 1; 1626 1627 rx_power[RF_PATH_A] -= 110; 1628 rx_power[RF_PATH_B] -= 110; 1629 1630 pkt_stat->rx_power[RF_PATH_A] = max3(rx_power[RF_PATH_A], 1631 rx_power[RF_PATH_B], 1632 min_rx_power); 1633 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1634 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1635 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 1636 min_rx_power); 1637 } 1638 1639 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 1640 struct rtw_rx_pkt_stat *pkt_stat) 1641 { 1642 u8 rxsc, bw; 1643 s8 min_rx_power = -120; 1644 1645 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 1646 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 1647 else 1648 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 1649 1650 if (rxsc >= 9 && rxsc <= 12) 1651 bw = RTW_CHANNEL_WIDTH_40; 1652 else if (rxsc >= 13) 1653 bw = RTW_CHANNEL_WIDTH_80; 1654 else 1655 bw = RTW_CHANNEL_WIDTH_20; 1656 1657 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 1658 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 1659 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 1660 pkt_stat->bw = bw; 1661 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 1662 pkt_stat->rx_power[RF_PATH_B], 1663 min_rx_power); 1664 } 1665 1666 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1667 struct rtw_rx_pkt_stat *pkt_stat) 1668 { 1669 u8 page; 1670 1671 page = *phy_status & 0xf; 1672 1673 switch (page) { 1674 case 0: 1675 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 1676 break; 1677 case 1: 1678 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 1679 break; 1680 default: 1681 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 1682 return; 1683 } 1684 } 1685 1686 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1687 struct rtw_rx_pkt_stat *pkt_stat, 1688 struct ieee80211_rx_status *rx_status) 1689 { 1690 struct ieee80211_hdr *hdr; 1691 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1692 u8 *phy_status = NULL; 1693 1694 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1695 1696 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1697 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1698 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1699 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc); 1700 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1701 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1702 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1703 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1704 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1705 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1706 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 1707 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1708 1709 /* drv_info_sz is in unit of 8-bytes */ 1710 pkt_stat->drv_info_sz *= 8; 1711 1712 /* c2h cmd pkt's rx/phy status is not interested */ 1713 if (pkt_stat->is_c2h) 1714 return; 1715 1716 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1717 pkt_stat->drv_info_sz); 1718 if (pkt_stat->phy_status) { 1719 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1720 query_phy_status(rtwdev, phy_status, pkt_stat); 1721 } 1722 1723 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1724 } 1725 1726 static void 1727 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 1728 u8 *tx_pwr_ref_ofdm) 1729 { 1730 struct rtw_hal *hal = &rtwdev->hal; 1731 u32 txref_cck[2] = {0x18a0, 0x41a0}; 1732 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 1733 u8 path; 1734 1735 for (path = 0; path < hal->rf_path_num; path++) { 1736 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1737 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 1738 tx_pwr_ref_cck[path]); 1739 } 1740 for (path = 0; path < hal->rf_path_num; path++) { 1741 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1742 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 1743 tx_pwr_ref_ofdm[path]); 1744 } 1745 } 1746 1747 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 1748 s8 *diff_idx) 1749 { 1750 u32 offset_txagc = 0x3a00; 1751 u8 rate_idx = rate & 0xfc; 1752 u8 pwr_idx[4]; 1753 u32 phy_pwr_idx; 1754 int i; 1755 1756 for (i = 0; i < 4; i++) 1757 pwr_idx[i] = diff_idx[i] & 0x7f; 1758 1759 phy_pwr_idx = pwr_idx[0] | 1760 (pwr_idx[1] << 8) | 1761 (pwr_idx[2] << 16) | 1762 (pwr_idx[3] << 24); 1763 1764 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 1765 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 1766 phy_pwr_idx); 1767 } 1768 1769 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 1770 { 1771 struct rtw_hal *hal = &rtwdev->hal; 1772 u8 rs, rate, j; 1773 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 1774 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 1775 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 1776 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 1777 s8 diff_a, diff_b; 1778 u8 pwr_a, pwr_b; 1779 s8 diff_idx[4]; 1780 1781 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 1782 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 1783 for (j = 0; j < rtw_rate_size[rs]; j++) { 1784 rate = rtw_rate_section[rs][j]; 1785 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 1786 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 1787 if (rs == 0) { 1788 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 1789 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 1790 } else { 1791 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 1792 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 1793 } 1794 diff_idx[rate % 4] = min(diff_a, diff_b); 1795 if (rate % 4 == 3) 1796 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 1797 diff_idx); 1798 } 1799 } 1800 } 1801 1802 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1803 { 1804 u8 ldo_pwr; 1805 1806 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 1807 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 1808 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 1809 } 1810 1811 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 1812 { 1813 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1814 u32 cck_enable; 1815 u32 cck_fa_cnt; 1816 u32 crc32_cnt; 1817 u32 ofdm_fa_cnt; 1818 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 1819 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 1820 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 1821 1822 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 1823 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 1824 1825 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 1826 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 1827 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 1828 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 1829 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 1830 1831 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 1832 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 1833 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 1834 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 1835 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 1836 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 1837 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 1838 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 1839 1840 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 1841 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 1842 1843 dm_info->cck_fa_cnt = cck_fa_cnt; 1844 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1845 dm_info->total_fa_cnt = ofdm_fa_cnt; 1846 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 1847 1848 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 1849 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 1850 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1851 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 1852 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 1853 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1854 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 1855 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 1856 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1857 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 1858 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 1859 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1860 1861 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 1862 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 1863 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 1864 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 1865 1866 /* disable rx clk gating to reset counters */ 1867 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 1868 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 1869 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 1870 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 1871 } 1872 1873 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 1874 { 1875 } 1876 1877 /* for coex */ 1878 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 1879 { 1880 /* enable TBTT nterrupt */ 1881 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1882 1883 /* BT report packet sample rate */ 1884 /* 0x790[5:0]=0x5 */ 1885 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 1886 1887 /* enable BT counter statistics */ 1888 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1889 1890 /* enable PTA (3-wire function form BT side) */ 1891 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1892 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 1893 1894 /* enable PTA (tx/rx signal form WiFi side) */ 1895 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1896 /* wl tx signal to PTA not case EDCCA */ 1897 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 1898 /* GNT_BT=1 while select both */ 1899 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 1900 /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */ 1901 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 1902 1903 /* to avoid RF parameter error */ 1904 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000); 1905 } 1906 1907 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1908 { 1909 struct rtw_coex *coex = &rtwdev->coex; 1910 struct rtw_coex_stat *coex_stat = &coex->stat; 1911 struct rtw_efuse *efuse = &rtwdev->efuse; 1912 u32 rf_0x1; 1913 1914 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 1915 return; 1916 1917 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 1918 1919 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 1920 rf_0x1 = 0x40021; 1921 else 1922 rf_0x1 = 0x40000; 1923 1924 /* BT at S1 for Shared-Ant */ 1925 if (efuse->share_ant) 1926 rf_0x1 |= BIT(13); 1927 1928 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 1929 1930 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 1931 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 1932 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 1933 * 1934 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 1935 * disable 0x1c30[22] = 0, 1936 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 1937 * 1938 * disable WL-S1 BB chage RF mode if GNT_BT 1939 * since RF TRx mask can do it 1940 */ 1941 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1); 1942 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0); 1943 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1); 1944 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1); 1945 1946 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 1947 * or antenna path is separated 1948 */ 1949 if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 1950 coex->under_5g || !efuse->share_ant) { 1951 if (coex_stat->kt_ver >= 3) { 1952 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 1953 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1); 1954 } else { 1955 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1); 1956 } 1957 } else { 1958 /* shared-antenna */ 1959 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 1960 if (coex_stat->kt_ver >= 3) 1961 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0); 1962 } 1963 } 1964 1965 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1966 { 1967 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0); 1968 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0); 1969 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0); 1970 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0); 1971 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0); 1972 } 1973 1974 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1975 { 1976 struct rtw_coex *coex = &rtwdev->coex; 1977 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1978 struct rtw_efuse *efuse = &rtwdev->efuse; 1979 1980 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1981 coex_rfe->ant_switch_polarity = 0; 1982 coex_rfe->ant_switch_exist = false; 1983 coex_rfe->ant_switch_with_bt = false; 1984 coex_rfe->ant_switch_diversity = false; 1985 1986 if (efuse->share_ant) 1987 coex_rfe->wlg_at_btg = true; 1988 else 1989 coex_rfe->wlg_at_btg = false; 1990 1991 /* disable LTE coex in wifi side */ 1992 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0); 1993 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff); 1994 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff); 1995 } 1996 1997 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1998 { 1999 struct rtw_coex *coex = &rtwdev->coex; 2000 struct rtw_coex_dm *coex_dm = &coex->dm; 2001 2002 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 2003 return; 2004 2005 coex_dm->cur_wl_pwr_lvl = wl_pwr; 2006 } 2007 2008 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 2009 { 2010 struct rtw_coex *coex = &rtwdev->coex; 2011 struct rtw_coex_dm *coex_dm = &coex->dm; 2012 2013 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 2014 return; 2015 2016 coex_dm->cur_wl_rx_low_gain_en = low_gain; 2017 2018 if (coex_dm->cur_wl_rx_low_gain_en) { 2019 /* set Rx filter corner RCK offset */ 2020 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22); 2021 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36); 2022 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22); 2023 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36); 2024 } else { 2025 /* set Rx filter corner RCK offset */ 2026 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20); 2027 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0); 2028 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0); 2029 } 2030 } 2031 2032 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 2033 {0x0086, 2034 RTW_PWR_CUT_ALL_MSK, 2035 RTW_PWR_INTF_SDIO_MSK, 2036 RTW_PWR_ADDR_SDIO, 2037 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2038 {0x0086, 2039 RTW_PWR_CUT_ALL_MSK, 2040 RTW_PWR_INTF_SDIO_MSK, 2041 RTW_PWR_ADDR_SDIO, 2042 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2043 {0x002E, 2044 RTW_PWR_CUT_ALL_MSK, 2045 RTW_PWR_INTF_ALL_MSK, 2046 RTW_PWR_ADDR_MAC, 2047 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2048 {0x002D, 2049 RTW_PWR_CUT_ALL_MSK, 2050 RTW_PWR_INTF_ALL_MSK, 2051 RTW_PWR_ADDR_MAC, 2052 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2053 {0x007F, 2054 RTW_PWR_CUT_ALL_MSK, 2055 RTW_PWR_INTF_ALL_MSK, 2056 RTW_PWR_ADDR_MAC, 2057 RTW_PWR_CMD_WRITE, BIT(7), 0}, 2058 {0x004A, 2059 RTW_PWR_CUT_ALL_MSK, 2060 RTW_PWR_INTF_USB_MSK, 2061 RTW_PWR_ADDR_MAC, 2062 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2063 {0x0005, 2064 RTW_PWR_CUT_ALL_MSK, 2065 RTW_PWR_INTF_ALL_MSK, 2066 RTW_PWR_ADDR_MAC, 2067 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 2068 {0xFFFF, 2069 RTW_PWR_CUT_ALL_MSK, 2070 RTW_PWR_INTF_ALL_MSK, 2071 0, 2072 RTW_PWR_CMD_END, 0, 0}, 2073 }; 2074 2075 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 2076 {0x0000, 2077 RTW_PWR_CUT_ALL_MSK, 2078 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2079 RTW_PWR_ADDR_MAC, 2080 RTW_PWR_CMD_WRITE, BIT(5), 0}, 2081 {0x0005, 2082 RTW_PWR_CUT_ALL_MSK, 2083 RTW_PWR_INTF_ALL_MSK, 2084 RTW_PWR_ADDR_MAC, 2085 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 2086 {0x0075, 2087 RTW_PWR_CUT_ALL_MSK, 2088 RTW_PWR_INTF_PCI_MSK, 2089 RTW_PWR_ADDR_MAC, 2090 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2091 {0x0006, 2092 RTW_PWR_CUT_ALL_MSK, 2093 RTW_PWR_INTF_ALL_MSK, 2094 RTW_PWR_ADDR_MAC, 2095 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2096 {0x0075, 2097 RTW_PWR_CUT_ALL_MSK, 2098 RTW_PWR_INTF_PCI_MSK, 2099 RTW_PWR_ADDR_MAC, 2100 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2101 {0xFF1A, 2102 RTW_PWR_CUT_ALL_MSK, 2103 RTW_PWR_INTF_USB_MSK, 2104 RTW_PWR_ADDR_MAC, 2105 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2106 {0x002E, 2107 RTW_PWR_CUT_ALL_MSK, 2108 RTW_PWR_INTF_ALL_MSK, 2109 RTW_PWR_ADDR_MAC, 2110 RTW_PWR_CMD_WRITE, BIT(3), 0}, 2111 {0x0006, 2112 RTW_PWR_CUT_ALL_MSK, 2113 RTW_PWR_INTF_ALL_MSK, 2114 RTW_PWR_ADDR_MAC, 2115 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2116 {0x0005, 2117 RTW_PWR_CUT_ALL_MSK, 2118 RTW_PWR_INTF_ALL_MSK, 2119 RTW_PWR_ADDR_MAC, 2120 RTW_PWR_CMD_WRITE, BIT(7), 0}, 2121 {0x0005, 2122 RTW_PWR_CUT_ALL_MSK, 2123 RTW_PWR_INTF_ALL_MSK, 2124 RTW_PWR_ADDR_MAC, 2125 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 2126 {0x0005, 2127 RTW_PWR_CUT_ALL_MSK, 2128 RTW_PWR_INTF_ALL_MSK, 2129 RTW_PWR_ADDR_MAC, 2130 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2131 {0x0005, 2132 RTW_PWR_CUT_ALL_MSK, 2133 RTW_PWR_INTF_ALL_MSK, 2134 RTW_PWR_ADDR_MAC, 2135 RTW_PWR_CMD_POLLING, BIT(0), 0}, 2136 {0x0074, 2137 RTW_PWR_CUT_ALL_MSK, 2138 RTW_PWR_INTF_PCI_MSK, 2139 RTW_PWR_ADDR_MAC, 2140 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2141 {0x0071, 2142 RTW_PWR_CUT_ALL_MSK, 2143 RTW_PWR_INTF_PCI_MSK, 2144 RTW_PWR_ADDR_MAC, 2145 RTW_PWR_CMD_WRITE, BIT(4), 0}, 2146 {0x0062, 2147 RTW_PWR_CUT_ALL_MSK, 2148 RTW_PWR_INTF_PCI_MSK, 2149 RTW_PWR_ADDR_MAC, 2150 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 2151 (BIT(7) | BIT(6) | BIT(5))}, 2152 {0x0061, 2153 RTW_PWR_CUT_ALL_MSK, 2154 RTW_PWR_INTF_PCI_MSK, 2155 RTW_PWR_ADDR_MAC, 2156 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 2157 {0x001F, 2158 RTW_PWR_CUT_ALL_MSK, 2159 RTW_PWR_INTF_ALL_MSK, 2160 RTW_PWR_ADDR_MAC, 2161 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 2162 {0x00EF, 2163 RTW_PWR_CUT_ALL_MSK, 2164 RTW_PWR_INTF_ALL_MSK, 2165 RTW_PWR_ADDR_MAC, 2166 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 2167 {0x1045, 2168 RTW_PWR_CUT_ALL_MSK, 2169 RTW_PWR_INTF_ALL_MSK, 2170 RTW_PWR_ADDR_MAC, 2171 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 2172 {0x0010, 2173 RTW_PWR_CUT_ALL_MSK, 2174 RTW_PWR_INTF_ALL_MSK, 2175 RTW_PWR_ADDR_MAC, 2176 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2177 {0xFFFF, 2178 RTW_PWR_CUT_ALL_MSK, 2179 RTW_PWR_INTF_ALL_MSK, 2180 0, 2181 RTW_PWR_CMD_END, 0, 0}, 2182 }; 2183 2184 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 2185 {0x0093, 2186 RTW_PWR_CUT_ALL_MSK, 2187 RTW_PWR_INTF_ALL_MSK, 2188 RTW_PWR_ADDR_MAC, 2189 RTW_PWR_CMD_WRITE, BIT(3), 0}, 2190 {0x001F, 2191 RTW_PWR_CUT_ALL_MSK, 2192 RTW_PWR_INTF_ALL_MSK, 2193 RTW_PWR_ADDR_MAC, 2194 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2195 {0x00EF, 2196 RTW_PWR_CUT_ALL_MSK, 2197 RTW_PWR_INTF_ALL_MSK, 2198 RTW_PWR_ADDR_MAC, 2199 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2200 {0x1045, 2201 RTW_PWR_CUT_ALL_MSK, 2202 RTW_PWR_INTF_ALL_MSK, 2203 RTW_PWR_ADDR_MAC, 2204 RTW_PWR_CMD_WRITE, BIT(4), 0}, 2205 {0xFF1A, 2206 RTW_PWR_CUT_ALL_MSK, 2207 RTW_PWR_INTF_USB_MSK, 2208 RTW_PWR_ADDR_MAC, 2209 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 2210 {0x0049, 2211 RTW_PWR_CUT_ALL_MSK, 2212 RTW_PWR_INTF_ALL_MSK, 2213 RTW_PWR_ADDR_MAC, 2214 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2215 {0x0006, 2216 RTW_PWR_CUT_ALL_MSK, 2217 RTW_PWR_INTF_ALL_MSK, 2218 RTW_PWR_ADDR_MAC, 2219 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2220 {0x0002, 2221 RTW_PWR_CUT_ALL_MSK, 2222 RTW_PWR_INTF_ALL_MSK, 2223 RTW_PWR_ADDR_MAC, 2224 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2225 {0x0005, 2226 RTW_PWR_CUT_ALL_MSK, 2227 RTW_PWR_INTF_ALL_MSK, 2228 RTW_PWR_ADDR_MAC, 2229 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2230 {0x0005, 2231 RTW_PWR_CUT_ALL_MSK, 2232 RTW_PWR_INTF_ALL_MSK, 2233 RTW_PWR_ADDR_MAC, 2234 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2235 {0x0000, 2236 RTW_PWR_CUT_ALL_MSK, 2237 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2238 RTW_PWR_ADDR_MAC, 2239 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2240 {0xFFFF, 2241 RTW_PWR_CUT_ALL_MSK, 2242 RTW_PWR_INTF_ALL_MSK, 2243 0, 2244 RTW_PWR_CMD_END, 0, 0}, 2245 }; 2246 2247 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 2248 {0x0005, 2249 RTW_PWR_CUT_ALL_MSK, 2250 RTW_PWR_INTF_SDIO_MSK, 2251 RTW_PWR_ADDR_MAC, 2252 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 2253 {0x0007, 2254 RTW_PWR_CUT_ALL_MSK, 2255 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2256 RTW_PWR_ADDR_MAC, 2257 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2258 {0x0067, 2259 RTW_PWR_CUT_ALL_MSK, 2260 RTW_PWR_INTF_ALL_MSK, 2261 RTW_PWR_ADDR_MAC, 2262 RTW_PWR_CMD_WRITE, BIT(5), 0}, 2263 {0x004A, 2264 RTW_PWR_CUT_ALL_MSK, 2265 RTW_PWR_INTF_USB_MSK, 2266 RTW_PWR_ADDR_MAC, 2267 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2268 {0x0081, 2269 RTW_PWR_CUT_ALL_MSK, 2270 RTW_PWR_INTF_ALL_MSK, 2271 RTW_PWR_ADDR_MAC, 2272 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 2273 {0x0090, 2274 RTW_PWR_CUT_ALL_MSK, 2275 RTW_PWR_INTF_ALL_MSK, 2276 RTW_PWR_ADDR_MAC, 2277 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2278 {0x0005, 2279 RTW_PWR_CUT_ALL_MSK, 2280 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2281 RTW_PWR_ADDR_MAC, 2282 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 2283 {0x0005, 2284 RTW_PWR_CUT_ALL_MSK, 2285 RTW_PWR_INTF_PCI_MSK, 2286 RTW_PWR_ADDR_MAC, 2287 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2288 {0x0086, 2289 RTW_PWR_CUT_ALL_MSK, 2290 RTW_PWR_INTF_SDIO_MSK, 2291 RTW_PWR_ADDR_SDIO, 2292 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2293 {0xFFFF, 2294 RTW_PWR_CUT_ALL_MSK, 2295 RTW_PWR_INTF_ALL_MSK, 2296 0, 2297 RTW_PWR_CMD_END, 0, 0}, 2298 }; 2299 2300 static struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 2301 trans_carddis_to_cardemu_8822c, 2302 trans_cardemu_to_act_8822c, 2303 NULL 2304 }; 2305 2306 static struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 2307 trans_act_to_cardemu_8822c, 2308 trans_cardemu_to_carddis_8822c, 2309 NULL 2310 }; 2311 2312 static struct rtw_intf_phy_para usb2_param_8822c[] = { 2313 {0xFFFF, 0x00, 2314 RTW_IP_SEL_PHY, 2315 RTW_INTF_PHY_CUT_ALL, 2316 RTW_INTF_PHY_PLATFORM_ALL}, 2317 }; 2318 2319 static struct rtw_intf_phy_para usb3_param_8822c[] = { 2320 {0xFFFF, 0x0000, 2321 RTW_IP_SEL_PHY, 2322 RTW_INTF_PHY_CUT_ALL, 2323 RTW_INTF_PHY_PLATFORM_ALL}, 2324 }; 2325 2326 static struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 2327 {0xFFFF, 0x0000, 2328 RTW_IP_SEL_PHY, 2329 RTW_INTF_PHY_CUT_ALL, 2330 RTW_INTF_PHY_PLATFORM_ALL}, 2331 }; 2332 2333 static struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 2334 {0xFFFF, 0x0000, 2335 RTW_IP_SEL_PHY, 2336 RTW_INTF_PHY_CUT_ALL, 2337 RTW_INTF_PHY_PLATFORM_ALL}, 2338 }; 2339 2340 static struct rtw_intf_phy_para_table phy_para_table_8822c = { 2341 .usb2_para = usb2_param_8822c, 2342 .usb3_para = usb3_param_8822c, 2343 .gen1_para = pcie_gen1_param_8822c, 2344 .gen2_para = pcie_gen2_param_8822c, 2345 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 2346 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 2347 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 2348 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 2349 }; 2350 2351 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 2352 [0] = RTW_DEF_RFE(8822c, 0, 0), 2353 [1] = RTW_DEF_RFE(8822c, 0, 0), 2354 [2] = RTW_DEF_RFE(8822c, 0, 0), 2355 }; 2356 2357 static struct rtw_hw_reg rtw8822c_dig[] = { 2358 [0] = { .addr = 0x1d70, .mask = 0x7f }, 2359 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 2360 }; 2361 2362 static struct rtw_page_table page_table_8822c[] = { 2363 {64, 64, 64, 64, 1}, 2364 {64, 64, 64, 64, 1}, 2365 {64, 64, 0, 0, 1}, 2366 {64, 64, 64, 0, 1}, 2367 {64, 64, 64, 64, 1}, 2368 }; 2369 2370 static struct rtw_rqpn rqpn_table_8822c[] = { 2371 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2372 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2373 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2374 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2375 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2376 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2377 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2378 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2379 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2380 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2381 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2382 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2383 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2384 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2385 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2386 }; 2387 2388 static struct rtw_chip_ops rtw8822c_ops = { 2389 .phy_set_param = rtw8822c_phy_set_param, 2390 .read_efuse = rtw8822c_read_efuse, 2391 .query_rx_desc = rtw8822c_query_rx_desc, 2392 .set_channel = rtw8822c_set_channel, 2393 .mac_init = rtw8822c_mac_init, 2394 .read_rf = rtw_phy_read_rf, 2395 .write_rf = rtw_phy_write_rf_reg_mix, 2396 .set_tx_power_index = rtw8822c_set_tx_power_index, 2397 .cfg_ldo25 = rtw8822c_cfg_ldo25, 2398 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 2399 .do_iqk = rtw8822c_do_iqk, 2400 2401 .coex_set_init = rtw8822c_coex_cfg_init, 2402 .coex_set_ant_switch = NULL, 2403 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 2404 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 2405 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 2406 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 2407 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 2408 }; 2409 2410 /* Shared-Antenna Coex Table */ 2411 static const struct coex_table_para table_sant_8822c[] = { 2412 {0xffffffff, 0xffffffff}, /* case-0 */ 2413 {0x55555555, 0x55555555}, 2414 {0x66555555, 0x66555555}, 2415 {0xaaaaaaaa, 0xaaaaaaaa}, 2416 {0x5a5a5a5a, 0x5a5a5a5a}, 2417 {0xfafafafa, 0xfafafafa}, /* case-5 */ 2418 {0x6a5a6a5a, 0xaaaaaaaa}, 2419 {0x6a5a56aa, 0x6a5a56aa}, 2420 {0x6a5a5a5a, 0x6a5a5a5a}, 2421 {0x66555555, 0x5a5a5a5a}, 2422 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 2423 {0x66555555, 0xfafafafa}, 2424 {0x66555555, 0x6a5a5aaa}, 2425 {0x66555555, 0x5aaa5aaa}, 2426 {0x66555555, 0xaaaa5aaa}, 2427 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 2428 {0xffff55ff, 0xfafafafa}, 2429 {0xffff55ff, 0x6afa5afa}, 2430 {0xaaffffaa, 0xfafafafa}, 2431 {0xaa5555aa, 0x5a5a5a5a}, 2432 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 2433 {0xaa5555aa, 0xaaaaaaaa}, 2434 {0xffffffff, 0x5a5a5a5a}, 2435 {0xffffffff, 0x6a5a5a5a}, 2436 {0xffffffff, 0x55555555}, 2437 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 2438 {0x55555555, 0x5a5a5a5a}, 2439 {0x55555555, 0xaaaaaaaa}, 2440 {0x55555555, 0x6a5a6a5a}, 2441 {0x66556655, 0x66556655} 2442 }; 2443 2444 /* Non-Shared-Antenna Coex Table */ 2445 static const struct coex_table_para table_nsant_8822c[] = { 2446 {0xffffffff, 0xffffffff}, /* case-100 */ 2447 {0x55555555, 0x55555555}, 2448 {0x66555555, 0x66555555}, 2449 {0xaaaaaaaa, 0xaaaaaaaa}, 2450 {0x5a5a5a5a, 0x5a5a5a5a}, 2451 {0xfafafafa, 0xfafafafa}, /* case-105 */ 2452 {0x5afa5afa, 0x5afa5afa}, 2453 {0x55555555, 0xfafafafa}, 2454 {0x66555555, 0xfafafafa}, 2455 {0x66555555, 0x5a5a5a5a}, 2456 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 2457 {0x66555555, 0xaaaaaaaa}, 2458 {0xffff55ff, 0xfafafafa}, 2459 {0xffff55ff, 0x5afa5afa}, 2460 {0xffff55ff, 0xaaaaaaaa}, 2461 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 2462 {0xaaffffaa, 0x5afa5afa}, 2463 {0xaaffffaa, 0xaaaaaaaa}, 2464 {0xffffffff, 0xfafafafa}, 2465 {0xffffffff, 0x5afa5afa}, 2466 {0xffffffff, 0xaaaaaaaa},/* case-120 */ 2467 {0x55ff55ff, 0x5afa5afa}, 2468 {0x55ff55ff, 0xaaaaaaaa}, 2469 {0x55ff55ff, 0x55ff55ff} 2470 }; 2471 2472 /* Shared-Antenna TDMA */ 2473 static const struct coex_tdma_para tdma_sant_8822c[] = { 2474 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2475 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 2476 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2477 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2478 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2479 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2480 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2481 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2482 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2483 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2484 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2485 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2486 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2487 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2488 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2489 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 2490 { {0x51, 0x45, 0x03, 0x10, 0x10} }, 2491 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2492 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2493 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2494 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 2495 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2496 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2497 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2498 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 2499 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 2500 { {0x51, 0x08, 0x03, 0x10, 0x50} } 2501 }; 2502 2503 /* Non-Shared-Antenna TDMA */ 2504 static const struct coex_tdma_para tdma_nsant_8822c[] = { 2505 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 2506 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 2507 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2508 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2509 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2510 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2511 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2512 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2513 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2514 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2515 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2516 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2517 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2518 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2519 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2520 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2521 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2522 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2523 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2524 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2525 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ 2526 }; 2527 2528 /* rssi in percentage % (dbm = % - 100) */ 2529 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 2530 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 2531 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 2532 2533 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2534 static const struct coex_rf_para rf_para_tx_8822c[] = { 2535 {0, 0, false, 7}, /* for normal */ 2536 {0, 16, false, 7}, /* for WL-CPT */ 2537 {8, 17, true, 4}, 2538 {7, 18, true, 4}, 2539 {6, 19, true, 4}, 2540 {5, 20, true, 4} 2541 }; 2542 2543 static const struct coex_rf_para rf_para_rx_8822c[] = { 2544 {0, 0, false, 7}, /* for normal */ 2545 {0, 16, false, 7}, /* for WL-CPT */ 2546 {3, 24, true, 5}, 2547 {2, 26, true, 5}, 2548 {1, 27, true, 5}, 2549 {0, 28, true, 5} 2550 }; 2551 2552 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 2553 2554 struct rtw_chip_info rtw8822c_hw_spec = { 2555 .ops = &rtw8822c_ops, 2556 .id = RTW_CHIP_TYPE_8822C, 2557 .fw_name = "rtw88/rtw8822c_fw.bin", 2558 .tx_pkt_desc_sz = 48, 2559 .tx_buf_desc_sz = 16, 2560 .rx_pkt_desc_sz = 24, 2561 .rx_buf_desc_sz = 8, 2562 .phy_efuse_size = 512, 2563 .log_efuse_size = 768, 2564 .ptct_efuse_size = 124, 2565 .txff_size = 262144, 2566 .rxff_size = 24576, 2567 .txgi_factor = 2, 2568 .is_pwr_by_rate_dec = false, 2569 .max_power_index = 0x7f, 2570 .csi_buf_pg_num = 50, 2571 .band = RTW_BAND_2G | RTW_BAND_5G, 2572 .page_size = 128, 2573 .dig_min = 0x20, 2574 .ht_supported = true, 2575 .vht_supported = true, 2576 .sys_func_en = 0xD8, 2577 .pwr_on_seq = card_enable_flow_8822c, 2578 .pwr_off_seq = card_disable_flow_8822c, 2579 .page_table = page_table_8822c, 2580 .rqpn_table = rqpn_table_8822c, 2581 .intf_table = &phy_para_table_8822c, 2582 .dig = rtw8822c_dig, 2583 .rf_base_addr = {0x3c00, 0x4c00}, 2584 .rf_sipi_addr = {0x1808, 0x4108}, 2585 .mac_tbl = &rtw8822c_mac_tbl, 2586 .agc_tbl = &rtw8822c_agc_tbl, 2587 .bb_tbl = &rtw8822c_bb_tbl, 2588 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 2589 .rf_tbl = {&rtw8822c_rf_a_tbl, &rtw8822c_rf_b_tbl}, 2590 .rfe_defs = rtw8822c_rfe_defs, 2591 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 2592 2593 .coex_para_ver = 0x19062706, 2594 .bt_desired_ver = 0x6, 2595 .scbd_support = true, 2596 .new_scbd10_def = true, 2597 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2598 .bt_rssi_type = COEX_BTRSSI_DBM, 2599 .ant_isolation = 15, 2600 .rssi_tolerance = 2, 2601 .wl_rssi_step = wl_rssi_step_8822c, 2602 .bt_rssi_step = bt_rssi_step_8822c, 2603 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 2604 .table_sant = table_sant_8822c, 2605 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 2606 .table_nsant = table_nsant_8822c, 2607 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 2608 .tdma_sant = tdma_sant_8822c, 2609 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 2610 .tdma_nsant = tdma_nsant_8822c, 2611 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 2612 .wl_rf_para_tx = rf_para_tx_8822c, 2613 .wl_rf_para_rx = rf_para_rx_8822c, 2614 .bt_afh_span_bw20 = 0x24, 2615 .bt_afh_span_bw40 = 0x36, 2616 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 2617 .afh_5g = afh_5g_8822c, 2618 }; 2619 EXPORT_SYMBOL(rtw8822c_hw_spec); 2620 2621 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 2622