1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822c.h" 13 #include "rtw8822c_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "util.h" 18 #include "bf.h" 19 #include "efuse.h" 20 21 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 22 u8 rx_path, bool is_tx2_path); 23 24 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 25 struct rtw8822c_efuse *map) 26 { 27 ether_addr_copy(efuse->addr, map->e.mac_addr); 28 } 29 30 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 31 { 32 struct rtw_efuse *efuse = &rtwdev->efuse; 33 struct rtw8822c_efuse *map; 34 int i; 35 36 map = (struct rtw8822c_efuse *)log_map; 37 38 efuse->rfe_option = map->rfe_option; 39 efuse->rf_board_option = map->rf_board_option; 40 efuse->crystal_cap = map->xtal_k; 41 efuse->channel_plan = map->channel_plan; 42 efuse->country_code[0] = map->country_code[0]; 43 efuse->country_code[1] = map->country_code[1]; 44 efuse->bt_setting = map->rf_bt_setting; 45 efuse->regd = map->rf_board_option & 0x7; 46 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 47 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 48 efuse->thermal_meter_k = 49 (map->path_a_thermal + map->path_b_thermal) >> 1; 50 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 51 52 for (i = 0; i < 4; i++) 53 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 54 55 switch (rtw_hci_type(rtwdev)) { 56 case RTW_HCI_TYPE_PCIE: 57 rtw8822ce_efuse_parsing(efuse, map); 58 break; 59 default: 60 /* unsupported now */ 61 return -ENOTSUPP; 62 } 63 64 return 0; 65 } 66 67 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 68 { 69 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 70 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 71 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 72 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 73 74 if (pre) 75 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 76 else 77 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 78 } 79 80 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 81 struct rtw_backup_info *backup, 82 struct rtw_backup_info *backup_rf) 83 { 84 u32 path, i; 85 u32 val; 86 u32 reg; 87 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 88 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 89 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 90 0x1a00, 0x1a14, 0x1d58, 0x1c38, 91 0x1e24, 0x1e28, 0x1860, 0x4160}; 92 93 for (i = 0; i < DACK_REG_8822C; i++) { 94 backup[i].len = 4; 95 backup[i].reg = addrs[i]; 96 backup[i].val = rtw_read32(rtwdev, addrs[i]); 97 } 98 99 for (path = 0; path < DACK_PATH_8822C; path++) { 100 for (i = 0; i < DACK_RF_8822C; i++) { 101 reg = rf_addr[i]; 102 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 103 backup_rf[path * i + i].reg = reg; 104 backup_rf[path * i + i].val = val; 105 } 106 } 107 } 108 109 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 110 struct rtw_backup_info *backup, 111 struct rtw_backup_info *backup_rf) 112 { 113 u32 path, i; 114 u32 val; 115 u32 reg; 116 117 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 118 119 for (path = 0; path < DACK_PATH_8822C; path++) { 120 for (i = 0; i < DACK_RF_8822C; i++) { 121 val = backup_rf[path * i + i].val; 122 reg = backup_rf[path * i + i].reg; 123 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 124 } 125 } 126 } 127 128 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 129 u32 *min, u32 *max) 130 { 131 if (value >= 0x200) { 132 if (*min >= 0x200) { 133 if (*min > value) 134 *min = value; 135 } else { 136 *min = value; 137 } 138 if (*max >= 0x200) { 139 if (*max < value) 140 *max = value; 141 } 142 } else { 143 if (*min < 0x200) { 144 if (*min > value) 145 *min = value; 146 } 147 148 if (*max >= 0x200) { 149 *max = value; 150 } else { 151 if (*max < value) 152 *max = value; 153 } 154 } 155 } 156 157 static void swap_u32(u32 *v1, u32 *v2) 158 { 159 u32 tmp; 160 161 tmp = *v1; 162 *v1 = *v2; 163 *v2 = tmp; 164 } 165 166 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 167 { 168 if (*v1 >= 0x200 && *v2 >= 0x200) { 169 if (*v1 > *v2) 170 swap_u32(v1, v2); 171 } else if (*v1 < 0x200 && *v2 < 0x200) { 172 if (*v1 > *v2) 173 swap_u32(v1, v2); 174 } else if (*v1 < 0x200 && *v2 >= 0x200) { 175 swap_u32(v1, v2); 176 } 177 } 178 179 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 180 { 181 u32 i, j; 182 183 for (i = 0; i < DACK_SN_8822C - 1; i++) { 184 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 185 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 186 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 187 } 188 } 189 } 190 191 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 192 { 193 u32 p, m, t, i; 194 195 m = 0; 196 p = 0; 197 for (i = 10; i < DACK_SN_8822C - 10; i++) { 198 if (vec[i] > 0x200) 199 m = (0x400 - vec[i]) + m; 200 else 201 p = vec[i] + p; 202 } 203 204 if (p > m) { 205 t = p - m; 206 t = t / (DACK_SN_8822C - 20); 207 } else { 208 t = m - p; 209 t = t / (DACK_SN_8822C - 20); 210 if (t != 0x0) 211 t = 0x400 - t; 212 } 213 214 *val = t; 215 } 216 217 static u32 rtw8822c_get_path_write_addr(u8 path) 218 { 219 u32 base_addr; 220 221 switch (path) { 222 case RF_PATH_A: 223 base_addr = 0x1800; 224 break; 225 case RF_PATH_B: 226 base_addr = 0x4100; 227 break; 228 default: 229 WARN_ON(1); 230 return -1; 231 } 232 233 return base_addr; 234 } 235 236 static u32 rtw8822c_get_path_read_addr(u8 path) 237 { 238 u32 base_addr; 239 240 switch (path) { 241 case RF_PATH_A: 242 base_addr = 0x2800; 243 break; 244 case RF_PATH_B: 245 base_addr = 0x4500; 246 break; 247 default: 248 WARN_ON(1); 249 return -1; 250 } 251 252 return base_addr; 253 } 254 255 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 256 { 257 bool ret = true; 258 259 if ((value >= 0x200 && (0x400 - value) > 0x64) || 260 (value < 0x200 && value > 0x64)) { 261 ret = false; 262 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 263 } 264 265 return ret; 266 } 267 268 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 269 { 270 u32 temp; 271 int i = 0, cnt = 0; 272 273 while (i < DACK_SN_8822C && cnt < 10000) { 274 cnt++; 275 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 276 iv[i] = (temp & 0x3ff000) >> 12; 277 qv[i] = temp & 0x3ff; 278 279 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 280 rtw8822c_dac_iq_check(rtwdev, qv[i])) 281 i++; 282 } 283 } 284 285 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 286 u32 *iv, u32 *qv, 287 u32 *i_value, u32 *q_value) 288 { 289 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 290 u32 i_delta, q_delta; 291 u32 temp; 292 int i, cnt = 0; 293 294 do { 295 i_min = iv[0]; 296 i_max = iv[0]; 297 q_min = qv[0]; 298 q_max = qv[0]; 299 for (i = 0; i < DACK_SN_8822C; i++) { 300 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 301 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 302 } 303 304 if (i_max < 0x200 && i_min < 0x200) 305 i_delta = i_max - i_min; 306 else if (i_max >= 0x200 && i_min >= 0x200) 307 i_delta = i_max - i_min; 308 else 309 i_delta = i_max + (0x400 - i_min); 310 311 if (q_max < 0x200 && q_min < 0x200) 312 q_delta = q_max - q_min; 313 else if (q_max >= 0x200 && q_min >= 0x200) 314 q_delta = q_max - q_min; 315 else 316 q_delta = q_max + (0x400 - q_min); 317 318 rtw_dbg(rtwdev, RTW_DBG_RFK, 319 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 320 i_min, i_max, i_delta); 321 rtw_dbg(rtwdev, RTW_DBG_RFK, 322 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 323 q_min, q_max, q_delta); 324 325 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 326 327 if (i_delta > 5 || q_delta > 5) { 328 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 329 iv[0] = (temp & 0x3ff000) >> 12; 330 qv[0] = temp & 0x3ff; 331 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 332 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 333 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 334 } else { 335 break; 336 } 337 } while (cnt++ < 100); 338 339 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 340 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 341 } 342 343 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 344 u32 *i_value, u32 *q_value) 345 { 346 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 347 u32 rf_a, rf_b; 348 349 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 350 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 351 352 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 353 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 354 355 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 356 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 357 } 358 359 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 360 { 361 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 362 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 363 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 364 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 365 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 366 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 367 rtw_write32(rtwdev, 0x1b00, 0x00000008); 368 rtw_write8(rtwdev, 0x1bcc, 0x3f); 369 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 370 rtw_write8(rtwdev, 0x1bcc, 0x3f); 371 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 372 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 373 } 374 375 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 376 u8 path, u32 *adc_ic, u32 *adc_qc) 377 { 378 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 379 u32 ic = 0, qc = 0, temp = 0; 380 u32 base_addr; 381 u32 path_sel; 382 int i; 383 384 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 385 386 base_addr = rtw8822c_get_path_write_addr(path); 387 switch (path) { 388 case RF_PATH_A: 389 path_sel = 0xa0000; 390 break; 391 case RF_PATH_B: 392 path_sel = 0x80000; 393 break; 394 default: 395 WARN_ON(1); 396 return; 397 } 398 399 /* ADCK step1 */ 400 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 401 if (path == RF_PATH_B) 402 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 403 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 404 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 405 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 406 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 407 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 408 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 409 for (i = 0; i < 10; i++) { 410 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 411 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 412 rtw_write32(rtwdev, 0x1c24, 0x00010002); 413 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 414 rtw_dbg(rtwdev, RTW_DBG_RFK, 415 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 416 417 /* compensation value */ 418 if (ic != 0x0) { 419 ic = 0x400 - ic; 420 *adc_ic = ic; 421 } 422 if (qc != 0x0) { 423 qc = 0x400 - qc; 424 *adc_qc = qc; 425 } 426 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 427 rtw_write32(rtwdev, base_addr + 0x68, temp); 428 dm_info->dack_adck[path] = temp; 429 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 430 base_addr + 0x68, temp); 431 /* check ADC DC offset */ 432 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 433 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 434 rtw_dbg(rtwdev, RTW_DBG_RFK, 435 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 436 if (ic >= 0x200) 437 ic = 0x400 - ic; 438 if (qc >= 0x200) 439 qc = 0x400 - qc; 440 if (ic < 5 && qc < 5) 441 break; 442 } 443 444 /* ADCK step2 */ 445 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 446 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 447 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 448 449 /* release pull low switch on IQ path */ 450 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 451 } 452 453 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 454 { 455 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 456 u32 base_addr; 457 u32 read_addr; 458 459 base_addr = rtw8822c_get_path_write_addr(path); 460 read_addr = rtw8822c_get_path_read_addr(path); 461 462 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 463 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 464 if (path == RF_PATH_A) { 465 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 466 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 467 } 468 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 469 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 470 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 471 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 472 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 473 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 474 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 475 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 476 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 477 mdelay(2); 478 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 479 mdelay(2); 480 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 481 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 482 mdelay(1); 483 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 484 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 485 mdelay(20); 486 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 487 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 488 rtw_err(rtwdev, "failed to wait for dack ready\n"); 489 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 490 mdelay(1); 491 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 492 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 493 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 494 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 495 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 496 } 497 498 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 499 u8 path, u32 *ic_out, u32 *qc_out) 500 { 501 u32 base_addr; 502 u32 ic, qc, ic_in, qc_in; 503 504 base_addr = rtw8822c_get_path_write_addr(path); 505 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 506 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 507 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 508 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 509 510 rtw_write32(rtwdev, 0x1b00, 0x00000008); 511 rtw_write8(rtwdev, 0x1bcc, 0x03f); 512 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 513 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 514 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 515 516 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 517 ic = ic_in; 518 qc = qc_in; 519 520 /* compensation value */ 521 if (ic != 0x0) 522 ic = 0x400 - ic; 523 if (qc != 0x0) 524 qc = 0x400 - qc; 525 if (ic < 0x300) { 526 ic = ic * 2 * 6 / 5; 527 ic = ic + 0x80; 528 } else { 529 ic = (0x400 - ic) * 2 * 6 / 5; 530 ic = 0x7f - ic; 531 } 532 if (qc < 0x300) { 533 qc = qc * 2 * 6 / 5; 534 qc = qc + 0x80; 535 } else { 536 qc = (0x400 - qc) * 2 * 6 / 5; 537 qc = 0x7f - qc; 538 } 539 540 *ic_out = ic; 541 *qc_out = qc; 542 543 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 544 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 545 } 546 547 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 548 u32 adc_ic, u32 adc_qc, 549 u32 *ic_in, u32 *qc_in, 550 u32 *i_out, u32 *q_out) 551 { 552 u32 base_addr; 553 u32 read_addr; 554 u32 ic, qc; 555 u32 temp; 556 557 base_addr = rtw8822c_get_path_write_addr(path); 558 read_addr = rtw8822c_get_path_read_addr(path); 559 ic = *ic_in; 560 qc = *qc_in; 561 562 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 563 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 564 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 565 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 566 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 567 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 568 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 569 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 570 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 571 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 572 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 573 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 574 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 575 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 576 mdelay(2); 577 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 578 mdelay(2); 579 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 580 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 581 mdelay(1); 582 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 583 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 584 mdelay(20); 585 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 586 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 587 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 588 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 589 mdelay(1); 590 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 591 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 592 593 /* check DAC DC offset */ 594 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 595 rtw_write32(rtwdev, base_addr + 0x68, temp); 596 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 597 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 598 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 599 if (ic >= 0x10) 600 ic = ic - 0x10; 601 else 602 ic = 0x400 - (0x10 - ic); 603 604 if (qc >= 0x10) 605 qc = qc - 0x10; 606 else 607 qc = 0x400 - (0x10 - qc); 608 609 *i_out = ic; 610 *q_out = qc; 611 612 if (ic >= 0x200) 613 ic = 0x400 - ic; 614 if (qc >= 0x200) 615 qc = 0x400 - qc; 616 617 *ic_in = ic; 618 *qc_in = qc; 619 620 rtw_dbg(rtwdev, RTW_DBG_RFK, 621 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 622 } 623 624 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 625 { 626 u32 base_addr = rtw8822c_get_path_write_addr(path); 627 628 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 629 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 630 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 631 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 632 } 633 634 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 635 u8 path, u8 vec, u32 w_addr, u32 r_addr) 636 { 637 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 638 u16 val; 639 u32 i; 640 641 if (WARN_ON(vec >= 2)) 642 return; 643 644 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 645 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 646 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 647 dm_info->dack_msbk[path][vec][i] = val; 648 } 649 } 650 651 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 652 { 653 u32 w_off = 0x1c; 654 u32 r_off = 0x2c; 655 u32 w_addr, r_addr; 656 657 if (WARN_ON(path >= 2)) 658 return; 659 660 /* backup I vector */ 661 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 662 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 663 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 664 665 /* backup Q vector */ 666 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 667 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 668 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 669 } 670 671 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 672 { 673 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 674 u8 val; 675 676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 677 dm_info->dack_dck[RF_PATH_A][0][0] = val; 678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 679 dm_info->dack_dck[RF_PATH_A][0][1] = val; 680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 681 dm_info->dack_dck[RF_PATH_A][1][0] = val; 682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 683 dm_info->dack_dck[RF_PATH_A][1][1] = val; 684 685 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 686 dm_info->dack_dck[RF_PATH_B][0][0] = val; 687 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 688 dm_info->dack_dck[RF_PATH_B][1][0] = val; 689 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 690 dm_info->dack_dck[RF_PATH_B][0][1] = val; 691 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 692 dm_info->dack_dck[RF_PATH_B][1][1] = val; 693 } 694 695 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 696 { 697 u32 temp[3]; 698 699 temp[0] = rtw_read32(rtwdev, 0x1860); 700 temp[1] = rtw_read32(rtwdev, 0x4160); 701 temp[2] = rtw_read32(rtwdev, 0x9b4); 702 703 /* set clock */ 704 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 705 706 /* backup path-A I/Q */ 707 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 708 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 709 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 710 711 /* backup path-B I/Q */ 712 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 713 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 714 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 715 716 rtw8822c_dac_cal_backup_dck(rtwdev); 717 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 718 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 719 720 rtw_write32(rtwdev, 0x1860, temp[0]); 721 rtw_write32(rtwdev, 0x4160, temp[1]); 722 rtw_write32(rtwdev, 0x9b4, temp[2]); 723 } 724 725 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 726 { 727 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 728 u8 val; 729 730 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 731 val = dm_info->dack_dck[RF_PATH_A][0][0]; 732 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 733 val = dm_info->dack_dck[RF_PATH_A][0][1]; 734 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 735 736 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 737 val = dm_info->dack_dck[RF_PATH_A][1][0]; 738 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 739 val = dm_info->dack_dck[RF_PATH_A][1][1]; 740 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 741 742 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 743 val = dm_info->dack_dck[RF_PATH_B][0][0]; 744 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 745 val = dm_info->dack_dck[RF_PATH_B][0][1]; 746 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 747 748 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 749 val = dm_info->dack_dck[RF_PATH_B][1][0]; 750 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 751 val = dm_info->dack_dck[RF_PATH_B][1][1]; 752 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 753 } 754 755 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 756 { 757 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 758 759 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 760 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 761 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 762 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 763 764 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 765 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 766 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 767 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 768 769 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 770 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 771 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 772 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 773 774 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 775 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 776 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 777 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 778 779 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 780 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 781 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 782 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 783 784 rtw8822c_dac_cal_restore_dck(rtwdev); 785 786 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 787 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 788 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 789 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 790 791 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 792 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 793 794 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 795 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 796 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 797 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 798 799 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 800 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 801 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 802 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 803 804 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 805 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 806 } 807 808 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 809 u32 target_addr, u32 toggle_addr) 810 { 811 u32 cnt = 0; 812 813 do { 814 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 815 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 816 817 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 818 return true; 819 820 } while (cnt++ < 100); 821 822 return false; 823 } 824 825 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 826 { 827 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 828 u32 w_off = 0x1c; 829 u32 r_off = 0x2c; 830 u32 w_i, r_i, w_q, r_q; 831 u32 value; 832 u32 i; 833 834 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 835 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 836 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 837 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 838 839 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 840 return false; 841 842 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 843 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 844 value = dm_info->dack_msbk[path][0][i]; 845 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 846 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 847 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 848 } 849 850 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 851 852 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 853 return false; 854 855 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 856 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 857 value = dm_info->dack_msbk[path][1][i]; 858 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 859 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 860 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 861 } 862 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 863 864 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 865 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 866 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 867 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 868 869 return true; 870 } 871 872 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 873 { 874 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 875 return false; 876 877 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 878 return false; 879 880 return true; 881 } 882 883 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 884 { 885 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 886 u32 temp[3]; 887 888 /* sample the first element for both path's IQ vector */ 889 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 890 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 891 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 892 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 893 return false; 894 895 temp[0] = rtw_read32(rtwdev, 0x1860); 896 temp[1] = rtw_read32(rtwdev, 0x4160); 897 temp[2] = rtw_read32(rtwdev, 0x9b4); 898 899 rtw8822c_dac_cal_restore_prepare(rtwdev); 900 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 901 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 902 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 903 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 904 return false; 905 906 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 907 rtw_err(rtwdev, "failed to restore dack vectors\n"); 908 return false; 909 } 910 911 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 912 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 913 rtw_write32(rtwdev, 0x1860, temp[0]); 914 rtw_write32(rtwdev, 0x4160, temp[1]); 915 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 916 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 917 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 918 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 919 rtw_write32(rtwdev, 0x9b4, temp[2]); 920 921 return true; 922 } 923 924 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 925 { 926 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 927 struct rtw_backup_info backup[DACK_REG_8822C]; 928 u32 ic = 0, qc = 0, i; 929 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 930 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 931 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 932 933 if (rtw8822c_dac_cal_restore(rtwdev)) 934 return; 935 936 /* not able to restore, do it */ 937 938 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 939 940 rtw8822c_dac_bb_setting(rtwdev); 941 942 /* path-A */ 943 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 944 for (i = 0; i < 10; i++) { 945 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 946 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 947 ic_a = ic; 948 qc_a = qc; 949 950 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 951 &ic, &qc, &i_a, &q_a); 952 953 if (ic < 5 && qc < 5) 954 break; 955 } 956 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 957 958 /* path-B */ 959 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 960 for (i = 0; i < 10; i++) { 961 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 962 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 963 ic_b = ic; 964 qc_b = qc; 965 966 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 967 &ic, &qc, &i_b, &q_b); 968 969 if (ic < 5 && qc < 5) 970 break; 971 } 972 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 973 974 rtw_write32(rtwdev, 0x1b00, 0x00000008); 975 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 976 rtw_write8(rtwdev, 0x1bcc, 0x0); 977 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 978 rtw_write8(rtwdev, 0x1bcc, 0x0); 979 980 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 981 982 /* backup results to restore, saving a lot of time */ 983 rtw8822c_dac_cal_backup(rtwdev); 984 985 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 986 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 987 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 988 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 989 } 990 991 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 992 { 993 u8 x2k_busy; 994 995 mdelay(1); 996 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 997 if (x2k_busy == 1) { 998 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 999 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 1000 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 1001 mdelay(1); 1002 } 1003 } 1004 1005 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8]) 1006 { 1007 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \ 1008 do { \ 1009 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ 1010 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ 1011 bb_gain[_path][_idx]); \ 1012 } while (0) 1013 u8 path; 1014 1015 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1016 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); 1017 RF_SET_POWER_TRIM(path, 0x0, 0); 1018 RF_SET_POWER_TRIM(path, 0x1, 1); 1019 RF_SET_POWER_TRIM(path, 0x2, 2); 1020 RF_SET_POWER_TRIM(path, 0x3, 2); 1021 RF_SET_POWER_TRIM(path, 0x4, 3); 1022 RF_SET_POWER_TRIM(path, 0x5, 4); 1023 RF_SET_POWER_TRIM(path, 0x6, 5); 1024 RF_SET_POWER_TRIM(path, 0x7, 6); 1025 RF_SET_POWER_TRIM(path, 0x8, 7); 1026 RF_SET_POWER_TRIM(path, 0x9, 3); 1027 RF_SET_POWER_TRIM(path, 0xa, 4); 1028 RF_SET_POWER_TRIM(path, 0xb, 5); 1029 RF_SET_POWER_TRIM(path, 0xc, 6); 1030 RF_SET_POWER_TRIM(path, 0xd, 7); 1031 RF_SET_POWER_TRIM(path, 0xe, 7); 1032 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); 1033 } 1034 #undef RF_SET_POWER_TRIM 1035 } 1036 1037 static void rtw8822c_power_trim(struct rtw_dev *rtwdev) 1038 { 1039 u8 pg_pwr = 0xff, i, path, idx; 1040 s8 bb_gain[2][8] = {}; 1041 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB}; 1042 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA, 1043 PPG_5GM2_TXA, PPG_5GH1_TXA}, 1044 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB, 1045 PPG_5GM2_TXB, PPG_5GH1_TXB} }; 1046 bool set = false; 1047 1048 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { 1049 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr); 1050 if (pg_pwr == EFUSE_READ_FAIL) 1051 continue; 1052 set = true; 1053 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr); 1054 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr); 1055 } 1056 1057 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { 1058 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1059 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i], 1060 &pg_pwr); 1061 if (pg_pwr == EFUSE_READ_FAIL) 1062 continue; 1063 set = true; 1064 idx = i + ARRAY_SIZE(rf_efuse_2g); 1065 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr); 1066 } 1067 } 1068 if (set) 1069 rtw8822c_set_power_trim(rtwdev, bb_gain); 1070 1071 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1072 } 1073 1074 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev) 1075 { 1076 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B}; 1077 u8 pg_therm = 0xff, thermal[2] = {0}, path; 1078 1079 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1080 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm); 1081 if (pg_therm == EFUSE_READ_FAIL) 1082 return; 1083 /* Efuse value of BIT(0) shall be move to BIT(3), and the value 1084 * of BIT(1) to BIT(3) should be right shifted 1 bit. 1085 */ 1086 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm); 1087 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); 1088 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); 1089 } 1090 } 1091 1092 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 1093 { 1094 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB}; 1095 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB}; 1096 u8 pg_pa_bias = 0xff, path; 1097 1098 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1099 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path], 1100 &pg_pa_bias); 1101 if (pg_pa_bias == EFUSE_READ_FAIL) 1102 return; 1103 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1104 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias); 1105 } 1106 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1107 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path], 1108 &pg_pa_bias); 1109 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1110 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias); 1111 } 1112 } 1113 1114 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1115 { 1116 rtw8822c_rf_dac_cal(rtwdev); 1117 rtw8822c_rf_x2_check(rtwdev); 1118 rtw8822c_thermal_trim(rtwdev); 1119 rtw8822c_power_trim(rtwdev); 1120 rtw8822c_pa_bias(rtwdev); 1121 } 1122 1123 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1124 { 1125 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1126 u8 path; 1127 1128 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1129 dm_info->delta_power_index[path] = 0; 1130 ewma_thermal_init(&dm_info->avg_thermal[path]); 1131 dm_info->thermal_avg[path] = 0xff; 1132 } 1133 1134 dm_info->pwr_trk_triggered = false; 1135 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1136 } 1137 1138 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1139 { 1140 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1141 struct rtw_hal *hal = &rtwdev->hal; 1142 u8 crystal_cap; 1143 u8 cck_gi_u_bnd_msb = 0; 1144 u8 cck_gi_u_bnd_lsb = 0; 1145 u8 cck_gi_l_bnd_msb = 0; 1146 u8 cck_gi_l_bnd_lsb = 0; 1147 bool is_tx2_path; 1148 1149 /* power on BB/RF domain */ 1150 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1151 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1152 rtw_write8_set(rtwdev, REG_RF_CTRL, 1153 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1154 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1155 1156 /* disable low rate DPD */ 1157 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1158 1159 /* pre init before header files config */ 1160 rtw8822c_header_file_init(rtwdev, true); 1161 1162 rtw_phy_load_tables(rtwdev); 1163 1164 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1165 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1166 crystal_cap | (crystal_cap << 7)); 1167 1168 /* post init after header files config */ 1169 rtw8822c_header_file_init(rtwdev, false); 1170 1171 is_tx2_path = false; 1172 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1173 is_tx2_path); 1174 rtw_phy_init(rtwdev); 1175 1176 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1177 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1178 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1179 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1180 1181 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1182 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1183 1184 rtw8822c_rf_init(rtwdev); 1185 rtw8822c_pwrtrack_init(rtwdev); 1186 1187 rtw_bf_phy_init(rtwdev); 1188 } 1189 1190 #define WLAN_TXQ_RPT_EN 0x1F 1191 #define WLAN_SLOT_TIME 0x09 1192 #define WLAN_PIFS_TIME 0x1C 1193 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1194 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1195 #define WLAN_SIFS_CCK_TRX 0x0A 1196 #define WLAN_SIFS_OFDM_TRX 0x10 1197 #define WLAN_NAV_MAX 0xC8 1198 #define WLAN_RDG_NAV 0x05 1199 #define WLAN_TXOP_NAV 0x1B 1200 #define WLAN_CCK_RX_TSF 0x30 1201 #define WLAN_OFDM_RX_TSF 0x30 1202 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1203 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1204 #define WLAN_DRV_EARLY_INT 0x04 1205 #define WLAN_BCN_CTRL_CLT0 0x10 1206 #define WLAN_BCN_DMA_TIME 0x02 1207 #define WLAN_BCN_MAX_ERR 0xFF 1208 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1209 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1210 #define WLAN_SIFS_CCK_CTX 0x0A 1211 #define WLAN_SIFS_CCK_IRX 0x0A 1212 #define WLAN_SIFS_OFDM_CTX 0x0E 1213 #define WLAN_SIFS_OFDM_IRX 0x0E 1214 #define WLAN_EIFS_DUR_TUNE 0x40 1215 #define WLAN_EDCA_VO_PARAM 0x002FA226 1216 #define WLAN_EDCA_VI_PARAM 0x005EA328 1217 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1218 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1219 1220 #define WLAN_RX_FILTER0 0xFFFFFFFF 1221 #define WLAN_RX_FILTER2 0xFFFF 1222 #define WLAN_RCR_CFG 0xE400220E 1223 #define WLAN_RXPKT_MAX_SZ 12288 1224 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1225 1226 #define WLAN_AMPDU_MAX_TIME 0x70 1227 #define WLAN_RTS_LEN_TH 0xFF 1228 #define WLAN_RTS_TX_TIME_TH 0x08 1229 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1230 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1231 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1232 #define FAST_EDCA_VO_TH 0x06 1233 #define FAST_EDCA_VI_TH 0x06 1234 #define FAST_EDCA_BE_TH 0x06 1235 #define FAST_EDCA_BK_TH 0x06 1236 #define WLAN_BAR_RETRY_LIMIT 0x01 1237 #define WLAN_BAR_ACK_TYPE 0x05 1238 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1239 #define WLAN_RESP_TXRATE 0x84 1240 #define WLAN_ACK_TO 0x21 1241 #define WLAN_ACK_TO_CCK 0x6A 1242 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1243 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1244 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1245 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1246 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1247 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1248 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1249 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1250 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1251 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1252 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1253 #define WLAN_MULTI_ADDR 0xFFFFFFFF 1254 1255 #define WLAN_TX_FUNC_CFG1 0x30 1256 #define WLAN_TX_FUNC_CFG2 0x30 1257 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1258 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1259 #define WLAN_MAC_OPT_FUNC2 0x30810041 1260 #define WLAN_MAC_INT_MIG_CFG 0x33330000 1261 1262 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1263 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1264 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1265 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1266 1267 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1268 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1269 1270 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1271 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1272 1273 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1274 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1275 1276 #define MAC_CLK_SPEED 80 /* 80M */ 1277 #define EFUSE_PCB_INFO_OFFSET 0xCA 1278 1279 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1280 { 1281 u8 value8; 1282 u16 value16; 1283 u32 value32; 1284 u16 pre_txcnt; 1285 1286 /* txq control */ 1287 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1288 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1289 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1290 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1291 /* sifs control */ 1292 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1293 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1294 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1295 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1296 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1297 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1298 /* rate fallback control */ 1299 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 1300 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 1301 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 1302 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 1303 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 1304 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 1305 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 1306 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 1307 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 1308 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 1309 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 1310 /* protocol configuration */ 1311 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 1312 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 1313 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 1314 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 1315 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 1316 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 1317 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 1318 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 1319 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 1320 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 1321 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 1322 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 1323 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 1324 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 1325 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 1326 /* close BA parser */ 1327 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 1328 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 1329 1330 /* EDCA configuration */ 1331 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 1332 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 1333 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 1334 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 1335 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 1336 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 1337 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 1338 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 1339 BIT_DIS_STBC_CFE) >> 8); 1340 1341 /* MAC clock configuration */ 1342 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 1343 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 1344 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 1345 1346 rtw_write8_set(rtwdev, REG_MISC_CTRL, 1347 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 1348 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 1349 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 1350 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 1351 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 1352 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 1353 /* Set beacon cotnrol - enable TSF and other related functions */ 1354 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1355 /* Set send beacon related registers */ 1356 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 1357 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 1358 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 1359 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 1360 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 1361 1362 /* WMAC configuration */ 1363 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 1364 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 1365 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 1366 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 1367 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 1368 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 1369 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 1370 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 1371 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 1372 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 1373 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 1374 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 1375 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 1376 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 1377 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 1378 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 1379 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 1380 1381 /* init low power */ 1382 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 1383 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 1384 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 1385 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 1386 value16 = 0; 1387 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 1388 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 1389 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 1390 | BIT_RXPSF_OFDMRST; 1391 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1392 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 1393 /* rx ignore configuration */ 1394 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 1395 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 1396 BIT_RXPSF_CONT_ERRCHKEN); 1397 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 1398 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1399 1400 /* Interrupt migration configuration */ 1401 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 1402 1403 return 0; 1404 } 1405 1406 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 1407 { 1408 if (enable) { 1409 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 1410 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 1411 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 1412 } else { 1413 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 1414 } 1415 } 1416 1417 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 1418 { 1419 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 1420 #define RF18_BAND_2G (0) 1421 #define RF18_BAND_5G (BIT(16) | BIT(8)) 1422 #define RF18_CHANNEL_MASK (MASKBYTE0) 1423 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 1424 #define RF18_RFSI_GE_CH80 (BIT(17)) 1425 #define RF18_RFSI_GT_CH140 (BIT(18)) 1426 #define RF18_BW_MASK (BIT(13) | BIT(12)) 1427 #define RF18_BW_20M (BIT(13) | BIT(12)) 1428 #define RF18_BW_40M (BIT(13)) 1429 #define RF18_BW_80M (BIT(12)) 1430 1431 u32 rf_reg18 = 0; 1432 u32 rf_rxbb = 0; 1433 1434 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 1435 1436 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 1437 RF18_BW_MASK); 1438 1439 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 1440 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 1441 if (IS_CH_5G_BAND_4(channel)) 1442 rf_reg18 |= RF18_RFSI_GT_CH140; 1443 else if (IS_CH_5G_BAND_3(channel)) 1444 rf_reg18 |= RF18_RFSI_GE_CH80; 1445 1446 switch (bw) { 1447 case RTW_CHANNEL_WIDTH_5: 1448 case RTW_CHANNEL_WIDTH_10: 1449 case RTW_CHANNEL_WIDTH_20: 1450 default: 1451 rf_reg18 |= RF18_BW_20M; 1452 rf_rxbb = 0x18; 1453 break; 1454 case RTW_CHANNEL_WIDTH_40: 1455 /* RF bandwidth */ 1456 rf_reg18 |= RF18_BW_40M; 1457 rf_rxbb = 0x10; 1458 break; 1459 case RTW_CHANNEL_WIDTH_80: 1460 rf_reg18 |= RF18_BW_80M; 1461 rf_rxbb = 0x8; 1462 break; 1463 } 1464 1465 rtw8822c_rstb_3wire(rtwdev, false); 1466 1467 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 1468 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 1469 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 1470 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 1471 1472 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 1473 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 1474 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 1475 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 1476 1477 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 1478 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 1479 1480 rtw8822c_rstb_3wire(rtwdev, true); 1481 } 1482 1483 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 1484 { 1485 u32 igi; 1486 1487 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 1488 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 1489 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 1490 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 1491 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 1492 } 1493 1494 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1495 u8 primary_ch_idx) 1496 { 1497 if (IS_CH_2G_BAND(channel)) { 1498 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1499 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 1500 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1501 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1502 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 1503 1504 switch (bw) { 1505 case RTW_CHANNEL_WIDTH_20: 1506 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1507 0x5); 1508 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1509 0x5); 1510 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1511 0x6); 1512 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1513 0x6); 1514 break; 1515 case RTW_CHANNEL_WIDTH_40: 1516 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1517 0x4); 1518 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1519 0x4); 1520 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1521 0x0); 1522 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1523 0x0); 1524 break; 1525 } 1526 if (channel == 13 || channel == 14) 1527 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 1528 else if (channel == 11 || channel == 12) 1529 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 1530 else 1531 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 1532 if (channel == 14) { 1533 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 1534 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1535 0x4962c931); 1536 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 1537 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 1538 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 1539 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 1540 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1541 0xff012455); 1542 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 1543 } else { 1544 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 1545 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1546 0x3e18fec8); 1547 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 1548 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 1549 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 1550 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 1551 0x00faf0de); 1552 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1553 0x00122344); 1554 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 1555 0x0fffffff); 1556 } 1557 if (channel == 13) 1558 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1559 else 1560 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 1561 } else if (IS_CH_5G_BAND(channel)) { 1562 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1563 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1564 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1565 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 1566 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 1567 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1568 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 1569 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1570 0x1); 1571 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1572 0x1); 1573 } else if (IS_CH_5G_BAND_3(channel)) { 1574 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1575 0x2); 1576 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1577 0x2); 1578 } else if (IS_CH_5G_BAND_4(channel)) { 1579 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1580 0x3); 1581 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1582 0x3); 1583 } 1584 1585 if (channel >= 36 && channel <= 51) 1586 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 1587 else if (channel >= 52 && channel <= 55) 1588 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 1589 else if (channel >= 56 && channel <= 111) 1590 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 1591 else if (channel >= 112 && channel <= 119) 1592 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 1593 else if (channel >= 120 && channel <= 172) 1594 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 1595 else if (channel >= 173 && channel <= 177) 1596 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 1597 } 1598 1599 switch (bw) { 1600 case RTW_CHANNEL_WIDTH_20: 1601 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 1602 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1603 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 1604 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 1605 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 1606 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1607 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1608 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1609 break; 1610 case RTW_CHANNEL_WIDTH_40: 1611 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 1612 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 1613 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 1614 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1615 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1616 (primary_ch_idx | (primary_ch_idx << 4))); 1617 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 1618 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1619 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1620 break; 1621 case RTW_CHANNEL_WIDTH_80: 1622 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 1623 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1624 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1625 (primary_ch_idx | (primary_ch_idx << 4))); 1626 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 1627 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1628 break; 1629 case RTW_CHANNEL_WIDTH_5: 1630 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1631 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1632 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 1633 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 1634 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 1635 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1636 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1637 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1638 break; 1639 case RTW_CHANNEL_WIDTH_10: 1640 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1641 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1642 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 1643 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 1644 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 1645 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1646 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1647 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1648 break; 1649 } 1650 } 1651 1652 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1653 u8 primary_chan_idx) 1654 { 1655 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 1656 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 1657 rtw8822c_set_channel_rf(rtwdev, channel, bw); 1658 rtw8822c_toggle_igi(rtwdev); 1659 } 1660 1661 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1662 { 1663 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1664 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 1665 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 1666 } else if (rx_path == BB_PATH_AB) { 1667 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 1668 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 1669 } 1670 1671 if (rx_path == BB_PATH_A) 1672 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 1673 else if (rx_path == BB_PATH_B) 1674 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 1675 else if (rx_path == BB_PATH_AB) 1676 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 1677 } 1678 1679 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1680 { 1681 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1682 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 1683 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 1684 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 1685 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 1686 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 1687 } else if (rx_path == BB_PATH_AB) { 1688 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 1689 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 1690 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 1691 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 1692 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 1693 } 1694 1695 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 1696 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 1697 } 1698 1699 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1700 { 1701 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 1702 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 1703 } 1704 1705 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1706 bool is_tx2_path) 1707 { 1708 if (tx_path == BB_PATH_A) { 1709 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1710 } else if (tx_path == BB_PATH_B) { 1711 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 1712 } else { 1713 if (is_tx2_path) 1714 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 1715 else 1716 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1717 } 1718 } 1719 1720 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1721 bool is_tx2_path) 1722 { 1723 if (tx_path == BB_PATH_A) { 1724 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 1725 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1726 } else if (tx_path == BB_PATH_B) { 1727 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 1728 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1729 } else { 1730 if (is_tx2_path) { 1731 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 1732 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 1733 } else { 1734 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 1735 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 1736 } 1737 } 1738 } 1739 1740 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1741 bool is_tx2_path) 1742 { 1743 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 1744 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 1745 } 1746 1747 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 1748 u8 rx_path, bool is_tx2_path) 1749 { 1750 if ((tx_path | rx_path) & BB_PATH_A) 1751 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 1752 else 1753 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 1754 if ((tx_path | rx_path) & BB_PATH_B) 1755 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 1756 else 1757 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 1758 1759 rtw8822c_config_rx_path(rtwdev, rx_path); 1760 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 1761 1762 rtw8822c_toggle_igi(rtwdev); 1763 } 1764 1765 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 1766 struct rtw_rx_pkt_stat *pkt_stat) 1767 { 1768 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1769 u8 l_bnd, u_bnd; 1770 u8 gain_a, gain_b; 1771 s8 rx_power[RTW_RF_PATH_MAX]; 1772 s8 min_rx_power = -120; 1773 u8 rssi; 1774 int path; 1775 1776 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 1777 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 1778 l_bnd = dm_info->cck_gi_l_bnd; 1779 u_bnd = dm_info->cck_gi_u_bnd; 1780 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 1781 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 1782 if (gain_a < l_bnd) 1783 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 1784 else if (gain_a > u_bnd) 1785 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 1786 if (gain_b < l_bnd) 1787 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 1788 else if (gain_b > u_bnd) 1789 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 1790 1791 rx_power[RF_PATH_A] -= 110; 1792 rx_power[RF_PATH_B] -= 110; 1793 1794 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 1795 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 1796 1797 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1798 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1799 dm_info->rssi[path] = rssi; 1800 } 1801 1802 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1803 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1804 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 1805 min_rx_power); 1806 } 1807 1808 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 1809 struct rtw_rx_pkt_stat *pkt_stat) 1810 { 1811 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1812 u8 rxsc, bw; 1813 s8 min_rx_power = -120; 1814 s8 rx_evm; 1815 u8 evm_dbm = 0; 1816 u8 rssi; 1817 int path; 1818 1819 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 1820 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 1821 else 1822 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 1823 1824 if (rxsc >= 9 && rxsc <= 12) 1825 bw = RTW_CHANNEL_WIDTH_40; 1826 else if (rxsc >= 13) 1827 bw = RTW_CHANNEL_WIDTH_80; 1828 else 1829 bw = RTW_CHANNEL_WIDTH_20; 1830 1831 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 1832 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 1833 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 1834 pkt_stat->bw = bw; 1835 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 1836 pkt_stat->rx_power[RF_PATH_B], 1837 min_rx_power); 1838 1839 dm_info->curr_rx_rate = pkt_stat->rate; 1840 1841 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 1842 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 1843 1844 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 1845 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 1846 1847 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 1848 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 1849 1850 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1851 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1852 dm_info->rssi[path] = rssi; 1853 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 1854 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 1855 1856 rx_evm = pkt_stat->rx_evm[path]; 1857 1858 if (rx_evm < 0) { 1859 if (rx_evm == S8_MIN) 1860 evm_dbm = 0; 1861 else 1862 evm_dbm = ((u8)-rx_evm >> 1); 1863 } 1864 dm_info->rx_evm_dbm[path] = evm_dbm; 1865 } 1866 } 1867 1868 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1869 struct rtw_rx_pkt_stat *pkt_stat) 1870 { 1871 u8 page; 1872 1873 page = *phy_status & 0xf; 1874 1875 switch (page) { 1876 case 0: 1877 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 1878 break; 1879 case 1: 1880 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 1881 break; 1882 default: 1883 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 1884 return; 1885 } 1886 } 1887 1888 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1889 struct rtw_rx_pkt_stat *pkt_stat, 1890 struct ieee80211_rx_status *rx_status) 1891 { 1892 struct ieee80211_hdr *hdr; 1893 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1894 u8 *phy_status = NULL; 1895 1896 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1897 1898 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1899 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1900 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1901 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 1902 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 1903 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1904 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1905 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1906 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1907 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1908 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1909 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 1910 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1911 1912 /* drv_info_sz is in unit of 8-bytes */ 1913 pkt_stat->drv_info_sz *= 8; 1914 1915 /* c2h cmd pkt's rx/phy status is not interested */ 1916 if (pkt_stat->is_c2h) 1917 return; 1918 1919 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1920 pkt_stat->drv_info_sz); 1921 if (pkt_stat->phy_status) { 1922 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1923 query_phy_status(rtwdev, phy_status, pkt_stat); 1924 } 1925 1926 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1927 } 1928 1929 static void 1930 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 1931 u8 *tx_pwr_ref_ofdm) 1932 { 1933 struct rtw_hal *hal = &rtwdev->hal; 1934 u32 txref_cck[2] = {0x18a0, 0x41a0}; 1935 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 1936 u8 path; 1937 1938 for (path = 0; path < hal->rf_path_num; path++) { 1939 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1940 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 1941 tx_pwr_ref_cck[path]); 1942 } 1943 for (path = 0; path < hal->rf_path_num; path++) { 1944 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1945 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 1946 tx_pwr_ref_ofdm[path]); 1947 } 1948 } 1949 1950 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 1951 s8 *diff_idx) 1952 { 1953 u32 offset_txagc = 0x3a00; 1954 u8 rate_idx = rate & 0xfc; 1955 u8 pwr_idx[4]; 1956 u32 phy_pwr_idx; 1957 int i; 1958 1959 for (i = 0; i < 4; i++) 1960 pwr_idx[i] = diff_idx[i] & 0x7f; 1961 1962 phy_pwr_idx = pwr_idx[0] | 1963 (pwr_idx[1] << 8) | 1964 (pwr_idx[2] << 16) | 1965 (pwr_idx[3] << 24); 1966 1967 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 1968 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 1969 phy_pwr_idx); 1970 } 1971 1972 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 1973 { 1974 struct rtw_hal *hal = &rtwdev->hal; 1975 u8 rs, rate, j; 1976 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 1977 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 1978 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 1979 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 1980 s8 diff_a, diff_b; 1981 u8 pwr_a, pwr_b; 1982 s8 diff_idx[4]; 1983 1984 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 1985 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 1986 for (j = 0; j < rtw_rate_size[rs]; j++) { 1987 rate = rtw_rate_section[rs][j]; 1988 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 1989 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 1990 if (rs == 0) { 1991 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 1992 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 1993 } else { 1994 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 1995 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 1996 } 1997 diff_idx[rate % 4] = min(diff_a, diff_b); 1998 if (rate % 4 == 3) 1999 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 2000 diff_idx); 2001 } 2002 } 2003 } 2004 2005 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev, 2006 u32 antenna_tx, 2007 u32 antenna_rx) 2008 { 2009 struct rtw_hal *hal = &rtwdev->hal; 2010 2011 switch (antenna_tx) { 2012 case BB_PATH_A: 2013 case BB_PATH_B: 2014 case BB_PATH_AB: 2015 break; 2016 default: 2017 rtw_info(rtwdev, "unsupport tx path 0x%x\n", antenna_tx); 2018 return -EINVAL; 2019 } 2020 2021 /* path B only is not available for RX */ 2022 switch (antenna_rx) { 2023 case BB_PATH_A: 2024 case BB_PATH_AB: 2025 break; 2026 default: 2027 rtw_info(rtwdev, "unsupport rx path 0x%x\n", antenna_rx); 2028 return -EINVAL; 2029 } 2030 2031 hal->antenna_tx = antenna_tx; 2032 hal->antenna_rx = antenna_rx; 2033 2034 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 2035 2036 return 0; 2037 } 2038 2039 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 2040 { 2041 u8 ldo_pwr; 2042 2043 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 2044 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 2045 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 2046 } 2047 2048 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 2049 { 2050 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2051 u32 cck_enable; 2052 u32 cck_fa_cnt; 2053 u32 crc32_cnt; 2054 u32 cca32_cnt; 2055 u32 ofdm_fa_cnt; 2056 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 2057 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 2058 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 2059 2060 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 2061 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 2062 2063 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 2064 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 2065 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 2066 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 2067 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 2068 2069 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 2070 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 2071 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 2072 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 2073 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 2074 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 2075 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 2076 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 2077 2078 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 2079 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 2080 2081 dm_info->cck_fa_cnt = cck_fa_cnt; 2082 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 2083 dm_info->total_fa_cnt = ofdm_fa_cnt; 2084 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 2085 2086 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 2087 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 2088 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2089 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 2090 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 2091 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2092 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 2093 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 2094 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2095 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 2096 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 2097 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2098 2099 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 2100 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 2101 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 2102 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 2103 if (cck_enable) 2104 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 2105 2106 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 2107 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 2108 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 2109 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 2110 2111 /* disable rx clk gating to reset counters */ 2112 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2113 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2114 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2115 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2116 } 2117 2118 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 2119 { 2120 struct rtw_iqk_para para = {0}; 2121 u8 iqk_chk; 2122 int counter; 2123 2124 para.clear = 1; 2125 rtw_fw_do_iqk(rtwdev, ¶); 2126 2127 for (counter = 0; counter < 300; counter++) { 2128 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP); 2129 if (iqk_chk == 0xaa) 2130 break; 2131 msleep(20); 2132 } 2133 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 2134 2135 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter); 2136 } 2137 2138 /* for coex */ 2139 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 2140 { 2141 /* enable TBTT nterrupt */ 2142 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2143 2144 /* BT report packet sample rate */ 2145 /* 0x790[5:0]=0x5 */ 2146 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 2147 2148 /* enable BT counter statistics */ 2149 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2150 2151 /* enable PTA (3-wire function form BT side) */ 2152 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2153 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 2154 2155 /* enable PTA (tx/rx signal form WiFi side) */ 2156 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2157 /* wl tx signal to PTA not case EDCCA */ 2158 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2159 /* GNT_BT=1 while select both */ 2160 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2161 /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */ 2162 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2163 2164 /* to avoid RF parameter error */ 2165 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000); 2166 } 2167 2168 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2169 { 2170 struct rtw_coex *coex = &rtwdev->coex; 2171 struct rtw_coex_stat *coex_stat = &coex->stat; 2172 struct rtw_efuse *efuse = &rtwdev->efuse; 2173 u32 rf_0x1; 2174 2175 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2176 return; 2177 2178 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 2179 2180 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 2181 rf_0x1 = 0x40021; 2182 else 2183 rf_0x1 = 0x40000; 2184 2185 /* BT at S1 for Shared-Ant */ 2186 if (efuse->share_ant) 2187 rf_0x1 |= BIT(13); 2188 2189 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 2190 2191 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 2192 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 2193 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 2194 * 2195 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 2196 * disable 0x1c30[22] = 0, 2197 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 2198 * 2199 * disable WL-S1 BB chage RF mode if GNT_BT 2200 * since RF TRx mask can do it 2201 */ 2202 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1); 2203 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0); 2204 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1); 2205 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1); 2206 2207 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 2208 * or antenna path is separated 2209 */ 2210 if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 2211 coex->under_5g || !efuse->share_ant) { 2212 if (coex_stat->kt_ver >= 3) { 2213 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2214 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1); 2215 } else { 2216 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1); 2217 } 2218 } else { 2219 /* shared-antenna */ 2220 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2221 if (coex_stat->kt_ver >= 3) 2222 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0); 2223 } 2224 } 2225 2226 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 2227 { 2228 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0); 2229 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0); 2230 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0); 2231 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0); 2232 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0); 2233 } 2234 2235 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 2236 { 2237 struct rtw_coex *coex = &rtwdev->coex; 2238 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 2239 struct rtw_efuse *efuse = &rtwdev->efuse; 2240 2241 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 2242 coex_rfe->ant_switch_polarity = 0; 2243 coex_rfe->ant_switch_exist = false; 2244 coex_rfe->ant_switch_with_bt = false; 2245 coex_rfe->ant_switch_diversity = false; 2246 2247 if (efuse->share_ant) 2248 coex_rfe->wlg_at_btg = true; 2249 else 2250 coex_rfe->wlg_at_btg = false; 2251 2252 /* disable LTE coex in wifi side */ 2253 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0); 2254 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff); 2255 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff); 2256 } 2257 2258 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 2259 { 2260 struct rtw_coex *coex = &rtwdev->coex; 2261 struct rtw_coex_dm *coex_dm = &coex->dm; 2262 2263 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 2264 return; 2265 2266 coex_dm->cur_wl_pwr_lvl = wl_pwr; 2267 } 2268 2269 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 2270 { 2271 struct rtw_coex *coex = &rtwdev->coex; 2272 struct rtw_coex_dm *coex_dm = &coex->dm; 2273 2274 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 2275 return; 2276 2277 coex_dm->cur_wl_rx_low_gain_en = low_gain; 2278 2279 if (coex_dm->cur_wl_rx_low_gain_en) { 2280 /* set Rx filter corner RCK offset */ 2281 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22); 2282 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36); 2283 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22); 2284 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36); 2285 } else { 2286 /* set Rx filter corner RCK offset */ 2287 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20); 2288 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0); 2289 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0); 2290 } 2291 } 2292 2293 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 2294 struct rtw_vif *vif, 2295 struct rtw_bfee *bfee) 2296 { 2297 u8 csi_rsc = 0; 2298 u32 tmp6dc; 2299 2300 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 2301 2302 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 2303 BIT_WMAC_USE_NDPARATE | 2304 (csi_rsc << 13); 2305 if (vif->net_type == RTW_NET_AP_MODE) 2306 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 2307 else 2308 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 2309 2310 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 2311 } 2312 2313 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 2314 struct rtw_vif *vif, 2315 struct rtw_bfee *bfee, bool enable) 2316 { 2317 if (enable) 2318 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 2319 else 2320 rtw_bf_remove_bfee_su(rtwdev, bfee); 2321 } 2322 2323 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 2324 struct rtw_vif *vif, 2325 struct rtw_bfee *bfee, bool enable) 2326 { 2327 if (enable) 2328 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 2329 else 2330 rtw_bf_remove_bfee_mu(rtwdev, bfee); 2331 } 2332 2333 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 2334 struct rtw_bfee *bfee, bool enable) 2335 { 2336 if (bfee->role == RTW_BFEE_SU) 2337 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 2338 else if (bfee->role == RTW_BFEE_MU) 2339 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 2340 else 2341 rtw_warn(rtwdev, "wrong bfee role\n"); 2342 } 2343 2344 struct dpk_cfg_pair { 2345 u32 addr; 2346 u32 bitmask; 2347 u32 data; 2348 }; 2349 2350 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 2351 const struct rtw_table *tbl) 2352 { 2353 const struct dpk_cfg_pair *p = tbl->data; 2354 const struct dpk_cfg_pair *end = p + tbl->size / 3; 2355 2356 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 2357 2358 for (; p < end; p++) 2359 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 2360 } 2361 2362 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 2363 { 2364 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2365 2366 if (is_before_k) { 2367 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 2368 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 2369 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 2370 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 2371 } else { 2372 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 2373 dpk_info->gnt_value); 2374 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 2375 } 2376 } 2377 2378 static void 2379 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 2380 struct rtw_backup_info *bckp) 2381 { 2382 rtw_restore_reg(rtwdev, bckp, reg_num); 2383 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2384 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 2385 } 2386 2387 static void 2388 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 2389 u32 reg_num, struct rtw_backup_info *bckp) 2390 { 2391 u32 i; 2392 2393 for (i = 0; i < reg_num; i++) { 2394 bckp[i].len = 4; 2395 bckp[i].reg = reg[i]; 2396 bckp[i].val = rtw_read32(rtwdev, reg[i]); 2397 } 2398 } 2399 2400 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 2401 u32 *rf_reg, 2402 u32 rf_reg_bak[][2]) 2403 { 2404 u32 i; 2405 2406 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2407 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 2408 rf_reg[i], RFREG_MASK); 2409 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 2410 rf_reg[i], RFREG_MASK); 2411 } 2412 } 2413 2414 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 2415 u32 *rf_reg, 2416 u32 rf_reg_bak[][2]) 2417 { 2418 u32 i; 2419 2420 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2421 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 2422 rf_reg_bak[i][RF_PATH_A]); 2423 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 2424 rf_reg_bak[i][RF_PATH_B]); 2425 } 2426 } 2427 2428 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 2429 { 2430 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2431 u32 reg; 2432 u8 band_shift; 2433 2434 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2435 2436 band_shift = FIELD_GET(BIT(16), reg); 2437 dpk_info->dpk_band = 1 << band_shift; 2438 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 2439 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 2440 } 2441 2442 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 2443 { 2444 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2445 udelay(5); 2446 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 2447 usleep_range(600, 610); 2448 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2449 } 2450 2451 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 2452 { 2453 u16 dc_i, dc_q; 2454 u8 corr_val, corr_idx; 2455 2456 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 2457 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2458 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 2459 2460 if (dc_i & BIT(11)) 2461 dc_i = 0x1000 - dc_i; 2462 if (dc_q & BIT(11)) 2463 dc_q = 0x1000 - dc_q; 2464 2465 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2466 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 2467 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 2468 2469 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 2470 return 1; 2471 else 2472 return 0; 2473 2474 } 2475 2476 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 2477 { 2478 u8 reg_a, reg_b; 2479 u16 count = 0; 2480 2481 rtw_write8(rtwdev, 0x522, 0xff); 2482 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 2483 2484 do { 2485 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 2486 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 2487 udelay(2); 2488 count++; 2489 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 2490 } 2491 2492 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 2493 { 2494 rtw8822c_dpk_tx_pause(rtwdev); 2495 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 2496 } 2497 2498 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 2499 { 2500 if (is_do_dpk) 2501 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 2502 else 2503 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 2504 } 2505 2506 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 2507 { 2508 u8 path; 2509 2510 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 2511 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 2512 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2513 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 2514 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 2515 else 2516 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 2517 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 2518 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 2519 } 2520 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2521 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 2522 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 2523 } 2524 2525 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 2526 { 2527 u32 ori_txbb; 2528 2529 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 2530 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 2531 2532 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 2533 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 2534 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0); 2535 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 2536 2537 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 2538 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1); 2539 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 2540 } else { 2541 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 2542 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 2543 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 2544 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 2545 } 2546 2547 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2548 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 2549 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 2550 2551 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 2552 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 2553 else 2554 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 2555 2556 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 2557 2558 usleep_range(100, 110); 2559 2560 return ori_txbb & 0x1f; 2561 } 2562 2563 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 2564 { 2565 u16 cmd; 2566 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 2567 2568 switch (action) { 2569 case RTW_DPK_GAIN_LOSS: 2570 cmd = 0x14 + path; 2571 break; 2572 case RTW_DPK_DO_DPK: 2573 cmd = 0x16 + path + bw; 2574 break; 2575 case RTW_DPK_DPK_ON: 2576 cmd = 0x1a + path; 2577 break; 2578 case RTW_DPK_DAGC: 2579 cmd = 0x1c + path + bw; 2580 break; 2581 default: 2582 return 0; 2583 } 2584 2585 return (cmd << 8) | 0x48; 2586 } 2587 2588 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 2589 { 2590 u16 dpk_cmd; 2591 u8 result = 0; 2592 2593 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 2594 2595 if (action == RTW_DPK_CAL_PWR) { 2596 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 2597 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 2598 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 2599 msleep(10); 2600 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 2601 result = 1; 2602 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2603 } 2604 } else { 2605 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2606 0x8 | (path << 1)); 2607 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 2608 2609 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 2610 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 2611 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 2612 msleep(10); 2613 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 2614 result = 1; 2615 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2616 } 2617 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2618 0x8 | (path << 1)); 2619 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 2620 } 2621 2622 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 2623 2624 rtw_write8(rtwdev, 0x1b10, 0x0); 2625 2626 return result; 2627 } 2628 2629 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 2630 { 2631 u16 dgain; 2632 2633 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2634 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 2635 2636 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2637 2638 return dgain; 2639 } 2640 2641 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 2642 { 2643 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2644 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 2645 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2646 udelay(15); 2647 2648 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 2649 } 2650 2651 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 2652 { 2653 u32 i_val, q_val; 2654 2655 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2656 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2657 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 2658 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2659 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 2660 2661 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 2662 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 2663 2664 if (i_val & BIT(15)) 2665 i_val = 0x10000 - i_val; 2666 if (q_val & BIT(15)) 2667 q_val = 0x10000 - q_val; 2668 2669 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2670 2671 return i_val * i_val + q_val * q_val; 2672 } 2673 2674 static u32 rtw8822c_psd_log2base(u32 val) 2675 { 2676 u32 tmp, val_integerd_b, tindex; 2677 u32 result, val_fractiond_b; 2678 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 2679 151, 132, 115, 100, 86, 74, 62, 51, 2680 42, 32, 23, 15, 7, 0}; 2681 2682 if (val == 0) 2683 return 0; 2684 2685 val_integerd_b = __fls(val) + 1; 2686 2687 tmp = (val * 100) / (1 << val_integerd_b); 2688 tindex = tmp / 5; 2689 2690 if (tindex >= ARRAY_SIZE(table_fraction)) 2691 tindex = ARRAY_SIZE(table_fraction) - 1; 2692 2693 val_fractiond_b = table_fraction[tindex]; 2694 2695 result = val_integerd_b * 100 - val_fractiond_b; 2696 2697 return result; 2698 } 2699 2700 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 2701 { 2702 u8 result; 2703 2704 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2705 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 2706 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 2707 2708 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 2709 2710 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2711 2712 return result; 2713 } 2714 2715 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 2716 u8 limited_pga) 2717 { 2718 u8 result = 0; 2719 u16 dgain; 2720 2721 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 2722 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 2723 2724 if (dgain > 1535 && !limited_pga) 2725 return RTW_DPK_GAIN_LESS; 2726 else if (dgain < 768 && !limited_pga) 2727 return RTW_DPK_GAIN_LARGE; 2728 else 2729 return result; 2730 } 2731 2732 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 2733 { 2734 u32 loss, loss_db; 2735 2736 loss = rtw8822c_dpk_pas_read(rtwdev, path); 2737 if (loss < 0x4000000) 2738 return RTW_DPK_GL_LESS; 2739 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 2740 2741 if (loss_db > 1000) 2742 return RTW_DPK_GL_LARGE; 2743 else if (loss_db < 250) 2744 return RTW_DPK_GL_LESS; 2745 else 2746 return RTW_DPK_AGC_OUT; 2747 } 2748 2749 struct rtw8822c_dpk_data { 2750 u8 txbb; 2751 u8 pga; 2752 u8 limited_pga; 2753 u8 agc_cnt; 2754 bool loss_only; 2755 bool gain_only; 2756 u8 path; 2757 }; 2758 2759 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 2760 struct rtw8822c_dpk_data *data) 2761 { 2762 u8 state; 2763 2764 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 2765 BIT_GAIN_TXBB); 2766 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 2767 BIT_RXAGC); 2768 2769 if (data->loss_only) { 2770 state = RTW_DPK_LOSS_CHECK; 2771 goto check_end; 2772 } 2773 2774 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 2775 data->limited_pga); 2776 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 2777 state = RTW_DPK_AGC_OUT; 2778 else if (state == RTW_DPK_GAIN_CHECK) 2779 state = RTW_DPK_LOSS_CHECK; 2780 2781 check_end: 2782 data->agc_cnt++; 2783 if (data->agc_cnt >= 6) 2784 state = RTW_DPK_AGC_OUT; 2785 2786 return state; 2787 } 2788 2789 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 2790 struct rtw8822c_dpk_data *data) 2791 { 2792 u8 pga = data->pga; 2793 2794 if (pga > 0xe) 2795 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2796 else if (pga > 0xb && pga < 0xf) 2797 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 2798 else if (pga < 0xc) 2799 data->limited_pga = 1; 2800 2801 return RTW_DPK_GAIN_CHECK; 2802 } 2803 2804 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 2805 struct rtw8822c_dpk_data *data) 2806 { 2807 u8 pga = data->pga; 2808 2809 if (pga < 0xc) 2810 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2811 else if (pga > 0xb && pga < 0xf) 2812 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2813 else if (pga > 0xe) 2814 data->limited_pga = 1; 2815 2816 return RTW_DPK_GAIN_CHECK; 2817 } 2818 2819 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 2820 struct rtw8822c_dpk_data *data, u8 is_large) 2821 { 2822 u8 txbb_bound[] = {0x1f, 0}; 2823 2824 if (data->txbb == txbb_bound[is_large]) 2825 return RTW_DPK_AGC_OUT; 2826 2827 if (is_large == 1) 2828 data->txbb -= 2; 2829 else 2830 data->txbb += 3; 2831 2832 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 2833 data->limited_pga = 0; 2834 2835 return RTW_DPK_GAIN_CHECK; 2836 } 2837 2838 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 2839 struct rtw8822c_dpk_data *data) 2840 { 2841 return rtw8822c_gl_state(rtwdev, data, 1); 2842 } 2843 2844 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 2845 struct rtw8822c_dpk_data *data) 2846 { 2847 return rtw8822c_gl_state(rtwdev, data, 0); 2848 } 2849 2850 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 2851 struct rtw8822c_dpk_data *data) 2852 { 2853 u8 path = data->path; 2854 u8 state; 2855 2856 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 2857 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 2858 2859 return state; 2860 } 2861 2862 static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 2863 struct rtw8822c_dpk_data *data) = { 2864 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 2865 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 2866 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 2867 2868 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 2869 bool gain_only, bool loss_only) 2870 { 2871 struct rtw8822c_dpk_data data = {0}; 2872 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 2873 u8 state = RTW_DPK_GAIN_CHECK; 2874 2875 data.loss_only = loss_only; 2876 data.gain_only = gain_only; 2877 data.path = path; 2878 2879 for (;;) { 2880 func = dpk_state[state]; 2881 state = func(rtwdev, &data); 2882 if (state == RTW_DPK_AGC_OUT) 2883 break; 2884 } 2885 2886 return data.txbb; 2887 } 2888 2889 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 2890 u16 coef_i, u16 coef_q) 2891 { 2892 if (coef_i == 0x1000 || coef_i == 0x0fff || 2893 coef_q == 0x1000 || coef_q == 0x0fff) 2894 return true; 2895 2896 return false; 2897 } 2898 2899 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 2900 { 2901 u32 reg = 0; 2902 u16 coef_i = 0, coef_q = 0; 2903 2904 reg = rtw_read32(rtwdev, REG_STAT_RPT); 2905 2906 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 2907 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 2908 2909 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 2910 2911 reg = (coef_i << 16) | coef_q; 2912 2913 return reg; 2914 } 2915 2916 static const u32 rtw8822c_dpk_get_coef_tbl[] = { 2917 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 2918 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 2919 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 2920 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 2921 }; 2922 2923 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 2924 { 2925 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2926 int i; 2927 2928 for (i = 0; i < 20; i++) { 2929 rtw_write32(rtwdev, REG_RXSRAM_CTL, 2930 rtw8822c_dpk_get_coef_tbl[i]); 2931 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 2932 } 2933 } 2934 2935 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 2936 { 2937 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2938 2939 if (path == RF_PATH_A) { 2940 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 2941 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 2942 } else if (path == RF_PATH_B) { 2943 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 2944 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 2945 } 2946 2947 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 2948 } 2949 2950 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 2951 { 2952 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2953 u8 addr, result = 1; 2954 u16 coef_i, coef_q; 2955 2956 for (addr = 0; addr < 20; addr++) { 2957 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 2958 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 2959 2960 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 2961 result = 0; 2962 break; 2963 } 2964 } 2965 return result; 2966 } 2967 2968 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 2969 { 2970 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2971 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 2972 u32 coef; 2973 u8 addr; 2974 2975 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2976 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2977 2978 for (addr = 0; addr < 20; addr++) { 2979 if (result == 0) { 2980 if (addr == 3) 2981 coef = 0x04001fff; 2982 else 2983 coef = 0x00001fff; 2984 } else { 2985 coef = dpk_info->coef[path][addr]; 2986 } 2987 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 2988 } 2989 } 2990 2991 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 2992 u8 path, u8 result) 2993 { 2994 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2995 2996 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2997 2998 if (result) 2999 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 3000 else 3001 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 3002 3003 dpk_info->result[path] = result; 3004 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 3005 3006 rtw8822c_dpk_coef_write(rtwdev, path, result); 3007 } 3008 3009 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 3010 { 3011 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3012 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 3013 3014 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 3015 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 3016 3017 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3018 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3019 rtw8822c_dpk_dgain_read(rtwdev, path); 3020 3021 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 3022 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3023 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3024 rtw8822c_dpk_dc_corr_check(rtwdev, path); 3025 } 3026 3027 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 3028 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 3029 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 3030 3031 if (tx_bb < tx_agc_search) 3032 tx_bb = 0; 3033 else 3034 tx_bb = tx_bb - tx_agc_search; 3035 3036 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 3037 3038 tx_agc = ori_txagc - (ori_txbb - tx_bb); 3039 3040 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 3041 3042 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 3043 3044 return tx_agc; 3045 } 3046 3047 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 3048 { 3049 u8 result; 3050 3051 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 3052 3053 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3054 3055 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 3056 3057 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 3058 3059 rtw8822c_dpk_get_coef(rtwdev, path); 3060 3061 return result; 3062 } 3063 3064 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 3065 { 3066 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3067 u32 tmp_gs = 0; 3068 3069 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3070 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 3071 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3072 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3073 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 3074 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3075 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 3076 3077 if (path == RF_PATH_A) { 3078 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3079 0x1066680); 3080 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 3081 } else { 3082 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3083 0x1066680); 3084 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 3085 } 3086 3087 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 3088 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 3089 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 3090 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 3091 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 3092 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3093 rtw_write32(rtwdev, REG_DPD_CTL15, 3094 0x05020000 | (BIT(path) << 28)); 3095 } else { 3096 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 3097 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 3098 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 3099 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 3100 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3101 rtw_write32(rtwdev, REG_DPD_CTL15, 3102 0x05020008 | (BIT(path) << 28)); 3103 } 3104 3105 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 3106 3107 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 3108 3109 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 3110 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3111 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3112 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 3113 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3114 3115 if (path == RF_PATH_A) 3116 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 3117 else 3118 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 3119 3120 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3121 3122 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 3123 tmp_gs = (tmp_gs * 910) >> 10; 3124 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 3125 3126 if (path == RF_PATH_A) 3127 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 3128 else 3129 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 3130 3131 dpk_info->dpk_gs[path] = tmp_gs; 3132 } 3133 3134 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 3135 { 3136 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3137 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 3138 u32 i_scaling; 3139 u8 path; 3140 3141 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3142 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3143 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 3144 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 3145 3146 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 3147 3148 rtw_write8(rtwdev, 0x1b10, 0x0); 3149 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3150 3151 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3152 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 3153 3154 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 3155 i_scaling); 3156 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3157 GENMASK(31, 28), 0x9); 3158 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3159 GENMASK(31, 28), 0x1); 3160 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3161 GENMASK(31, 28), 0x0); 3162 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 3163 BIT(14), 0x0); 3164 } 3165 } 3166 3167 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 3168 { 3169 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3170 3171 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3172 3173 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3174 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3175 3176 if (test_bit(path, dpk_info->dpk_path_ok)) 3177 rtw8822c_dpk_cal_gs(rtwdev, path); 3178 } 3179 3180 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 3181 u32 dpk_txagc, u8 path) 3182 { 3183 bool result; 3184 3185 if (!is_fail) { 3186 if (rtw8822c_dpk_coef_read(rtwdev, path)) 3187 result = true; 3188 else 3189 result = false; 3190 } else { 3191 result = false; 3192 } 3193 3194 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 3195 3196 return result; 3197 } 3198 3199 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 3200 { 3201 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3202 u8 path; 3203 3204 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3205 clear_bit(path, dpk_info->dpk_path_ok); 3206 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3207 0x8 | (path << 1)); 3208 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 3209 3210 dpk_info->dpk_txagc[path] = 0; 3211 dpk_info->result[path] = 0; 3212 dpk_info->dpk_gs[path] = 0x5b; 3213 dpk_info->pre_pwsf[path] = 0; 3214 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 3215 path); 3216 } 3217 } 3218 3219 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 3220 { 3221 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3222 u32 dpk_txagc; 3223 u8 dpk_fail; 3224 3225 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 3226 3227 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 3228 3229 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 3230 3231 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 3232 rtw_err(rtwdev, "failed to do dpk calibration\n"); 3233 3234 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 3235 3236 if (dpk_info->result[path]) 3237 set_bit(path, dpk_info->dpk_path_ok); 3238 } 3239 3240 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 3241 { 3242 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 3243 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 3244 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 3245 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 3246 rtw8822c_dpk_cal_coef1(rtwdev); 3247 } 3248 3249 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 3250 { 3251 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3252 u32 mask = BIT(15) | BIT(14); 3253 3254 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3255 3256 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 3257 dpk_info->is_dpk_pwr_on); 3258 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 3259 dpk_info->is_dpk_pwr_on); 3260 3261 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 3262 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 3263 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 3264 } 3265 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 3266 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 3267 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 3268 } 3269 } 3270 3271 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 3272 { 3273 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3274 u8 path; 3275 3276 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 3277 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 3278 dpk_info->dpk_ch == 0) 3279 return; 3280 3281 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3282 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3283 0x8 | (path << 1)); 3284 if (dpk_info->dpk_band == RTW_BAND_2G) 3285 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 3286 else 3287 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 3288 3289 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 3290 3291 rtw8822c_dpk_coef_write(rtwdev, path, 3292 test_bit(path, dpk_info->dpk_path_ok)); 3293 3294 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3295 3296 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3297 3298 if (path == RF_PATH_A) 3299 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3300 dpk_info->dpk_gs[path]); 3301 else 3302 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3303 dpk_info->dpk_gs[path]); 3304 } 3305 rtw8822c_dpk_cal_coef1(rtwdev); 3306 } 3307 3308 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 3309 { 3310 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3311 u8 channel; 3312 3313 dpk_info->is_reload = false; 3314 3315 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 3316 3317 if (channel == dpk_info->dpk_ch) { 3318 rtw_dbg(rtwdev, RTW_DBG_RFK, 3319 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 3320 rtw8822c_dpk_reload_data(rtwdev); 3321 dpk_info->is_reload = true; 3322 } 3323 3324 return dpk_info->is_reload; 3325 } 3326 3327 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 3328 { 3329 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3330 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 3331 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 3332 u32 bb_reg[DPK_BB_REG_NUM] = { 3333 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 3334 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 3335 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 3336 u32 rf_reg[DPK_RF_REG_NUM] = { 3337 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 3338 u8 path; 3339 3340 if (!dpk_info->is_dpk_pwr_on) { 3341 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 3342 return; 3343 } else if (rtw8822c_dpk_reload(rtwdev)) { 3344 return; 3345 } 3346 3347 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 3348 ewma_thermal_init(&dpk_info->avg_thermal[path]); 3349 3350 rtw8822c_dpk_information(rtwdev); 3351 3352 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 3353 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3354 3355 rtw8822c_dpk_mac_bb_setting(rtwdev); 3356 rtw8822c_dpk_afe_setting(rtwdev, true); 3357 rtw8822c_dpk_pre_setting(rtwdev); 3358 rtw8822c_dpk_result_reset(rtwdev); 3359 rtw8822c_dpk_path_select(rtwdev); 3360 rtw8822c_dpk_afe_setting(rtwdev, false); 3361 rtw8822c_dpk_enable_disable(rtwdev); 3362 3363 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3364 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 3365 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3366 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 3367 } 3368 3369 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 3370 { 3371 rtw8822c_do_iqk(rtwdev); 3372 rtw8822c_do_dpk(rtwdev); 3373 } 3374 3375 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 3376 { 3377 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3378 u8 path; 3379 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 3380 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 3381 3382 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 3383 return; 3384 3385 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 3386 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 3387 ewma_thermal_add(&dpk_info->avg_thermal[path], 3388 thermal_value[path]); 3389 thermal_value[path] = 3390 ewma_thermal_read(&dpk_info->avg_thermal[path]); 3391 delta_dpk[path] = dpk_info->thermal_dpk[path] - 3392 thermal_value[path]; 3393 offset[path] = delta_dpk[path] - 3394 dpk_info->thermal_dpk_delta[path]; 3395 offset[path] &= 0x7f; 3396 3397 if (offset[path] != dpk_info->pre_pwsf[path]) { 3398 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3399 0x8 | (path << 1)); 3400 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 3401 offset[path]); 3402 dpk_info->pre_pwsf[path] = offset[path]; 3403 } 3404 } 3405 } 3406 3407 static const struct rtw_phy_cck_pd_reg 3408 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 3409 { 3410 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 3411 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 3412 }, 3413 { 3414 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 3415 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 3416 }, 3417 }; 3418 3419 #define RTW_CCK_PD_MAX 255 3420 #define RTW_CCK_CS_MAX 31 3421 #define RTW_CCK_CS_ERR1 27 3422 #define RTW_CCK_CS_ERR2 29 3423 static void 3424 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 3425 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 3426 { 3427 u32 pd, cs; 3428 3429 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 3430 return; 3431 3432 pd = rtw_read32_mask(rtwdev, 3433 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3434 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 3435 cs = rtw_read32_mask(rtwdev, 3436 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3437 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 3438 pd += pd_diff; 3439 cs += cs_diff; 3440 if (pd > RTW_CCK_PD_MAX) 3441 pd = RTW_CCK_PD_MAX; 3442 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 3443 cs++; 3444 else if (cs > RTW_CCK_CS_MAX) 3445 cs = RTW_CCK_CS_MAX; 3446 rtw_write32_mask(rtwdev, 3447 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3448 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 3449 pd); 3450 rtw_write32_mask(rtwdev, 3451 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3452 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 3453 cs); 3454 } 3455 3456 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 3457 { 3458 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3459 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 3460 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 3461 u8 cur_lvl; 3462 u8 nrx, bw; 3463 3464 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 3465 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 3466 3467 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 3468 return; 3469 3470 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 3471 3472 /* update cck pd info */ 3473 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 3474 3475 rtw8822c_phy_cck_pd_set_reg(rtwdev, 3476 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 3477 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 3478 bw, nrx); 3479 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 3480 } 3481 3482 #define PWR_TRACK_MASK 0x7f 3483 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 3484 { 3485 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3486 3487 switch (rf_path) { 3488 case RF_PATH_A: 3489 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 3490 dm_info->delta_power_index[rf_path]); 3491 break; 3492 case RF_PATH_B: 3493 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 3494 dm_info->delta_power_index[rf_path]); 3495 break; 3496 default: 3497 break; 3498 } 3499 } 3500 3501 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 3502 struct rtw_swing_table *swing_table, 3503 u8 path) 3504 { 3505 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3506 u8 thermal_value, delta; 3507 3508 if (rtwdev->efuse.thermal_meter[path] == 0xff) 3509 return; 3510 3511 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 3512 3513 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 3514 3515 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 3516 3517 dm_info->delta_power_index[path] = 3518 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 3519 delta); 3520 3521 rtw8822c_pwrtrack_set(rtwdev, path); 3522 } 3523 3524 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3525 { 3526 struct rtw_swing_table swing_table; 3527 u8 i; 3528 3529 rtw_phy_config_swing_table(rtwdev, &swing_table); 3530 3531 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 3532 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 3533 3534 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 3535 rtw8822c_do_iqk(rtwdev); 3536 } 3537 3538 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3539 { 3540 struct rtw_efuse *efuse = &rtwdev->efuse; 3541 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3542 3543 if (efuse->power_track_type != 0) 3544 return; 3545 3546 if (!dm_info->pwr_trk_triggered) { 3547 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3548 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 3549 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3550 3551 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3552 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 3553 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3554 3555 dm_info->pwr_trk_triggered = true; 3556 return; 3557 } 3558 3559 __rtw8822c_pwr_track(rtwdev); 3560 dm_info->pwr_trk_triggered = false; 3561 } 3562 3563 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 3564 {0x0086, 3565 RTW_PWR_CUT_ALL_MSK, 3566 RTW_PWR_INTF_SDIO_MSK, 3567 RTW_PWR_ADDR_SDIO, 3568 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3569 {0x0086, 3570 RTW_PWR_CUT_ALL_MSK, 3571 RTW_PWR_INTF_SDIO_MSK, 3572 RTW_PWR_ADDR_SDIO, 3573 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3574 {0x002E, 3575 RTW_PWR_CUT_ALL_MSK, 3576 RTW_PWR_INTF_ALL_MSK, 3577 RTW_PWR_ADDR_MAC, 3578 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3579 {0x002D, 3580 RTW_PWR_CUT_ALL_MSK, 3581 RTW_PWR_INTF_ALL_MSK, 3582 RTW_PWR_ADDR_MAC, 3583 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3584 {0x007F, 3585 RTW_PWR_CUT_ALL_MSK, 3586 RTW_PWR_INTF_ALL_MSK, 3587 RTW_PWR_ADDR_MAC, 3588 RTW_PWR_CMD_WRITE, BIT(7), 0}, 3589 {0x004A, 3590 RTW_PWR_CUT_ALL_MSK, 3591 RTW_PWR_INTF_USB_MSK, 3592 RTW_PWR_ADDR_MAC, 3593 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3594 {0x0005, 3595 RTW_PWR_CUT_ALL_MSK, 3596 RTW_PWR_INTF_ALL_MSK, 3597 RTW_PWR_ADDR_MAC, 3598 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 3599 {0xFFFF, 3600 RTW_PWR_CUT_ALL_MSK, 3601 RTW_PWR_INTF_ALL_MSK, 3602 0, 3603 RTW_PWR_CMD_END, 0, 0}, 3604 }; 3605 3606 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 3607 {0x0000, 3608 RTW_PWR_CUT_ALL_MSK, 3609 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3610 RTW_PWR_ADDR_MAC, 3611 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3612 {0x0005, 3613 RTW_PWR_CUT_ALL_MSK, 3614 RTW_PWR_INTF_ALL_MSK, 3615 RTW_PWR_ADDR_MAC, 3616 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 3617 {0x0075, 3618 RTW_PWR_CUT_ALL_MSK, 3619 RTW_PWR_INTF_PCI_MSK, 3620 RTW_PWR_ADDR_MAC, 3621 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3622 {0x0006, 3623 RTW_PWR_CUT_ALL_MSK, 3624 RTW_PWR_INTF_ALL_MSK, 3625 RTW_PWR_ADDR_MAC, 3626 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3627 {0x0075, 3628 RTW_PWR_CUT_ALL_MSK, 3629 RTW_PWR_INTF_PCI_MSK, 3630 RTW_PWR_ADDR_MAC, 3631 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3632 {0xFF1A, 3633 RTW_PWR_CUT_ALL_MSK, 3634 RTW_PWR_INTF_USB_MSK, 3635 RTW_PWR_ADDR_MAC, 3636 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3637 {0x002E, 3638 RTW_PWR_CUT_ALL_MSK, 3639 RTW_PWR_INTF_ALL_MSK, 3640 RTW_PWR_ADDR_MAC, 3641 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3642 {0x0006, 3643 RTW_PWR_CUT_ALL_MSK, 3644 RTW_PWR_INTF_ALL_MSK, 3645 RTW_PWR_ADDR_MAC, 3646 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3647 {0x0005, 3648 RTW_PWR_CUT_ALL_MSK, 3649 RTW_PWR_INTF_ALL_MSK, 3650 RTW_PWR_ADDR_MAC, 3651 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 3652 {0x1018, 3653 RTW_PWR_CUT_ALL_MSK, 3654 RTW_PWR_INTF_ALL_MSK, 3655 RTW_PWR_ADDR_MAC, 3656 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3657 {0x0005, 3658 RTW_PWR_CUT_ALL_MSK, 3659 RTW_PWR_INTF_ALL_MSK, 3660 RTW_PWR_ADDR_MAC, 3661 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3662 {0x0005, 3663 RTW_PWR_CUT_ALL_MSK, 3664 RTW_PWR_INTF_ALL_MSK, 3665 RTW_PWR_ADDR_MAC, 3666 RTW_PWR_CMD_POLLING, BIT(0), 0}, 3667 {0x0074, 3668 RTW_PWR_CUT_ALL_MSK, 3669 RTW_PWR_INTF_PCI_MSK, 3670 RTW_PWR_ADDR_MAC, 3671 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3672 {0x0071, 3673 RTW_PWR_CUT_ALL_MSK, 3674 RTW_PWR_INTF_PCI_MSK, 3675 RTW_PWR_ADDR_MAC, 3676 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3677 {0x0062, 3678 RTW_PWR_CUT_ALL_MSK, 3679 RTW_PWR_INTF_PCI_MSK, 3680 RTW_PWR_ADDR_MAC, 3681 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 3682 (BIT(7) | BIT(6) | BIT(5))}, 3683 {0x0061, 3684 RTW_PWR_CUT_ALL_MSK, 3685 RTW_PWR_INTF_PCI_MSK, 3686 RTW_PWR_ADDR_MAC, 3687 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 3688 {0x001F, 3689 RTW_PWR_CUT_ALL_MSK, 3690 RTW_PWR_INTF_ALL_MSK, 3691 RTW_PWR_ADDR_MAC, 3692 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3693 {0x00EF, 3694 RTW_PWR_CUT_ALL_MSK, 3695 RTW_PWR_INTF_ALL_MSK, 3696 RTW_PWR_ADDR_MAC, 3697 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3698 {0x1045, 3699 RTW_PWR_CUT_ALL_MSK, 3700 RTW_PWR_INTF_ALL_MSK, 3701 RTW_PWR_ADDR_MAC, 3702 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 3703 {0x0010, 3704 RTW_PWR_CUT_ALL_MSK, 3705 RTW_PWR_INTF_ALL_MSK, 3706 RTW_PWR_ADDR_MAC, 3707 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3708 {0x1064, 3709 RTW_PWR_CUT_ALL_MSK, 3710 RTW_PWR_INTF_ALL_MSK, 3711 RTW_PWR_ADDR_MAC, 3712 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3713 {0xFFFF, 3714 RTW_PWR_CUT_ALL_MSK, 3715 RTW_PWR_INTF_ALL_MSK, 3716 0, 3717 RTW_PWR_CMD_END, 0, 0}, 3718 }; 3719 3720 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 3721 {0x0093, 3722 RTW_PWR_CUT_ALL_MSK, 3723 RTW_PWR_INTF_ALL_MSK, 3724 RTW_PWR_ADDR_MAC, 3725 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3726 {0x001F, 3727 RTW_PWR_CUT_ALL_MSK, 3728 RTW_PWR_INTF_ALL_MSK, 3729 RTW_PWR_ADDR_MAC, 3730 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3731 {0x00EF, 3732 RTW_PWR_CUT_ALL_MSK, 3733 RTW_PWR_INTF_ALL_MSK, 3734 RTW_PWR_ADDR_MAC, 3735 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3736 {0x1045, 3737 RTW_PWR_CUT_ALL_MSK, 3738 RTW_PWR_INTF_ALL_MSK, 3739 RTW_PWR_ADDR_MAC, 3740 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3741 {0xFF1A, 3742 RTW_PWR_CUT_ALL_MSK, 3743 RTW_PWR_INTF_USB_MSK, 3744 RTW_PWR_ADDR_MAC, 3745 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 3746 {0x0049, 3747 RTW_PWR_CUT_ALL_MSK, 3748 RTW_PWR_INTF_ALL_MSK, 3749 RTW_PWR_ADDR_MAC, 3750 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3751 {0x0006, 3752 RTW_PWR_CUT_ALL_MSK, 3753 RTW_PWR_INTF_ALL_MSK, 3754 RTW_PWR_ADDR_MAC, 3755 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3756 {0x0002, 3757 RTW_PWR_CUT_ALL_MSK, 3758 RTW_PWR_INTF_ALL_MSK, 3759 RTW_PWR_ADDR_MAC, 3760 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3761 {0x0005, 3762 RTW_PWR_CUT_ALL_MSK, 3763 RTW_PWR_INTF_ALL_MSK, 3764 RTW_PWR_ADDR_MAC, 3765 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3766 {0x0005, 3767 RTW_PWR_CUT_ALL_MSK, 3768 RTW_PWR_INTF_ALL_MSK, 3769 RTW_PWR_ADDR_MAC, 3770 RTW_PWR_CMD_POLLING, BIT(1), 0}, 3771 {0x0000, 3772 RTW_PWR_CUT_ALL_MSK, 3773 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3774 RTW_PWR_ADDR_MAC, 3775 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3776 {0xFFFF, 3777 RTW_PWR_CUT_ALL_MSK, 3778 RTW_PWR_INTF_ALL_MSK, 3779 0, 3780 RTW_PWR_CMD_END, 0, 0}, 3781 }; 3782 3783 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 3784 {0x0005, 3785 RTW_PWR_CUT_ALL_MSK, 3786 RTW_PWR_INTF_SDIO_MSK, 3787 RTW_PWR_ADDR_MAC, 3788 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 3789 {0x0007, 3790 RTW_PWR_CUT_ALL_MSK, 3791 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3792 RTW_PWR_ADDR_MAC, 3793 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 3794 {0x0067, 3795 RTW_PWR_CUT_ALL_MSK, 3796 RTW_PWR_INTF_ALL_MSK, 3797 RTW_PWR_ADDR_MAC, 3798 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3799 {0x004A, 3800 RTW_PWR_CUT_ALL_MSK, 3801 RTW_PWR_INTF_USB_MSK, 3802 RTW_PWR_ADDR_MAC, 3803 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3804 {0x0081, 3805 RTW_PWR_CUT_ALL_MSK, 3806 RTW_PWR_INTF_ALL_MSK, 3807 RTW_PWR_ADDR_MAC, 3808 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 3809 {0x0090, 3810 RTW_PWR_CUT_ALL_MSK, 3811 RTW_PWR_INTF_ALL_MSK, 3812 RTW_PWR_ADDR_MAC, 3813 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3814 {0x0092, 3815 RTW_PWR_CUT_ALL_MSK, 3816 RTW_PWR_INTF_PCI_MSK, 3817 RTW_PWR_ADDR_MAC, 3818 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 3819 {0x0093, 3820 RTW_PWR_CUT_ALL_MSK, 3821 RTW_PWR_INTF_PCI_MSK, 3822 RTW_PWR_ADDR_MAC, 3823 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 3824 {0x0005, 3825 RTW_PWR_CUT_ALL_MSK, 3826 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3827 RTW_PWR_ADDR_MAC, 3828 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 3829 {0x0005, 3830 RTW_PWR_CUT_ALL_MSK, 3831 RTW_PWR_INTF_PCI_MSK, 3832 RTW_PWR_ADDR_MAC, 3833 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3834 {0x0086, 3835 RTW_PWR_CUT_ALL_MSK, 3836 RTW_PWR_INTF_SDIO_MSK, 3837 RTW_PWR_ADDR_SDIO, 3838 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3839 {0xFFFF, 3840 RTW_PWR_CUT_ALL_MSK, 3841 RTW_PWR_INTF_ALL_MSK, 3842 0, 3843 RTW_PWR_CMD_END, 0, 0}, 3844 }; 3845 3846 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 3847 trans_carddis_to_cardemu_8822c, 3848 trans_cardemu_to_act_8822c, 3849 NULL 3850 }; 3851 3852 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 3853 trans_act_to_cardemu_8822c, 3854 trans_cardemu_to_carddis_8822c, 3855 NULL 3856 }; 3857 3858 static const struct rtw_intf_phy_para usb2_param_8822c[] = { 3859 {0xFFFF, 0x00, 3860 RTW_IP_SEL_PHY, 3861 RTW_INTF_PHY_CUT_ALL, 3862 RTW_INTF_PHY_PLATFORM_ALL}, 3863 }; 3864 3865 static const struct rtw_intf_phy_para usb3_param_8822c[] = { 3866 {0xFFFF, 0x0000, 3867 RTW_IP_SEL_PHY, 3868 RTW_INTF_PHY_CUT_ALL, 3869 RTW_INTF_PHY_PLATFORM_ALL}, 3870 }; 3871 3872 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 3873 {0xFFFF, 0x0000, 3874 RTW_IP_SEL_PHY, 3875 RTW_INTF_PHY_CUT_ALL, 3876 RTW_INTF_PHY_PLATFORM_ALL}, 3877 }; 3878 3879 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 3880 {0xFFFF, 0x0000, 3881 RTW_IP_SEL_PHY, 3882 RTW_INTF_PHY_CUT_ALL, 3883 RTW_INTF_PHY_PLATFORM_ALL}, 3884 }; 3885 3886 static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 3887 .usb2_para = usb2_param_8822c, 3888 .usb3_para = usb3_param_8822c, 3889 .gen1_para = pcie_gen1_param_8822c, 3890 .gen2_para = pcie_gen2_param_8822c, 3891 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 3892 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 3893 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 3894 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 3895 }; 3896 3897 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 3898 [0] = RTW_DEF_RFE(8822c, 0, 0), 3899 [1] = RTW_DEF_RFE(8822c, 0, 0), 3900 [2] = RTW_DEF_RFE(8822c, 0, 0), 3901 [5] = RTW_DEF_RFE(8822c, 0, 5), 3902 [6] = RTW_DEF_RFE(8822c, 0, 0), 3903 }; 3904 3905 static const struct rtw_hw_reg rtw8822c_dig[] = { 3906 [0] = { .addr = 0x1d70, .mask = 0x7f }, 3907 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 3908 }; 3909 3910 static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = { 3911 .ctrl = LTECOEX_ACCESS_CTRL, 3912 .wdata = LTECOEX_WRITE_DATA, 3913 .rdata = LTECOEX_READ_DATA, 3914 }; 3915 3916 static const struct rtw_page_table page_table_8822c[] = { 3917 {64, 64, 64, 64, 1}, 3918 {64, 64, 64, 64, 1}, 3919 {64, 64, 0, 0, 1}, 3920 {64, 64, 64, 0, 1}, 3921 {64, 64, 64, 64, 1}, 3922 }; 3923 3924 static const struct rtw_rqpn rqpn_table_8822c[] = { 3925 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3926 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3927 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3928 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3929 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3930 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3931 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3932 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 3933 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3934 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3935 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3936 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3937 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3938 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3939 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3940 }; 3941 3942 static struct rtw_prioq_addrs prioq_addrs_8822c = { 3943 .prio[RTW_DMA_MAPPING_EXTRA] = { 3944 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 3945 }, 3946 .prio[RTW_DMA_MAPPING_LOW] = { 3947 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 3948 }, 3949 .prio[RTW_DMA_MAPPING_NORMAL] = { 3950 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 3951 }, 3952 .prio[RTW_DMA_MAPPING_HIGH] = { 3953 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 3954 }, 3955 .wsize = true, 3956 }; 3957 3958 static struct rtw_chip_ops rtw8822c_ops = { 3959 .phy_set_param = rtw8822c_phy_set_param, 3960 .read_efuse = rtw8822c_read_efuse, 3961 .query_rx_desc = rtw8822c_query_rx_desc, 3962 .set_channel = rtw8822c_set_channel, 3963 .mac_init = rtw8822c_mac_init, 3964 .read_rf = rtw_phy_read_rf, 3965 .write_rf = rtw_phy_write_rf_reg_mix, 3966 .set_tx_power_index = rtw8822c_set_tx_power_index, 3967 .set_antenna = rtw8822c_set_antenna, 3968 .cfg_ldo25 = rtw8822c_cfg_ldo25, 3969 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 3970 .dpk_track = rtw8822c_dpk_track, 3971 .phy_calibration = rtw8822c_phy_calibration, 3972 .cck_pd_set = rtw8822c_phy_cck_pd_set, 3973 .pwr_track = rtw8822c_pwr_track, 3974 .config_bfee = rtw8822c_bf_config_bfee, 3975 .set_gid_table = rtw_bf_set_gid_table, 3976 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 3977 3978 .coex_set_init = rtw8822c_coex_cfg_init, 3979 .coex_set_ant_switch = NULL, 3980 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 3981 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 3982 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 3983 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 3984 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 3985 }; 3986 3987 /* Shared-Antenna Coex Table */ 3988 static const struct coex_table_para table_sant_8822c[] = { 3989 {0xffffffff, 0xffffffff}, /* case-0 */ 3990 {0x55555555, 0x55555555}, 3991 {0x66555555, 0x66555555}, 3992 {0xaaaaaaaa, 0xaaaaaaaa}, 3993 {0x5a5a5a5a, 0x5a5a5a5a}, 3994 {0xfafafafa, 0xfafafafa}, /* case-5 */ 3995 {0x6a5a6a5a, 0xaaaaaaaa}, 3996 {0x6a5a56aa, 0x6a5a56aa}, 3997 {0x6a5a5a5a, 0x6a5a5a5a}, 3998 {0x66555555, 0x5a5a5a5a}, 3999 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 4000 {0x66555555, 0xfafafafa}, 4001 {0x66555555, 0x5a5a5aaa}, 4002 {0x66555555, 0x5aaa5aaa}, 4003 {0x66555555, 0xaaaa5aaa}, 4004 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 4005 {0xffff55ff, 0xfafafafa}, 4006 {0xffff55ff, 0x6afa5afa}, 4007 {0xaaffffaa, 0xfafafafa}, 4008 {0xaa5555aa, 0x5a5a5a5a}, 4009 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 4010 {0xaa5555aa, 0xaaaaaaaa}, 4011 {0xffffffff, 0x5a5a5a5a}, 4012 {0xffffffff, 0x6a5a5a5a}, 4013 {0xffffffff, 0x55555555}, 4014 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 4015 {0x55555555, 0x5a5a5a5a}, 4016 {0x55555555, 0xaaaaaaaa}, 4017 {0x55555555, 0x6a5a6a5a}, 4018 {0x66556655, 0x66556655} 4019 }; 4020 4021 /* Non-Shared-Antenna Coex Table */ 4022 static const struct coex_table_para table_nsant_8822c[] = { 4023 {0xffffffff, 0xffffffff}, /* case-100 */ 4024 {0x55555555, 0x55555555}, 4025 {0x66555555, 0x66555555}, 4026 {0xaaaaaaaa, 0xaaaaaaaa}, 4027 {0x5a5a5a5a, 0x5a5a5a5a}, 4028 {0xfafafafa, 0xfafafafa}, /* case-105 */ 4029 {0x5afa5afa, 0x5afa5afa}, 4030 {0x55555555, 0xfafafafa}, 4031 {0x66555555, 0xfafafafa}, 4032 {0x66555555, 0x5a5a5a5a}, 4033 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 4034 {0x66555555, 0xaaaaaaaa}, 4035 {0xffff55ff, 0xfafafafa}, 4036 {0xffff55ff, 0x5afa5afa}, 4037 {0xffff55ff, 0xaaaaaaaa}, 4038 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 4039 {0xaaffffaa, 0x5afa5afa}, 4040 {0xaaffffaa, 0xaaaaaaaa}, 4041 {0xffffffff, 0xfafafafa}, 4042 {0xffffffff, 0x5afa5afa}, 4043 {0xffffffff, 0xaaaaaaaa},/* case-120 */ 4044 {0x55ff55ff, 0x5afa5afa}, 4045 {0x55ff55ff, 0xaaaaaaaa}, 4046 {0x55ff55ff, 0x55ff55ff} 4047 }; 4048 4049 /* Shared-Antenna TDMA */ 4050 static const struct coex_tdma_para tdma_sant_8822c[] = { 4051 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 4052 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4053 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4054 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4055 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4056 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 4057 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4058 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4059 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4060 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4061 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 4062 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4063 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4064 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4065 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4066 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 4067 { {0x51, 0x45, 0x03, 0x10, 0x10} }, 4068 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4069 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4070 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4071 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 4072 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 4073 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 4074 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 4075 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 4076 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 4077 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 4078 { {0x61, 0x08, 0x03, 0x11, 0x11} } 4079 }; 4080 4081 /* Non-Shared-Antenna TDMA */ 4082 static const struct coex_tdma_para tdma_nsant_8822c[] = { 4083 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 4084 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4085 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4086 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4087 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4088 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 4089 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4090 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4091 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4092 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4093 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 4094 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4095 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4096 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4097 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4098 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 4099 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 4100 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4101 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4102 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4103 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ 4104 }; 4105 4106 /* rssi in percentage % (dbm = % - 100) */ 4107 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 4108 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 4109 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 4110 4111 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 4112 static const struct coex_rf_para rf_para_tx_8822c[] = { 4113 {0, 0, false, 7}, /* for normal */ 4114 {0, 16, false, 7}, /* for WL-CPT */ 4115 {8, 17, true, 4}, 4116 {7, 18, true, 4}, 4117 {6, 19, true, 4}, 4118 {5, 20, true, 4} 4119 }; 4120 4121 static const struct coex_rf_para rf_para_rx_8822c[] = { 4122 {0, 0, false, 7}, /* for normal */ 4123 {0, 16, false, 7}, /* for WL-CPT */ 4124 {3, 24, true, 5}, 4125 {2, 26, true, 5}, 4126 {1, 27, true, 5}, 4127 {0, 28, true, 5} 4128 }; 4129 4130 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 4131 4132 static const u8 4133 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4134 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4135 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4136 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4137 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4138 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4139 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4140 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4141 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4142 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4143 }; 4144 4145 static const u8 4146 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4147 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4148 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4149 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4150 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4151 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4152 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4153 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4154 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4155 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4156 }; 4157 4158 static const u8 4159 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4160 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4161 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4162 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4163 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4164 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4165 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4166 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4167 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4168 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4169 }; 4170 4171 static const u8 4172 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4173 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4174 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4175 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4176 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4177 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4178 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4179 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4180 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4181 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4182 }; 4183 4184 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 4185 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 4186 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 4187 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 4188 }; 4189 4190 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 4191 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4192 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 4193 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 4194 }; 4195 4196 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 4197 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 4198 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 4199 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 4200 }; 4201 4202 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 4203 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4204 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 4205 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 4206 }; 4207 4208 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 4209 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4210 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4211 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 4212 }; 4213 4214 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 4215 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4216 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 4217 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 4218 }; 4219 4220 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 4221 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 4222 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 4223 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 4224 }; 4225 4226 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 4227 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4228 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4229 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 4230 }; 4231 4232 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 4233 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 4234 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 4235 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 4236 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 4237 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 4238 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 4239 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 4240 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 4241 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 4242 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 4243 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 4244 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 4245 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 4246 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 4247 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 4248 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 4249 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 4250 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 4251 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 4252 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 4253 }; 4254 4255 #ifdef CONFIG_PM 4256 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 4257 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 4258 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 4259 WIPHY_WOWLAN_NET_DETECT, 4260 .n_patterns = RTW_MAX_PATTERN_NUM, 4261 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 4262 .pattern_min_len = 1, 4263 .max_nd_match_sets = 4, 4264 }; 4265 #endif 4266 4267 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 4268 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 4269 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 4270 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 4271 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 4272 {0, 0, RTW_REG_DOMAIN_NL}, 4273 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4274 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4275 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4276 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4277 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 4278 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4279 {0, 0, RTW_REG_DOMAIN_NL}, 4280 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 4281 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 4282 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 4283 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 4284 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 4285 {0, 0, RTW_REG_DOMAIN_NL}, 4286 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4287 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4288 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 4289 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4290 }; 4291 4292 struct rtw_chip_info rtw8822c_hw_spec = { 4293 .ops = &rtw8822c_ops, 4294 .id = RTW_CHIP_TYPE_8822C, 4295 .fw_name = "rtw88/rtw8822c_fw.bin", 4296 .wlan_cpu = RTW_WCPU_11AC, 4297 .tx_pkt_desc_sz = 48, 4298 .tx_buf_desc_sz = 16, 4299 .rx_pkt_desc_sz = 24, 4300 .rx_buf_desc_sz = 8, 4301 .phy_efuse_size = 512, 4302 .log_efuse_size = 768, 4303 .ptct_efuse_size = 124, 4304 .txff_size = 262144, 4305 .rxff_size = 24576, 4306 .txgi_factor = 2, 4307 .is_pwr_by_rate_dec = false, 4308 .max_power_index = 0x7f, 4309 .csi_buf_pg_num = 50, 4310 .band = RTW_BAND_2G | RTW_BAND_5G, 4311 .page_size = 128, 4312 .dig_min = 0x20, 4313 .ht_supported = true, 4314 .vht_supported = true, 4315 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 4316 .sys_func_en = 0xD8, 4317 .pwr_on_seq = card_enable_flow_8822c, 4318 .pwr_off_seq = card_disable_flow_8822c, 4319 .page_table = page_table_8822c, 4320 .rqpn_table = rqpn_table_8822c, 4321 .prioq_addrs = &prioq_addrs_8822c, 4322 .intf_table = &phy_para_table_8822c, 4323 .dig = rtw8822c_dig, 4324 .dig_cck = NULL, 4325 .rf_base_addr = {0x3c00, 0x4c00}, 4326 .rf_sipi_addr = {0x1808, 0x4108}, 4327 .ltecoex_addr = &rtw8822c_ltecoex_addr, 4328 .mac_tbl = &rtw8822c_mac_tbl, 4329 .agc_tbl = &rtw8822c_agc_tbl, 4330 .bb_tbl = &rtw8822c_bb_tbl, 4331 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 4332 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 4333 .rfe_defs = rtw8822c_rfe_defs, 4334 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 4335 .en_dis_dpd = true, 4336 .dpd_ratemask = DIS_DPD_RATEALL, 4337 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 4338 .iqk_threshold = 8, 4339 .bfer_su_max_num = 2, 4340 .bfer_mu_max_num = 1, 4341 .rx_ldpc = true, 4342 4343 #ifdef CONFIG_PM 4344 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 4345 .wowlan_stub = &rtw_wowlan_stub_8822c, 4346 .max_sched_scan_ssids = 4, 4347 #endif 4348 .coex_para_ver = 0x20070217, 4349 .bt_desired_ver = 0x17, 4350 .scbd_support = true, 4351 .new_scbd10_def = true, 4352 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 4353 .bt_rssi_type = COEX_BTRSSI_DBM, 4354 .ant_isolation = 15, 4355 .rssi_tolerance = 2, 4356 .wl_rssi_step = wl_rssi_step_8822c, 4357 .bt_rssi_step = bt_rssi_step_8822c, 4358 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 4359 .table_sant = table_sant_8822c, 4360 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 4361 .table_nsant = table_nsant_8822c, 4362 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 4363 .tdma_sant = tdma_sant_8822c, 4364 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 4365 .tdma_nsant = tdma_nsant_8822c, 4366 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 4367 .wl_rf_para_tx = rf_para_tx_8822c, 4368 .wl_rf_para_rx = rf_para_rx_8822c, 4369 .bt_afh_span_bw20 = 0x24, 4370 .bt_afh_span_bw40 = 0x36, 4371 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 4372 .afh_5g = afh_5g_8822c, 4373 4374 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 4375 .coex_info_hw_regs = coex_info_hw_regs_8822c, 4376 }; 4377 EXPORT_SYMBOL(rtw8822c_hw_spec); 4378 4379 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 4380 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 4381 4382 MODULE_AUTHOR("Realtek Corporation"); 4383 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver"); 4384 MODULE_LICENSE("Dual BSD/GPL"); 4385