1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822c.h" 13 #include "rtw8822c_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "util.h" 18 #include "bf.h" 19 #include "efuse.h" 20 #include "coex.h" 21 22 #define IQK_DONE_8822C 0xaa 23 24 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 25 u8 rx_path, bool is_tx2_path); 26 27 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 28 struct rtw8822c_efuse *map) 29 { 30 ether_addr_copy(efuse->addr, map->e.mac_addr); 31 } 32 33 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 34 { 35 struct rtw_efuse *efuse = &rtwdev->efuse; 36 struct rtw8822c_efuse *map; 37 int i; 38 39 map = (struct rtw8822c_efuse *)log_map; 40 41 efuse->rfe_option = map->rfe_option; 42 efuse->rf_board_option = map->rf_board_option; 43 efuse->crystal_cap = map->xtal_k & XCAP_MASK; 44 efuse->channel_plan = map->channel_plan; 45 efuse->country_code[0] = map->country_code[0]; 46 efuse->country_code[1] = map->country_code[1]; 47 efuse->bt_setting = map->rf_bt_setting; 48 efuse->regd = map->rf_board_option & 0x7; 49 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 50 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 51 efuse->thermal_meter_k = 52 (map->path_a_thermal + map->path_b_thermal) >> 1; 53 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 54 55 for (i = 0; i < 4; i++) 56 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 57 58 switch (rtw_hci_type(rtwdev)) { 59 case RTW_HCI_TYPE_PCIE: 60 rtw8822ce_efuse_parsing(efuse, map); 61 break; 62 default: 63 /* unsupported now */ 64 return -ENOTSUPP; 65 } 66 67 return 0; 68 } 69 70 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 71 { 72 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 73 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 74 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 75 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 76 77 if (pre) 78 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 79 else 80 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 81 } 82 83 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 84 struct rtw_backup_info *backup, 85 struct rtw_backup_info *backup_rf) 86 { 87 u32 path, i; 88 u32 val; 89 u32 reg; 90 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 91 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 92 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 93 0x1a00, 0x1a14, 0x1d58, 0x1c38, 94 0x1e24, 0x1e28, 0x1860, 0x4160}; 95 96 for (i = 0; i < DACK_REG_8822C; i++) { 97 backup[i].len = 4; 98 backup[i].reg = addrs[i]; 99 backup[i].val = rtw_read32(rtwdev, addrs[i]); 100 } 101 102 for (path = 0; path < DACK_PATH_8822C; path++) { 103 for (i = 0; i < DACK_RF_8822C; i++) { 104 reg = rf_addr[i]; 105 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 106 backup_rf[path * i + i].reg = reg; 107 backup_rf[path * i + i].val = val; 108 } 109 } 110 } 111 112 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 113 struct rtw_backup_info *backup, 114 struct rtw_backup_info *backup_rf) 115 { 116 u32 path, i; 117 u32 val; 118 u32 reg; 119 120 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 121 122 for (path = 0; path < DACK_PATH_8822C; path++) { 123 for (i = 0; i < DACK_RF_8822C; i++) { 124 val = backup_rf[path * i + i].val; 125 reg = backup_rf[path * i + i].reg; 126 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 127 } 128 } 129 } 130 131 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 132 u32 *min, u32 *max) 133 { 134 if (value >= 0x200) { 135 if (*min >= 0x200) { 136 if (*min > value) 137 *min = value; 138 } else { 139 *min = value; 140 } 141 if (*max >= 0x200) { 142 if (*max < value) 143 *max = value; 144 } 145 } else { 146 if (*min < 0x200) { 147 if (*min > value) 148 *min = value; 149 } 150 151 if (*max >= 0x200) { 152 *max = value; 153 } else { 154 if (*max < value) 155 *max = value; 156 } 157 } 158 } 159 160 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 161 { 162 if (*v1 >= 0x200 && *v2 >= 0x200) { 163 if (*v1 > *v2) 164 swap(*v1, *v2); 165 } else if (*v1 < 0x200 && *v2 < 0x200) { 166 if (*v1 > *v2) 167 swap(*v1, *v2); 168 } else if (*v1 < 0x200 && *v2 >= 0x200) { 169 swap(*v1, *v2); 170 } 171 } 172 173 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 174 { 175 u32 i, j; 176 177 for (i = 0; i < DACK_SN_8822C - 1; i++) { 178 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 179 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 180 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 181 } 182 } 183 } 184 185 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 186 { 187 u32 p, m, t, i; 188 189 m = 0; 190 p = 0; 191 for (i = 10; i < DACK_SN_8822C - 10; i++) { 192 if (vec[i] > 0x200) 193 m = (0x400 - vec[i]) + m; 194 else 195 p = vec[i] + p; 196 } 197 198 if (p > m) { 199 t = p - m; 200 t = t / (DACK_SN_8822C - 20); 201 } else { 202 t = m - p; 203 t = t / (DACK_SN_8822C - 20); 204 if (t != 0x0) 205 t = 0x400 - t; 206 } 207 208 *val = t; 209 } 210 211 static u32 rtw8822c_get_path_write_addr(u8 path) 212 { 213 u32 base_addr; 214 215 switch (path) { 216 case RF_PATH_A: 217 base_addr = 0x1800; 218 break; 219 case RF_PATH_B: 220 base_addr = 0x4100; 221 break; 222 default: 223 WARN_ON(1); 224 return -1; 225 } 226 227 return base_addr; 228 } 229 230 static u32 rtw8822c_get_path_read_addr(u8 path) 231 { 232 u32 base_addr; 233 234 switch (path) { 235 case RF_PATH_A: 236 base_addr = 0x2800; 237 break; 238 case RF_PATH_B: 239 base_addr = 0x4500; 240 break; 241 default: 242 WARN_ON(1); 243 return -1; 244 } 245 246 return base_addr; 247 } 248 249 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 250 { 251 bool ret = true; 252 253 if ((value >= 0x200 && (0x400 - value) > 0x64) || 254 (value < 0x200 && value > 0x64)) { 255 ret = false; 256 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 257 } 258 259 return ret; 260 } 261 262 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 263 { 264 u32 temp; 265 int i = 0, cnt = 0; 266 267 while (i < DACK_SN_8822C && cnt < 10000) { 268 cnt++; 269 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 270 iv[i] = (temp & 0x3ff000) >> 12; 271 qv[i] = temp & 0x3ff; 272 273 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 274 rtw8822c_dac_iq_check(rtwdev, qv[i])) 275 i++; 276 } 277 } 278 279 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 280 u32 *iv, u32 *qv, 281 u32 *i_value, u32 *q_value) 282 { 283 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 284 u32 i_delta, q_delta; 285 u32 temp; 286 int i, cnt = 0; 287 288 do { 289 i_min = iv[0]; 290 i_max = iv[0]; 291 q_min = qv[0]; 292 q_max = qv[0]; 293 for (i = 0; i < DACK_SN_8822C; i++) { 294 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 295 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 296 } 297 298 if (i_max < 0x200 && i_min < 0x200) 299 i_delta = i_max - i_min; 300 else if (i_max >= 0x200 && i_min >= 0x200) 301 i_delta = i_max - i_min; 302 else 303 i_delta = i_max + (0x400 - i_min); 304 305 if (q_max < 0x200 && q_min < 0x200) 306 q_delta = q_max - q_min; 307 else if (q_max >= 0x200 && q_min >= 0x200) 308 q_delta = q_max - q_min; 309 else 310 q_delta = q_max + (0x400 - q_min); 311 312 rtw_dbg(rtwdev, RTW_DBG_RFK, 313 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 314 i_min, i_max, i_delta); 315 rtw_dbg(rtwdev, RTW_DBG_RFK, 316 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 317 q_min, q_max, q_delta); 318 319 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 320 321 if (i_delta > 5 || q_delta > 5) { 322 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 323 iv[0] = (temp & 0x3ff000) >> 12; 324 qv[0] = temp & 0x3ff; 325 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 326 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 327 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 328 } else { 329 break; 330 } 331 } while (cnt++ < 100); 332 333 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 334 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 335 } 336 337 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 338 u32 *i_value, u32 *q_value) 339 { 340 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 341 u32 rf_a, rf_b; 342 343 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 344 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 345 346 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 347 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 348 349 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 350 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 351 } 352 353 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 354 { 355 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 356 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 357 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 358 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 359 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 360 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 361 rtw_write32(rtwdev, 0x1b00, 0x00000008); 362 rtw_write8(rtwdev, 0x1bcc, 0x3f); 363 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 364 rtw_write8(rtwdev, 0x1bcc, 0x3f); 365 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 366 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 367 } 368 369 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 370 u8 path, u32 *adc_ic, u32 *adc_qc) 371 { 372 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 373 u32 ic = 0, qc = 0, temp = 0; 374 u32 base_addr; 375 u32 path_sel; 376 int i; 377 378 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 379 380 base_addr = rtw8822c_get_path_write_addr(path); 381 switch (path) { 382 case RF_PATH_A: 383 path_sel = 0xa0000; 384 break; 385 case RF_PATH_B: 386 path_sel = 0x80000; 387 break; 388 default: 389 WARN_ON(1); 390 return; 391 } 392 393 /* ADCK step1 */ 394 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 395 if (path == RF_PATH_B) 396 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 397 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 398 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 399 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 400 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 401 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 402 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 403 for (i = 0; i < 10; i++) { 404 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 405 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 406 rtw_write32(rtwdev, 0x1c24, 0x00010002); 407 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 408 rtw_dbg(rtwdev, RTW_DBG_RFK, 409 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 410 411 /* compensation value */ 412 if (ic != 0x0) { 413 ic = 0x400 - ic; 414 *adc_ic = ic; 415 } 416 if (qc != 0x0) { 417 qc = 0x400 - qc; 418 *adc_qc = qc; 419 } 420 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 421 rtw_write32(rtwdev, base_addr + 0x68, temp); 422 dm_info->dack_adck[path] = temp; 423 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 424 base_addr + 0x68, temp); 425 /* check ADC DC offset */ 426 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 427 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 428 rtw_dbg(rtwdev, RTW_DBG_RFK, 429 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 430 if (ic >= 0x200) 431 ic = 0x400 - ic; 432 if (qc >= 0x200) 433 qc = 0x400 - qc; 434 if (ic < 5 && qc < 5) 435 break; 436 } 437 438 /* ADCK step2 */ 439 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 440 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 441 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 442 443 /* release pull low switch on IQ path */ 444 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 445 } 446 447 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 448 { 449 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 450 u32 base_addr; 451 u32 read_addr; 452 453 base_addr = rtw8822c_get_path_write_addr(path); 454 read_addr = rtw8822c_get_path_read_addr(path); 455 456 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 457 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 458 if (path == RF_PATH_A) { 459 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 460 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 461 } 462 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 463 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 464 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 465 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 466 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 467 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 468 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 469 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 470 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 471 mdelay(2); 472 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 473 mdelay(2); 474 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 475 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 476 mdelay(1); 477 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 478 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 479 mdelay(20); 480 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 481 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 482 rtw_err(rtwdev, "failed to wait for dack ready\n"); 483 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 484 mdelay(1); 485 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 486 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 487 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 488 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 489 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 490 } 491 492 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 493 u8 path, u32 *ic_out, u32 *qc_out) 494 { 495 u32 base_addr; 496 u32 ic, qc, ic_in, qc_in; 497 498 base_addr = rtw8822c_get_path_write_addr(path); 499 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 500 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 501 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 502 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 503 504 rtw_write32(rtwdev, 0x1b00, 0x00000008); 505 rtw_write8(rtwdev, 0x1bcc, 0x03f); 506 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 507 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 508 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 509 510 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 511 ic = ic_in; 512 qc = qc_in; 513 514 /* compensation value */ 515 if (ic != 0x0) 516 ic = 0x400 - ic; 517 if (qc != 0x0) 518 qc = 0x400 - qc; 519 if (ic < 0x300) { 520 ic = ic * 2 * 6 / 5; 521 ic = ic + 0x80; 522 } else { 523 ic = (0x400 - ic) * 2 * 6 / 5; 524 ic = 0x7f - ic; 525 } 526 if (qc < 0x300) { 527 qc = qc * 2 * 6 / 5; 528 qc = qc + 0x80; 529 } else { 530 qc = (0x400 - qc) * 2 * 6 / 5; 531 qc = 0x7f - qc; 532 } 533 534 *ic_out = ic; 535 *qc_out = qc; 536 537 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 538 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 539 } 540 541 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 542 u32 adc_ic, u32 adc_qc, 543 u32 *ic_in, u32 *qc_in, 544 u32 *i_out, u32 *q_out) 545 { 546 u32 base_addr; 547 u32 read_addr; 548 u32 ic, qc; 549 u32 temp; 550 551 base_addr = rtw8822c_get_path_write_addr(path); 552 read_addr = rtw8822c_get_path_read_addr(path); 553 ic = *ic_in; 554 qc = *qc_in; 555 556 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 557 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 558 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 559 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 560 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 561 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 562 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 563 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 564 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 565 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 566 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 567 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 568 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 569 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 570 mdelay(2); 571 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 572 mdelay(2); 573 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 574 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 575 mdelay(1); 576 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 577 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 578 mdelay(20); 579 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 580 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 581 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 582 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 583 mdelay(1); 584 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 585 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 586 587 /* check DAC DC offset */ 588 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 589 rtw_write32(rtwdev, base_addr + 0x68, temp); 590 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 591 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 592 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 593 if (ic >= 0x10) 594 ic = ic - 0x10; 595 else 596 ic = 0x400 - (0x10 - ic); 597 598 if (qc >= 0x10) 599 qc = qc - 0x10; 600 else 601 qc = 0x400 - (0x10 - qc); 602 603 *i_out = ic; 604 *q_out = qc; 605 606 if (ic >= 0x200) 607 ic = 0x400 - ic; 608 if (qc >= 0x200) 609 qc = 0x400 - qc; 610 611 *ic_in = ic; 612 *qc_in = qc; 613 614 rtw_dbg(rtwdev, RTW_DBG_RFK, 615 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 616 } 617 618 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 619 { 620 u32 base_addr = rtw8822c_get_path_write_addr(path); 621 622 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 623 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 624 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 625 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 626 } 627 628 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 629 u8 path, u8 vec, u32 w_addr, u32 r_addr) 630 { 631 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 632 u16 val; 633 u32 i; 634 635 if (WARN_ON(vec >= 2)) 636 return; 637 638 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 639 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 640 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 641 dm_info->dack_msbk[path][vec][i] = val; 642 } 643 } 644 645 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 646 { 647 u32 w_off = 0x1c; 648 u32 r_off = 0x2c; 649 u32 w_addr, r_addr; 650 651 if (WARN_ON(path >= 2)) 652 return; 653 654 /* backup I vector */ 655 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 656 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 657 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 658 659 /* backup Q vector */ 660 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 661 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 662 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 663 } 664 665 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 666 { 667 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 668 u8 val; 669 670 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 671 dm_info->dack_dck[RF_PATH_A][0][0] = val; 672 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 673 dm_info->dack_dck[RF_PATH_A][0][1] = val; 674 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 675 dm_info->dack_dck[RF_PATH_A][1][0] = val; 676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 677 dm_info->dack_dck[RF_PATH_A][1][1] = val; 678 679 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 680 dm_info->dack_dck[RF_PATH_B][0][0] = val; 681 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 682 dm_info->dack_dck[RF_PATH_B][1][0] = val; 683 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 684 dm_info->dack_dck[RF_PATH_B][0][1] = val; 685 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 686 dm_info->dack_dck[RF_PATH_B][1][1] = val; 687 } 688 689 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 690 { 691 u32 temp[3]; 692 693 temp[0] = rtw_read32(rtwdev, 0x1860); 694 temp[1] = rtw_read32(rtwdev, 0x4160); 695 temp[2] = rtw_read32(rtwdev, 0x9b4); 696 697 /* set clock */ 698 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 699 700 /* backup path-A I/Q */ 701 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 702 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 703 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 704 705 /* backup path-B I/Q */ 706 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 707 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 708 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 709 710 rtw8822c_dac_cal_backup_dck(rtwdev); 711 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 712 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 713 714 rtw_write32(rtwdev, 0x1860, temp[0]); 715 rtw_write32(rtwdev, 0x4160, temp[1]); 716 rtw_write32(rtwdev, 0x9b4, temp[2]); 717 } 718 719 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 720 { 721 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 722 u8 val; 723 724 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 725 val = dm_info->dack_dck[RF_PATH_A][0][0]; 726 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 727 val = dm_info->dack_dck[RF_PATH_A][0][1]; 728 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 729 730 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 731 val = dm_info->dack_dck[RF_PATH_A][1][0]; 732 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 733 val = dm_info->dack_dck[RF_PATH_A][1][1]; 734 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 735 736 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 737 val = dm_info->dack_dck[RF_PATH_B][0][0]; 738 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 739 val = dm_info->dack_dck[RF_PATH_B][0][1]; 740 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 741 742 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 743 val = dm_info->dack_dck[RF_PATH_B][1][0]; 744 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 745 val = dm_info->dack_dck[RF_PATH_B][1][1]; 746 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 747 } 748 749 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 750 { 751 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 752 753 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 754 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 755 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 756 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 757 758 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 759 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 760 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 761 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 762 763 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 764 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 765 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 766 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 767 768 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 769 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 770 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 771 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 772 773 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 774 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 775 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 776 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 777 778 rtw8822c_dac_cal_restore_dck(rtwdev); 779 780 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 781 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 782 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 783 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 784 785 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 786 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 787 788 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 789 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 790 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 791 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 792 793 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 794 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 795 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 796 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 797 798 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 799 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 800 } 801 802 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 803 u32 target_addr, u32 toggle_addr) 804 { 805 u32 cnt = 0; 806 807 do { 808 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 809 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 810 811 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 812 return true; 813 814 } while (cnt++ < 100); 815 816 return false; 817 } 818 819 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 820 { 821 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 822 u32 w_off = 0x1c; 823 u32 r_off = 0x2c; 824 u32 w_i, r_i, w_q, r_q; 825 u32 value; 826 u32 i; 827 828 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 829 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 830 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 831 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 832 833 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 834 return false; 835 836 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 837 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 838 value = dm_info->dack_msbk[path][0][i]; 839 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 840 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 842 } 843 844 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 845 846 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 847 return false; 848 849 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 850 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 851 value = dm_info->dack_msbk[path][1][i]; 852 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 853 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 854 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 855 } 856 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 857 858 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 859 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 860 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 861 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 862 863 return true; 864 } 865 866 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 867 { 868 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 869 return false; 870 871 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 872 return false; 873 874 return true; 875 } 876 877 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 878 { 879 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 880 u32 temp[3]; 881 882 /* sample the first element for both path's IQ vector */ 883 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 884 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 885 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 886 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 887 return false; 888 889 temp[0] = rtw_read32(rtwdev, 0x1860); 890 temp[1] = rtw_read32(rtwdev, 0x4160); 891 temp[2] = rtw_read32(rtwdev, 0x9b4); 892 893 rtw8822c_dac_cal_restore_prepare(rtwdev); 894 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 895 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 896 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 897 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 898 return false; 899 900 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 901 rtw_err(rtwdev, "failed to restore dack vectors\n"); 902 return false; 903 } 904 905 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 906 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 907 rtw_write32(rtwdev, 0x1860, temp[0]); 908 rtw_write32(rtwdev, 0x4160, temp[1]); 909 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 910 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 911 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 912 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 913 rtw_write32(rtwdev, 0x9b4, temp[2]); 914 915 return true; 916 } 917 918 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 919 { 920 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 921 struct rtw_backup_info backup[DACK_REG_8822C]; 922 u32 ic = 0, qc = 0, i; 923 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 924 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 925 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 926 927 if (rtw8822c_dac_cal_restore(rtwdev)) 928 return; 929 930 /* not able to restore, do it */ 931 932 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 933 934 rtw8822c_dac_bb_setting(rtwdev); 935 936 /* path-A */ 937 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 938 for (i = 0; i < 10; i++) { 939 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 940 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 941 ic_a = ic; 942 qc_a = qc; 943 944 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 945 &ic, &qc, &i_a, &q_a); 946 947 if (ic < 5 && qc < 5) 948 break; 949 } 950 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 951 952 /* path-B */ 953 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 954 for (i = 0; i < 10; i++) { 955 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 956 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 957 ic_b = ic; 958 qc_b = qc; 959 960 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 961 &ic, &qc, &i_b, &q_b); 962 963 if (ic < 5 && qc < 5) 964 break; 965 } 966 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 967 968 rtw_write32(rtwdev, 0x1b00, 0x00000008); 969 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 970 rtw_write8(rtwdev, 0x1bcc, 0x0); 971 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 972 rtw_write8(rtwdev, 0x1bcc, 0x0); 973 974 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 975 976 /* backup results to restore, saving a lot of time */ 977 rtw8822c_dac_cal_backup(rtwdev); 978 979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 980 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 981 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 982 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 983 } 984 985 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 986 { 987 u8 x2k_busy; 988 989 mdelay(1); 990 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 991 if (x2k_busy == 1) { 992 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 993 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 994 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 995 mdelay(1); 996 } 997 } 998 999 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8]) 1000 { 1001 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \ 1002 do { \ 1003 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ 1004 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ 1005 bb_gain[_path][_idx]); \ 1006 } while (0) 1007 u8 path; 1008 1009 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1010 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); 1011 RF_SET_POWER_TRIM(path, 0x0, 0); 1012 RF_SET_POWER_TRIM(path, 0x1, 1); 1013 RF_SET_POWER_TRIM(path, 0x2, 2); 1014 RF_SET_POWER_TRIM(path, 0x3, 2); 1015 RF_SET_POWER_TRIM(path, 0x4, 3); 1016 RF_SET_POWER_TRIM(path, 0x5, 4); 1017 RF_SET_POWER_TRIM(path, 0x6, 5); 1018 RF_SET_POWER_TRIM(path, 0x7, 6); 1019 RF_SET_POWER_TRIM(path, 0x8, 7); 1020 RF_SET_POWER_TRIM(path, 0x9, 3); 1021 RF_SET_POWER_TRIM(path, 0xa, 4); 1022 RF_SET_POWER_TRIM(path, 0xb, 5); 1023 RF_SET_POWER_TRIM(path, 0xc, 6); 1024 RF_SET_POWER_TRIM(path, 0xd, 7); 1025 RF_SET_POWER_TRIM(path, 0xe, 7); 1026 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); 1027 } 1028 #undef RF_SET_POWER_TRIM 1029 } 1030 1031 static void rtw8822c_power_trim(struct rtw_dev *rtwdev) 1032 { 1033 u8 pg_pwr = 0xff, i, path, idx; 1034 s8 bb_gain[2][8] = {}; 1035 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB}; 1036 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA, 1037 PPG_5GM2_TXA, PPG_5GH1_TXA}, 1038 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB, 1039 PPG_5GM2_TXB, PPG_5GH1_TXB} }; 1040 bool set = false; 1041 1042 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { 1043 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr); 1044 if (pg_pwr == EFUSE_READ_FAIL) 1045 continue; 1046 set = true; 1047 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr); 1048 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr); 1049 } 1050 1051 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { 1052 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1053 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i], 1054 &pg_pwr); 1055 if (pg_pwr == EFUSE_READ_FAIL) 1056 continue; 1057 set = true; 1058 idx = i + ARRAY_SIZE(rf_efuse_2g); 1059 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr); 1060 } 1061 } 1062 if (set) 1063 rtw8822c_set_power_trim(rtwdev, bb_gain); 1064 1065 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1066 } 1067 1068 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev) 1069 { 1070 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B}; 1071 u8 pg_therm = 0xff, thermal[2] = {0}, path; 1072 1073 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1074 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm); 1075 if (pg_therm == EFUSE_READ_FAIL) 1076 return; 1077 /* Efuse value of BIT(0) shall be move to BIT(3), and the value 1078 * of BIT(1) to BIT(3) should be right shifted 1 bit. 1079 */ 1080 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm); 1081 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); 1082 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); 1083 } 1084 } 1085 1086 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 1087 { 1088 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB}; 1089 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB}; 1090 u8 pg_pa_bias = 0xff, path; 1091 1092 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1093 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path], 1094 &pg_pa_bias); 1095 if (pg_pa_bias == EFUSE_READ_FAIL) 1096 return; 1097 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1098 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias); 1099 } 1100 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1101 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path], 1102 &pg_pa_bias); 1103 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1104 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias); 1105 } 1106 } 1107 1108 static void rtw8822c_rfk_handshake(struct rtw_dev *rtwdev, bool is_before_k) 1109 { 1110 struct rtw_dm_info *dm = &rtwdev->dm_info; 1111 u8 u1b_tmp; 1112 u8 u4b_tmp; 1113 int ret; 1114 1115 if (is_before_k) { 1116 rtw_dbg(rtwdev, RTW_DBG_RFK, 1117 "[RFK] WiFi / BT RFK handshake start!!\n"); 1118 1119 if (!dm->is_bt_iqk_timeout) { 1120 ret = read_poll_timeout(rtw_read32_mask, u4b_tmp, 1121 u4b_tmp == 0, 20, 600000, false, 1122 rtwdev, REG_PMC_DBG_CTRL1, 1123 BITS_PMC_BT_IQK_STS); 1124 if (ret) { 1125 rtw_dbg(rtwdev, RTW_DBG_RFK, 1126 "[RFK] Wait BT IQK finish timeout!!\n"); 1127 dm->is_bt_iqk_timeout = true; 1128 } 1129 } 1130 1131 rtw_fw_inform_rfk_status(rtwdev, true); 1132 1133 ret = read_poll_timeout(rtw_read8_mask, u1b_tmp, 1134 u1b_tmp == 1, 20, 100000, false, 1135 rtwdev, REG_ARFR4, BIT_WL_RFK); 1136 if (ret) 1137 rtw_dbg(rtwdev, RTW_DBG_RFK, 1138 "[RFK] Send WiFi RFK start H2C cmd FAIL!!\n"); 1139 } else { 1140 rtw_fw_inform_rfk_status(rtwdev, false); 1141 ret = read_poll_timeout(rtw_read8_mask, u1b_tmp, 1142 u1b_tmp == 1, 20, 100000, false, 1143 rtwdev, REG_ARFR4, 1144 BIT_WL_RFK); 1145 if (ret) 1146 rtw_dbg(rtwdev, RTW_DBG_RFK, 1147 "[RFK] Send WiFi RFK finish H2C cmd FAIL!!\n"); 1148 1149 rtw_dbg(rtwdev, RTW_DBG_RFK, 1150 "[RFK] WiFi / BT RFK handshake finish!!\n"); 1151 } 1152 } 1153 1154 static void rtw8822c_rfk_power_save(struct rtw_dev *rtwdev, 1155 bool is_power_save) 1156 { 1157 u8 path; 1158 1159 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1160 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1161 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_PS_EN, 1162 is_power_save ? 0 : 1); 1163 } 1164 } 1165 1166 static void rtw8822c_txgapk_backup_bb_reg(struct rtw_dev *rtwdev, const u32 reg[], 1167 u32 reg_backup[], u32 reg_num) 1168 { 1169 u32 i; 1170 1171 for (i = 0; i < reg_num; i++) { 1172 reg_backup[i] = rtw_read32(rtwdev, reg[i]); 1173 1174 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n", 1175 reg[i], reg_backup[i]); 1176 } 1177 } 1178 1179 static void rtw8822c_txgapk_reload_bb_reg(struct rtw_dev *rtwdev, 1180 const u32 reg[], u32 reg_backup[], 1181 u32 reg_num) 1182 { 1183 u32 i; 1184 1185 for (i = 0; i < reg_num; i++) { 1186 rtw_write32(rtwdev, reg[i], reg_backup[i]); 1187 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n", 1188 reg[i], reg_backup[i]); 1189 } 1190 } 1191 1192 static bool check_rf_status(struct rtw_dev *rtwdev, u8 status) 1193 { 1194 u8 reg_rf0_a, reg_rf0_b; 1195 1196 reg_rf0_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 1197 RF_MODE_TRXAGC, BIT_RF_MODE); 1198 reg_rf0_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 1199 RF_MODE_TRXAGC, BIT_RF_MODE); 1200 1201 if (reg_rf0_a == status || reg_rf0_b == status) 1202 return false; 1203 1204 return true; 1205 } 1206 1207 static void rtw8822c_txgapk_tx_pause(struct rtw_dev *rtwdev) 1208 { 1209 bool status; 1210 int ret; 1211 1212 rtw_write8(rtwdev, REG_TXPAUSE, BIT_AC_QUEUE); 1213 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2); 1214 1215 ret = read_poll_timeout_atomic(check_rf_status, status, status, 1216 2, 5000, false, rtwdev, 2); 1217 if (ret) 1218 rtw_warn(rtwdev, "failed to pause TX\n"); 1219 1220 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Tx pause!!\n"); 1221 } 1222 1223 static void rtw8822c_txgapk_bb_dpk(struct rtw_dev *rtwdev, u8 path) 1224 { 1225 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1226 1227 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1); 1228 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, 1229 BIT_IQK_DPK_CLOCK_SRC, 0x1); 1230 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, 1231 BIT_IQK_DPK_RESET_SRC, 0x1); 1232 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1); 1233 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0); 1234 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff); 1235 1236 if (path == RF_PATH_A) { 1237 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A, 1238 BIT_RFTXEN_GCK_FORCE_ON, 0x1); 1239 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1); 1240 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A, 1241 BIT_TX_SCALE_0DB, 0x1); 1242 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0); 1243 } else if (path == RF_PATH_B) { 1244 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B, 1245 BIT_RFTXEN_GCK_FORCE_ON, 0x1); 1246 rtw_write32_mask(rtwdev, REG_3WIRE2, 1247 BIT_DIS_SHARERX_TXGAT, 0x1); 1248 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B, 1249 BIT_TX_SCALE_0DB, 0x1); 1250 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0); 1251 } 1252 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2); 1253 } 1254 1255 static void rtw8822c_txgapk_afe_dpk(struct rtw_dev *rtwdev, u8 path) 1256 { 1257 u32 reg; 1258 1259 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1260 1261 if (path == RF_PATH_A) { 1262 reg = REG_ANAPAR_A; 1263 } else if (path == RF_PATH_B) { 1264 reg = REG_ANAPAR_B; 1265 } else { 1266 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path); 1267 return; 1268 } 1269 1270 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, MASKDWORD); 1271 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); 1272 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); 1273 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001); 1274 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001); 1275 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001); 1276 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001); 1277 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001); 1278 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001); 1279 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001); 1280 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001); 1281 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001); 1282 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001); 1283 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001); 1284 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001); 1285 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001); 1286 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001); 1287 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); 1288 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); 1289 } 1290 1291 static void rtw8822c_txgapk_afe_dpk_restore(struct rtw_dev *rtwdev, u8 path) 1292 { 1293 u32 reg; 1294 1295 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1296 1297 if (path == RF_PATH_A) { 1298 reg = REG_ANAPAR_A; 1299 } else if (path == RF_PATH_B) { 1300 reg = REG_ANAPAR_B; 1301 } else { 1302 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path); 1303 return; 1304 } 1305 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e); 1306 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041); 1307 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041); 1308 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041); 1309 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041); 1310 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041); 1311 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041); 1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041); 1313 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041); 1314 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041); 1315 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041); 1316 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041); 1317 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041); 1318 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041); 1319 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041); 1320 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041); 1321 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041); 1322 } 1323 1324 static void rtw8822c_txgapk_bb_dpk_restore(struct rtw_dev *rtwdev, u8 path) 1325 { 1326 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1327 1328 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0); 1329 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0); 1330 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0); 1331 1332 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); 1333 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1334 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1335 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); 1336 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1); 1337 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1338 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1339 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); 1340 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); 1341 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0); 1342 1343 if (path == RF_PATH_A) { 1344 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A, 1345 BIT_RFTXEN_GCK_FORCE_ON, 0x0); 1346 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0); 1347 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A, 1348 BIT_TX_SCALE_0DB, 0x0); 1349 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3); 1350 } else if (path == RF_PATH_B) { 1351 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B, 1352 BIT_RFTXEN_GCK_FORCE_ON, 0x0); 1353 rtw_write32_mask(rtwdev, REG_3WIRE2, 1354 BIT_DIS_SHARERX_TXGAT, 0x0); 1355 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B, 1356 BIT_TX_SCALE_0DB, 0x0); 1357 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3); 1358 } 1359 1360 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0); 1361 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5); 1362 } 1363 1364 static bool _rtw8822c_txgapk_gain_valid(struct rtw_dev *rtwdev, u32 gain) 1365 { 1366 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) && 1367 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe)) 1368 return true; 1369 1370 return false; 1371 } 1372 1373 static void _rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev, 1374 u8 band, u8 path) 1375 { 1376 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1377 u32 v, tmp_3f = 0; 1378 u8 gain, check_txgain; 1379 1380 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1381 1382 switch (band) { 1383 case RF_BAND_2G_OFDM: 1384 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); 1385 break; 1386 case RF_BAND_5G_L: 1387 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); 1388 break; 1389 case RF_BAND_5G_M: 1390 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); 1391 break; 1392 case RF_BAND_5G_H: 1393 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); 1394 break; 1395 default: 1396 break; 1397 } 1398 1399 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88); 1400 1401 check_txgain = 0; 1402 for (gain = 0; gain < RF_GAIN_NUM; gain++) { 1403 v = txgapk->rf3f_bp[band][gain][path]; 1404 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) { 1405 if (!check_txgain) { 1406 tmp_3f = txgapk->rf3f_bp[band][gain][path]; 1407 check_txgain = 1; 1408 } 1409 rtw_dbg(rtwdev, RTW_DBG_RFK, 1410 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", 1411 txgapk->rf3f_bp[band][gain][path]); 1412 } else { 1413 tmp_3f = txgapk->rf3f_bp[band][gain][path]; 1414 } 1415 1416 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN, tmp_3f); 1417 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_I_GAIN, gain); 1418 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1); 1419 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0); 1420 1421 rtw_dbg(rtwdev, RTW_DBG_RFK, 1422 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n", 1423 band, tmp_3f, path); 1424 } 1425 } 1426 1427 static void rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev) 1428 { 1429 u8 path, band; 1430 1431 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n", 1432 __func__, rtwdev->dm_info.gapk.channel); 1433 1434 for (band = 0; band < RF_BAND_MAX; band++) { 1435 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1436 _rtw8822c_txgapk_write_gain_bb_table(rtwdev, 1437 band, path); 1438 } 1439 } 1440 } 1441 1442 static void rtw8822c_txgapk_read_offset(struct rtw_dev *rtwdev, u8 path) 1443 { 1444 static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a}; 1445 static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b}; 1446 static const u32 set_pi[2] = {REG_RSV_CTRL, REG_WLRF1}; 1447 static const u32 path_setting[2] = {REG_ORITXCODE, REG_ORITXCODE2}; 1448 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1449 u8 channel = txgapk->channel; 1450 u32 val; 1451 int i; 1452 1453 if (path >= ARRAY_SIZE(cfg1_1b00) || 1454 path >= ARRAY_SIZE(cfg2_1b00) || 1455 path >= ARRAY_SIZE(set_pi) || 1456 path >= ARRAY_SIZE(path_setting)) { 1457 rtw_warn(rtwdev, "[TXGAPK] wrong path %d\n", path); 1458 return; 1459 } 1460 1461 rtw_write32_mask(rtwdev, REG_ANTMAP0, BIT_ANT_PATH, path + 1); 1462 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000); 1463 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3); 1464 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312); 1465 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1); 1466 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0); 1467 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1); 1468 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820); 1469 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1470 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); 1471 1472 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018); 1473 fsleep(1000); 1474 if (channel >= 1 && channel <= 14) 1475 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_2G_SWING); 1476 else 1477 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_5G_SWING); 1478 fsleep(1000); 1479 1480 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg1_1b00[path]); 1481 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg2_1b00[path]); 1482 1483 read_poll_timeout(rtw_read32_mask, val, 1484 val == 0x55, 1000, 100000, false, 1485 rtwdev, REG_RPT_CIP, BIT_RPT_CIP_STATUS); 1486 1487 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2); 1488 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1489 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1); 1490 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12); 1491 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3); 1492 val = rtw_read32(rtwdev, REG_STAT_RPT); 1493 1494 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); 1495 txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val); 1496 txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val); 1497 txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val); 1498 txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val); 1499 txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val); 1500 txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val); 1501 txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val); 1502 1503 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4); 1504 val = rtw_read32(rtwdev, REG_STAT_RPT); 1505 1506 txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); 1507 txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val); 1508 1509 for (i = 0; i < RF_HW_OFFSET_NUM; i++) 1510 if (txgapk->offset[i][path] & BIT(3)) 1511 txgapk->offset[i][path] = txgapk->offset[i][path] | 1512 0xf0; 1513 for (i = 0; i < RF_HW_OFFSET_NUM; i++) 1514 rtw_dbg(rtwdev, RTW_DBG_RFK, 1515 "[TXGAPK] offset %d %d path=%d\n", 1516 txgapk->offset[i][path], i, path); 1517 } 1518 1519 static void rtw8822c_txgapk_calculate_offset(struct rtw_dev *rtwdev, u8 path) 1520 { 1521 static const u32 bb_reg[] = {REG_ANTMAP0, REG_TXLGMAP, REG_TXANTSEG, 1522 REG_ORITXCODE, REG_ORITXCODE2}; 1523 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1524 u8 channel = txgapk->channel; 1525 u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0}; 1526 1527 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n", 1528 __func__, channel); 1529 1530 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg, 1531 reg_backup, ARRAY_SIZE(bb_reg)); 1532 1533 if (channel >= 1 && channel <= 14) { 1534 rtw_write32_mask(rtwdev, 1535 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1536 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1537 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); 1538 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1539 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 1540 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f); 1541 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0); 1542 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1); 1543 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f); 1544 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 1545 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 1546 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 1547 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); 1548 1549 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00); 1550 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); 1551 1552 rtw8822c_txgapk_read_offset(rtwdev, path); 1553 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n"); 1554 1555 } else { 1556 rtw_write32_mask(rtwdev, 1557 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1558 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1559 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); 1560 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1561 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 1562 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011); 1563 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3); 1564 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3); 1565 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 1566 rtw_write_rf(rtwdev, path, 1567 RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2); 1568 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12); 1569 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 1571 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); 1572 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5); 1573 1574 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); 1575 1576 if (channel >= 36 && channel <= 64) 1577 rtw_write32_mask(rtwdev, 1578 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); 1579 else if (channel >= 100 && channel <= 144) 1580 rtw_write32_mask(rtwdev, 1581 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); 1582 else if (channel >= 149 && channel <= 177) 1583 rtw_write32_mask(rtwdev, 1584 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); 1585 1586 rtw8822c_txgapk_read_offset(rtwdev, path); 1587 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n"); 1588 } 1589 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg, 1590 reg_backup, ARRAY_SIZE(bb_reg)); 1591 } 1592 1593 static void rtw8822c_txgapk_rf_restore(struct rtw_dev *rtwdev, u8 path) 1594 { 1595 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1596 1597 if (path >= rtwdev->hal.rf_path_num) 1598 return; 1599 1600 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3); 1601 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0); 1602 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0); 1603 } 1604 1605 static u32 rtw8822c_txgapk_cal_gain(struct rtw_dev *rtwdev, u32 gain, s8 offset) 1606 { 1607 u32 gain_x2, new_gain; 1608 1609 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1610 1611 if (_rtw8822c_txgapk_gain_valid(rtwdev, gain)) { 1612 new_gain = gain; 1613 rtw_dbg(rtwdev, RTW_DBG_RFK, 1614 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n", 1615 gain, offset, new_gain); 1616 return new_gain; 1617 } 1618 1619 gain_x2 = (gain << 1) + offset; 1620 new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0); 1621 1622 rtw_dbg(rtwdev, RTW_DBG_RFK, 1623 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n", 1624 gain, offset, new_gain); 1625 1626 return new_gain; 1627 } 1628 1629 static void rtw8822c_txgapk_write_tx_gain(struct rtw_dev *rtwdev) 1630 { 1631 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1632 u32 i, j, tmp = 0x20, tmp_3f, v; 1633 s8 offset_tmp[RF_GAIN_NUM] = {0}; 1634 u8 path, band = RF_BAND_2G_OFDM, channel = txgapk->channel; 1635 1636 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1637 1638 if (channel >= 1 && channel <= 14) { 1639 tmp = 0x20; 1640 band = RF_BAND_2G_OFDM; 1641 } else if (channel >= 36 && channel <= 64) { 1642 tmp = 0x200; 1643 band = RF_BAND_5G_L; 1644 } else if (channel >= 100 && channel <= 144) { 1645 tmp = 0x280; 1646 band = RF_BAND_5G_M; 1647 } else if (channel >= 149 && channel <= 177) { 1648 tmp = 0x300; 1649 band = RF_BAND_5G_H; 1650 } else { 1651 rtw_err(rtwdev, "[TXGAPK] unknown channel %d!!\n", channel); 1652 return; 1653 } 1654 1655 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1656 for (i = 0; i < RF_GAIN_NUM; i++) { 1657 offset_tmp[i] = 0; 1658 for (j = i; j < RF_GAIN_NUM; j++) { 1659 v = txgapk->rf3f_bp[band][j][path]; 1660 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) 1661 continue; 1662 1663 offset_tmp[i] += txgapk->offset[j][path]; 1664 txgapk->fianl_offset[i][path] = offset_tmp[i]; 1665 } 1666 1667 v = txgapk->rf3f_bp[band][i][path]; 1668 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) { 1669 rtw_dbg(rtwdev, RTW_DBG_RFK, 1670 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", 1671 txgapk->rf3f_bp[band][i][path]); 1672 } else { 1673 txgapk->rf3f_fs[path][i] = offset_tmp[i]; 1674 rtw_dbg(rtwdev, RTW_DBG_RFK, 1675 "[TXGAPK] offset %d %d\n", 1676 offset_tmp[i], i); 1677 } 1678 } 1679 1680 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000); 1681 for (i = 0; i < RF_GAIN_NUM; i++) { 1682 rtw_write_rf(rtwdev, path, 1683 RF_LUTWA, RFREG_MASK, tmp + i); 1684 1685 tmp_3f = rtw8822c_txgapk_cal_gain(rtwdev, 1686 txgapk->rf3f_bp[band][i][path], 1687 offset_tmp[i]); 1688 rtw_write_rf(rtwdev, path, RF_LUTWD0, 1689 BIT_GAIN_EXT | BIT_DATA_L, tmp_3f); 1690 1691 rtw_dbg(rtwdev, RTW_DBG_RFK, 1692 "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n", 1693 tmp + i, tmp_3f); 1694 } 1695 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0); 1696 } 1697 } 1698 1699 static void rtw8822c_txgapk_save_all_tx_gain_table(struct rtw_dev *rtwdev) 1700 { 1701 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1702 static const u32 three_wire[2] = {REG_3WIRE, REG_3WIRE2}; 1703 static const u8 ch_num[RF_BAND_MAX] = {1, 1, 36, 100, 149}; 1704 static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5}; 1705 static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0}; 1706 u8 path, band, gain, rf0_idx; 1707 u32 rf18, v; 1708 1709 if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK)) 1710 return; 1711 1712 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1713 1714 if (txgapk->read_txgain == 1) { 1715 rtw_dbg(rtwdev, RTW_DBG_RFK, 1716 "[TXGAPK] Already Read txgapk->read_txgain return!!!\n"); 1717 rtw8822c_txgapk_write_gain_bb_table(rtwdev); 1718 return; 1719 } 1720 1721 for (band = 0; band < RF_BAND_MAX; band++) { 1722 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1723 rf18 = rtw_read_rf(rtwdev, path, RF_CFGCH, RFREG_MASK); 1724 1725 rtw_write32_mask(rtwdev, 1726 three_wire[path], BIT_3WIRE_EN, 0x0); 1727 rtw_write_rf(rtwdev, path, 1728 RF_CFGCH, MASKBYTE0, ch_num[band]); 1729 rtw_write_rf(rtwdev, path, 1730 RF_CFGCH, BIT_BAND, band_num[band]); 1731 rtw_write_rf(rtwdev, path, 1732 RF_BW_TRXBB, BIT_DBG_CCK_CCA, cck[band]); 1733 rtw_write_rf(rtwdev, path, 1734 RF_BW_TRXBB, BIT_TX_CCK_IND, cck[band]); 1735 gain = 0; 1736 for (rf0_idx = 1; rf0_idx < 32; rf0_idx += 3) { 1737 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, 1738 MASKBYTE0, rf0_idx); 1739 v = rtw_read_rf(rtwdev, path, 1740 RF_TX_RESULT, RFREG_MASK); 1741 txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L; 1742 1743 rtw_dbg(rtwdev, RTW_DBG_RFK, 1744 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n", 1745 txgapk->rf3f_bp[band][gain][path], 1746 band, path); 1747 gain++; 1748 } 1749 rtw_write_rf(rtwdev, path, RF_CFGCH, RFREG_MASK, rf18); 1750 rtw_write32_mask(rtwdev, 1751 three_wire[path], BIT_3WIRE_EN, 0x3); 1752 } 1753 } 1754 rtw8822c_txgapk_write_gain_bb_table(rtwdev); 1755 txgapk->read_txgain = 1; 1756 } 1757 1758 static void rtw8822c_txgapk(struct rtw_dev *rtwdev) 1759 { 1760 static const u32 bb_reg[2] = {REG_TX_PTCL_CTRL, REG_TX_FIFO}; 1761 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1762 u32 bb_reg_backup[2]; 1763 u8 path; 1764 1765 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1766 1767 rtw8822c_txgapk_save_all_tx_gain_table(rtwdev); 1768 1769 if (txgapk->read_txgain == 0) { 1770 rtw_dbg(rtwdev, RTW_DBG_RFK, 1771 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n"); 1772 return; 1773 } 1774 1775 if (rtwdev->efuse.power_track_type >= 4 && 1776 rtwdev->efuse.power_track_type <= 7) { 1777 rtw_dbg(rtwdev, RTW_DBG_RFK, 1778 "[TXGAPK] Normal Mode in TSSI mode. return!!!\n"); 1779 return; 1780 } 1781 1782 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg, 1783 bb_reg_backup, ARRAY_SIZE(bb_reg)); 1784 rtw8822c_txgapk_tx_pause(rtwdev); 1785 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1786 txgapk->channel = rtw_read_rf(rtwdev, path, 1787 RF_CFGCH, RFREG_MASK) & MASKBYTE0; 1788 rtw8822c_txgapk_bb_dpk(rtwdev, path); 1789 rtw8822c_txgapk_afe_dpk(rtwdev, path); 1790 rtw8822c_txgapk_calculate_offset(rtwdev, path); 1791 rtw8822c_txgapk_rf_restore(rtwdev, path); 1792 rtw8822c_txgapk_afe_dpk_restore(rtwdev, path); 1793 rtw8822c_txgapk_bb_dpk_restore(rtwdev, path); 1794 } 1795 rtw8822c_txgapk_write_tx_gain(rtwdev); 1796 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg, 1797 bb_reg_backup, ARRAY_SIZE(bb_reg)); 1798 } 1799 1800 static void rtw8822c_do_gapk(struct rtw_dev *rtwdev) 1801 { 1802 struct rtw_dm_info *dm = &rtwdev->dm_info; 1803 1804 if (dm->dm_flags & BIT(RTW_DM_CAP_TXGAPK)) { 1805 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] feature disable!!!\n"); 1806 return; 1807 } 1808 rtw8822c_rfk_handshake(rtwdev, true); 1809 rtw8822c_txgapk(rtwdev); 1810 rtw8822c_rfk_handshake(rtwdev, false); 1811 } 1812 1813 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1814 { 1815 rtw8822c_rf_dac_cal(rtwdev); 1816 rtw8822c_rf_x2_check(rtwdev); 1817 rtw8822c_thermal_trim(rtwdev); 1818 rtw8822c_power_trim(rtwdev); 1819 rtw8822c_pa_bias(rtwdev); 1820 } 1821 1822 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1823 { 1824 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1825 u8 path; 1826 1827 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1828 dm_info->delta_power_index[path] = 0; 1829 ewma_thermal_init(&dm_info->avg_thermal[path]); 1830 dm_info->thermal_avg[path] = 0xff; 1831 } 1832 1833 dm_info->pwr_trk_triggered = false; 1834 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1835 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k; 1836 } 1837 1838 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1839 { 1840 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1841 struct rtw_hal *hal = &rtwdev->hal; 1842 u8 crystal_cap; 1843 u8 cck_gi_u_bnd_msb = 0; 1844 u8 cck_gi_u_bnd_lsb = 0; 1845 u8 cck_gi_l_bnd_msb = 0; 1846 u8 cck_gi_l_bnd_lsb = 0; 1847 bool is_tx2_path; 1848 1849 /* power on BB/RF domain */ 1850 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1851 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1852 rtw_write8_set(rtwdev, REG_RF_CTRL, 1853 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1854 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1855 1856 /* disable low rate DPD */ 1857 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1858 1859 /* pre init before header files config */ 1860 rtw8822c_header_file_init(rtwdev, true); 1861 1862 rtw_phy_load_tables(rtwdev); 1863 1864 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1865 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1866 crystal_cap | (crystal_cap << 7)); 1867 1868 /* post init after header files config */ 1869 rtw8822c_header_file_init(rtwdev, false); 1870 1871 is_tx2_path = false; 1872 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1873 is_tx2_path); 1874 rtw_phy_init(rtwdev); 1875 1876 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1877 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1878 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1879 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1880 1881 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1882 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1883 1884 rtw8822c_rf_init(rtwdev); 1885 rtw8822c_pwrtrack_init(rtwdev); 1886 1887 rtw_bf_phy_init(rtwdev); 1888 } 1889 1890 #define WLAN_TXQ_RPT_EN 0x1F 1891 #define WLAN_SLOT_TIME 0x09 1892 #define WLAN_PIFS_TIME 0x1C 1893 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1894 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1895 #define WLAN_SIFS_CCK_TRX 0x0A 1896 #define WLAN_SIFS_OFDM_TRX 0x10 1897 #define WLAN_NAV_MAX 0xC8 1898 #define WLAN_RDG_NAV 0x05 1899 #define WLAN_TXOP_NAV 0x1B 1900 #define WLAN_CCK_RX_TSF 0x30 1901 #define WLAN_OFDM_RX_TSF 0x30 1902 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1903 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1904 #define WLAN_DRV_EARLY_INT 0x04 1905 #define WLAN_BCN_CTRL_CLT0 0x10 1906 #define WLAN_BCN_DMA_TIME 0x02 1907 #define WLAN_BCN_MAX_ERR 0xFF 1908 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1909 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1910 #define WLAN_SIFS_CCK_CTX 0x0A 1911 #define WLAN_SIFS_CCK_IRX 0x0A 1912 #define WLAN_SIFS_OFDM_CTX 0x0E 1913 #define WLAN_SIFS_OFDM_IRX 0x0E 1914 #define WLAN_EIFS_DUR_TUNE 0x40 1915 #define WLAN_EDCA_VO_PARAM 0x002FA226 1916 #define WLAN_EDCA_VI_PARAM 0x005EA328 1917 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1918 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1919 1920 #define WLAN_RX_FILTER0 0xFFFFFFFF 1921 #define WLAN_RX_FILTER2 0xFFFF 1922 #define WLAN_RCR_CFG 0xE400220E 1923 #define WLAN_RXPKT_MAX_SZ 12288 1924 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1925 1926 #define WLAN_AMPDU_MAX_TIME 0x70 1927 #define WLAN_RTS_LEN_TH 0xFF 1928 #define WLAN_RTS_TX_TIME_TH 0x08 1929 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1930 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1931 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1932 #define FAST_EDCA_VO_TH 0x06 1933 #define FAST_EDCA_VI_TH 0x06 1934 #define FAST_EDCA_BE_TH 0x06 1935 #define FAST_EDCA_BK_TH 0x06 1936 #define WLAN_BAR_RETRY_LIMIT 0x01 1937 #define WLAN_BAR_ACK_TYPE 0x05 1938 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1939 #define WLAN_RESP_TXRATE 0x84 1940 #define WLAN_ACK_TO 0x21 1941 #define WLAN_ACK_TO_CCK 0x6A 1942 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1943 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1944 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1945 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1946 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1947 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1948 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1949 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1950 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1951 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1952 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1953 #define WLAN_MULTI_ADDR 0xFFFFFFFF 1954 1955 #define WLAN_TX_FUNC_CFG1 0x30 1956 #define WLAN_TX_FUNC_CFG2 0x30 1957 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1958 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1959 #define WLAN_MAC_OPT_FUNC2 0x30810041 1960 #define WLAN_MAC_INT_MIG_CFG 0x33330000 1961 1962 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1963 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1964 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1965 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1966 1967 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1968 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1969 1970 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1971 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1972 1973 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1974 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1975 1976 #define MAC_CLK_SPEED 80 /* 80M */ 1977 #define EFUSE_PCB_INFO_OFFSET 0xCA 1978 1979 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1980 { 1981 u8 value8; 1982 u16 value16; 1983 u32 value32; 1984 u16 pre_txcnt; 1985 1986 /* txq control */ 1987 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1988 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1989 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1990 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1991 /* sifs control */ 1992 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1993 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1994 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1995 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1996 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1997 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1998 /* rate fallback control */ 1999 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 2000 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 2001 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 2002 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 2003 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 2004 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 2005 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 2006 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 2007 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 2008 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 2009 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 2010 /* protocol configuration */ 2011 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 2012 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 2013 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 2014 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 2015 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 2016 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 2017 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 2018 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 2019 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 2020 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 2021 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 2022 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 2023 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 2024 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 2025 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 2026 /* close BA parser */ 2027 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 2028 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 2029 2030 /* EDCA configuration */ 2031 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 2032 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 2033 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 2034 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 2035 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 2036 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 2037 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 2038 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 2039 BIT_DIS_STBC_CFE) >> 8); 2040 2041 /* MAC clock configuration */ 2042 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 2043 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 2044 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 2045 2046 rtw_write8_set(rtwdev, REG_MISC_CTRL, 2047 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 2048 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 2049 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 2050 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 2051 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 2052 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 2053 /* Set beacon cotnrol - enable TSF and other related functions */ 2054 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2055 /* Set send beacon related registers */ 2056 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 2057 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 2058 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 2059 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 2060 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 2061 2062 /* WMAC configuration */ 2063 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 2064 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 2065 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 2066 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 2067 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 2068 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 2069 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 2070 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 2071 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 2072 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 2073 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 2074 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 2075 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 2076 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 2077 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 2078 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 2079 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 2080 2081 /* init low power */ 2082 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 2083 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 2084 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 2085 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 2086 value16 = 0; 2087 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 2088 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 2089 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 2090 | BIT_RXPSF_OFDMRST; 2091 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 2092 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 2093 /* rx ignore configuration */ 2094 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 2095 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 2096 BIT_RXPSF_CONT_ERRCHKEN); 2097 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 2098 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 2099 2100 /* Interrupt migration configuration */ 2101 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 2102 2103 return 0; 2104 } 2105 2106 static void rtw8822c_dump_fw_crash(struct rtw_dev *rtwdev) 2107 { 2108 rtw_dump_reg(rtwdev, 0x0, 0x2000, "rtw8822c reg_"); 2109 rtw_dump_fw(rtwdev, OCPBASE_DMEM_88XX, 0x10000, "rtw8822c DMEM_"); 2110 rtw_dump_fw(rtwdev, OCPBASE_IMEM_88XX, 0x10000, "rtw8822c IMEM_"); 2111 rtw_dump_fw(rtwdev, OCPBASE_EMEM_88XX, 0x20000, "rtw8822c EMEM_"); 2112 rtw_dump_fw(rtwdev, OCPBASE_ROM_88XX, 0x10000, "rtw8822c ROM_"); 2113 } 2114 2115 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 2116 { 2117 if (enable) { 2118 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 2119 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 2120 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 2121 } else { 2122 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 2123 } 2124 } 2125 2126 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 2127 { 2128 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 2129 #define RF18_BAND_2G (0) 2130 #define RF18_BAND_5G (BIT(16) | BIT(8)) 2131 #define RF18_CHANNEL_MASK (MASKBYTE0) 2132 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 2133 #define RF18_RFSI_GE_CH80 (BIT(17)) 2134 #define RF18_RFSI_GT_CH140 (BIT(18)) 2135 #define RF18_BW_MASK (BIT(13) | BIT(12)) 2136 #define RF18_BW_20M (BIT(13) | BIT(12)) 2137 #define RF18_BW_40M (BIT(13)) 2138 #define RF18_BW_80M (BIT(12)) 2139 2140 u32 rf_reg18 = 0; 2141 u32 rf_rxbb = 0; 2142 2143 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2144 2145 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 2146 RF18_BW_MASK); 2147 2148 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 2149 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 2150 if (IS_CH_5G_BAND_4(channel)) 2151 rf_reg18 |= RF18_RFSI_GT_CH140; 2152 else if (IS_CH_5G_BAND_3(channel)) 2153 rf_reg18 |= RF18_RFSI_GE_CH80; 2154 2155 switch (bw) { 2156 case RTW_CHANNEL_WIDTH_5: 2157 case RTW_CHANNEL_WIDTH_10: 2158 case RTW_CHANNEL_WIDTH_20: 2159 default: 2160 rf_reg18 |= RF18_BW_20M; 2161 rf_rxbb = 0x18; 2162 break; 2163 case RTW_CHANNEL_WIDTH_40: 2164 /* RF bandwidth */ 2165 rf_reg18 |= RF18_BW_40M; 2166 rf_rxbb = 0x10; 2167 break; 2168 case RTW_CHANNEL_WIDTH_80: 2169 rf_reg18 |= RF18_BW_80M; 2170 rf_rxbb = 0x8; 2171 break; 2172 } 2173 2174 rtw8822c_rstb_3wire(rtwdev, false); 2175 2176 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 2177 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 2178 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 2179 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 2180 2181 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 2182 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 2183 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 2184 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 2185 2186 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 2187 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 2188 2189 rtw8822c_rstb_3wire(rtwdev, true); 2190 } 2191 2192 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 2193 { 2194 u32 igi; 2195 2196 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 2197 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 2198 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 2199 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 2200 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 2201 } 2202 2203 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 2204 u8 primary_ch_idx) 2205 { 2206 if (IS_CH_2G_BAND(channel)) { 2207 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 2208 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 2209 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 2210 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 2211 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 2212 2213 switch (bw) { 2214 case RTW_CHANNEL_WIDTH_20: 2215 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 2216 0x5); 2217 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 2218 0x5); 2219 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2220 0x6); 2221 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2222 0x6); 2223 break; 2224 case RTW_CHANNEL_WIDTH_40: 2225 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 2226 0x4); 2227 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 2228 0x4); 2229 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2230 0x0); 2231 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2232 0x0); 2233 break; 2234 } 2235 if (channel == 13 || channel == 14) 2236 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 2237 else if (channel == 11 || channel == 12) 2238 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 2239 else 2240 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 2241 if (channel == 14) { 2242 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 2243 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 2244 0x4962c931); 2245 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 2246 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 2247 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 2248 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 2249 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 2250 0xff012455); 2251 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 2252 } else { 2253 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 2254 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 2255 0x3e18fec8); 2256 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 2257 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 2258 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 2259 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 2260 0x00faf0de); 2261 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 2262 0x00122344); 2263 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 2264 0x0fffffff); 2265 } 2266 if (channel == 13) 2267 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 2268 else 2269 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 2270 } else if (IS_CH_5G_BAND(channel)) { 2271 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 2272 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 2273 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 2274 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 2275 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 2276 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 2277 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 2278 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2279 0x1); 2280 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2281 0x1); 2282 } else if (IS_CH_5G_BAND_3(channel)) { 2283 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2284 0x2); 2285 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2286 0x2); 2287 } else if (IS_CH_5G_BAND_4(channel)) { 2288 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2289 0x3); 2290 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2291 0x3); 2292 } 2293 2294 if (channel >= 36 && channel <= 51) 2295 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 2296 else if (channel >= 52 && channel <= 55) 2297 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 2298 else if (channel >= 56 && channel <= 111) 2299 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 2300 else if (channel >= 112 && channel <= 119) 2301 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 2302 else if (channel >= 120 && channel <= 172) 2303 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 2304 else if (channel >= 173 && channel <= 177) 2305 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 2306 } 2307 2308 switch (bw) { 2309 case RTW_CHANNEL_WIDTH_20: 2310 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 2311 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2312 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 2313 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 2314 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 2315 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2316 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2317 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2318 break; 2319 case RTW_CHANNEL_WIDTH_40: 2320 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 2321 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 2322 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 2323 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 2324 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 2325 (primary_ch_idx | (primary_ch_idx << 4))); 2326 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 2327 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2328 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 2329 break; 2330 case RTW_CHANNEL_WIDTH_80: 2331 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 2332 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 2333 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 2334 (primary_ch_idx | (primary_ch_idx << 4))); 2335 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 2336 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 2337 break; 2338 case RTW_CHANNEL_WIDTH_5: 2339 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 2340 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2341 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 2342 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 2343 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 2344 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2345 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2346 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2347 break; 2348 case RTW_CHANNEL_WIDTH_10: 2349 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 2350 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2351 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 2352 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 2353 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 2354 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2355 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2356 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2357 break; 2358 } 2359 } 2360 2361 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 2362 u8 primary_chan_idx) 2363 { 2364 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 2365 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 2366 rtw8822c_set_channel_rf(rtwdev, channel, bw); 2367 rtw8822c_toggle_igi(rtwdev); 2368 } 2369 2370 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2371 { 2372 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 2373 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 2374 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 2375 } else if (rx_path == BB_PATH_AB) { 2376 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 2377 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 2378 } 2379 2380 if (rx_path == BB_PATH_A) 2381 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 2382 else if (rx_path == BB_PATH_B) 2383 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 2384 else if (rx_path == BB_PATH_AB) 2385 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 2386 } 2387 2388 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2389 { 2390 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 2391 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 2392 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 2393 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 2394 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 2395 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 2396 } else if (rx_path == BB_PATH_AB) { 2397 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 2398 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 2399 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 2400 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 2401 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 2402 } 2403 2404 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 2405 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 2406 } 2407 2408 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2409 { 2410 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 2411 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 2412 } 2413 2414 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2415 bool is_tx2_path) 2416 { 2417 if (tx_path == BB_PATH_A) { 2418 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 2419 } else if (tx_path == BB_PATH_B) { 2420 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 2421 } else { 2422 if (is_tx2_path) 2423 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 2424 else 2425 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 2426 } 2427 } 2428 2429 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2430 bool is_tx2_path) 2431 { 2432 if (tx_path == BB_PATH_A) { 2433 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 2434 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 2435 } else if (tx_path == BB_PATH_B) { 2436 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 2437 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 2438 } else { 2439 if (is_tx2_path) { 2440 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 2441 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 2442 } else { 2443 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 2444 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 2445 } 2446 } 2447 } 2448 2449 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2450 bool is_tx2_path) 2451 { 2452 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 2453 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 2454 } 2455 2456 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 2457 u8 rx_path, bool is_tx2_path) 2458 { 2459 if ((tx_path | rx_path) & BB_PATH_A) 2460 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 2461 else 2462 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 2463 if ((tx_path | rx_path) & BB_PATH_B) 2464 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 2465 else 2466 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 2467 2468 rtw8822c_config_rx_path(rtwdev, rx_path); 2469 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 2470 2471 rtw8822c_toggle_igi(rtwdev); 2472 } 2473 2474 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 2475 struct rtw_rx_pkt_stat *pkt_stat) 2476 { 2477 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2478 u8 l_bnd, u_bnd; 2479 u8 gain_a, gain_b; 2480 s8 rx_power[RTW_RF_PATH_MAX]; 2481 s8 min_rx_power = -120; 2482 u8 rssi; 2483 int path; 2484 2485 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 2486 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 2487 l_bnd = dm_info->cck_gi_l_bnd; 2488 u_bnd = dm_info->cck_gi_u_bnd; 2489 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 2490 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 2491 if (gain_a < l_bnd) 2492 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 2493 else if (gain_a > u_bnd) 2494 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 2495 if (gain_b < l_bnd) 2496 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 2497 else if (gain_b > u_bnd) 2498 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 2499 2500 rx_power[RF_PATH_A] -= 110; 2501 rx_power[RF_PATH_B] -= 110; 2502 2503 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 2504 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 2505 2506 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 2507 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 2508 dm_info->rssi[path] = rssi; 2509 } 2510 2511 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 2512 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 2513 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 2514 min_rx_power); 2515 } 2516 2517 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 2518 struct rtw_rx_pkt_stat *pkt_stat) 2519 { 2520 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2521 u8 rxsc, bw; 2522 s8 min_rx_power = -120; 2523 s8 rx_evm; 2524 u8 evm_dbm = 0; 2525 u8 rssi; 2526 int path; 2527 2528 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 2529 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 2530 else 2531 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 2532 2533 if (rxsc >= 9 && rxsc <= 12) 2534 bw = RTW_CHANNEL_WIDTH_40; 2535 else if (rxsc >= 13) 2536 bw = RTW_CHANNEL_WIDTH_80; 2537 else 2538 bw = RTW_CHANNEL_WIDTH_20; 2539 2540 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 2541 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 2542 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 2543 pkt_stat->bw = bw; 2544 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 2545 pkt_stat->rx_power[RF_PATH_B], 2546 min_rx_power); 2547 2548 dm_info->curr_rx_rate = pkt_stat->rate; 2549 2550 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 2551 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 2552 2553 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 2554 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 2555 2556 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 2557 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 2558 2559 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 2560 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 2561 dm_info->rssi[path] = rssi; 2562 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 2563 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 2564 2565 rx_evm = pkt_stat->rx_evm[path]; 2566 2567 if (rx_evm < 0) { 2568 if (rx_evm == S8_MIN) 2569 evm_dbm = 0; 2570 else 2571 evm_dbm = ((u8)-rx_evm >> 1); 2572 } 2573 dm_info->rx_evm_dbm[path] = evm_dbm; 2574 } 2575 rtw_phy_parsing_cfo(rtwdev, pkt_stat); 2576 } 2577 2578 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 2579 struct rtw_rx_pkt_stat *pkt_stat) 2580 { 2581 u8 page; 2582 2583 page = *phy_status & 0xf; 2584 2585 switch (page) { 2586 case 0: 2587 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 2588 break; 2589 case 1: 2590 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 2591 break; 2592 default: 2593 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 2594 return; 2595 } 2596 } 2597 2598 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 2599 struct rtw_rx_pkt_stat *pkt_stat, 2600 struct ieee80211_rx_status *rx_status) 2601 { 2602 struct ieee80211_hdr *hdr; 2603 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 2604 u8 *phy_status = NULL; 2605 2606 memset(pkt_stat, 0, sizeof(*pkt_stat)); 2607 2608 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 2609 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 2610 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 2611 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 2612 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 2613 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 2614 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 2615 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 2616 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 2617 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 2618 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 2619 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 2620 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 2621 2622 /* drv_info_sz is in unit of 8-bytes */ 2623 pkt_stat->drv_info_sz *= 8; 2624 2625 /* c2h cmd pkt's rx/phy status is not interested */ 2626 if (pkt_stat->is_c2h) 2627 return; 2628 2629 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 2630 pkt_stat->drv_info_sz); 2631 pkt_stat->hdr = hdr; 2632 if (pkt_stat->phy_status) { 2633 phy_status = rx_desc + desc_sz + pkt_stat->shift; 2634 query_phy_status(rtwdev, phy_status, pkt_stat); 2635 } 2636 2637 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 2638 } 2639 2640 static void 2641 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 2642 u8 *tx_pwr_ref_ofdm) 2643 { 2644 struct rtw_hal *hal = &rtwdev->hal; 2645 u32 txref_cck[2] = {0x18a0, 0x41a0}; 2646 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 2647 u8 path; 2648 2649 for (path = 0; path < hal->rf_path_num; path++) { 2650 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 2651 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 2652 tx_pwr_ref_cck[path]); 2653 } 2654 for (path = 0; path < hal->rf_path_num; path++) { 2655 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 2656 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 2657 tx_pwr_ref_ofdm[path]); 2658 } 2659 } 2660 2661 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 2662 s8 *diff_idx) 2663 { 2664 u32 offset_txagc = 0x3a00; 2665 u8 rate_idx = rate & 0xfc; 2666 u8 pwr_idx[4]; 2667 u32 phy_pwr_idx; 2668 int i; 2669 2670 for (i = 0; i < 4; i++) 2671 pwr_idx[i] = diff_idx[i] & 0x7f; 2672 2673 phy_pwr_idx = pwr_idx[0] | 2674 (pwr_idx[1] << 8) | 2675 (pwr_idx[2] << 16) | 2676 (pwr_idx[3] << 24); 2677 2678 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 2679 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 2680 phy_pwr_idx); 2681 } 2682 2683 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 2684 { 2685 struct rtw_hal *hal = &rtwdev->hal; 2686 u8 rs, rate, j; 2687 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 2688 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 2689 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 2690 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 2691 s8 diff_a, diff_b; 2692 u8 pwr_a, pwr_b; 2693 s8 diff_idx[4]; 2694 2695 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 2696 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 2697 for (j = 0; j < rtw_rate_size[rs]; j++) { 2698 rate = rtw_rate_section[rs][j]; 2699 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 2700 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 2701 if (rs == 0) { 2702 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 2703 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 2704 } else { 2705 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 2706 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 2707 } 2708 diff_idx[rate % 4] = min(diff_a, diff_b); 2709 if (rate % 4 == 3) 2710 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 2711 diff_idx); 2712 } 2713 } 2714 } 2715 2716 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev, 2717 u32 antenna_tx, 2718 u32 antenna_rx) 2719 { 2720 struct rtw_hal *hal = &rtwdev->hal; 2721 2722 switch (antenna_tx) { 2723 case BB_PATH_A: 2724 case BB_PATH_B: 2725 case BB_PATH_AB: 2726 break; 2727 default: 2728 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 2729 return -EINVAL; 2730 } 2731 2732 /* path B only is not available for RX */ 2733 switch (antenna_rx) { 2734 case BB_PATH_A: 2735 case BB_PATH_AB: 2736 break; 2737 default: 2738 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 2739 return -EINVAL; 2740 } 2741 2742 hal->antenna_tx = antenna_tx; 2743 hal->antenna_rx = antenna_rx; 2744 2745 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 2746 2747 return 0; 2748 } 2749 2750 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 2751 { 2752 u8 ldo_pwr; 2753 2754 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 2755 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 2756 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 2757 } 2758 2759 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 2760 { 2761 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2762 u32 cck_enable; 2763 u32 cck_fa_cnt; 2764 u32 crc32_cnt; 2765 u32 cca32_cnt; 2766 u32 ofdm_fa_cnt; 2767 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 2768 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 2769 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 2770 2771 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 2772 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 2773 2774 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 2775 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 2776 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 2777 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 2778 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 2779 2780 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 2781 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 2782 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 2783 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 2784 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 2785 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 2786 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 2787 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 2788 2789 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 2790 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 2791 2792 dm_info->cck_fa_cnt = cck_fa_cnt; 2793 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 2794 dm_info->total_fa_cnt = ofdm_fa_cnt; 2795 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 2796 2797 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 2798 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 2799 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2800 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 2801 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 2802 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2803 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 2804 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 2805 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2806 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 2807 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 2808 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2809 2810 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 2811 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 2812 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 2813 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 2814 if (cck_enable) 2815 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 2816 2817 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 2818 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 2819 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 2820 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 2821 2822 /* disable rx clk gating to reset counters */ 2823 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2824 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2825 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2826 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2827 } 2828 2829 static void rtw8822c_do_lck(struct rtw_dev *rtwdev) 2830 { 2831 u32 val; 2832 2833 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2834 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA); 2835 fsleep(1); 2836 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000); 2837 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001); 2838 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000, 2839 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000); 2840 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8); 2841 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2842 2843 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2844 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000); 2845 fsleep(1); 2846 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2847 } 2848 2849 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 2850 { 2851 struct rtw_iqk_para para = {0}; 2852 u8 iqk_chk; 2853 int ret; 2854 2855 para.clear = 1; 2856 rtw_fw_do_iqk(rtwdev, ¶); 2857 2858 ret = read_poll_timeout(rtw_read8, iqk_chk, iqk_chk == IQK_DONE_8822C, 2859 20000, 300000, false, rtwdev, REG_RPT_CIP); 2860 if (ret) 2861 rtw_warn(rtwdev, "failed to poll iqk status bit\n"); 2862 2863 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 2864 } 2865 2866 /* for coex */ 2867 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 2868 { 2869 /* enable TBTT nterrupt */ 2870 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2871 2872 /* BT report packet sample rate */ 2873 /* 0x790[5:0]=0x5 */ 2874 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 2875 2876 /* enable BT counter statistics */ 2877 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2878 2879 /* enable PTA (3-wire function form BT side) */ 2880 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2881 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 2882 2883 /* enable PTA (tx/rx signal form WiFi side) */ 2884 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2885 /* wl tx signal to PTA not case EDCCA */ 2886 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2887 /* GNT_BT=1 while select both */ 2888 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2889 /* BT_CCA = ~GNT_WL_BB, not or GNT_BT_BB, LTE_Rx */ 2890 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2891 2892 /* to avoid RF parameter error */ 2893 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000); 2894 } 2895 2896 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2897 { 2898 struct rtw_coex *coex = &rtwdev->coex; 2899 struct rtw_coex_stat *coex_stat = &coex->stat; 2900 struct rtw_efuse *efuse = &rtwdev->efuse; 2901 u32 rf_0x1; 2902 2903 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2904 return; 2905 2906 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 2907 2908 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 2909 rf_0x1 = 0x40021; 2910 else 2911 rf_0x1 = 0x40000; 2912 2913 /* BT at S1 for Shared-Ant */ 2914 if (efuse->share_ant) 2915 rf_0x1 |= BIT(13); 2916 2917 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 2918 2919 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 2920 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 2921 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 2922 * 2923 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 2924 * disable 0x1c30[22] = 0, 2925 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 2926 * 2927 * disable WL-S1 BB chage RF mode if GNT_BT 2928 * since RF TRx mask can do it 2929 */ 2930 rtw_write8_mask(rtwdev, REG_ANAPAR + 2, BIT_ANAPAR_BTPS >> 16, 1); 2931 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1, BIT_DAC_OFF_ENABLE, 0); 2932 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3, BIT_DAC_OFF_ENABLE, 1); 2933 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4, BIT_PI_IGNORE_GNT_BT, 1); 2934 2935 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 2936 * or antenna path is separated 2937 */ 2938 if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 2939 coex->under_5g || !efuse->share_ant) { 2940 if (coex_stat->kt_ver >= 3) { 2941 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 2942 BIT_PI_IGNORE_GNT_BT, 0); 2943 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 2944 BIT_NOMASK_TXBT_ENABLE, 1); 2945 } else { 2946 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 2947 BIT_PI_IGNORE_GNT_BT, 1); 2948 } 2949 } else { 2950 /* shared-antenna */ 2951 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 2952 BIT_PI_IGNORE_GNT_BT, 0); 2953 if (coex_stat->kt_ver >= 3) { 2954 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 2955 BIT_NOMASK_TXBT_ENABLE, 0); 2956 } 2957 } 2958 } 2959 2960 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 2961 { 2962 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 2963 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 2964 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 2965 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 2966 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 2967 } 2968 2969 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 2970 { 2971 struct rtw_coex *coex = &rtwdev->coex; 2972 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 2973 struct rtw_efuse *efuse = &rtwdev->efuse; 2974 2975 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 2976 coex_rfe->ant_switch_polarity = 0; 2977 coex_rfe->ant_switch_exist = false; 2978 coex_rfe->ant_switch_with_bt = false; 2979 coex_rfe->ant_switch_diversity = false; 2980 2981 if (efuse->share_ant) 2982 coex_rfe->wlg_at_btg = true; 2983 else 2984 coex_rfe->wlg_at_btg = false; 2985 2986 /* disable LTE coex in wifi side */ 2987 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 2988 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 2989 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 2990 } 2991 2992 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 2993 { 2994 struct rtw_coex *coex = &rtwdev->coex; 2995 struct rtw_coex_dm *coex_dm = &coex->dm; 2996 2997 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 2998 return; 2999 3000 coex_dm->cur_wl_pwr_lvl = wl_pwr; 3001 } 3002 3003 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 3004 { 3005 struct rtw_coex *coex = &rtwdev->coex; 3006 struct rtw_coex_dm *coex_dm = &coex->dm; 3007 3008 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 3009 return; 3010 3011 coex_dm->cur_wl_rx_low_gain_en = low_gain; 3012 3013 if (coex_dm->cur_wl_rx_low_gain_en) { 3014 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); 3015 3016 /* set Rx filter corner RCK offset */ 3017 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22); 3018 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36); 3019 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22); 3020 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36); 3021 3022 } else { 3023 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); 3024 3025 /* set Rx filter corner RCK offset */ 3026 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20); 3027 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0); 3028 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20); 3029 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0); 3030 } 3031 } 3032 3033 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 3034 struct rtw_vif *vif, 3035 struct rtw_bfee *bfee) 3036 { 3037 u8 csi_rsc = 0; 3038 u32 tmp6dc; 3039 3040 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 3041 3042 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 3043 BIT_WMAC_USE_NDPARATE | 3044 (csi_rsc << 13); 3045 if (vif->net_type == RTW_NET_AP_MODE) 3046 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 3047 else 3048 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 3049 3050 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 3051 } 3052 3053 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 3054 struct rtw_vif *vif, 3055 struct rtw_bfee *bfee, bool enable) 3056 { 3057 if (enable) 3058 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 3059 else 3060 rtw_bf_remove_bfee_su(rtwdev, bfee); 3061 } 3062 3063 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 3064 struct rtw_vif *vif, 3065 struct rtw_bfee *bfee, bool enable) 3066 { 3067 if (enable) 3068 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 3069 else 3070 rtw_bf_remove_bfee_mu(rtwdev, bfee); 3071 } 3072 3073 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 3074 struct rtw_bfee *bfee, bool enable) 3075 { 3076 if (bfee->role == RTW_BFEE_SU) 3077 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 3078 else if (bfee->role == RTW_BFEE_MU) 3079 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 3080 else 3081 rtw_warn(rtwdev, "wrong bfee role\n"); 3082 } 3083 3084 struct dpk_cfg_pair { 3085 u32 addr; 3086 u32 bitmask; 3087 u32 data; 3088 }; 3089 3090 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 3091 const struct rtw_table *tbl) 3092 { 3093 const struct dpk_cfg_pair *p = tbl->data; 3094 const struct dpk_cfg_pair *end = p + tbl->size / 3; 3095 3096 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 3097 3098 for (; p < end; p++) 3099 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 3100 } 3101 3102 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 3103 { 3104 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3105 3106 if (is_before_k) { 3107 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 3108 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 3109 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 3110 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 3111 } else { 3112 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 3113 dpk_info->gnt_value); 3114 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 3115 } 3116 } 3117 3118 static void 3119 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 3120 struct rtw_backup_info *bckp) 3121 { 3122 rtw_restore_reg(rtwdev, bckp, reg_num); 3123 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3124 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 3125 } 3126 3127 static void 3128 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 3129 u32 reg_num, struct rtw_backup_info *bckp) 3130 { 3131 u32 i; 3132 3133 for (i = 0; i < reg_num; i++) { 3134 bckp[i].len = 4; 3135 bckp[i].reg = reg[i]; 3136 bckp[i].val = rtw_read32(rtwdev, reg[i]); 3137 } 3138 } 3139 3140 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 3141 u32 *rf_reg, 3142 u32 rf_reg_bak[][2]) 3143 { 3144 u32 i; 3145 3146 for (i = 0; i < DPK_RF_REG_NUM; i++) { 3147 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 3148 rf_reg[i], RFREG_MASK); 3149 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 3150 rf_reg[i], RFREG_MASK); 3151 } 3152 } 3153 3154 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 3155 u32 *rf_reg, 3156 u32 rf_reg_bak[][2]) 3157 { 3158 u32 i; 3159 3160 for (i = 0; i < DPK_RF_REG_NUM; i++) { 3161 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 3162 rf_reg_bak[i][RF_PATH_A]); 3163 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 3164 rf_reg_bak[i][RF_PATH_B]); 3165 } 3166 } 3167 3168 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 3169 { 3170 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3171 u32 reg; 3172 u8 band_shift; 3173 3174 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 3175 3176 band_shift = FIELD_GET(BIT(16), reg); 3177 dpk_info->dpk_band = 1 << band_shift; 3178 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 3179 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 3180 } 3181 3182 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 3183 { 3184 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 3185 udelay(5); 3186 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 3187 usleep_range(600, 610); 3188 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 3189 } 3190 3191 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 3192 { 3193 u16 dc_i, dc_q; 3194 u8 corr_idx; 3195 3196 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 3197 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 3198 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 3199 3200 if (dc_i & BIT(11)) 3201 dc_i = 0x1000 - dc_i; 3202 if (dc_q & BIT(11)) 3203 dc_q = 0x1000 - dc_q; 3204 3205 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3206 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 3207 rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 3208 3209 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 3210 return 1; 3211 else 3212 return 0; 3213 3214 } 3215 3216 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 3217 { 3218 u8 reg_a, reg_b; 3219 u16 count = 0; 3220 3221 rtw_write8(rtwdev, 0x522, 0xff); 3222 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 3223 3224 do { 3225 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 3226 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 3227 udelay(2); 3228 count++; 3229 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 3230 } 3231 3232 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 3233 { 3234 rtw8822c_dpk_tx_pause(rtwdev); 3235 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 3236 } 3237 3238 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 3239 { 3240 if (is_do_dpk) 3241 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 3242 else 3243 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 3244 } 3245 3246 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 3247 { 3248 u8 path; 3249 3250 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3251 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 3252 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 3253 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 3254 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); 3255 else 3256 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); 3257 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 3258 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 3259 } 3260 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3261 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 3262 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 3263 } 3264 3265 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 3266 { 3267 u32 ori_txbb; 3268 3269 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 3270 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 3271 3272 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 3273 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 3274 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0); 3275 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 3276 3277 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 3278 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1); 3279 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 3280 } else { 3281 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 3282 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 3283 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 3284 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 3285 } 3286 3287 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 3288 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 3289 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 3290 3291 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 3292 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 3293 else 3294 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 3295 3296 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 3297 3298 usleep_range(100, 110); 3299 3300 return ori_txbb & 0x1f; 3301 } 3302 3303 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 3304 { 3305 u16 cmd; 3306 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 3307 3308 switch (action) { 3309 case RTW_DPK_GAIN_LOSS: 3310 cmd = 0x14 + path; 3311 break; 3312 case RTW_DPK_DO_DPK: 3313 cmd = 0x16 + path + bw; 3314 break; 3315 case RTW_DPK_DPK_ON: 3316 cmd = 0x1a + path; 3317 break; 3318 case RTW_DPK_DAGC: 3319 cmd = 0x1c + path + bw; 3320 break; 3321 default: 3322 return 0; 3323 } 3324 3325 return (cmd << 8) | 0x48; 3326 } 3327 3328 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 3329 { 3330 u16 dpk_cmd; 3331 u8 result = 0; 3332 3333 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 3334 3335 if (action == RTW_DPK_CAL_PWR) { 3336 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 3337 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 3338 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3339 msleep(10); 3340 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 3341 result = 1; 3342 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 3343 } 3344 } else { 3345 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3346 0x8 | (path << 1)); 3347 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3348 3349 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 3350 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 3351 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 3352 msleep(10); 3353 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 3354 result = 1; 3355 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 3356 } 3357 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3358 0x8 | (path << 1)); 3359 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3360 } 3361 3362 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 3363 3364 rtw_write8(rtwdev, 0x1b10, 0x0); 3365 3366 return result; 3367 } 3368 3369 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 3370 { 3371 u16 dgain; 3372 3373 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3374 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 3375 3376 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 3377 3378 return dgain; 3379 } 3380 3381 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 3382 { 3383 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 3384 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 3385 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 3386 udelay(15); 3387 3388 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 3389 } 3390 3391 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 3392 { 3393 u32 i_val, q_val; 3394 3395 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 3396 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 3397 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 3398 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 3399 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 3400 3401 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 3402 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 3403 3404 if (i_val & BIT(15)) 3405 i_val = 0x10000 - i_val; 3406 if (q_val & BIT(15)) 3407 q_val = 0x10000 - q_val; 3408 3409 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 3410 3411 return i_val * i_val + q_val * q_val; 3412 } 3413 3414 static u32 rtw8822c_psd_log2base(u32 val) 3415 { 3416 u32 tmp, val_integerd_b, tindex; 3417 u32 result, val_fractiond_b; 3418 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 3419 151, 132, 115, 100, 86, 74, 62, 51, 3420 42, 32, 23, 15, 7, 0}; 3421 3422 if (val == 0) 3423 return 0; 3424 3425 val_integerd_b = __fls(val) + 1; 3426 3427 tmp = (val * 100) / (1 << val_integerd_b); 3428 tindex = tmp / 5; 3429 3430 if (tindex >= ARRAY_SIZE(table_fraction)) 3431 tindex = ARRAY_SIZE(table_fraction) - 1; 3432 3433 val_fractiond_b = table_fraction[tindex]; 3434 3435 result = val_integerd_b * 100 - val_fractiond_b; 3436 3437 return result; 3438 } 3439 3440 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 3441 { 3442 u8 result; 3443 3444 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3445 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 3446 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 3447 3448 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 3449 3450 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 3451 3452 return result; 3453 } 3454 3455 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 3456 u8 limited_pga) 3457 { 3458 u8 result = 0; 3459 u16 dgain; 3460 3461 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3462 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 3463 3464 if (dgain > 1535 && !limited_pga) 3465 return RTW_DPK_GAIN_LESS; 3466 else if (dgain < 768 && !limited_pga) 3467 return RTW_DPK_GAIN_LARGE; 3468 else 3469 return result; 3470 } 3471 3472 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 3473 { 3474 u32 loss, loss_db; 3475 3476 loss = rtw8822c_dpk_pas_read(rtwdev, path); 3477 if (loss < 0x4000000) 3478 return RTW_DPK_GL_LESS; 3479 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 3480 3481 if (loss_db > 1000) 3482 return RTW_DPK_GL_LARGE; 3483 else if (loss_db < 250) 3484 return RTW_DPK_GL_LESS; 3485 else 3486 return RTW_DPK_AGC_OUT; 3487 } 3488 3489 struct rtw8822c_dpk_data { 3490 u8 txbb; 3491 u8 pga; 3492 u8 limited_pga; 3493 u8 agc_cnt; 3494 bool loss_only; 3495 bool gain_only; 3496 u8 path; 3497 }; 3498 3499 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 3500 struct rtw8822c_dpk_data *data) 3501 { 3502 u8 state; 3503 3504 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 3505 BIT_GAIN_TXBB); 3506 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 3507 BIT_RXAGC); 3508 3509 if (data->loss_only) { 3510 state = RTW_DPK_LOSS_CHECK; 3511 goto check_end; 3512 } 3513 3514 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 3515 data->limited_pga); 3516 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 3517 state = RTW_DPK_AGC_OUT; 3518 else if (state == RTW_DPK_GAIN_CHECK) 3519 state = RTW_DPK_LOSS_CHECK; 3520 3521 check_end: 3522 data->agc_cnt++; 3523 if (data->agc_cnt >= 6) 3524 state = RTW_DPK_AGC_OUT; 3525 3526 return state; 3527 } 3528 3529 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 3530 struct rtw8822c_dpk_data *data) 3531 { 3532 u8 pga = data->pga; 3533 3534 if (pga > 0xe) 3535 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 3536 else if (pga > 0xb && pga < 0xf) 3537 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 3538 else if (pga < 0xc) 3539 data->limited_pga = 1; 3540 3541 return RTW_DPK_GAIN_CHECK; 3542 } 3543 3544 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 3545 struct rtw8822c_dpk_data *data) 3546 { 3547 u8 pga = data->pga; 3548 3549 if (pga < 0xc) 3550 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 3551 else if (pga > 0xb && pga < 0xf) 3552 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 3553 else if (pga > 0xe) 3554 data->limited_pga = 1; 3555 3556 return RTW_DPK_GAIN_CHECK; 3557 } 3558 3559 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 3560 struct rtw8822c_dpk_data *data, u8 is_large) 3561 { 3562 u8 txbb_bound[] = {0x1f, 0}; 3563 3564 if (data->txbb == txbb_bound[is_large]) 3565 return RTW_DPK_AGC_OUT; 3566 3567 if (is_large == 1) 3568 data->txbb -= 2; 3569 else 3570 data->txbb += 3; 3571 3572 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 3573 data->limited_pga = 0; 3574 3575 return RTW_DPK_GAIN_CHECK; 3576 } 3577 3578 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 3579 struct rtw8822c_dpk_data *data) 3580 { 3581 return rtw8822c_gl_state(rtwdev, data, 1); 3582 } 3583 3584 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 3585 struct rtw8822c_dpk_data *data) 3586 { 3587 return rtw8822c_gl_state(rtwdev, data, 0); 3588 } 3589 3590 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 3591 struct rtw8822c_dpk_data *data) 3592 { 3593 u8 path = data->path; 3594 u8 state; 3595 3596 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 3597 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 3598 3599 return state; 3600 } 3601 3602 static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 3603 struct rtw8822c_dpk_data *data) = { 3604 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 3605 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 3606 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 3607 3608 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 3609 bool gain_only, bool loss_only) 3610 { 3611 struct rtw8822c_dpk_data data = {0}; 3612 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 3613 u8 state = RTW_DPK_GAIN_CHECK; 3614 3615 data.loss_only = loss_only; 3616 data.gain_only = gain_only; 3617 data.path = path; 3618 3619 for (;;) { 3620 func = dpk_state[state]; 3621 state = func(rtwdev, &data); 3622 if (state == RTW_DPK_AGC_OUT) 3623 break; 3624 } 3625 3626 return data.txbb; 3627 } 3628 3629 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 3630 u16 coef_i, u16 coef_q) 3631 { 3632 if (coef_i == 0x1000 || coef_i == 0x0fff || 3633 coef_q == 0x1000 || coef_q == 0x0fff) 3634 return true; 3635 3636 return false; 3637 } 3638 3639 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 3640 { 3641 u32 reg = 0; 3642 u16 coef_i = 0, coef_q = 0; 3643 3644 reg = rtw_read32(rtwdev, REG_STAT_RPT); 3645 3646 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 3647 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 3648 3649 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 3650 3651 reg = (coef_i << 16) | coef_q; 3652 3653 return reg; 3654 } 3655 3656 static const u32 rtw8822c_dpk_get_coef_tbl[] = { 3657 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 3658 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 3659 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 3660 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 3661 }; 3662 3663 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 3664 { 3665 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3666 int i; 3667 3668 for (i = 0; i < 20; i++) { 3669 rtw_write32(rtwdev, REG_RXSRAM_CTL, 3670 rtw8822c_dpk_get_coef_tbl[i]); 3671 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 3672 } 3673 } 3674 3675 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 3676 { 3677 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 3678 3679 if (path == RF_PATH_A) { 3680 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 3681 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 3682 } else if (path == RF_PATH_B) { 3683 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 3684 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 3685 } 3686 3687 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 3688 } 3689 3690 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 3691 { 3692 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3693 u8 addr, result = 1; 3694 u16 coef_i, coef_q; 3695 3696 for (addr = 0; addr < 20; addr++) { 3697 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 3698 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 3699 3700 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 3701 result = 0; 3702 break; 3703 } 3704 } 3705 return result; 3706 } 3707 3708 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 3709 { 3710 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3711 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 3712 u32 coef; 3713 u8 addr; 3714 3715 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 3716 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3717 3718 for (addr = 0; addr < 20; addr++) { 3719 if (result == 0) { 3720 if (addr == 3) 3721 coef = 0x04001fff; 3722 else 3723 coef = 0x00001fff; 3724 } else { 3725 coef = dpk_info->coef[path][addr]; 3726 } 3727 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 3728 } 3729 } 3730 3731 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 3732 u8 path, u8 result) 3733 { 3734 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3735 3736 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3737 3738 if (result) 3739 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 3740 else 3741 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 3742 3743 dpk_info->result[path] = result; 3744 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 3745 3746 rtw8822c_dpk_coef_write(rtwdev, path, result); 3747 } 3748 3749 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 3750 { 3751 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3752 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 3753 3754 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 3755 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 3756 3757 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3758 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3759 rtw8822c_dpk_dgain_read(rtwdev, path); 3760 3761 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 3762 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3763 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3764 rtw8822c_dpk_dc_corr_check(rtwdev, path); 3765 } 3766 3767 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 3768 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 3769 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 3770 3771 if (tx_bb < tx_agc_search) 3772 tx_bb = 0; 3773 else 3774 tx_bb = tx_bb - tx_agc_search; 3775 3776 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 3777 3778 tx_agc = ori_txagc - (ori_txbb - tx_bb); 3779 3780 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 3781 3782 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 3783 3784 return tx_agc; 3785 } 3786 3787 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 3788 { 3789 u8 result; 3790 3791 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 3792 3793 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3794 3795 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 3796 3797 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 3798 3799 rtw8822c_dpk_get_coef(rtwdev, path); 3800 3801 return result; 3802 } 3803 3804 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 3805 { 3806 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3807 u32 tmp_gs = 0; 3808 3809 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3810 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 3811 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3812 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3813 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 3814 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3815 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 3816 3817 if (path == RF_PATH_A) { 3818 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3819 0x1066680); 3820 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 3821 } else { 3822 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3823 0x1066680); 3824 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 3825 } 3826 3827 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 3828 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 3829 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 3830 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 3831 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 3832 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3833 rtw_write32(rtwdev, REG_DPD_CTL15, 3834 0x05020000 | (BIT(path) << 28)); 3835 } else { 3836 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 3837 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 3838 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 3839 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 3840 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3841 rtw_write32(rtwdev, REG_DPD_CTL15, 3842 0x05020008 | (BIT(path) << 28)); 3843 } 3844 3845 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 3846 3847 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 3848 3849 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 3850 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3851 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3852 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 3853 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3854 3855 if (path == RF_PATH_A) 3856 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 3857 else 3858 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 3859 3860 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3861 3862 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 3863 tmp_gs = (tmp_gs * 910) >> 10; 3864 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 3865 3866 if (path == RF_PATH_A) 3867 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 3868 else 3869 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 3870 3871 dpk_info->dpk_gs[path] = tmp_gs; 3872 } 3873 3874 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 3875 { 3876 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3877 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 3878 u32 i_scaling; 3879 u8 path; 3880 3881 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3882 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3883 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 3884 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 3885 3886 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 3887 3888 rtw_write8(rtwdev, 0x1b10, 0x0); 3889 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3890 3891 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3892 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 3893 3894 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 3895 i_scaling); 3896 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3897 GENMASK(31, 28), 0x9); 3898 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3899 GENMASK(31, 28), 0x1); 3900 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3901 GENMASK(31, 28), 0x0); 3902 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 3903 BIT(14), 0x0); 3904 } 3905 } 3906 3907 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 3908 { 3909 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3910 3911 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3912 3913 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3914 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3915 3916 if (test_bit(path, dpk_info->dpk_path_ok)) 3917 rtw8822c_dpk_cal_gs(rtwdev, path); 3918 } 3919 3920 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 3921 u32 dpk_txagc, u8 path) 3922 { 3923 bool result; 3924 3925 if (!is_fail) { 3926 if (rtw8822c_dpk_coef_read(rtwdev, path)) 3927 result = true; 3928 else 3929 result = false; 3930 } else { 3931 result = false; 3932 } 3933 3934 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 3935 3936 return result; 3937 } 3938 3939 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 3940 { 3941 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3942 u8 path; 3943 3944 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3945 clear_bit(path, dpk_info->dpk_path_ok); 3946 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3947 0x8 | (path << 1)); 3948 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 3949 3950 dpk_info->dpk_txagc[path] = 0; 3951 dpk_info->result[path] = 0; 3952 dpk_info->dpk_gs[path] = 0x5b; 3953 dpk_info->pre_pwsf[path] = 0; 3954 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 3955 path); 3956 } 3957 } 3958 3959 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 3960 { 3961 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3962 u32 dpk_txagc; 3963 u8 dpk_fail; 3964 3965 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 3966 3967 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 3968 3969 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 3970 3971 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 3972 rtw_err(rtwdev, "failed to do dpk calibration\n"); 3973 3974 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 3975 3976 if (dpk_info->result[path]) 3977 set_bit(path, dpk_info->dpk_path_ok); 3978 } 3979 3980 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 3981 { 3982 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 3983 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 3984 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 3985 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 3986 rtw8822c_dpk_cal_coef1(rtwdev); 3987 } 3988 3989 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 3990 { 3991 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3992 u32 mask = BIT(15) | BIT(14); 3993 3994 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3995 3996 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 3997 dpk_info->is_dpk_pwr_on); 3998 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 3999 dpk_info->is_dpk_pwr_on); 4000 4001 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 4002 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 4003 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 4004 } 4005 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 4006 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 4007 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 4008 } 4009 } 4010 4011 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 4012 { 4013 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4014 u8 path; 4015 4016 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 4017 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 4018 dpk_info->dpk_ch == 0) 4019 return; 4020 4021 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 4022 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4023 0x8 | (path << 1)); 4024 if (dpk_info->dpk_band == RTW_BAND_2G) 4025 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); 4026 else 4027 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); 4028 4029 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 4030 4031 rtw8822c_dpk_coef_write(rtwdev, path, 4032 test_bit(path, dpk_info->dpk_path_ok)); 4033 4034 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 4035 4036 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 4037 4038 if (path == RF_PATH_A) 4039 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 4040 dpk_info->dpk_gs[path]); 4041 else 4042 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 4043 dpk_info->dpk_gs[path]); 4044 } 4045 rtw8822c_dpk_cal_coef1(rtwdev); 4046 } 4047 4048 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 4049 { 4050 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4051 u8 channel; 4052 4053 dpk_info->is_reload = false; 4054 4055 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 4056 4057 if (channel == dpk_info->dpk_ch) { 4058 rtw_dbg(rtwdev, RTW_DBG_RFK, 4059 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 4060 rtw8822c_dpk_reload_data(rtwdev); 4061 dpk_info->is_reload = true; 4062 } 4063 4064 return dpk_info->is_reload; 4065 } 4066 4067 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 4068 { 4069 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4070 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 4071 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 4072 u32 bb_reg[DPK_BB_REG_NUM] = { 4073 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 4074 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 4075 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 4076 u32 rf_reg[DPK_RF_REG_NUM] = { 4077 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 4078 u8 path; 4079 4080 if (!dpk_info->is_dpk_pwr_on) { 4081 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 4082 return; 4083 } else if (rtw8822c_dpk_reload(rtwdev)) { 4084 return; 4085 } 4086 4087 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 4088 ewma_thermal_init(&dpk_info->avg_thermal[path]); 4089 4090 rtw8822c_dpk_information(rtwdev); 4091 4092 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 4093 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 4094 4095 rtw8822c_dpk_mac_bb_setting(rtwdev); 4096 rtw8822c_dpk_afe_setting(rtwdev, true); 4097 rtw8822c_dpk_pre_setting(rtwdev); 4098 rtw8822c_dpk_result_reset(rtwdev); 4099 rtw8822c_dpk_path_select(rtwdev); 4100 rtw8822c_dpk_afe_setting(rtwdev, false); 4101 rtw8822c_dpk_enable_disable(rtwdev); 4102 4103 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 4104 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 4105 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 4106 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 4107 } 4108 4109 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 4110 { 4111 rtw8822c_rfk_power_save(rtwdev, false); 4112 rtw8822c_do_gapk(rtwdev); 4113 rtw8822c_do_iqk(rtwdev); 4114 rtw8822c_do_dpk(rtwdev); 4115 rtw8822c_rfk_power_save(rtwdev, true); 4116 } 4117 4118 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 4119 { 4120 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4121 u8 path; 4122 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 4123 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 4124 4125 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 4126 return; 4127 4128 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 4129 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 4130 ewma_thermal_add(&dpk_info->avg_thermal[path], 4131 thermal_value[path]); 4132 thermal_value[path] = 4133 ewma_thermal_read(&dpk_info->avg_thermal[path]); 4134 delta_dpk[path] = dpk_info->thermal_dpk[path] - 4135 thermal_value[path]; 4136 offset[path] = delta_dpk[path] - 4137 dpk_info->thermal_dpk_delta[path]; 4138 offset[path] &= 0x7f; 4139 4140 if (offset[path] != dpk_info->pre_pwsf[path]) { 4141 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4142 0x8 | (path << 1)); 4143 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 4144 offset[path]); 4145 dpk_info->pre_pwsf[path] = offset[path]; 4146 } 4147 } 4148 } 4149 4150 #define XCAP_EXTEND(val) ({typeof(val) _v = (val); _v | _v << 7; }) 4151 static void rtw8822c_set_crystal_cap_reg(struct rtw_dev *rtwdev, u8 crystal_cap) 4152 { 4153 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4154 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4155 u32 val = 0; 4156 4157 val = XCAP_EXTEND(crystal_cap); 4158 cfo->crystal_cap = crystal_cap; 4159 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, BIT_XCAP_0, val); 4160 } 4161 4162 static void rtw8822c_set_crystal_cap(struct rtw_dev *rtwdev, u8 crystal_cap) 4163 { 4164 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4165 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4166 4167 if (cfo->crystal_cap == crystal_cap) 4168 return; 4169 4170 rtw8822c_set_crystal_cap_reg(rtwdev, crystal_cap); 4171 } 4172 4173 static void rtw8822c_cfo_tracking_reset(struct rtw_dev *rtwdev) 4174 { 4175 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4176 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4177 4178 cfo->is_adjust = true; 4179 4180 if (cfo->crystal_cap > rtwdev->efuse.crystal_cap) 4181 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap - 1); 4182 else if (cfo->crystal_cap < rtwdev->efuse.crystal_cap) 4183 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap + 1); 4184 } 4185 4186 static void rtw8822c_cfo_init(struct rtw_dev *rtwdev) 4187 { 4188 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4189 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4190 4191 cfo->crystal_cap = rtwdev->efuse.crystal_cap; 4192 cfo->is_adjust = true; 4193 } 4194 4195 #define REPORT_TO_KHZ(val) ({typeof(val) _v = (val); (_v << 1) + (_v >> 1); }) 4196 static s32 rtw8822c_cfo_calc_avg(struct rtw_dev *rtwdev, u8 path_num) 4197 { 4198 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4199 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4200 s32 cfo_avg, cfo_path_sum = 0, cfo_rpt_sum; 4201 u8 i; 4202 4203 for (i = 0; i < path_num; i++) { 4204 cfo_rpt_sum = REPORT_TO_KHZ(cfo->cfo_tail[i]); 4205 4206 if (cfo->cfo_cnt[i]) 4207 cfo_avg = cfo_rpt_sum / cfo->cfo_cnt[i]; 4208 else 4209 cfo_avg = 0; 4210 4211 cfo_path_sum += cfo_avg; 4212 } 4213 4214 for (i = 0; i < path_num; i++) { 4215 cfo->cfo_tail[i] = 0; 4216 cfo->cfo_cnt[i] = 0; 4217 } 4218 4219 return cfo_path_sum / path_num; 4220 } 4221 4222 static void rtw8822c_cfo_need_adjust(struct rtw_dev *rtwdev, s32 cfo_avg) 4223 { 4224 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4225 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4226 4227 if (!cfo->is_adjust) { 4228 if (abs(cfo_avg) > CFO_TRK_ENABLE_TH) 4229 cfo->is_adjust = true; 4230 } else { 4231 if (abs(cfo_avg) <= CFO_TRK_STOP_TH) 4232 cfo->is_adjust = false; 4233 } 4234 4235 if (!rtw_coex_disabled(rtwdev)) { 4236 cfo->is_adjust = false; 4237 rtw8822c_set_crystal_cap(rtwdev, rtwdev->efuse.crystal_cap); 4238 } 4239 } 4240 4241 static void rtw8822c_cfo_track(struct rtw_dev *rtwdev) 4242 { 4243 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4244 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4245 u8 path_num = rtwdev->hal.rf_path_num; 4246 s8 crystal_cap = cfo->crystal_cap; 4247 s32 cfo_avg = 0; 4248 4249 if (rtwdev->sta_cnt != 1) { 4250 rtw8822c_cfo_tracking_reset(rtwdev); 4251 return; 4252 } 4253 4254 if (cfo->packet_count == cfo->packet_count_pre) 4255 return; 4256 4257 cfo->packet_count_pre = cfo->packet_count; 4258 cfo_avg = rtw8822c_cfo_calc_avg(rtwdev, path_num); 4259 rtw8822c_cfo_need_adjust(rtwdev, cfo_avg); 4260 4261 if (cfo->is_adjust) { 4262 if (cfo_avg > CFO_TRK_ADJ_TH) 4263 crystal_cap++; 4264 else if (cfo_avg < -CFO_TRK_ADJ_TH) 4265 crystal_cap--; 4266 4267 crystal_cap = clamp_t(s8, crystal_cap, 0, XCAP_MASK); 4268 rtw8822c_set_crystal_cap(rtwdev, (u8)crystal_cap); 4269 } 4270 } 4271 4272 static const struct rtw_phy_cck_pd_reg 4273 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 4274 { 4275 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 4276 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 4277 }, 4278 { 4279 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 4280 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 4281 }, 4282 }; 4283 4284 #define RTW_CCK_PD_MAX 255 4285 #define RTW_CCK_CS_MAX 31 4286 #define RTW_CCK_CS_ERR1 27 4287 #define RTW_CCK_CS_ERR2 29 4288 static void 4289 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 4290 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 4291 { 4292 u32 pd, cs; 4293 4294 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 4295 return; 4296 4297 pd = rtw_read32_mask(rtwdev, 4298 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 4299 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 4300 cs = rtw_read32_mask(rtwdev, 4301 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 4302 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 4303 pd += pd_diff; 4304 cs += cs_diff; 4305 if (pd > RTW_CCK_PD_MAX) 4306 pd = RTW_CCK_PD_MAX; 4307 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 4308 cs++; 4309 else if (cs > RTW_CCK_CS_MAX) 4310 cs = RTW_CCK_CS_MAX; 4311 rtw_write32_mask(rtwdev, 4312 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 4313 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 4314 pd); 4315 rtw_write32_mask(rtwdev, 4316 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 4317 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 4318 cs); 4319 4320 rtw_dbg(rtwdev, RTW_DBG_PHY, 4321 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n", 4322 rtw_is_assoc(rtwdev), bw, nrx, cs, pd); 4323 } 4324 4325 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 4326 { 4327 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4328 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 4329 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 4330 u8 cur_lvl; 4331 u8 nrx, bw; 4332 4333 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 4334 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 4335 4336 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n", 4337 dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx, 4338 dm_info->cck_fa_avg); 4339 4340 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 4341 return; 4342 4343 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 4344 4345 /* update cck pd info */ 4346 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 4347 4348 rtw8822c_phy_cck_pd_set_reg(rtwdev, 4349 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 4350 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 4351 bw, nrx); 4352 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 4353 } 4354 4355 #define PWR_TRACK_MASK 0x7f 4356 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 4357 { 4358 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4359 4360 switch (rf_path) { 4361 case RF_PATH_A: 4362 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 4363 dm_info->delta_power_index[rf_path]); 4364 break; 4365 case RF_PATH_B: 4366 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 4367 dm_info->delta_power_index[rf_path]); 4368 break; 4369 default: 4370 break; 4371 } 4372 } 4373 4374 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 4375 struct rtw_swing_table *swing_table, 4376 u8 path) 4377 { 4378 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4379 u8 thermal_value, delta; 4380 4381 if (rtwdev->efuse.thermal_meter[path] == 0xff) 4382 return; 4383 4384 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 4385 4386 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 4387 4388 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 4389 4390 dm_info->delta_power_index[path] = 4391 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 4392 delta); 4393 4394 rtw8822c_pwrtrack_set(rtwdev, path); 4395 } 4396 4397 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 4398 { 4399 struct rtw_swing_table swing_table; 4400 u8 i; 4401 4402 rtw_phy_config_swing_table(rtwdev, &swing_table); 4403 4404 if (rtw_phy_pwrtrack_need_lck(rtwdev)) 4405 rtw8822c_do_lck(rtwdev); 4406 4407 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 4408 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 4409 4410 } 4411 4412 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 4413 { 4414 struct rtw_efuse *efuse = &rtwdev->efuse; 4415 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4416 4417 if (efuse->power_track_type != 0) 4418 return; 4419 4420 if (!dm_info->pwr_trk_triggered) { 4421 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 4422 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 4423 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 4424 4425 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 4426 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 4427 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 4428 4429 dm_info->pwr_trk_triggered = true; 4430 return; 4431 } 4432 4433 __rtw8822c_pwr_track(rtwdev); 4434 dm_info->pwr_trk_triggered = false; 4435 } 4436 4437 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 4438 {0x0086, 4439 RTW_PWR_CUT_ALL_MSK, 4440 RTW_PWR_INTF_SDIO_MSK, 4441 RTW_PWR_ADDR_SDIO, 4442 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4443 {0x0086, 4444 RTW_PWR_CUT_ALL_MSK, 4445 RTW_PWR_INTF_SDIO_MSK, 4446 RTW_PWR_ADDR_SDIO, 4447 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 4448 {0x002E, 4449 RTW_PWR_CUT_ALL_MSK, 4450 RTW_PWR_INTF_ALL_MSK, 4451 RTW_PWR_ADDR_MAC, 4452 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4453 {0x002D, 4454 RTW_PWR_CUT_ALL_MSK, 4455 RTW_PWR_INTF_ALL_MSK, 4456 RTW_PWR_ADDR_MAC, 4457 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4458 {0x007F, 4459 RTW_PWR_CUT_ALL_MSK, 4460 RTW_PWR_INTF_ALL_MSK, 4461 RTW_PWR_ADDR_MAC, 4462 RTW_PWR_CMD_WRITE, BIT(7), 0}, 4463 {0x004A, 4464 RTW_PWR_CUT_ALL_MSK, 4465 RTW_PWR_INTF_USB_MSK, 4466 RTW_PWR_ADDR_MAC, 4467 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4468 {0x0005, 4469 RTW_PWR_CUT_ALL_MSK, 4470 RTW_PWR_INTF_ALL_MSK, 4471 RTW_PWR_ADDR_MAC, 4472 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 4473 {0xFFFF, 4474 RTW_PWR_CUT_ALL_MSK, 4475 RTW_PWR_INTF_ALL_MSK, 4476 0, 4477 RTW_PWR_CMD_END, 0, 0}, 4478 }; 4479 4480 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 4481 {0x0000, 4482 RTW_PWR_CUT_ALL_MSK, 4483 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4484 RTW_PWR_ADDR_MAC, 4485 RTW_PWR_CMD_WRITE, BIT(5), 0}, 4486 {0x0005, 4487 RTW_PWR_CUT_ALL_MSK, 4488 RTW_PWR_INTF_ALL_MSK, 4489 RTW_PWR_ADDR_MAC, 4490 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 4491 {0x0075, 4492 RTW_PWR_CUT_ALL_MSK, 4493 RTW_PWR_INTF_PCI_MSK, 4494 RTW_PWR_ADDR_MAC, 4495 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4496 {0x0006, 4497 RTW_PWR_CUT_ALL_MSK, 4498 RTW_PWR_INTF_ALL_MSK, 4499 RTW_PWR_ADDR_MAC, 4500 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 4501 {0x0075, 4502 RTW_PWR_CUT_ALL_MSK, 4503 RTW_PWR_INTF_PCI_MSK, 4504 RTW_PWR_ADDR_MAC, 4505 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4506 {0xFF1A, 4507 RTW_PWR_CUT_ALL_MSK, 4508 RTW_PWR_INTF_USB_MSK, 4509 RTW_PWR_ADDR_MAC, 4510 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4511 {0x002E, 4512 RTW_PWR_CUT_ALL_MSK, 4513 RTW_PWR_INTF_ALL_MSK, 4514 RTW_PWR_ADDR_MAC, 4515 RTW_PWR_CMD_WRITE, BIT(3), 0}, 4516 {0x0006, 4517 RTW_PWR_CUT_ALL_MSK, 4518 RTW_PWR_INTF_ALL_MSK, 4519 RTW_PWR_ADDR_MAC, 4520 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4521 {0x0005, 4522 RTW_PWR_CUT_ALL_MSK, 4523 RTW_PWR_INTF_ALL_MSK, 4524 RTW_PWR_ADDR_MAC, 4525 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 4526 {0x1018, 4527 RTW_PWR_CUT_ALL_MSK, 4528 RTW_PWR_INTF_ALL_MSK, 4529 RTW_PWR_ADDR_MAC, 4530 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4531 {0x0005, 4532 RTW_PWR_CUT_ALL_MSK, 4533 RTW_PWR_INTF_ALL_MSK, 4534 RTW_PWR_ADDR_MAC, 4535 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4536 {0x0005, 4537 RTW_PWR_CUT_ALL_MSK, 4538 RTW_PWR_INTF_ALL_MSK, 4539 RTW_PWR_ADDR_MAC, 4540 RTW_PWR_CMD_POLLING, BIT(0), 0}, 4541 {0x0074, 4542 RTW_PWR_CUT_ALL_MSK, 4543 RTW_PWR_INTF_PCI_MSK, 4544 RTW_PWR_ADDR_MAC, 4545 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 4546 {0x0071, 4547 RTW_PWR_CUT_ALL_MSK, 4548 RTW_PWR_INTF_PCI_MSK, 4549 RTW_PWR_ADDR_MAC, 4550 RTW_PWR_CMD_WRITE, BIT(4), 0}, 4551 {0x0062, 4552 RTW_PWR_CUT_ALL_MSK, 4553 RTW_PWR_INTF_PCI_MSK, 4554 RTW_PWR_ADDR_MAC, 4555 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 4556 (BIT(7) | BIT(6) | BIT(5))}, 4557 {0x0061, 4558 RTW_PWR_CUT_ALL_MSK, 4559 RTW_PWR_INTF_PCI_MSK, 4560 RTW_PWR_ADDR_MAC, 4561 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 4562 {0x001F, 4563 RTW_PWR_CUT_ALL_MSK, 4564 RTW_PWR_INTF_ALL_MSK, 4565 RTW_PWR_ADDR_MAC, 4566 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 4567 {0x00EF, 4568 RTW_PWR_CUT_ALL_MSK, 4569 RTW_PWR_INTF_ALL_MSK, 4570 RTW_PWR_ADDR_MAC, 4571 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 4572 {0x1045, 4573 RTW_PWR_CUT_ALL_MSK, 4574 RTW_PWR_INTF_ALL_MSK, 4575 RTW_PWR_ADDR_MAC, 4576 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 4577 {0x0010, 4578 RTW_PWR_CUT_ALL_MSK, 4579 RTW_PWR_INTF_ALL_MSK, 4580 RTW_PWR_ADDR_MAC, 4581 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4582 {0x1064, 4583 RTW_PWR_CUT_ALL_MSK, 4584 RTW_PWR_INTF_ALL_MSK, 4585 RTW_PWR_ADDR_MAC, 4586 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 4587 {0xFFFF, 4588 RTW_PWR_CUT_ALL_MSK, 4589 RTW_PWR_INTF_ALL_MSK, 4590 0, 4591 RTW_PWR_CMD_END, 0, 0}, 4592 }; 4593 4594 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 4595 {0x0093, 4596 RTW_PWR_CUT_ALL_MSK, 4597 RTW_PWR_INTF_ALL_MSK, 4598 RTW_PWR_ADDR_MAC, 4599 RTW_PWR_CMD_WRITE, BIT(3), 0}, 4600 {0x001F, 4601 RTW_PWR_CUT_ALL_MSK, 4602 RTW_PWR_INTF_ALL_MSK, 4603 RTW_PWR_ADDR_MAC, 4604 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4605 {0x00EF, 4606 RTW_PWR_CUT_ALL_MSK, 4607 RTW_PWR_INTF_ALL_MSK, 4608 RTW_PWR_ADDR_MAC, 4609 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4610 {0x1045, 4611 RTW_PWR_CUT_ALL_MSK, 4612 RTW_PWR_INTF_ALL_MSK, 4613 RTW_PWR_ADDR_MAC, 4614 RTW_PWR_CMD_WRITE, BIT(4), 0}, 4615 {0xFF1A, 4616 RTW_PWR_CUT_ALL_MSK, 4617 RTW_PWR_INTF_USB_MSK, 4618 RTW_PWR_ADDR_MAC, 4619 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 4620 {0x0049, 4621 RTW_PWR_CUT_ALL_MSK, 4622 RTW_PWR_INTF_ALL_MSK, 4623 RTW_PWR_ADDR_MAC, 4624 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4625 {0x0006, 4626 RTW_PWR_CUT_ALL_MSK, 4627 RTW_PWR_INTF_ALL_MSK, 4628 RTW_PWR_ADDR_MAC, 4629 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4630 {0x0002, 4631 RTW_PWR_CUT_ALL_MSK, 4632 RTW_PWR_INTF_ALL_MSK, 4633 RTW_PWR_ADDR_MAC, 4634 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4635 {0x0005, 4636 RTW_PWR_CUT_ALL_MSK, 4637 RTW_PWR_INTF_ALL_MSK, 4638 RTW_PWR_ADDR_MAC, 4639 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 4640 {0x0005, 4641 RTW_PWR_CUT_ALL_MSK, 4642 RTW_PWR_INTF_ALL_MSK, 4643 RTW_PWR_ADDR_MAC, 4644 RTW_PWR_CMD_POLLING, BIT(1), 0}, 4645 {0x0000, 4646 RTW_PWR_CUT_ALL_MSK, 4647 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4648 RTW_PWR_ADDR_MAC, 4649 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 4650 {0xFFFF, 4651 RTW_PWR_CUT_ALL_MSK, 4652 RTW_PWR_INTF_ALL_MSK, 4653 0, 4654 RTW_PWR_CMD_END, 0, 0}, 4655 }; 4656 4657 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 4658 {0x0005, 4659 RTW_PWR_CUT_ALL_MSK, 4660 RTW_PWR_INTF_SDIO_MSK, 4661 RTW_PWR_ADDR_MAC, 4662 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 4663 {0x0007, 4664 RTW_PWR_CUT_ALL_MSK, 4665 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4666 RTW_PWR_ADDR_MAC, 4667 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 4668 {0x0067, 4669 RTW_PWR_CUT_ALL_MSK, 4670 RTW_PWR_INTF_ALL_MSK, 4671 RTW_PWR_ADDR_MAC, 4672 RTW_PWR_CMD_WRITE, BIT(5), 0}, 4673 {0x004A, 4674 RTW_PWR_CUT_ALL_MSK, 4675 RTW_PWR_INTF_USB_MSK, 4676 RTW_PWR_ADDR_MAC, 4677 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4678 {0x0081, 4679 RTW_PWR_CUT_ALL_MSK, 4680 RTW_PWR_INTF_ALL_MSK, 4681 RTW_PWR_ADDR_MAC, 4682 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 4683 {0x0090, 4684 RTW_PWR_CUT_ALL_MSK, 4685 RTW_PWR_INTF_ALL_MSK, 4686 RTW_PWR_ADDR_MAC, 4687 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4688 {0x0092, 4689 RTW_PWR_CUT_ALL_MSK, 4690 RTW_PWR_INTF_PCI_MSK, 4691 RTW_PWR_ADDR_MAC, 4692 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 4693 {0x0093, 4694 RTW_PWR_CUT_ALL_MSK, 4695 RTW_PWR_INTF_PCI_MSK, 4696 RTW_PWR_ADDR_MAC, 4697 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 4698 {0x0005, 4699 RTW_PWR_CUT_ALL_MSK, 4700 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4701 RTW_PWR_ADDR_MAC, 4702 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 4703 {0x0005, 4704 RTW_PWR_CUT_ALL_MSK, 4705 RTW_PWR_INTF_PCI_MSK, 4706 RTW_PWR_ADDR_MAC, 4707 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4708 {0x0086, 4709 RTW_PWR_CUT_ALL_MSK, 4710 RTW_PWR_INTF_SDIO_MSK, 4711 RTW_PWR_ADDR_SDIO, 4712 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4713 {0xFFFF, 4714 RTW_PWR_CUT_ALL_MSK, 4715 RTW_PWR_INTF_ALL_MSK, 4716 0, 4717 RTW_PWR_CMD_END, 0, 0}, 4718 }; 4719 4720 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 4721 trans_carddis_to_cardemu_8822c, 4722 trans_cardemu_to_act_8822c, 4723 NULL 4724 }; 4725 4726 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 4727 trans_act_to_cardemu_8822c, 4728 trans_cardemu_to_carddis_8822c, 4729 NULL 4730 }; 4731 4732 static const struct rtw_intf_phy_para usb2_param_8822c[] = { 4733 {0xFFFF, 0x00, 4734 RTW_IP_SEL_PHY, 4735 RTW_INTF_PHY_CUT_ALL, 4736 RTW_INTF_PHY_PLATFORM_ALL}, 4737 }; 4738 4739 static const struct rtw_intf_phy_para usb3_param_8822c[] = { 4740 {0xFFFF, 0x0000, 4741 RTW_IP_SEL_PHY, 4742 RTW_INTF_PHY_CUT_ALL, 4743 RTW_INTF_PHY_PLATFORM_ALL}, 4744 }; 4745 4746 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 4747 {0xFFFF, 0x0000, 4748 RTW_IP_SEL_PHY, 4749 RTW_INTF_PHY_CUT_ALL, 4750 RTW_INTF_PHY_PLATFORM_ALL}, 4751 }; 4752 4753 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 4754 {0xFFFF, 0x0000, 4755 RTW_IP_SEL_PHY, 4756 RTW_INTF_PHY_CUT_ALL, 4757 RTW_INTF_PHY_PLATFORM_ALL}, 4758 }; 4759 4760 static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 4761 .usb2_para = usb2_param_8822c, 4762 .usb3_para = usb3_param_8822c, 4763 .gen1_para = pcie_gen1_param_8822c, 4764 .gen2_para = pcie_gen2_param_8822c, 4765 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 4766 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 4767 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 4768 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 4769 }; 4770 4771 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 4772 [0] = RTW_DEF_RFE(8822c, 0, 0), 4773 [1] = RTW_DEF_RFE(8822c, 0, 0), 4774 [2] = RTW_DEF_RFE(8822c, 0, 0), 4775 [5] = RTW_DEF_RFE(8822c, 0, 5), 4776 [6] = RTW_DEF_RFE(8822c, 0, 0), 4777 }; 4778 4779 static const struct rtw_hw_reg rtw8822c_dig[] = { 4780 [0] = { .addr = 0x1d70, .mask = 0x7f }, 4781 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 4782 }; 4783 4784 static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = { 4785 .ctrl = LTECOEX_ACCESS_CTRL, 4786 .wdata = LTECOEX_WRITE_DATA, 4787 .rdata = LTECOEX_READ_DATA, 4788 }; 4789 4790 static const struct rtw_page_table page_table_8822c[] = { 4791 {64, 64, 64, 64, 1}, 4792 {64, 64, 64, 64, 1}, 4793 {64, 64, 0, 0, 1}, 4794 {64, 64, 64, 0, 1}, 4795 {64, 64, 64, 64, 1}, 4796 }; 4797 4798 static const struct rtw_rqpn rqpn_table_8822c[] = { 4799 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4800 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4801 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4802 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4803 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4804 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4805 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4806 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 4807 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 4808 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4809 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4810 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 4811 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4812 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4813 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4814 }; 4815 4816 static struct rtw_prioq_addrs prioq_addrs_8822c = { 4817 .prio[RTW_DMA_MAPPING_EXTRA] = { 4818 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 4819 }, 4820 .prio[RTW_DMA_MAPPING_LOW] = { 4821 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 4822 }, 4823 .prio[RTW_DMA_MAPPING_NORMAL] = { 4824 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 4825 }, 4826 .prio[RTW_DMA_MAPPING_HIGH] = { 4827 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 4828 }, 4829 .wsize = true, 4830 }; 4831 4832 static struct rtw_chip_ops rtw8822c_ops = { 4833 .phy_set_param = rtw8822c_phy_set_param, 4834 .read_efuse = rtw8822c_read_efuse, 4835 .query_rx_desc = rtw8822c_query_rx_desc, 4836 .set_channel = rtw8822c_set_channel, 4837 .mac_init = rtw8822c_mac_init, 4838 .dump_fw_crash = rtw8822c_dump_fw_crash, 4839 .read_rf = rtw_phy_read_rf, 4840 .write_rf = rtw_phy_write_rf_reg_mix, 4841 .set_tx_power_index = rtw8822c_set_tx_power_index, 4842 .set_antenna = rtw8822c_set_antenna, 4843 .cfg_ldo25 = rtw8822c_cfg_ldo25, 4844 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 4845 .dpk_track = rtw8822c_dpk_track, 4846 .phy_calibration = rtw8822c_phy_calibration, 4847 .cck_pd_set = rtw8822c_phy_cck_pd_set, 4848 .pwr_track = rtw8822c_pwr_track, 4849 .config_bfee = rtw8822c_bf_config_bfee, 4850 .set_gid_table = rtw_bf_set_gid_table, 4851 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 4852 .cfo_init = rtw8822c_cfo_init, 4853 .cfo_track = rtw8822c_cfo_track, 4854 4855 .coex_set_init = rtw8822c_coex_cfg_init, 4856 .coex_set_ant_switch = NULL, 4857 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 4858 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 4859 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 4860 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 4861 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 4862 }; 4863 4864 /* Shared-Antenna Coex Table */ 4865 static const struct coex_table_para table_sant_8822c[] = { 4866 {0xffffffff, 0xffffffff}, /* case-0 */ 4867 {0x55555555, 0x55555555}, 4868 {0x66555555, 0x66555555}, 4869 {0xaaaaaaaa, 0xaaaaaaaa}, 4870 {0x5a5a5a5a, 0x5a5a5a5a}, 4871 {0xfafafafa, 0xfafafafa}, /* case-5 */ 4872 {0x6a5a5555, 0xaaaaaaaa}, 4873 {0x6a5a56aa, 0x6a5a56aa}, 4874 {0x6a5a5a5a, 0x6a5a5a5a}, 4875 {0x66555555, 0x5a5a5a5a}, 4876 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 4877 {0x66555555, 0x6a5a5aaa}, 4878 {0x66555555, 0x5a5a5aaa}, 4879 {0x66555555, 0x6aaa5aaa}, 4880 {0x66555555, 0xaaaa5aaa}, 4881 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 4882 {0xffff55ff, 0xfafafafa}, 4883 {0xffff55ff, 0x6afa5afa}, 4884 {0xaaffffaa, 0xfafafafa}, 4885 {0xaa5555aa, 0x5a5a5a5a}, 4886 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 4887 {0xaa5555aa, 0xaaaaaaaa}, 4888 {0xffffffff, 0x5a5a5a5a}, 4889 {0xffffffff, 0x5a5a5a5a}, 4890 {0xffffffff, 0x55555555}, 4891 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 4892 {0x55555555, 0x5a5a5a5a}, 4893 {0x55555555, 0xaaaaaaaa}, 4894 {0x55555555, 0x6a5a6a5a}, 4895 {0x66556655, 0x66556655}, 4896 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/ 4897 {0xffffffff, 0x5aaa5aaa}, 4898 {0x56555555, 0x5a5a5aaa}, 4899 }; 4900 4901 /* Non-Shared-Antenna Coex Table */ 4902 static const struct coex_table_para table_nsant_8822c[] = { 4903 {0xffffffff, 0xffffffff}, /* case-100 */ 4904 {0x55555555, 0x55555555}, 4905 {0x66555555, 0x66555555}, 4906 {0xaaaaaaaa, 0xaaaaaaaa}, 4907 {0x5a5a5a5a, 0x5a5a5a5a}, 4908 {0xfafafafa, 0xfafafafa}, /* case-105 */ 4909 {0x5afa5afa, 0x5afa5afa}, 4910 {0x55555555, 0xfafafafa}, 4911 {0x66555555, 0xfafafafa}, 4912 {0x66555555, 0x5a5a5a5a}, 4913 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 4914 {0x66555555, 0xaaaaaaaa}, 4915 {0xffff55ff, 0xfafafafa}, 4916 {0xffff55ff, 0x5afa5afa}, 4917 {0xffff55ff, 0xaaaaaaaa}, 4918 {0xffff55ff, 0xffff55ff}, /* case-115 */ 4919 {0xaaffffaa, 0x5afa5afa}, 4920 {0xaaffffaa, 0xaaaaaaaa}, 4921 {0xffffffff, 0xfafafafa}, 4922 {0xffffffff, 0x5afa5afa}, 4923 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 4924 {0x55ff55ff, 0x5afa5afa}, 4925 {0x55ff55ff, 0xaaaaaaaa}, 4926 {0x55ff55ff, 0x55ff55ff} 4927 }; 4928 4929 /* Shared-Antenna TDMA */ 4930 static const struct coex_tdma_para tdma_sant_8822c[] = { 4931 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 4932 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 4933 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4934 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4935 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4936 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 4937 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4938 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4939 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4940 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4941 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 4942 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4943 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4944 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4945 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4946 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 4947 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 4948 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4949 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4950 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4951 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 4952 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 4953 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 4954 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 4955 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 4956 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 4957 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 4958 { {0x61, 0x08, 0x03, 0x11, 0x11} } 4959 }; 4960 4961 /* Non-Shared-Antenna TDMA */ 4962 static const struct coex_tdma_para tdma_nsant_8822c[] = { 4963 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 4964 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4965 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4966 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4967 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4968 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 4969 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4970 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4971 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4972 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4973 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 4974 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4975 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4976 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4977 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4978 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 4979 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 4980 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4981 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4982 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4983 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 4984 { {0x51, 0x08, 0x03, 0x10, 0x50} } 4985 }; 4986 4987 /* rssi in percentage % (dbm = % - 100) */ 4988 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 4989 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 4990 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 4991 4992 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 4993 static const struct coex_rf_para rf_para_tx_8822c[] = { 4994 {0, 0, false, 7}, /* for normal */ 4995 {0, 16, false, 7}, /* for WL-CPT */ 4996 {8, 17, true, 4}, 4997 {7, 18, true, 4}, 4998 {6, 19, true, 4}, 4999 {5, 20, true, 4} 5000 }; 5001 5002 static const struct coex_rf_para rf_para_rx_8822c[] = { 5003 {0, 0, false, 7}, /* for normal */ 5004 {0, 16, false, 7}, /* for WL-CPT */ 5005 {3, 24, true, 5}, 5006 {2, 26, true, 5}, 5007 {1, 27, true, 5}, 5008 {0, 28, true, 5} 5009 }; 5010 5011 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 5012 5013 static const u8 5014 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5015 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5016 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5017 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5018 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5019 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5020 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5021 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5022 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5023 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5024 }; 5025 5026 static const u8 5027 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5028 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5029 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5030 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5031 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5032 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5033 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5034 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5035 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5036 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5037 }; 5038 5039 static const u8 5040 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5041 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5042 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5043 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5044 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5045 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5046 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5047 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5048 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5049 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5050 }; 5051 5052 static const u8 5053 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5054 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5055 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5056 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5057 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5058 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5059 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5060 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5061 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5062 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5063 }; 5064 5065 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 5066 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 5067 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 5068 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 5069 }; 5070 5071 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 5072 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5073 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 5074 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 5075 }; 5076 5077 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 5078 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 5079 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 5080 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 5081 }; 5082 5083 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 5084 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5085 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 5086 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 5087 }; 5088 5089 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 5090 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 5091 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 5092 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 5093 }; 5094 5095 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 5096 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5097 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 5098 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 5099 }; 5100 5101 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 5102 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 5103 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 5104 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 5105 }; 5106 5107 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 5108 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 5109 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 5110 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 5111 }; 5112 5113 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 5114 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 5115 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 5116 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 5117 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 5118 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 5119 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 5120 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 5121 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 5122 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 5123 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 5124 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 5125 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 5126 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 5127 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 5128 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 5129 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 5130 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 5131 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 5132 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 5133 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 5134 }; 5135 5136 #ifdef CONFIG_PM 5137 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 5138 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 5139 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 5140 WIPHY_WOWLAN_NET_DETECT, 5141 .n_patterns = RTW_MAX_PATTERN_NUM, 5142 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 5143 .pattern_min_len = 1, 5144 .max_nd_match_sets = 4, 5145 }; 5146 #endif 5147 5148 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 5149 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 5150 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 5151 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 5152 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 5153 {0, 0, RTW_REG_DOMAIN_NL}, 5154 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5155 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5156 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 5157 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5158 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 5159 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 5160 {0, 0, RTW_REG_DOMAIN_NL}, 5161 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 5162 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 5163 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 5164 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 5165 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 5166 {0, 0, RTW_REG_DOMAIN_NL}, 5167 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5168 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5169 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 5170 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5171 }; 5172 5173 struct rtw_chip_info rtw8822c_hw_spec = { 5174 .ops = &rtw8822c_ops, 5175 .id = RTW_CHIP_TYPE_8822C, 5176 .fw_name = "rtw88/rtw8822c_fw.bin", 5177 .wlan_cpu = RTW_WCPU_11AC, 5178 .tx_pkt_desc_sz = 48, 5179 .tx_buf_desc_sz = 16, 5180 .rx_pkt_desc_sz = 24, 5181 .rx_buf_desc_sz = 8, 5182 .phy_efuse_size = 512, 5183 .log_efuse_size = 768, 5184 .ptct_efuse_size = 124, 5185 .txff_size = 262144, 5186 .rxff_size = 24576, 5187 .fw_rxff_size = 12288, 5188 .txgi_factor = 2, 5189 .is_pwr_by_rate_dec = false, 5190 .max_power_index = 0x7f, 5191 .csi_buf_pg_num = 50, 5192 .band = RTW_BAND_2G | RTW_BAND_5G, 5193 .page_size = 128, 5194 .dig_min = 0x20, 5195 .ht_supported = true, 5196 .vht_supported = true, 5197 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 5198 .sys_func_en = 0xD8, 5199 .pwr_on_seq = card_enable_flow_8822c, 5200 .pwr_off_seq = card_disable_flow_8822c, 5201 .page_table = page_table_8822c, 5202 .rqpn_table = rqpn_table_8822c, 5203 .prioq_addrs = &prioq_addrs_8822c, 5204 .intf_table = &phy_para_table_8822c, 5205 .dig = rtw8822c_dig, 5206 .dig_cck = NULL, 5207 .rf_base_addr = {0x3c00, 0x4c00}, 5208 .rf_sipi_addr = {0x1808, 0x4108}, 5209 .ltecoex_addr = &rtw8822c_ltecoex_addr, 5210 .mac_tbl = &rtw8822c_mac_tbl, 5211 .agc_tbl = &rtw8822c_agc_tbl, 5212 .bb_tbl = &rtw8822c_bb_tbl, 5213 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 5214 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 5215 .rfe_defs = rtw8822c_rfe_defs, 5216 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 5217 .en_dis_dpd = true, 5218 .dpd_ratemask = DIS_DPD_RATEALL, 5219 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 5220 .iqk_threshold = 8, 5221 .lck_threshold = 8, 5222 .bfer_su_max_num = 2, 5223 .bfer_mu_max_num = 1, 5224 .rx_ldpc = true, 5225 5226 #ifdef CONFIG_PM 5227 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 5228 .wowlan_stub = &rtw_wowlan_stub_8822c, 5229 .max_sched_scan_ssids = 4, 5230 #endif 5231 .coex_para_ver = 0x2103181c, 5232 .bt_desired_ver = 0x1c, 5233 .scbd_support = true, 5234 .new_scbd10_def = true, 5235 .ble_hid_profile_support = true, 5236 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 5237 .bt_rssi_type = COEX_BTRSSI_DBM, 5238 .ant_isolation = 15, 5239 .rssi_tolerance = 2, 5240 .wl_rssi_step = wl_rssi_step_8822c, 5241 .bt_rssi_step = bt_rssi_step_8822c, 5242 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 5243 .table_sant = table_sant_8822c, 5244 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 5245 .table_nsant = table_nsant_8822c, 5246 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 5247 .tdma_sant = tdma_sant_8822c, 5248 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 5249 .tdma_nsant = tdma_nsant_8822c, 5250 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 5251 .wl_rf_para_tx = rf_para_tx_8822c, 5252 .wl_rf_para_rx = rf_para_rx_8822c, 5253 .bt_afh_span_bw20 = 0x24, 5254 .bt_afh_span_bw40 = 0x36, 5255 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 5256 .afh_5g = afh_5g_8822c, 5257 5258 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 5259 .coex_info_hw_regs = coex_info_hw_regs_8822c, 5260 5261 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 5262 }; 5263 EXPORT_SYMBOL(rtw8822c_hw_spec); 5264 5265 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 5266 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 5267 5268 MODULE_AUTHOR("Realtek Corporation"); 5269 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver"); 5270 MODULE_LICENSE("Dual BSD/GPL"); 5271