1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822b.h" 13 #include "rtw8822b_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "bf.h" 18 #include "regd.h" 19 20 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 21 u8 rx_path, bool is_tx2_path); 22 23 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8822b_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 30 { 31 struct rtw_efuse *efuse = &rtwdev->efuse; 32 struct rtw8822b_efuse *map; 33 int i; 34 35 map = (struct rtw8822b_efuse *)log_map; 36 37 efuse->rfe_option = map->rfe_option; 38 efuse->rf_board_option = map->rf_board_option; 39 efuse->crystal_cap = map->xtal_k; 40 efuse->pa_type_2g = map->pa_type; 41 efuse->pa_type_5g = map->pa_type; 42 efuse->lna_type_2g = map->lna_type_2g[0]; 43 efuse->lna_type_5g = map->lna_type_5g[0]; 44 efuse->channel_plan = map->channel_plan; 45 efuse->country_code[0] = map->country_code[0]; 46 efuse->country_code[1] = map->country_code[1]; 47 efuse->bt_setting = map->rf_bt_setting; 48 efuse->regd = map->rf_board_option & 0x7; 49 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; 50 efuse->thermal_meter_k = map->thermal_meter; 51 52 for (i = 0; i < 4; i++) 53 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 54 55 switch (rtw_hci_type(rtwdev)) { 56 case RTW_HCI_TYPE_PCIE: 57 rtw8822be_efuse_parsing(efuse, map); 58 break; 59 default: 60 /* unsupported now */ 61 return -ENOTSUPP; 62 } 63 64 return 0; 65 } 66 67 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev) 68 { 69 /* chip top mux */ 70 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); 71 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); 72 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); 73 74 /* from s0 or s1 */ 75 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); 76 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); 77 78 /* input or output */ 79 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); 80 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); 81 } 82 83 #define RTW_TXSCALE_SIZE 37 84 static const u32 rtw8822b_txscale_tbl[RTW_TXSCALE_SIZE] = { 85 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 86 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 87 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 88 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 89 }; 90 91 static u8 rtw8822b_get_swing_index(struct rtw_dev *rtwdev) 92 { 93 u8 i = 0; 94 u32 swing, table_value; 95 96 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); 97 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { 98 table_value = rtw8822b_txscale_tbl[i]; 99 if (swing == table_value) 100 break; 101 } 102 103 return i; 104 } 105 106 static void rtw8822b_pwrtrack_init(struct rtw_dev *rtwdev) 107 { 108 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 109 u8 swing_idx = rtw8822b_get_swing_index(rtwdev); 110 u8 path; 111 112 if (swing_idx >= RTW_TXSCALE_SIZE) 113 dm_info->default_ofdm_index = 24; 114 else 115 dm_info->default_ofdm_index = swing_idx; 116 117 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 118 ewma_thermal_init(&dm_info->avg_thermal[path]); 119 dm_info->delta_power_index[path] = 0; 120 } 121 dm_info->pwr_trk_triggered = false; 122 dm_info->pwr_trk_init_trigger = true; 123 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 124 } 125 126 static void rtw8822b_phy_bf_init(struct rtw_dev *rtwdev) 127 { 128 rtw_bf_phy_init(rtwdev); 129 /* Grouping bitmap parameters */ 130 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 131 } 132 133 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev) 134 { 135 struct rtw_hal *hal = &rtwdev->hal; 136 u8 crystal_cap; 137 bool is_tx2_path; 138 139 /* power on BB/RF domain */ 140 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 141 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 142 rtw_write8_set(rtwdev, REG_RF_CTRL, 143 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 144 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 145 146 /* pre init before header files config */ 147 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 148 149 rtw_phy_load_tables(rtwdev); 150 151 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 152 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); 153 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); 154 155 /* post init after header files config */ 156 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 157 158 is_tx2_path = false; 159 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 160 is_tx2_path); 161 rtw_phy_init(rtwdev); 162 163 rtw8822b_phy_rfe_init(rtwdev); 164 rtw8822b_pwrtrack_init(rtwdev); 165 166 rtw8822b_phy_bf_init(rtwdev); 167 } 168 169 #define WLAN_SLOT_TIME 0x09 170 #define WLAN_PIFS_TIME 0x19 171 #define WLAN_SIFS_CCK_CONT_TX 0xA 172 #define WLAN_SIFS_OFDM_CONT_TX 0xE 173 #define WLAN_SIFS_CCK_TRX 0x10 174 #define WLAN_SIFS_OFDM_TRX 0x10 175 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ 176 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ 177 #define WLAN_RDG_NAV 0x05 178 #define WLAN_TXOP_NAV 0x1B 179 #define WLAN_CCK_RX_TSF 0x30 180 #define WLAN_OFDM_RX_TSF 0x30 181 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 182 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 183 #define WLAN_DRV_EARLY_INT 0x04 184 #define WLAN_BCN_DMA_TIME 0x02 185 186 #define WLAN_RX_FILTER0 0x0FFFFFFF 187 #define WLAN_RX_FILTER2 0xFFFF 188 #define WLAN_RCR_CFG 0xE400220E 189 #define WLAN_RXPKT_MAX_SZ 12288 190 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 191 192 #define WLAN_AMPDU_MAX_TIME 0x70 193 #define WLAN_RTS_LEN_TH 0xFF 194 #define WLAN_RTS_TX_TIME_TH 0x08 195 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 196 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 197 #define FAST_EDCA_VO_TH 0x06 198 #define FAST_EDCA_VI_TH 0x06 199 #define FAST_EDCA_BE_TH 0x06 200 #define FAST_EDCA_BK_TH 0x06 201 #define WLAN_BAR_RETRY_LIMIT 0x01 202 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 203 204 #define WLAN_TX_FUNC_CFG1 0x30 205 #define WLAN_TX_FUNC_CFG2 0x30 206 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 207 #define WLAN_MAC_OPT_LB_FUNC1 0x80 208 #define WLAN_MAC_OPT_FUNC2 0x30810041 209 210 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 211 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 212 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 213 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 214 215 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 216 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 217 218 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 219 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 220 221 static int rtw8822b_mac_init(struct rtw_dev *rtwdev) 222 { 223 u32 value32; 224 225 /* protocol configuration */ 226 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD); 227 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 228 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 229 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 230 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 231 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 232 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 233 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 234 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 235 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 236 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 237 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 238 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 239 /* EDCA configuration */ 240 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 241 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 242 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 243 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 244 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 245 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 246 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 247 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 248 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 249 /* Set beacon cotnrol - enable TSF and other related functions */ 250 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 251 /* Set send beacon related registers */ 252 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 253 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 254 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 255 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 256 /* WMAC configuration */ 257 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 258 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 259 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 260 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 261 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 262 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 263 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 264 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 265 266 return 0; 267 } 268 269 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel) 270 { 271 struct rtw_hal *hal = &rtwdev->hal; 272 273 if (IS_CH_2G_BAND(channel)) { 274 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); 275 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 276 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); 277 } else { 278 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); 279 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 280 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); 281 } 282 283 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 284 285 if (hal->antenna_rx == BB_PATH_AB || 286 hal->antenna_tx == BB_PATH_AB) { 287 /* 2TX or 2RX */ 288 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 289 } else if (hal->antenna_rx == hal->antenna_tx) { 290 /* TXA+RXA or TXB+RXB */ 291 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 292 } else { 293 /* TXB+RXA or TXA+RXB */ 294 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 295 } 296 } 297 298 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel) 299 { 300 struct rtw_hal *hal = &rtwdev->hal; 301 302 if (IS_CH_2G_BAND(channel)) { 303 /* signal source */ 304 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); 305 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 306 } else { 307 /* signal source */ 308 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); 309 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 310 } 311 312 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 313 314 if (IS_CH_2G_BAND(channel)) { 315 if (hal->antenna_rx == BB_PATH_AB || 316 hal->antenna_tx == BB_PATH_AB) { 317 /* 2TX or 2RX */ 318 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 319 } else if (hal->antenna_rx == hal->antenna_tx) { 320 /* TXA+RXA or TXB+RXB */ 321 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 322 } else { 323 /* TXB+RXA or TXA+RXB */ 324 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 325 } 326 } else { 327 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); 328 } 329 } 330 331 enum { 332 CCUT_IDX_1R_2G, 333 CCUT_IDX_2R_2G, 334 CCUT_IDX_1R_5G, 335 CCUT_IDX_2R_5G, 336 CCUT_IDX_NR, 337 }; 338 339 struct cca_ccut { 340 u32 reg82c[CCUT_IDX_NR]; 341 u32 reg830[CCUT_IDX_NR]; 342 u32 reg838[CCUT_IDX_NR]; 343 }; 344 345 static const struct cca_ccut cca_ifem_ccut = { 346 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ 347 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 348 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/ 349 }; 350 351 static const struct cca_ccut cca_efem_ccut = { 352 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ 353 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/ 354 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ 355 }; 356 357 static const struct cca_ccut cca_ifem_ccut_ext = { 358 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ 359 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 360 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/ 361 }; 362 363 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col, 364 u32 *reg82c, u32 *reg830, u32 *reg838) 365 { 366 *reg82c = cca_ccut->reg82c[col]; 367 *reg830 = cca_ccut->reg830[col]; 368 *reg838 = cca_ccut->reg838[col]; 369 } 370 371 struct rtw8822b_rfe_info { 372 const struct cca_ccut *cca_ccut_2g; 373 const struct cca_ccut *cca_ccut_5g; 374 enum rtw_rfe_fem fem; 375 bool ifem_ext; 376 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel); 377 }; 378 379 #define I2GE5G_CCUT(set_ch) { \ 380 .cca_ccut_2g = &cca_ifem_ccut, \ 381 .cca_ccut_5g = &cca_efem_ccut, \ 382 .fem = RTW_RFE_IFEM2G_EFEM5G, \ 383 .ifem_ext = false, \ 384 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 385 } 386 #define IFEM_EXT_CCUT(set_ch) { \ 387 .cca_ccut_2g = &cca_ifem_ccut_ext, \ 388 .cca_ccut_5g = &cca_ifem_ccut_ext, \ 389 .fem = RTW_RFE_IFEM, \ 390 .ifem_ext = true, \ 391 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 392 } 393 394 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = { 395 [2] = I2GE5G_CCUT(efem), 396 [3] = IFEM_EXT_CCUT(ifem), 397 [5] = IFEM_EXT_CCUT(ifem), 398 }; 399 400 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw, 401 const struct rtw8822b_rfe_info *rfe_info) 402 { 403 struct rtw_hal *hal = &rtwdev->hal; 404 struct rtw_efuse *efuse = &rtwdev->efuse; 405 const struct cca_ccut *cca_ccut; 406 u8 col; 407 u32 reg82c, reg830, reg838; 408 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; 409 410 if (IS_CH_2G_BAND(channel)) { 411 cca_ccut = rfe_info->cca_ccut_2g; 412 413 if (hal->antenna_rx == BB_PATH_A || 414 hal->antenna_rx == BB_PATH_B) 415 col = CCUT_IDX_1R_2G; 416 else 417 col = CCUT_IDX_2R_2G; 418 } else { 419 cca_ccut = rfe_info->cca_ccut_5g; 420 421 if (hal->antenna_rx == BB_PATH_A || 422 hal->antenna_rx == BB_PATH_B) 423 col = CCUT_IDX_1R_5G; 424 else 425 col = CCUT_IDX_2R_5G; 426 } 427 428 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838); 429 430 switch (rfe_info->fem) { 431 case RTW_RFE_IFEM: 432 default: 433 is_ifem_cca = true; 434 if (rfe_info->ifem_ext) 435 is_rfe_type = true; 436 break; 437 case RTW_RFE_EFEM: 438 is_efem_cca = true; 439 break; 440 case RTW_RFE_IFEM2G_EFEM5G: 441 if (IS_CH_2G_BAND(channel)) 442 is_ifem_cca = true; 443 else 444 is_efem_cca = true; 445 break; 446 } 447 448 if (is_ifem_cca) { 449 if ((hal->cut_version == RTW_CHIP_VER_CUT_B && 450 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) && 451 bw == RTW_CHANNEL_WIDTH_40) || 452 (!is_rfe_type && col == CCUT_IDX_2R_5G && 453 bw == RTW_CHANNEL_WIDTH_40) || 454 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G)) 455 reg830 = 0x79a0ea28; 456 } 457 458 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c); 459 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830); 460 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838); 461 462 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B)) 463 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); 464 465 if (bw == RTW_CHANNEL_WIDTH_20 && IS_CH_5G_BAND_MID(channel)) 466 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); 467 } 468 469 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 470 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; 471 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 472 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 473 0x6, 0x5, 0x0, 0x0, 0x7}; 474 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 475 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; 476 477 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 478 { 479 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 480 #define RF18_BAND_2G (0) 481 #define RF18_BAND_5G (BIT(16) | BIT(8)) 482 #define RF18_CHANNEL_MASK (MASKBYTE0) 483 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 484 #define RF18_RFSI_GE_CH80 (BIT(17)) 485 #define RF18_RFSI_GT_CH144 (BIT(18)) 486 #define RF18_BW_MASK (BIT(11) | BIT(10)) 487 #define RF18_BW_20M (BIT(11) | BIT(10)) 488 #define RF18_BW_40M (BIT(11)) 489 #define RF18_BW_80M (BIT(10)) 490 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) 491 492 struct rtw_hal *hal = &rtwdev->hal; 493 u32 rf_reg18, rf_reg_be; 494 495 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 496 497 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 498 RF18_BW_MASK); 499 500 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 501 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 502 if (channel > 144) 503 rf_reg18 |= RF18_RFSI_GT_CH144; 504 else if (channel >= 80) 505 rf_reg18 |= RF18_RFSI_GE_CH80; 506 507 switch (bw) { 508 case RTW_CHANNEL_WIDTH_5: 509 case RTW_CHANNEL_WIDTH_10: 510 case RTW_CHANNEL_WIDTH_20: 511 default: 512 rf_reg18 |= RF18_BW_20M; 513 break; 514 case RTW_CHANNEL_WIDTH_40: 515 rf_reg18 |= RF18_BW_40M; 516 break; 517 case RTW_CHANNEL_WIDTH_80: 518 rf_reg18 |= RF18_BW_80M; 519 break; 520 } 521 522 if (IS_CH_2G_BAND(channel)) 523 rf_reg_be = 0x0; 524 else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 525 rf_reg_be = low_band[(channel - 36) >> 1]; 526 else if (IS_CH_5G_BAND_3(channel)) 527 rf_reg_be = middle_band[(channel - 100) >> 1]; 528 else if (IS_CH_5G_BAND_4(channel)) 529 rf_reg_be = high_band[(channel - 149) >> 1]; 530 else 531 goto err; 532 533 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be); 534 535 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ 536 if (channel == 144) 537 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); 538 else 539 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); 540 541 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 542 if (hal->rf_type > RF_1T1R) 543 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); 544 545 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 546 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 547 548 return; 549 550 err: 551 WARN_ON(1); 552 } 553 554 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev) 555 { 556 struct rtw_hal *hal = &rtwdev->hal; 557 u32 igi; 558 559 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); 560 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); 561 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); 562 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); 563 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); 564 565 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); 566 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 567 hal->antenna_rx | (hal->antenna_rx << 4)); 568 } 569 570 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 571 { 572 if (bw == RTW_CHANNEL_WIDTH_40) { 573 /* RX DFIR for BW40 */ 574 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); 575 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); 576 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 577 } else if (bw == RTW_CHANNEL_WIDTH_80) { 578 /* RX DFIR for BW80 */ 579 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 580 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 581 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 582 } else { 583 /* RX DFIR for BW20, BW10 and BW5*/ 584 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 585 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 586 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 587 } 588 } 589 590 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 591 u8 primary_ch_idx) 592 { 593 struct rtw_efuse *efuse = &rtwdev->efuse; 594 u8 rfe_option = efuse->rfe_option; 595 u32 val32; 596 597 if (IS_CH_2G_BAND(channel)) { 598 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 599 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 600 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 601 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 602 603 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); 604 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 605 if (channel == 14) { 606 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); 607 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 608 } else { 609 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); 610 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); 611 } 612 613 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); 614 } else if (IS_CH_5G_BAND(channel)) { 615 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 616 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 617 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 618 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); 619 620 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 621 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); 622 else if (IS_CH_5G_BAND_3(channel)) 623 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); 624 else if (IS_CH_5G_BAND_4(channel)) 625 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); 626 627 if (IS_CH_5G_BAND_1(channel)) 628 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 629 else if (IS_CH_5G_BAND_2(channel)) 630 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 631 else if (channel >= 100 && channel <= 116) 632 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 633 else if (channel >= 118 && channel <= 177) 634 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 635 636 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); 637 } 638 639 switch (bw) { 640 case RTW_CHANNEL_WIDTH_20: 641 default: 642 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 643 val32 &= 0xFFCFFC00; 644 val32 |= (RTW_CHANNEL_WIDTH_20); 645 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 646 647 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 648 break; 649 case RTW_CHANNEL_WIDTH_40: 650 if (primary_ch_idx == RTW_SC_20_UPPER) 651 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 652 else 653 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 654 655 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 656 val32 &= 0xFF3FF300; 657 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); 658 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 659 660 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 661 break; 662 case RTW_CHANNEL_WIDTH_80: 663 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 664 val32 &= 0xFCEFCF00; 665 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); 666 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 667 668 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 669 670 if (rfe_option == 2 || rfe_option == 3) { 671 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); 672 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); 673 } 674 break; 675 case RTW_CHANNEL_WIDTH_5: 676 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 677 val32 &= 0xEFEEFE00; 678 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); 679 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 680 681 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 682 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 683 break; 684 case RTW_CHANNEL_WIDTH_10: 685 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 686 val32 &= 0xEFFEFF00; 687 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); 688 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 689 690 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 691 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 692 break; 693 } 694 } 695 696 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 697 u8 primary_chan_idx) 698 { 699 struct rtw_efuse *efuse = &rtwdev->efuse; 700 const struct rtw8822b_rfe_info *rfe_info; 701 702 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 703 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 704 return; 705 706 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 707 708 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 709 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 710 rtw8822b_set_channel_rf(rtwdev, channel, bw); 711 rtw8822b_set_channel_rxdfir(rtwdev, bw); 712 rtw8822b_toggle_igi(rtwdev); 713 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info); 714 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel); 715 } 716 717 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 718 u8 rx_path, bool is_tx2_path) 719 { 720 struct rtw_efuse *efuse = &rtwdev->efuse; 721 const struct rtw8822b_rfe_info *rfe_info; 722 u8 ch = rtwdev->hal.current_channel; 723 u8 tx_path_sel, rx_path_sel; 724 int counter; 725 726 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 727 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 728 return; 729 730 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 731 732 if ((tx_path | rx_path) & BB_PATH_A) 733 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); 734 else 735 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); 736 737 if ((tx_path | rx_path) & BB_PATH_B) 738 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); 739 else 740 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); 741 742 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); 743 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); 744 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); 745 746 if (tx_path & BB_PATH_A) { 747 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); 748 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); 749 } else if (tx_path & BB_PATH_B) { 750 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); 751 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); 752 } 753 754 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B) 755 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); 756 else 757 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); 758 759 tx_path_sel = (tx_path << 4) | tx_path; 760 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel); 761 762 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) { 763 if (is_tx2_path || rtwdev->mp_mode) { 764 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); 765 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); 766 } 767 } 768 769 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); 770 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); 771 772 if (rx_path & BB_PATH_A) 773 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); 774 else if (rx_path & BB_PATH_B) 775 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); 776 777 rx_path_sel = (rx_path << 4) | rx_path; 778 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); 779 780 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 781 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); 782 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); 783 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); 784 } else { 785 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); 786 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); 787 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); 788 } 789 790 for (counter = 100; counter > 0; counter--) { 791 u32 rf_reg33; 792 793 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 794 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 795 796 udelay(2); 797 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); 798 799 if (rf_reg33 == 0x00001) 800 break; 801 } 802 803 if (WARN(counter <= 0, "write RF mode table fail\n")) 804 return; 805 806 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 807 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 808 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); 809 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); 810 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 811 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 812 813 rtw8822b_toggle_igi(rtwdev); 814 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info); 815 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch); 816 } 817 818 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 819 struct rtw_rx_pkt_stat *pkt_stat) 820 { 821 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 822 s8 min_rx_power = -120; 823 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 824 825 /* 8822B uses only 1 antenna to RX CCK rates */ 826 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110; 827 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 828 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 829 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 830 min_rx_power); 831 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 832 } 833 834 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 835 struct rtw_rx_pkt_stat *pkt_stat) 836 { 837 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 838 u8 rxsc, bw; 839 s8 min_rx_power = -120; 840 s8 rx_evm; 841 u8 evm_dbm = 0; 842 u8 rssi; 843 int path; 844 845 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 846 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 847 else 848 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 849 850 if (rxsc >= 1 && rxsc <= 8) 851 bw = RTW_CHANNEL_WIDTH_20; 852 else if (rxsc >= 9 && rxsc <= 12) 853 bw = RTW_CHANNEL_WIDTH_40; 854 else if (rxsc >= 13) 855 bw = RTW_CHANNEL_WIDTH_80; 856 else 857 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 858 859 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 860 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 861 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 862 pkt_stat->bw = bw; 863 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 864 pkt_stat->rx_power[RF_PATH_B], 865 min_rx_power); 866 867 dm_info->curr_rx_rate = pkt_stat->rate; 868 869 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 870 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 871 872 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 873 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 874 875 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 876 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 877 878 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 879 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 880 dm_info->rssi[path] = rssi; 881 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 882 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 883 884 rx_evm = pkt_stat->rx_evm[path]; 885 886 if (rx_evm < 0) { 887 if (rx_evm == S8_MIN) 888 evm_dbm = 0; 889 else 890 evm_dbm = ((u8)-rx_evm >> 1); 891 } 892 dm_info->rx_evm_dbm[path] = evm_dbm; 893 } 894 } 895 896 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 897 struct rtw_rx_pkt_stat *pkt_stat) 898 { 899 u8 page; 900 901 page = *phy_status & 0xf; 902 903 switch (page) { 904 case 0: 905 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 906 break; 907 case 1: 908 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 909 break; 910 default: 911 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 912 return; 913 } 914 } 915 916 static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 917 struct rtw_rx_pkt_stat *pkt_stat, 918 struct ieee80211_rx_status *rx_status) 919 { 920 struct ieee80211_hdr *hdr; 921 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 922 u8 *phy_status = NULL; 923 924 memset(pkt_stat, 0, sizeof(*pkt_stat)); 925 926 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 927 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 928 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 929 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 930 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 931 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 932 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 933 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 934 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 935 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 936 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 937 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 938 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 939 940 /* drv_info_sz is in unit of 8-bytes */ 941 pkt_stat->drv_info_sz *= 8; 942 943 /* c2h cmd pkt's rx/phy status is not interested */ 944 if (pkt_stat->is_c2h) 945 return; 946 947 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 948 pkt_stat->drv_info_sz); 949 if (pkt_stat->phy_status) { 950 phy_status = rx_desc + desc_sz + pkt_stat->shift; 951 query_phy_status(rtwdev, phy_status, pkt_stat); 952 } 953 954 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 955 } 956 957 static void 958 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 959 { 960 struct rtw_hal *hal = &rtwdev->hal; 961 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 962 static u32 phy_pwr_idx; 963 u8 rate, rate_idx, pwr_index, shift; 964 int j; 965 966 for (j = 0; j < rtw_rate_size[rs]; j++) { 967 rate = rtw_rate_section[rs][j]; 968 pwr_index = hal->tx_pwr_tbl[path][rate]; 969 shift = rate & 0x3; 970 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 971 if (shift == 0x3) { 972 rate_idx = rate & 0xfc; 973 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 974 phy_pwr_idx); 975 phy_pwr_idx = 0; 976 } 977 } 978 } 979 980 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev) 981 { 982 struct rtw_hal *hal = &rtwdev->hal; 983 int rs, path; 984 985 for (path = 0; path < hal->rf_path_num; path++) { 986 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 987 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs); 988 } 989 } 990 991 static bool rtw8822b_check_rf_path(u8 antenna) 992 { 993 switch (antenna) { 994 case BB_PATH_A: 995 case BB_PATH_B: 996 case BB_PATH_AB: 997 return true; 998 default: 999 return false; 1000 } 1001 } 1002 1003 static int rtw8822b_set_antenna(struct rtw_dev *rtwdev, 1004 u32 antenna_tx, 1005 u32 antenna_rx) 1006 { 1007 struct rtw_hal *hal = &rtwdev->hal; 1008 1009 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", 1010 antenna_tx, antenna_rx); 1011 1012 if (!rtw8822b_check_rf_path(antenna_tx)) { 1013 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 1014 return -EINVAL; 1015 } 1016 1017 if (!rtw8822b_check_rf_path(antenna_rx)) { 1018 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 1019 return -EINVAL; 1020 } 1021 1022 hal->antenna_tx = antenna_tx; 1023 hal->antenna_rx = antenna_rx; 1024 1025 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 1026 1027 return 0; 1028 } 1029 1030 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1031 { 1032 u8 ldo_pwr; 1033 1034 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 1035 ldo_pwr = enable ? ldo_pwr | BIT_LDO25_EN : ldo_pwr & ~BIT_LDO25_EN; 1036 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 1037 } 1038 1039 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev) 1040 { 1041 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1042 u32 cck_enable; 1043 u32 cck_fa_cnt; 1044 u32 ofdm_fa_cnt; 1045 u32 crc32_cnt; 1046 u32 cca32_cnt; 1047 1048 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); 1049 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); 1050 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); 1051 1052 dm_info->cck_fa_cnt = cck_fa_cnt; 1053 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1054 dm_info->total_fa_cnt = ofdm_fa_cnt; 1055 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 1056 1057 crc32_cnt = rtw_read32(rtwdev, 0xf04); 1058 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 1059 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1060 crc32_cnt = rtw_read32(rtwdev, 0xf14); 1061 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 1062 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1063 crc32_cnt = rtw_read32(rtwdev, 0xf10); 1064 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 1065 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1066 crc32_cnt = rtw_read32(rtwdev, 0xf0c); 1067 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 1068 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1069 1070 cca32_cnt = rtw_read32(rtwdev, 0xf08); 1071 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 1072 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 1073 if (cck_enable) { 1074 cca32_cnt = rtw_read32(rtwdev, 0xfcc); 1075 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 1076 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 1077 } 1078 1079 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); 1080 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); 1081 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); 1082 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); 1083 rtw_write32_set(rtwdev, 0xb58, BIT(0)); 1084 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); 1085 } 1086 1087 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev) 1088 { 1089 static int do_iqk_cnt; 1090 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 1091 u32 rf_reg, iqk_fail_mask; 1092 int counter; 1093 bool reload; 1094 1095 rtw_fw_do_iqk(rtwdev, ¶); 1096 1097 for (counter = 0; counter < 300; counter++) { 1098 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 1099 if (rf_reg == 0xabcde) 1100 break; 1101 msleep(20); 1102 } 1103 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 1104 1105 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 1106 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 1107 rtw_dbg(rtwdev, RTW_DBG_PHY, 1108 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 1109 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 1110 } 1111 1112 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev) 1113 { 1114 rtw8822b_do_iqk(rtwdev); 1115 } 1116 1117 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev) 1118 { 1119 /* enable TBTT nterrupt */ 1120 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1121 1122 /* BT report packet sample rate */ 1123 /* 0x790[5:0]=0x5 */ 1124 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 1125 1126 /* enable BT counter statistics */ 1127 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1128 1129 /* enable PTA (3-wire function form BT side) */ 1130 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1131 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 1132 1133 /* enable PTA (tx/rx signal form WiFi side) */ 1134 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1135 /* wl tx signal to PTA not case EDCCA */ 1136 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 1137 /* GNT_BT=1 while select both */ 1138 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 1139 } 1140 1141 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev, 1142 u8 ctrl_type, u8 pos_type) 1143 { 1144 struct rtw_coex *coex = &rtwdev->coex; 1145 struct rtw_coex_dm *coex_dm = &coex->dm; 1146 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1147 bool polarity_inverse; 1148 u8 regval = 0; 1149 1150 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status) 1151 return; 1152 1153 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type; 1154 1155 if (coex_rfe->ant_switch_diversity && 1156 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 1157 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 1158 1159 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 1160 1161 switch (ctrl_type) { 1162 default: 1163 case COEX_SWITCH_CTRL_BY_BBSW: 1164 /* 0x4c[23] = 0 */ 1165 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1166 /* 0x4c[24] = 1 */ 1167 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1168 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1169 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); 1170 1171 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 1172 if (coex_rfe->rfe_module_type != 0x4 && 1173 coex_rfe->rfe_module_type != 0x2) 1174 regval = 0x3; 1175 else 1176 regval = (!polarity_inverse ? 0x2 : 0x1); 1177 } else if (pos_type == COEX_SWITCH_TO_WLG) { 1178 regval = (!polarity_inverse ? 0x2 : 0x1); 1179 } else { 1180 regval = (!polarity_inverse ? 0x1 : 0x2); 1181 } 1182 1183 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1184 break; 1185 case COEX_SWITCH_CTRL_BY_PTA: 1186 /* 0x4c[23] = 0 */ 1187 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1188 /* 0x4c[24] = 1 */ 1189 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1190 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1191 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); 1192 1193 regval = (!polarity_inverse ? 0x2 : 0x1); 1194 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1195 break; 1196 case COEX_SWITCH_CTRL_BY_ANTDIV: 1197 /* 0x4c[23] = 0 */ 1198 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1199 /* 0x4c[24] = 1 */ 1200 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1201 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); 1202 break; 1203 case COEX_SWITCH_CTRL_BY_MAC: 1204 /* 0x4c[23] = 1 */ 1205 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); 1206 1207 regval = (!polarity_inverse ? 0x0 : 0x1); 1208 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); 1209 break; 1210 case COEX_SWITCH_CTRL_BY_FW: 1211 /* 0x4c[23] = 0 */ 1212 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1213 /* 0x4c[24] = 1 */ 1214 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1215 break; 1216 case COEX_SWITCH_CTRL_BY_BT: 1217 /* 0x4c[23] = 0 */ 1218 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1219 /* 0x4c[24] = 0 */ 1220 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); 1221 break; 1222 } 1223 } 1224 1225 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1226 { 1227 } 1228 1229 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1230 { 1231 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 1232 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 1233 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 1234 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 1235 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 1236 } 1237 1238 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1239 { 1240 struct rtw_coex *coex = &rtwdev->coex; 1241 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1242 struct rtw_efuse *efuse = &rtwdev->efuse; 1243 bool is_ext_fem = false; 1244 1245 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1246 coex_rfe->ant_switch_polarity = 0; 1247 coex_rfe->ant_switch_diversity = false; 1248 if (coex_rfe->rfe_module_type == 0x12 || 1249 coex_rfe->rfe_module_type == 0x15 || 1250 coex_rfe->rfe_module_type == 0x16) 1251 coex_rfe->ant_switch_exist = false; 1252 else 1253 coex_rfe->ant_switch_exist = true; 1254 1255 if (coex_rfe->rfe_module_type == 2 || 1256 coex_rfe->rfe_module_type == 4) { 1257 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true); 1258 is_ext_fem = true; 1259 } else { 1260 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false); 1261 } 1262 1263 coex_rfe->wlg_at_btg = false; 1264 1265 if (efuse->share_ant && 1266 coex_rfe->ant_switch_exist && !is_ext_fem) 1267 coex_rfe->ant_switch_with_bt = true; 1268 else 1269 coex_rfe->ant_switch_with_bt = false; 1270 1271 /* Ext switch buffer mux */ 1272 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); 1273 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); 1274 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); 1275 1276 /* Disable LTE Coex Function in WiFi side */ 1277 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); 1278 1279 /* BTC_CTT_WL_VS_LTE */ 1280 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1281 1282 /* BTC_CTT_BT_VS_LTE */ 1283 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1284 } 1285 1286 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1287 { 1288 struct rtw_coex *coex = &rtwdev->coex; 1289 struct rtw_coex_dm *coex_dm = &coex->dm; 1290 static const u16 reg_addr[] = {0xc58, 0xe58}; 1291 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; 1292 u8 i, pwr; 1293 1294 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1295 return; 1296 1297 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1298 1299 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1300 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1301 1302 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1303 1304 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) 1305 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); 1306 } 1307 1308 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1309 { 1310 struct rtw_coex *coex = &rtwdev->coex; 1311 struct rtw_coex_dm *coex_dm = &coex->dm; 1312 /* WL Rx Low gain on */ 1313 static const u32 wl_rx_low_gain_on[] = { 1314 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 1315 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 1316 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 1317 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 1318 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 1319 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 1320 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 1321 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, 1322 0x007e0403 1323 }; 1324 1325 /* WL Rx Low gain off */ 1326 static const u32 wl_rx_low_gain_off[] = { 1327 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 1328 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 1329 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 1330 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 1331 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 1332 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 1333 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 1334 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, 1335 0x007e0403 1336 }; 1337 u8 i; 1338 1339 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1340 return; 1341 1342 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1343 1344 if (coex_dm->cur_wl_rx_low_gain_en) { 1345 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); 1346 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1347 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]); 1348 1349 /* set Rx filter corner RCK offset */ 1350 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); 1351 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); 1352 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); 1353 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); 1354 } else { 1355 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); 1356 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1357 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); 1358 1359 /* set Rx filter corner RCK offset */ 1360 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); 1361 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); 1362 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); 1363 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); 1364 } 1365 } 1366 1367 static void rtw8822b_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path, 1368 u8 tx_pwr_idx_offset, 1369 s8 *txagc_idx, u8 *swing_idx) 1370 { 1371 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1372 s8 delta_pwr_idx = dm_info->delta_power_index[path]; 1373 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 1374 u8 swing_lower_bound = 0; 1375 u8 max_tx_pwr_idx_offset = 0xf; 1376 s8 agc_index = 0; 1377 u8 swing_index = dm_info->default_ofdm_index; 1378 1379 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset); 1380 1381 if (delta_pwr_idx >= 0) { 1382 if (delta_pwr_idx <= tx_pwr_idx_offset) { 1383 agc_index = delta_pwr_idx; 1384 swing_index = dm_info->default_ofdm_index; 1385 } else if (delta_pwr_idx > tx_pwr_idx_offset) { 1386 agc_index = tx_pwr_idx_offset; 1387 swing_index = dm_info->default_ofdm_index + 1388 delta_pwr_idx - tx_pwr_idx_offset; 1389 swing_index = min_t(u8, swing_index, swing_upper_bound); 1390 } 1391 } else { 1392 if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) 1393 swing_index = 1394 dm_info->default_ofdm_index + delta_pwr_idx; 1395 else 1396 swing_index = swing_lower_bound; 1397 swing_index = max_t(u8, swing_index, swing_lower_bound); 1398 1399 agc_index = 0; 1400 } 1401 1402 if (swing_index >= RTW_TXSCALE_SIZE) { 1403 rtw_warn(rtwdev, "swing index overflow\n"); 1404 swing_index = RTW_TXSCALE_SIZE - 1; 1405 } 1406 *txagc_idx = agc_index; 1407 *swing_idx = swing_index; 1408 } 1409 1410 static void rtw8822b_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path, 1411 u8 pwr_idx_offset) 1412 { 1413 s8 txagc_idx; 1414 u8 swing_idx; 1415 u32 reg1, reg2; 1416 1417 if (path == RF_PATH_A) { 1418 reg1 = 0xc94; 1419 reg2 = 0xc1c; 1420 } else if (path == RF_PATH_B) { 1421 reg1 = 0xe94; 1422 reg2 = 0xe1c; 1423 } else { 1424 return; 1425 } 1426 1427 rtw8822b_txagc_swing_offset(rtwdev, path, pwr_idx_offset, 1428 &txagc_idx, &swing_idx); 1429 rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx); 1430 rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21), 1431 rtw8822b_txscale_tbl[swing_idx]); 1432 } 1433 1434 static void rtw8822b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1435 { 1436 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1437 u8 pwr_idx_offset, tx_pwr_idx; 1438 u8 channel = rtwdev->hal.current_channel; 1439 u8 band_width = rtwdev->hal.current_band_width; 1440 u8 regd = rtw_regd_get(rtwdev); 1441 u8 tx_rate = dm_info->tx_rate; 1442 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1443 1444 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate, 1445 band_width, channel, regd); 1446 1447 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1448 1449 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1450 1451 rtw8822b_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset); 1452 } 1453 1454 static void rtw8822b_phy_pwrtrack_path(struct rtw_dev *rtwdev, 1455 struct rtw_swing_table *swing_table, 1456 u8 path) 1457 { 1458 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1459 u8 power_idx_cur, power_idx_last; 1460 u8 delta; 1461 1462 /* 8822B only has one thermal meter at PATH A */ 1463 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1464 1465 power_idx_last = dm_info->delta_power_index[path]; 1466 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, 1467 path, RF_PATH_A, delta); 1468 1469 /* if delta of power indexes are the same, just skip */ 1470 if (power_idx_cur == power_idx_last) 1471 return; 1472 1473 dm_info->delta_power_index[path] = power_idx_cur; 1474 rtw8822b_pwrtrack_set(rtwdev, path); 1475 } 1476 1477 static void rtw8822b_phy_pwrtrack(struct rtw_dev *rtwdev) 1478 { 1479 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1480 struct rtw_swing_table swing_table; 1481 u8 thermal_value, path; 1482 1483 rtw_phy_config_swing_table(rtwdev, &swing_table); 1484 1485 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) 1486 return; 1487 1488 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1489 1490 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1491 1492 if (dm_info->pwr_trk_init_trigger) 1493 dm_info->pwr_trk_init_trigger = false; 1494 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1495 RF_PATH_A)) 1496 goto iqk; 1497 1498 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 1499 rtw8822b_phy_pwrtrack_path(rtwdev, &swing_table, path); 1500 1501 iqk: 1502 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1503 rtw8822b_do_iqk(rtwdev); 1504 } 1505 1506 static void rtw8822b_pwr_track(struct rtw_dev *rtwdev) 1507 { 1508 struct rtw_efuse *efuse = &rtwdev->efuse; 1509 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1510 1511 if (efuse->power_track_type != 0) 1512 return; 1513 1514 if (!dm_info->pwr_trk_triggered) { 1515 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1516 GENMASK(17, 16), 0x03); 1517 dm_info->pwr_trk_triggered = true; 1518 return; 1519 } 1520 1521 rtw8822b_phy_pwrtrack(rtwdev); 1522 dm_info->pwr_trk_triggered = false; 1523 } 1524 1525 static void rtw8822b_bf_config_bfee_su(struct rtw_dev *rtwdev, 1526 struct rtw_vif *vif, 1527 struct rtw_bfee *bfee, bool enable) 1528 { 1529 if (enable) 1530 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1531 else 1532 rtw_bf_remove_bfee_su(rtwdev, bfee); 1533 } 1534 1535 static void rtw8822b_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1536 struct rtw_vif *vif, 1537 struct rtw_bfee *bfee, bool enable) 1538 { 1539 if (enable) 1540 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1541 else 1542 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1543 } 1544 1545 static void rtw8822b_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1546 struct rtw_bfee *bfee, bool enable) 1547 { 1548 if (bfee->role == RTW_BFEE_SU) 1549 rtw8822b_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1550 else if (bfee->role == RTW_BFEE_MU) 1551 rtw8822b_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1552 else 1553 rtw_warn(rtwdev, "wrong bfee role\n"); 1554 } 1555 1556 static void rtw8822b_adaptivity_init(struct rtw_dev *rtwdev) 1557 { 1558 rtw_phy_set_edcca_th(rtwdev, RTW8822B_EDCCA_MAX, RTW8822B_EDCCA_MAX); 1559 1560 /* mac edcca state setting */ 1561 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA); 1562 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN); 1563 rtw_write32_mask(rtwdev, REG_EDCCA_SOURCE, BIT_SOURCE_OPTION, 1564 RTW8822B_EDCCA_SRC_DEF); 1565 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0); 1566 1567 /* edcca decision opt */ 1568 rtw_write32_set(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION); 1569 } 1570 1571 static void rtw8822b_adaptivity(struct rtw_dev *rtwdev) 1572 { 1573 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1574 s8 l2h, h2l; 1575 u8 igi; 1576 1577 igi = dm_info->igi_history[0]; 1578 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) { 1579 l2h = max_t(s8, igi + EDCCA_IGI_L2H_DIFF, EDCCA_TH_L2H_LB); 1580 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL; 1581 } else { 1582 l2h = min_t(s8, igi, dm_info->l2h_th_ini); 1583 h2l = l2h - EDCCA_L2H_H2L_DIFF; 1584 } 1585 1586 rtw_phy_set_edcca_th(rtwdev, l2h, h2l); 1587 } 1588 1589 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = { 1590 {0x0086, 1591 RTW_PWR_CUT_ALL_MSK, 1592 RTW_PWR_INTF_SDIO_MSK, 1593 RTW_PWR_ADDR_SDIO, 1594 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1595 {0x0086, 1596 RTW_PWR_CUT_ALL_MSK, 1597 RTW_PWR_INTF_SDIO_MSK, 1598 RTW_PWR_ADDR_SDIO, 1599 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1600 {0x004A, 1601 RTW_PWR_CUT_ALL_MSK, 1602 RTW_PWR_INTF_USB_MSK, 1603 RTW_PWR_ADDR_MAC, 1604 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1605 {0x0005, 1606 RTW_PWR_CUT_ALL_MSK, 1607 RTW_PWR_INTF_ALL_MSK, 1608 RTW_PWR_ADDR_MAC, 1609 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1610 {0x0300, 1611 RTW_PWR_CUT_ALL_MSK, 1612 RTW_PWR_INTF_PCI_MSK, 1613 RTW_PWR_ADDR_MAC, 1614 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1615 {0x0301, 1616 RTW_PWR_CUT_ALL_MSK, 1617 RTW_PWR_INTF_PCI_MSK, 1618 RTW_PWR_ADDR_MAC, 1619 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1620 {0xFFFF, 1621 RTW_PWR_CUT_ALL_MSK, 1622 RTW_PWR_INTF_ALL_MSK, 1623 0, 1624 RTW_PWR_CMD_END, 0, 0}, 1625 }; 1626 1627 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = { 1628 {0x0012, 1629 RTW_PWR_CUT_ALL_MSK, 1630 RTW_PWR_INTF_ALL_MSK, 1631 RTW_PWR_ADDR_MAC, 1632 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1633 {0x0012, 1634 RTW_PWR_CUT_ALL_MSK, 1635 RTW_PWR_INTF_ALL_MSK, 1636 RTW_PWR_ADDR_MAC, 1637 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1638 {0x0020, 1639 RTW_PWR_CUT_ALL_MSK, 1640 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1641 RTW_PWR_ADDR_MAC, 1642 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1643 {0x0001, 1644 RTW_PWR_CUT_ALL_MSK, 1645 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1646 RTW_PWR_ADDR_MAC, 1647 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1648 {0x0000, 1649 RTW_PWR_CUT_ALL_MSK, 1650 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1651 RTW_PWR_ADDR_MAC, 1652 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1653 {0x0005, 1654 RTW_PWR_CUT_ALL_MSK, 1655 RTW_PWR_INTF_ALL_MSK, 1656 RTW_PWR_ADDR_MAC, 1657 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1658 {0x0075, 1659 RTW_PWR_CUT_ALL_MSK, 1660 RTW_PWR_INTF_PCI_MSK, 1661 RTW_PWR_ADDR_MAC, 1662 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1663 {0x0006, 1664 RTW_PWR_CUT_ALL_MSK, 1665 RTW_PWR_INTF_ALL_MSK, 1666 RTW_PWR_ADDR_MAC, 1667 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1668 {0x0075, 1669 RTW_PWR_CUT_ALL_MSK, 1670 RTW_PWR_INTF_PCI_MSK, 1671 RTW_PWR_ADDR_MAC, 1672 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1673 {0xFF1A, 1674 RTW_PWR_CUT_ALL_MSK, 1675 RTW_PWR_INTF_USB_MSK, 1676 RTW_PWR_ADDR_MAC, 1677 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1678 {0x0006, 1679 RTW_PWR_CUT_ALL_MSK, 1680 RTW_PWR_INTF_ALL_MSK, 1681 RTW_PWR_ADDR_MAC, 1682 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1683 {0x0005, 1684 RTW_PWR_CUT_ALL_MSK, 1685 RTW_PWR_INTF_ALL_MSK, 1686 RTW_PWR_ADDR_MAC, 1687 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1688 {0x0005, 1689 RTW_PWR_CUT_ALL_MSK, 1690 RTW_PWR_INTF_ALL_MSK, 1691 RTW_PWR_ADDR_MAC, 1692 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1693 {0x10C3, 1694 RTW_PWR_CUT_ALL_MSK, 1695 RTW_PWR_INTF_USB_MSK, 1696 RTW_PWR_ADDR_MAC, 1697 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1698 {0x0005, 1699 RTW_PWR_CUT_ALL_MSK, 1700 RTW_PWR_INTF_ALL_MSK, 1701 RTW_PWR_ADDR_MAC, 1702 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1703 {0x0005, 1704 RTW_PWR_CUT_ALL_MSK, 1705 RTW_PWR_INTF_ALL_MSK, 1706 RTW_PWR_ADDR_MAC, 1707 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1708 {0x0020, 1709 RTW_PWR_CUT_ALL_MSK, 1710 RTW_PWR_INTF_ALL_MSK, 1711 RTW_PWR_ADDR_MAC, 1712 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1713 {0x10A8, 1714 RTW_PWR_CUT_C_MSK, 1715 RTW_PWR_INTF_ALL_MSK, 1716 RTW_PWR_ADDR_MAC, 1717 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1718 {0x10A9, 1719 RTW_PWR_CUT_C_MSK, 1720 RTW_PWR_INTF_ALL_MSK, 1721 RTW_PWR_ADDR_MAC, 1722 RTW_PWR_CMD_WRITE, 0xFF, 0xef}, 1723 {0x10AA, 1724 RTW_PWR_CUT_C_MSK, 1725 RTW_PWR_INTF_ALL_MSK, 1726 RTW_PWR_ADDR_MAC, 1727 RTW_PWR_CMD_WRITE, 0xFF, 0x0c}, 1728 {0x0068, 1729 RTW_PWR_CUT_C_MSK, 1730 RTW_PWR_INTF_SDIO_MSK, 1731 RTW_PWR_ADDR_MAC, 1732 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1733 {0x0029, 1734 RTW_PWR_CUT_ALL_MSK, 1735 RTW_PWR_INTF_ALL_MSK, 1736 RTW_PWR_ADDR_MAC, 1737 RTW_PWR_CMD_WRITE, 0xFF, 0xF9}, 1738 {0x0024, 1739 RTW_PWR_CUT_ALL_MSK, 1740 RTW_PWR_INTF_ALL_MSK, 1741 RTW_PWR_ADDR_MAC, 1742 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1743 {0x0074, 1744 RTW_PWR_CUT_ALL_MSK, 1745 RTW_PWR_INTF_PCI_MSK, 1746 RTW_PWR_ADDR_MAC, 1747 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1748 {0x00AF, 1749 RTW_PWR_CUT_ALL_MSK, 1750 RTW_PWR_INTF_ALL_MSK, 1751 RTW_PWR_ADDR_MAC, 1752 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1753 {0xFFFF, 1754 RTW_PWR_CUT_ALL_MSK, 1755 RTW_PWR_INTF_ALL_MSK, 1756 0, 1757 RTW_PWR_CMD_END, 0, 0}, 1758 }; 1759 1760 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = { 1761 {0x0003, 1762 RTW_PWR_CUT_ALL_MSK, 1763 RTW_PWR_INTF_SDIO_MSK, 1764 RTW_PWR_ADDR_MAC, 1765 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1766 {0x0093, 1767 RTW_PWR_CUT_ALL_MSK, 1768 RTW_PWR_INTF_ALL_MSK, 1769 RTW_PWR_ADDR_MAC, 1770 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1771 {0x001F, 1772 RTW_PWR_CUT_ALL_MSK, 1773 RTW_PWR_INTF_ALL_MSK, 1774 RTW_PWR_ADDR_MAC, 1775 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1776 {0x00EF, 1777 RTW_PWR_CUT_ALL_MSK, 1778 RTW_PWR_INTF_ALL_MSK, 1779 RTW_PWR_ADDR_MAC, 1780 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1781 {0xFF1A, 1782 RTW_PWR_CUT_ALL_MSK, 1783 RTW_PWR_INTF_USB_MSK, 1784 RTW_PWR_ADDR_MAC, 1785 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 1786 {0x0049, 1787 RTW_PWR_CUT_ALL_MSK, 1788 RTW_PWR_INTF_ALL_MSK, 1789 RTW_PWR_ADDR_MAC, 1790 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1791 {0x0006, 1792 RTW_PWR_CUT_ALL_MSK, 1793 RTW_PWR_INTF_ALL_MSK, 1794 RTW_PWR_ADDR_MAC, 1795 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1796 {0x0002, 1797 RTW_PWR_CUT_ALL_MSK, 1798 RTW_PWR_INTF_ALL_MSK, 1799 RTW_PWR_ADDR_MAC, 1800 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1801 {0x10C3, 1802 RTW_PWR_CUT_ALL_MSK, 1803 RTW_PWR_INTF_USB_MSK, 1804 RTW_PWR_ADDR_MAC, 1805 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1806 {0x0005, 1807 RTW_PWR_CUT_ALL_MSK, 1808 RTW_PWR_INTF_ALL_MSK, 1809 RTW_PWR_ADDR_MAC, 1810 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1811 {0x0005, 1812 RTW_PWR_CUT_ALL_MSK, 1813 RTW_PWR_INTF_ALL_MSK, 1814 RTW_PWR_ADDR_MAC, 1815 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1816 {0x0020, 1817 RTW_PWR_CUT_ALL_MSK, 1818 RTW_PWR_INTF_ALL_MSK, 1819 RTW_PWR_ADDR_MAC, 1820 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1821 {0x0000, 1822 RTW_PWR_CUT_ALL_MSK, 1823 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1824 RTW_PWR_ADDR_MAC, 1825 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1826 {0xFFFF, 1827 RTW_PWR_CUT_ALL_MSK, 1828 RTW_PWR_INTF_ALL_MSK, 1829 0, 1830 RTW_PWR_CMD_END, 0, 0}, 1831 }; 1832 1833 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = { 1834 {0x0005, 1835 RTW_PWR_CUT_ALL_MSK, 1836 RTW_PWR_INTF_SDIO_MSK, 1837 RTW_PWR_ADDR_MAC, 1838 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1839 {0x0007, 1840 RTW_PWR_CUT_ALL_MSK, 1841 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1842 RTW_PWR_ADDR_MAC, 1843 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1844 {0x0067, 1845 RTW_PWR_CUT_ALL_MSK, 1846 RTW_PWR_INTF_ALL_MSK, 1847 RTW_PWR_ADDR_MAC, 1848 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1849 {0x0005, 1850 RTW_PWR_CUT_ALL_MSK, 1851 RTW_PWR_INTF_PCI_MSK, 1852 RTW_PWR_ADDR_MAC, 1853 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1854 {0x004A, 1855 RTW_PWR_CUT_ALL_MSK, 1856 RTW_PWR_INTF_USB_MSK, 1857 RTW_PWR_ADDR_MAC, 1858 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1859 {0x0067, 1860 RTW_PWR_CUT_ALL_MSK, 1861 RTW_PWR_INTF_SDIO_MSK, 1862 RTW_PWR_ADDR_MAC, 1863 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1864 {0x0067, 1865 RTW_PWR_CUT_ALL_MSK, 1866 RTW_PWR_INTF_SDIO_MSK, 1867 RTW_PWR_ADDR_MAC, 1868 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1869 {0x004F, 1870 RTW_PWR_CUT_ALL_MSK, 1871 RTW_PWR_INTF_SDIO_MSK, 1872 RTW_PWR_ADDR_MAC, 1873 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1874 {0x0067, 1875 RTW_PWR_CUT_ALL_MSK, 1876 RTW_PWR_INTF_SDIO_MSK, 1877 RTW_PWR_ADDR_MAC, 1878 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1879 {0x0046, 1880 RTW_PWR_CUT_ALL_MSK, 1881 RTW_PWR_INTF_SDIO_MSK, 1882 RTW_PWR_ADDR_MAC, 1883 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1884 {0x0067, 1885 RTW_PWR_CUT_ALL_MSK, 1886 RTW_PWR_INTF_SDIO_MSK, 1887 RTW_PWR_ADDR_MAC, 1888 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1889 {0x0046, 1890 RTW_PWR_CUT_ALL_MSK, 1891 RTW_PWR_INTF_SDIO_MSK, 1892 RTW_PWR_ADDR_MAC, 1893 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1894 {0x0062, 1895 RTW_PWR_CUT_ALL_MSK, 1896 RTW_PWR_INTF_SDIO_MSK, 1897 RTW_PWR_ADDR_MAC, 1898 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1899 {0x0081, 1900 RTW_PWR_CUT_ALL_MSK, 1901 RTW_PWR_INTF_ALL_MSK, 1902 RTW_PWR_ADDR_MAC, 1903 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1904 {0x0005, 1905 RTW_PWR_CUT_ALL_MSK, 1906 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1907 RTW_PWR_ADDR_MAC, 1908 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1909 {0x0086, 1910 RTW_PWR_CUT_ALL_MSK, 1911 RTW_PWR_INTF_SDIO_MSK, 1912 RTW_PWR_ADDR_SDIO, 1913 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1914 {0x0086, 1915 RTW_PWR_CUT_ALL_MSK, 1916 RTW_PWR_INTF_SDIO_MSK, 1917 RTW_PWR_ADDR_SDIO, 1918 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1919 {0x0090, 1920 RTW_PWR_CUT_ALL_MSK, 1921 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1922 RTW_PWR_ADDR_MAC, 1923 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1924 {0x0044, 1925 RTW_PWR_CUT_ALL_MSK, 1926 RTW_PWR_INTF_SDIO_MSK, 1927 RTW_PWR_ADDR_SDIO, 1928 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1929 {0x0040, 1930 RTW_PWR_CUT_ALL_MSK, 1931 RTW_PWR_INTF_SDIO_MSK, 1932 RTW_PWR_ADDR_SDIO, 1933 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1934 {0x0041, 1935 RTW_PWR_CUT_ALL_MSK, 1936 RTW_PWR_INTF_SDIO_MSK, 1937 RTW_PWR_ADDR_SDIO, 1938 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1939 {0x0042, 1940 RTW_PWR_CUT_ALL_MSK, 1941 RTW_PWR_INTF_SDIO_MSK, 1942 RTW_PWR_ADDR_SDIO, 1943 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1944 {0xFFFF, 1945 RTW_PWR_CUT_ALL_MSK, 1946 RTW_PWR_INTF_ALL_MSK, 1947 0, 1948 RTW_PWR_CMD_END, 0, 0}, 1949 }; 1950 1951 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = { 1952 trans_carddis_to_cardemu_8822b, 1953 trans_cardemu_to_act_8822b, 1954 NULL 1955 }; 1956 1957 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = { 1958 trans_act_to_cardemu_8822b, 1959 trans_cardemu_to_carddis_8822b, 1960 NULL 1961 }; 1962 1963 static const struct rtw_intf_phy_para usb2_param_8822b[] = { 1964 {0xFFFF, 0x00, 1965 RTW_IP_SEL_PHY, 1966 RTW_INTF_PHY_CUT_ALL, 1967 RTW_INTF_PHY_PLATFORM_ALL}, 1968 }; 1969 1970 static const struct rtw_intf_phy_para usb3_param_8822b[] = { 1971 {0x0001, 0xA841, 1972 RTW_IP_SEL_PHY, 1973 RTW_INTF_PHY_CUT_D, 1974 RTW_INTF_PHY_PLATFORM_ALL}, 1975 {0xFFFF, 0x0000, 1976 RTW_IP_SEL_PHY, 1977 RTW_INTF_PHY_CUT_ALL, 1978 RTW_INTF_PHY_PLATFORM_ALL}, 1979 }; 1980 1981 static const struct rtw_intf_phy_para pcie_gen1_param_8822b[] = { 1982 {0x0001, 0xA841, 1983 RTW_IP_SEL_PHY, 1984 RTW_INTF_PHY_CUT_C, 1985 RTW_INTF_PHY_PLATFORM_ALL}, 1986 {0x0002, 0x60C6, 1987 RTW_IP_SEL_PHY, 1988 RTW_INTF_PHY_CUT_C, 1989 RTW_INTF_PHY_PLATFORM_ALL}, 1990 {0x0008, 0x3596, 1991 RTW_IP_SEL_PHY, 1992 RTW_INTF_PHY_CUT_C, 1993 RTW_INTF_PHY_PLATFORM_ALL}, 1994 {0x0009, 0x321C, 1995 RTW_IP_SEL_PHY, 1996 RTW_INTF_PHY_CUT_C, 1997 RTW_INTF_PHY_PLATFORM_ALL}, 1998 {0x000A, 0x9623, 1999 RTW_IP_SEL_PHY, 2000 RTW_INTF_PHY_CUT_C, 2001 RTW_INTF_PHY_PLATFORM_ALL}, 2002 {0x0020, 0x94FF, 2003 RTW_IP_SEL_PHY, 2004 RTW_INTF_PHY_CUT_C, 2005 RTW_INTF_PHY_PLATFORM_ALL}, 2006 {0x0021, 0xFFCF, 2007 RTW_IP_SEL_PHY, 2008 RTW_INTF_PHY_CUT_C, 2009 RTW_INTF_PHY_PLATFORM_ALL}, 2010 {0x0026, 0xC006, 2011 RTW_IP_SEL_PHY, 2012 RTW_INTF_PHY_CUT_C, 2013 RTW_INTF_PHY_PLATFORM_ALL}, 2014 {0x0029, 0xFF0E, 2015 RTW_IP_SEL_PHY, 2016 RTW_INTF_PHY_CUT_C, 2017 RTW_INTF_PHY_PLATFORM_ALL}, 2018 {0x002A, 0x1840, 2019 RTW_IP_SEL_PHY, 2020 RTW_INTF_PHY_CUT_C, 2021 RTW_INTF_PHY_PLATFORM_ALL}, 2022 {0xFFFF, 0x0000, 2023 RTW_IP_SEL_PHY, 2024 RTW_INTF_PHY_CUT_ALL, 2025 RTW_INTF_PHY_PLATFORM_ALL}, 2026 }; 2027 2028 static const struct rtw_intf_phy_para pcie_gen2_param_8822b[] = { 2029 {0x0001, 0xA841, 2030 RTW_IP_SEL_PHY, 2031 RTW_INTF_PHY_CUT_C, 2032 RTW_INTF_PHY_PLATFORM_ALL}, 2033 {0x0002, 0x60C6, 2034 RTW_IP_SEL_PHY, 2035 RTW_INTF_PHY_CUT_C, 2036 RTW_INTF_PHY_PLATFORM_ALL}, 2037 {0x0008, 0x3597, 2038 RTW_IP_SEL_PHY, 2039 RTW_INTF_PHY_CUT_C, 2040 RTW_INTF_PHY_PLATFORM_ALL}, 2041 {0x0009, 0x321C, 2042 RTW_IP_SEL_PHY, 2043 RTW_INTF_PHY_CUT_C, 2044 RTW_INTF_PHY_PLATFORM_ALL}, 2045 {0x000A, 0x9623, 2046 RTW_IP_SEL_PHY, 2047 RTW_INTF_PHY_CUT_C, 2048 RTW_INTF_PHY_PLATFORM_ALL}, 2049 {0x0020, 0x94FF, 2050 RTW_IP_SEL_PHY, 2051 RTW_INTF_PHY_CUT_C, 2052 RTW_INTF_PHY_PLATFORM_ALL}, 2053 {0x0021, 0xFFCF, 2054 RTW_IP_SEL_PHY, 2055 RTW_INTF_PHY_CUT_C, 2056 RTW_INTF_PHY_PLATFORM_ALL}, 2057 {0x0026, 0xC006, 2058 RTW_IP_SEL_PHY, 2059 RTW_INTF_PHY_CUT_C, 2060 RTW_INTF_PHY_PLATFORM_ALL}, 2061 {0x0029, 0xFF0E, 2062 RTW_IP_SEL_PHY, 2063 RTW_INTF_PHY_CUT_C, 2064 RTW_INTF_PHY_PLATFORM_ALL}, 2065 {0x002A, 0x3040, 2066 RTW_IP_SEL_PHY, 2067 RTW_INTF_PHY_CUT_C, 2068 RTW_INTF_PHY_PLATFORM_ALL}, 2069 {0xFFFF, 0x0000, 2070 RTW_IP_SEL_PHY, 2071 RTW_INTF_PHY_CUT_ALL, 2072 RTW_INTF_PHY_PLATFORM_ALL}, 2073 }; 2074 2075 static const struct rtw_intf_phy_para_table phy_para_table_8822b = { 2076 .usb2_para = usb2_param_8822b, 2077 .usb3_para = usb3_param_8822b, 2078 .gen1_para = pcie_gen1_param_8822b, 2079 .gen2_para = pcie_gen2_param_8822b, 2080 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b), 2081 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b), 2082 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b), 2083 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b), 2084 }; 2085 2086 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = { 2087 [2] = RTW_DEF_RFE(8822b, 2, 2), 2088 [3] = RTW_DEF_RFE(8822b, 3, 0), 2089 [5] = RTW_DEF_RFE(8822b, 5, 5), 2090 }; 2091 2092 static const struct rtw_hw_reg rtw8822b_dig[] = { 2093 [0] = { .addr = 0xc50, .mask = 0x7f }, 2094 [1] = { .addr = 0xe50, .mask = 0x7f }, 2095 }; 2096 2097 static const struct rtw_ltecoex_addr rtw8822b_ltecoex_addr = { 2098 .ctrl = LTECOEX_ACCESS_CTRL, 2099 .wdata = LTECOEX_WRITE_DATA, 2100 .rdata = LTECOEX_READ_DATA, 2101 }; 2102 2103 static const struct rtw_page_table page_table_8822b[] = { 2104 {64, 64, 64, 64, 1}, 2105 {64, 64, 64, 64, 1}, 2106 {64, 64, 0, 0, 1}, 2107 {64, 64, 64, 0, 1}, 2108 {64, 64, 64, 64, 1}, 2109 }; 2110 2111 static const struct rtw_rqpn rqpn_table_8822b[] = { 2112 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2113 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2114 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2115 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2116 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2117 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2118 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2119 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2120 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2121 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2122 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2123 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2124 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2125 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2126 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2127 }; 2128 2129 static struct rtw_prioq_addrs prioq_addrs_8822b = { 2130 .prio[RTW_DMA_MAPPING_EXTRA] = { 2131 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 2132 }, 2133 .prio[RTW_DMA_MAPPING_LOW] = { 2134 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 2135 }, 2136 .prio[RTW_DMA_MAPPING_NORMAL] = { 2137 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 2138 }, 2139 .prio[RTW_DMA_MAPPING_HIGH] = { 2140 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 2141 }, 2142 .wsize = true, 2143 }; 2144 2145 static struct rtw_chip_ops rtw8822b_ops = { 2146 .phy_set_param = rtw8822b_phy_set_param, 2147 .read_efuse = rtw8822b_read_efuse, 2148 .query_rx_desc = rtw8822b_query_rx_desc, 2149 .set_channel = rtw8822b_set_channel, 2150 .mac_init = rtw8822b_mac_init, 2151 .read_rf = rtw_phy_read_rf, 2152 .write_rf = rtw_phy_write_rf_reg_sipi, 2153 .set_tx_power_index = rtw8822b_set_tx_power_index, 2154 .set_antenna = rtw8822b_set_antenna, 2155 .cfg_ldo25 = rtw8822b_cfg_ldo25, 2156 .false_alarm_statistics = rtw8822b_false_alarm_statistics, 2157 .phy_calibration = rtw8822b_phy_calibration, 2158 .pwr_track = rtw8822b_pwr_track, 2159 .config_bfee = rtw8822b_bf_config_bfee, 2160 .set_gid_table = rtw_bf_set_gid_table, 2161 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 2162 .adaptivity_init = rtw8822b_adaptivity_init, 2163 .adaptivity = rtw8822b_adaptivity, 2164 2165 .coex_set_init = rtw8822b_coex_cfg_init, 2166 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch, 2167 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix, 2168 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug, 2169 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type, 2170 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power, 2171 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain, 2172 }; 2173 2174 /* Shared-Antenna Coex Table */ 2175 static const struct coex_table_para table_sant_8822b[] = { 2176 {0xffffffff, 0xffffffff}, /* case-0 */ 2177 {0x55555555, 0x55555555}, 2178 {0x66555555, 0x66555555}, 2179 {0xaaaaaaaa, 0xaaaaaaaa}, 2180 {0x5a5a5a5a, 0x5a5a5a5a}, 2181 {0xfafafafa, 0xfafafafa}, /* case-5 */ 2182 {0x6a5a5555, 0xaaaaaaaa}, 2183 {0x6a5a56aa, 0x6a5a56aa}, 2184 {0x6a5a5a5a, 0x6a5a5a5a}, 2185 {0x66555555, 0x5a5a5a5a}, 2186 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 2187 {0x66555555, 0xfafafafa}, 2188 {0x66555555, 0x5a5a5aaa}, 2189 {0x66555555, 0x6aaa5aaa}, 2190 {0x66555555, 0xaaaa5aaa}, 2191 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 2192 {0xffff55ff, 0xfafafafa}, 2193 {0xffff55ff, 0x6afa5afa}, 2194 {0xaaffffaa, 0xfafafafa}, 2195 {0xaa5555aa, 0x5a5a5a5a}, 2196 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 2197 {0xaa5555aa, 0xaaaaaaaa}, 2198 {0xffffffff, 0x5a5a5a5a}, 2199 {0xffffffff, 0x5a5a5a5a}, 2200 {0xffffffff, 0x55555555}, 2201 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 2202 {0x55555555, 0x5a5a5a5a}, 2203 {0x55555555, 0xaaaaaaaa}, 2204 {0x55555555, 0x6a5a6a5a}, 2205 {0x66556655, 0x66556655}, 2206 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 2207 {0xffffffff, 0x5aaa5aaa}, 2208 {0x56555555, 0x5a5a5aaa}, 2209 }; 2210 2211 /* Non-Shared-Antenna Coex Table */ 2212 static const struct coex_table_para table_nsant_8822b[] = { 2213 {0xffffffff, 0xffffffff}, /* case-100 */ 2214 {0x55555555, 0x55555555}, 2215 {0x66555555, 0x66555555}, 2216 {0xaaaaaaaa, 0xaaaaaaaa}, 2217 {0x5a5a5a5a, 0x5a5a5a5a}, 2218 {0xfafafafa, 0xfafafafa}, /* case-105 */ 2219 {0x5afa5afa, 0x5afa5afa}, 2220 {0x55555555, 0xfafafafa}, 2221 {0x66555555, 0xfafafafa}, 2222 {0x66555555, 0x5a5a5a5a}, 2223 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 2224 {0x66555555, 0xaaaaaaaa}, 2225 {0xffff55ff, 0xfafafafa}, 2226 {0xffff55ff, 0x5afa5afa}, 2227 {0xffff55ff, 0xaaaaaaaa}, 2228 {0xffff55ff, 0xffff55ff}, /* case-115 */ 2229 {0xaaffffaa, 0x5afa5afa}, 2230 {0xaaffffaa, 0xaaaaaaaa}, 2231 {0xffffffff, 0xfafafafa}, 2232 {0xffffffff, 0x5afa5afa}, 2233 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 2234 {0x55ff55ff, 0x5afa5afa}, 2235 {0x55ff55ff, 0xaaaaaaaa}, 2236 {0x55ff55ff, 0x55ff55ff} 2237 }; 2238 2239 /* Shared-Antenna TDMA */ 2240 static const struct coex_tdma_para tdma_sant_8822b[] = { 2241 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2242 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 2243 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2244 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2245 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2246 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2247 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2248 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2249 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2250 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2251 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2252 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2253 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2254 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2255 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2256 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 2257 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2258 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2259 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2260 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2261 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 2262 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2263 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2264 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2265 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 2266 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 2267 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 2268 { {0x61, 0x08, 0x03, 0x11, 0x11} } 2269 }; 2270 2271 /* Non-Shared-Antenna TDMA */ 2272 static const struct coex_tdma_para tdma_nsant_8822b[] = { 2273 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 2274 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */ 2275 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2276 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2277 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2278 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2279 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2280 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2281 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2282 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2283 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2284 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2285 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2286 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2287 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2288 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2289 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2290 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2291 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2292 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2293 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 2294 { {0x51, 0x08, 0x03, 0x10, 0x50} } 2295 }; 2296 2297 /* rssi in percentage % (dbm = % - 100) */ 2298 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30}; 2299 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30}; 2300 2301 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2302 static const struct coex_rf_para rf_para_tx_8822b[] = { 2303 {0, 0, false, 7}, /* for normal */ 2304 {0, 16, false, 7}, /* for WL-CPT */ 2305 {4, 0, true, 1}, 2306 {3, 6, true, 1}, 2307 {2, 9, true, 1}, 2308 {1, 13, true, 1} 2309 }; 2310 2311 static const struct coex_rf_para rf_para_rx_8822b[] = { 2312 {0, 0, false, 7}, /* for normal */ 2313 {0, 16, false, 7}, /* for WL-CPT */ 2314 {4, 0, true, 1}, 2315 {3, 6, true, 1}, 2316 {2, 9, true, 1}, 2317 {1, 13, true, 1} 2318 }; 2319 2320 static const struct coex_5g_afh_map afh_5g_8822b[] = { 2321 {120, 2, 4}, 2322 {124, 8, 8}, 2323 {128, 17, 8}, 2324 {132, 26, 10}, 2325 {136, 34, 8}, 2326 {140, 42, 10}, 2327 {144, 51, 8}, 2328 {149, 62, 8}, 2329 {153, 71, 10}, 2330 {157, 77, 4}, 2331 {118, 2, 4}, 2332 {126, 12, 16}, 2333 {134, 29, 16}, 2334 {142, 46, 16}, 2335 {151, 66, 16}, 2336 {159, 76, 4}, 2337 {122, 10, 20}, 2338 {138, 37, 34}, 2339 {155, 68, 20} 2340 }; 2341 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b)); 2342 2343 static const u8 2344 rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2345 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2346 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2347 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2348 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2349 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2350 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2351 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2352 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2353 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2354 }; 2355 2356 static const u8 2357 rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2358 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2359 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2360 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2361 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2362 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2363 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2364 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2365 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2366 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2367 }; 2368 2369 static const u8 2370 rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2371 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2372 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2373 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2374 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2375 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2376 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2377 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2378 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2379 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2380 }; 2381 2382 static const u8 2383 rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2384 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2385 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2386 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2387 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2388 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2389 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2390 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2391 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2392 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2393 }; 2394 2395 static const u8 rtw8822b_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 2396 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2397 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2398 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2399 }; 2400 2401 static const u8 rtw8822b_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 2402 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2403 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2404 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2405 }; 2406 2407 static const u8 rtw8822b_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 2408 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2409 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2410 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2411 }; 2412 2413 static const u8 rtw8822b_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 2414 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2415 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2416 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2417 }; 2418 2419 static const u8 rtw8822b_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 2420 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2421 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2422 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2423 }; 2424 2425 static const u8 rtw8822b_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 2426 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2427 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2428 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2429 }; 2430 2431 static const u8 rtw8822b_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 2432 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2433 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2434 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2435 }; 2436 2437 static const u8 rtw8822b_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 2438 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2439 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2440 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2441 }; 2442 2443 static const struct rtw_pwr_track_tbl rtw8822b_rtw_pwr_track_tbl = { 2444 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 2445 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 2446 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 2447 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 2448 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 2449 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 2450 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 2451 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 2452 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 2453 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 2454 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 2455 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 2456 .pwrtrk_2gb_n = rtw8822b_pwrtrk_2gb_n, 2457 .pwrtrk_2gb_p = rtw8822b_pwrtrk_2gb_p, 2458 .pwrtrk_2ga_n = rtw8822b_pwrtrk_2ga_n, 2459 .pwrtrk_2ga_p = rtw8822b_pwrtrk_2ga_p, 2460 .pwrtrk_2g_cckb_n = rtw8822b_pwrtrk_2g_cck_b_n, 2461 .pwrtrk_2g_cckb_p = rtw8822b_pwrtrk_2g_cck_b_p, 2462 .pwrtrk_2g_ccka_n = rtw8822b_pwrtrk_2g_cck_a_n, 2463 .pwrtrk_2g_ccka_p = rtw8822b_pwrtrk_2g_cck_a_p, 2464 }; 2465 2466 static const struct rtw_reg_domain coex_info_hw_regs_8822b[] = { 2467 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2468 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2469 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2470 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2471 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2472 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8}, 2473 {0, 0, RTW_REG_DOMAIN_NL}, 2474 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2475 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2476 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2477 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2478 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2479 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2480 {0, 0, RTW_REG_DOMAIN_NL}, 2481 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 2482 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 2483 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2484 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2485 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 2486 {0, 0, RTW_REG_DOMAIN_NL}, 2487 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2488 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2489 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2490 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2491 }; 2492 2493 static struct rtw_hw_reg_offset rtw8822b_edcca_th[] = { 2494 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0}, 2495 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0}, 2496 }; 2497 2498 struct rtw_chip_info rtw8822b_hw_spec = { 2499 .ops = &rtw8822b_ops, 2500 .id = RTW_CHIP_TYPE_8822B, 2501 .fw_name = "rtw88/rtw8822b_fw.bin", 2502 .wlan_cpu = RTW_WCPU_11AC, 2503 .tx_pkt_desc_sz = 48, 2504 .tx_buf_desc_sz = 16, 2505 .rx_pkt_desc_sz = 24, 2506 .rx_buf_desc_sz = 8, 2507 .phy_efuse_size = 1024, 2508 .log_efuse_size = 768, 2509 .ptct_efuse_size = 96, 2510 .txff_size = 262144, 2511 .rxff_size = 24576, 2512 .fw_rxff_size = 12288, 2513 .txgi_factor = 1, 2514 .is_pwr_by_rate_dec = true, 2515 .max_power_index = 0x3f, 2516 .csi_buf_pg_num = 0, 2517 .band = RTW_BAND_2G | RTW_BAND_5G, 2518 .page_size = 128, 2519 .dig_min = 0x1c, 2520 .ht_supported = true, 2521 .vht_supported = true, 2522 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 2523 .sys_func_en = 0xDC, 2524 .pwr_on_seq = card_enable_flow_8822b, 2525 .pwr_off_seq = card_disable_flow_8822b, 2526 .page_table = page_table_8822b, 2527 .rqpn_table = rqpn_table_8822b, 2528 .prioq_addrs = &prioq_addrs_8822b, 2529 .intf_table = &phy_para_table_8822b, 2530 .dig = rtw8822b_dig, 2531 .dig_cck = NULL, 2532 .rf_base_addr = {0x2800, 0x2c00}, 2533 .rf_sipi_addr = {0xc90, 0xe90}, 2534 .ltecoex_addr = &rtw8822b_ltecoex_addr, 2535 .mac_tbl = &rtw8822b_mac_tbl, 2536 .agc_tbl = &rtw8822b_agc_tbl, 2537 .bb_tbl = &rtw8822b_bb_tbl, 2538 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl}, 2539 .rfe_defs = rtw8822b_rfe_defs, 2540 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs), 2541 .pwr_track_tbl = &rtw8822b_rtw_pwr_track_tbl, 2542 .iqk_threshold = 8, 2543 .bfer_su_max_num = 2, 2544 .bfer_mu_max_num = 1, 2545 .rx_ldpc = true, 2546 .edcca_th = rtw8822b_edcca_th, 2547 .l2h_th_ini_cs = 10 + EDCCA_IGI_BASE, 2548 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE, 2549 2550 .coex_para_ver = 0x20070206, 2551 .bt_desired_ver = 0x6, 2552 .scbd_support = true, 2553 .new_scbd10_def = false, 2554 .ble_hid_profile_support = false, 2555 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2556 .bt_rssi_type = COEX_BTRSSI_RATIO, 2557 .ant_isolation = 15, 2558 .rssi_tolerance = 2, 2559 .wl_rssi_step = wl_rssi_step_8822b, 2560 .bt_rssi_step = bt_rssi_step_8822b, 2561 .table_sant_num = ARRAY_SIZE(table_sant_8822b), 2562 .table_sant = table_sant_8822b, 2563 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b), 2564 .table_nsant = table_nsant_8822b, 2565 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b), 2566 .tdma_sant = tdma_sant_8822b, 2567 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b), 2568 .tdma_nsant = tdma_nsant_8822b, 2569 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b), 2570 .wl_rf_para_tx = rf_para_tx_8822b, 2571 .wl_rf_para_rx = rf_para_rx_8822b, 2572 .bt_afh_span_bw20 = 0x24, 2573 .bt_afh_span_bw40 = 0x36, 2574 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b), 2575 .afh_5g = afh_5g_8822b, 2576 2577 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822b), 2578 .coex_info_hw_regs = coex_info_hw_regs_8822b, 2579 2580 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 2581 }; 2582 EXPORT_SYMBOL(rtw8822b_hw_spec); 2583 2584 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin"); 2585 2586 MODULE_AUTHOR("Realtek Corporation"); 2587 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822b driver"); 2588 MODULE_LICENSE("Dual BSD/GPL"); 2589