1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8822b.h" 12 #include "rtw8822b_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 17 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 18 u8 rx_path, bool is_tx2_path); 19 20 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse, 21 struct rtw8822b_efuse *map) 22 { 23 ether_addr_copy(efuse->addr, map->e.mac_addr); 24 } 25 26 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 27 { 28 struct rtw_efuse *efuse = &rtwdev->efuse; 29 struct rtw8822b_efuse *map; 30 int i; 31 32 map = (struct rtw8822b_efuse *)log_map; 33 34 efuse->rfe_option = map->rfe_option; 35 efuse->rf_board_option = map->rf_board_option; 36 efuse->crystal_cap = map->xtal_k; 37 efuse->pa_type_2g = map->pa_type; 38 efuse->pa_type_5g = map->pa_type; 39 efuse->lna_type_2g = map->lna_type_2g[0]; 40 efuse->lna_type_5g = map->lna_type_5g[0]; 41 efuse->channel_plan = map->channel_plan; 42 efuse->country_code[0] = map->country_code[0]; 43 efuse->country_code[1] = map->country_code[1]; 44 efuse->bt_setting = map->rf_bt_setting; 45 efuse->regd = map->rf_board_option & 0x7; 46 47 for (i = 0; i < 4; i++) 48 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 49 50 switch (rtw_hci_type(rtwdev)) { 51 case RTW_HCI_TYPE_PCIE: 52 rtw8822be_efuse_parsing(efuse, map); 53 break; 54 default: 55 /* unsupported now */ 56 return -ENOTSUPP; 57 } 58 59 return 0; 60 } 61 62 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev) 63 { 64 /* chip top mux */ 65 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); 66 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); 67 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); 68 69 /* from s0 or s1 */ 70 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); 71 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); 72 73 /* input or output */ 74 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); 75 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); 76 } 77 78 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev) 79 { 80 struct rtw_hal *hal = &rtwdev->hal; 81 u8 crystal_cap; 82 bool is_tx2_path; 83 84 /* power on BB/RF domain */ 85 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 86 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 87 rtw_write8_set(rtwdev, REG_RF_CTRL, 88 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 89 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 90 91 /* pre init before header files config */ 92 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 93 94 rtw_phy_load_tables(rtwdev); 95 96 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 97 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); 98 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); 99 100 /* post init after header files config */ 101 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 102 103 is_tx2_path = false; 104 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 105 is_tx2_path); 106 rtw_phy_init(rtwdev); 107 108 rtw8822b_phy_rfe_init(rtwdev); 109 } 110 111 #define WLAN_SLOT_TIME 0x09 112 #define WLAN_PIFS_TIME 0x19 113 #define WLAN_SIFS_CCK_CONT_TX 0xA 114 #define WLAN_SIFS_OFDM_CONT_TX 0xE 115 #define WLAN_SIFS_CCK_TRX 0x10 116 #define WLAN_SIFS_OFDM_TRX 0x10 117 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ 118 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ 119 #define WLAN_RDG_NAV 0x05 120 #define WLAN_TXOP_NAV 0x1B 121 #define WLAN_CCK_RX_TSF 0x30 122 #define WLAN_OFDM_RX_TSF 0x30 123 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 124 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 125 #define WLAN_DRV_EARLY_INT 0x04 126 #define WLAN_BCN_DMA_TIME 0x02 127 128 #define WLAN_RX_FILTER0 0x0FFFFFFF 129 #define WLAN_RX_FILTER2 0xFFFF 130 #define WLAN_RCR_CFG 0xE400220E 131 #define WLAN_RXPKT_MAX_SZ 12288 132 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 133 134 #define WLAN_AMPDU_MAX_TIME 0x70 135 #define WLAN_RTS_LEN_TH 0xFF 136 #define WLAN_RTS_TX_TIME_TH 0x08 137 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 138 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 139 #define FAST_EDCA_VO_TH 0x06 140 #define FAST_EDCA_VI_TH 0x06 141 #define FAST_EDCA_BE_TH 0x06 142 #define FAST_EDCA_BK_TH 0x06 143 #define WLAN_BAR_RETRY_LIMIT 0x01 144 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 145 146 #define WLAN_TX_FUNC_CFG1 0x30 147 #define WLAN_TX_FUNC_CFG2 0x30 148 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 149 #define WLAN_MAC_OPT_LB_FUNC1 0x80 150 #define WLAN_MAC_OPT_FUNC2 0x30810041 151 152 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 153 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 154 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 155 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 156 157 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 158 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 159 160 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 161 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 162 163 static int rtw8822b_mac_init(struct rtw_dev *rtwdev) 164 { 165 u32 value32; 166 167 /* protocol configuration */ 168 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD); 169 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 170 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 171 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 172 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 173 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 174 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 175 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 176 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 177 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 178 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 179 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 180 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 181 /* EDCA configuration */ 182 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 183 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 184 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 185 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 186 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 187 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 188 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 189 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 190 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 191 /* Set beacon cotnrol - enable TSF and other related functions */ 192 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 193 /* Set send beacon related registers */ 194 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 195 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 196 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 197 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 198 /* WMAC configuration */ 199 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 200 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 201 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 202 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 203 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 204 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 205 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 206 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 207 208 return 0; 209 } 210 211 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel) 212 { 213 struct rtw_hal *hal = &rtwdev->hal; 214 bool is_channel_2g = (channel <= 14) ? true : false; 215 216 if (is_channel_2g) { 217 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); 218 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 219 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); 220 } else { 221 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); 222 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 223 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); 224 } 225 226 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 227 228 if (hal->antenna_rx == BB_PATH_AB || 229 hal->antenna_tx == BB_PATH_AB) { 230 /* 2TX or 2RX */ 231 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 232 } else if (hal->antenna_rx == hal->antenna_tx) { 233 /* TXA+RXA or TXB+RXB */ 234 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 235 } else { 236 /* TXB+RXA or TXA+RXB */ 237 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 238 } 239 } 240 241 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel) 242 { 243 struct rtw_hal *hal = &rtwdev->hal; 244 bool is_channel_2g = (channel <= 14) ? true : false; 245 246 if (is_channel_2g) { 247 /* signal source */ 248 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); 249 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 250 } else { 251 /* signal source */ 252 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); 253 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 254 } 255 256 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 257 258 if (is_channel_2g) { 259 if (hal->antenna_rx == BB_PATH_AB || 260 hal->antenna_tx == BB_PATH_AB) { 261 /* 2TX or 2RX */ 262 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 263 } else if (hal->antenna_rx == hal->antenna_tx) { 264 /* TXA+RXA or TXB+RXB */ 265 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 266 } else { 267 /* TXB+RXA or TXA+RXB */ 268 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 269 } 270 } else { 271 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); 272 } 273 } 274 275 enum { 276 CCUT_IDX_1R_2G, 277 CCUT_IDX_2R_2G, 278 CCUT_IDX_1R_5G, 279 CCUT_IDX_2R_5G, 280 CCUT_IDX_NR, 281 }; 282 283 struct cca_ccut { 284 u32 reg82c[CCUT_IDX_NR]; 285 u32 reg830[CCUT_IDX_NR]; 286 u32 reg838[CCUT_IDX_NR]; 287 }; 288 289 static const struct cca_ccut cca_ifem_ccut = { 290 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ 291 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 292 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/ 293 }; 294 295 static const struct cca_ccut cca_efem_ccut = { 296 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ 297 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/ 298 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ 299 }; 300 301 static const struct cca_ccut cca_ifem_ccut_ext = { 302 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ 303 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 304 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/ 305 }; 306 307 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col, 308 u32 *reg82c, u32 *reg830, u32 *reg838) 309 { 310 *reg82c = cca_ccut->reg82c[col]; 311 *reg830 = cca_ccut->reg830[col]; 312 *reg838 = cca_ccut->reg838[col]; 313 } 314 315 struct rtw8822b_rfe_info { 316 const struct cca_ccut *cca_ccut_2g; 317 const struct cca_ccut *cca_ccut_5g; 318 enum rtw_rfe_fem fem; 319 bool ifem_ext; 320 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel); 321 }; 322 323 #define I2GE5G_CCUT(set_ch) { \ 324 .cca_ccut_2g = &cca_ifem_ccut, \ 325 .cca_ccut_5g = &cca_efem_ccut, \ 326 .fem = RTW_RFE_IFEM2G_EFEM5G, \ 327 .ifem_ext = false, \ 328 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 329 } 330 #define IFEM_EXT_CCUT(set_ch) { \ 331 .cca_ccut_2g = &cca_ifem_ccut_ext, \ 332 .cca_ccut_5g = &cca_ifem_ccut_ext, \ 333 .fem = RTW_RFE_IFEM, \ 334 .ifem_ext = true, \ 335 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 336 } 337 338 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = { 339 [2] = I2GE5G_CCUT(efem), 340 [5] = IFEM_EXT_CCUT(ifem), 341 }; 342 343 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw, 344 const struct rtw8822b_rfe_info *rfe_info) 345 { 346 struct rtw_hal *hal = &rtwdev->hal; 347 struct rtw_efuse *efuse = &rtwdev->efuse; 348 const struct cca_ccut *cca_ccut; 349 u8 col; 350 u32 reg82c, reg830, reg838; 351 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; 352 353 if (channel <= 14) { 354 cca_ccut = rfe_info->cca_ccut_2g; 355 356 if (hal->antenna_rx == BB_PATH_A || 357 hal->antenna_rx == BB_PATH_B) 358 col = CCUT_IDX_1R_2G; 359 else 360 col = CCUT_IDX_2R_2G; 361 } else { 362 cca_ccut = rfe_info->cca_ccut_5g; 363 364 if (hal->antenna_rx == BB_PATH_A || 365 hal->antenna_rx == BB_PATH_B) 366 col = CCUT_IDX_1R_5G; 367 else 368 col = CCUT_IDX_2R_5G; 369 } 370 371 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838); 372 373 switch (rfe_info->fem) { 374 case RTW_RFE_IFEM: 375 default: 376 is_ifem_cca = true; 377 if (rfe_info->ifem_ext) 378 is_rfe_type = true; 379 break; 380 case RTW_RFE_EFEM: 381 is_efem_cca = true; 382 break; 383 case RTW_RFE_IFEM2G_EFEM5G: 384 if (channel <= 14) 385 is_ifem_cca = true; 386 else 387 is_efem_cca = true; 388 break; 389 } 390 391 if (is_ifem_cca) { 392 if ((hal->cut_version == RTW_CHIP_VER_CUT_B && 393 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) && 394 bw == RTW_CHANNEL_WIDTH_40) || 395 (!is_rfe_type && col == CCUT_IDX_2R_5G && 396 bw == RTW_CHANNEL_WIDTH_40) || 397 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G)) 398 reg830 = 0x79a0ea28; 399 } 400 401 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c); 402 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830); 403 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838); 404 405 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B)) 406 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); 407 408 if (bw == RTW_CHANNEL_WIDTH_20 && 409 ((channel >= 52 && channel <= 64) || 410 (channel >= 100 && channel <= 144))) 411 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); 412 } 413 414 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 415 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; 416 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 417 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 418 0x6, 0x5, 0x0, 0x0, 0x7}; 419 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 420 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; 421 422 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 423 { 424 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 425 #define RF18_BAND_2G (0) 426 #define RF18_BAND_5G (BIT(16) | BIT(8)) 427 #define RF18_CHANNEL_MASK (MASKBYTE0) 428 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 429 #define RF18_RFSI_GE_CH80 (BIT(17)) 430 #define RF18_RFSI_GT_CH144 (BIT(18)) 431 #define RF18_BW_MASK (BIT(11) | BIT(10)) 432 #define RF18_BW_20M (BIT(11) | BIT(10)) 433 #define RF18_BW_40M (BIT(11)) 434 #define RF18_BW_80M (BIT(10)) 435 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) 436 437 struct rtw_hal *hal = &rtwdev->hal; 438 u32 rf_reg18, rf_reg_be; 439 440 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 441 442 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 443 RF18_BW_MASK); 444 445 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 446 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 447 if (channel > 144) 448 rf_reg18 |= RF18_RFSI_GT_CH144; 449 else if (channel >= 80) 450 rf_reg18 |= RF18_RFSI_GE_CH80; 451 452 switch (bw) { 453 case RTW_CHANNEL_WIDTH_5: 454 case RTW_CHANNEL_WIDTH_10: 455 case RTW_CHANNEL_WIDTH_20: 456 default: 457 rf_reg18 |= RF18_BW_20M; 458 break; 459 case RTW_CHANNEL_WIDTH_40: 460 rf_reg18 |= RF18_BW_40M; 461 break; 462 case RTW_CHANNEL_WIDTH_80: 463 rf_reg18 |= RF18_BW_80M; 464 break; 465 } 466 467 if (channel <= 14) 468 rf_reg_be = 0x0; 469 else if (channel >= 36 && channel <= 64) 470 rf_reg_be = low_band[(channel - 36) >> 1]; 471 else if (channel >= 100 && channel <= 144) 472 rf_reg_be = middle_band[(channel - 100) >> 1]; 473 else if (channel >= 149 && channel <= 177) 474 rf_reg_be = high_band[(channel - 149) >> 1]; 475 else 476 goto err; 477 478 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be); 479 480 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ 481 if (channel == 144) 482 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); 483 else 484 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); 485 486 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 487 if (hal->rf_type > RF_1T1R) 488 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); 489 490 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 491 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 492 493 return; 494 495 err: 496 WARN_ON(1); 497 } 498 499 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev) 500 { 501 struct rtw_hal *hal = &rtwdev->hal; 502 u32 igi; 503 504 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); 505 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); 506 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); 507 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); 508 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); 509 510 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); 511 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 512 hal->antenna_rx | (hal->antenna_rx << 4)); 513 } 514 515 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 516 { 517 if (bw == RTW_CHANNEL_WIDTH_40) { 518 /* RX DFIR for BW40 */ 519 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); 520 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); 521 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 522 } else if (bw == RTW_CHANNEL_WIDTH_80) { 523 /* RX DFIR for BW80 */ 524 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 525 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 526 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 527 } else { 528 /* RX DFIR for BW20, BW10 and BW5*/ 529 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 530 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 531 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 532 } 533 } 534 535 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 536 u8 primary_ch_idx) 537 { 538 struct rtw_efuse *efuse = &rtwdev->efuse; 539 u8 rfe_option = efuse->rfe_option; 540 u32 val32; 541 542 if (channel <= 14) { 543 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 544 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 545 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 546 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 547 548 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); 549 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 550 if (channel == 14) { 551 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); 552 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 553 } else { 554 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); 555 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); 556 } 557 558 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); 559 } else if (channel > 35) { 560 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 561 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 562 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 563 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); 564 565 if (channel >= 36 && channel <= 64) 566 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); 567 else if (channel >= 100 && channel <= 144) 568 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); 569 else if (channel >= 149) 570 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); 571 572 if (channel >= 36 && channel <= 48) 573 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 574 else if (channel >= 52 && channel <= 64) 575 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 576 else if (channel >= 100 && channel <= 116) 577 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 578 else if (channel >= 118 && channel <= 177) 579 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 580 581 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); 582 } 583 584 switch (bw) { 585 case RTW_CHANNEL_WIDTH_20: 586 default: 587 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 588 val32 &= 0xFFCFFC00; 589 val32 |= (RTW_CHANNEL_WIDTH_20); 590 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 591 592 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 593 break; 594 case RTW_CHANNEL_WIDTH_40: 595 if (primary_ch_idx == 1) 596 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 597 else 598 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 599 600 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 601 val32 &= 0xFF3FF300; 602 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); 603 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 604 605 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 606 break; 607 case RTW_CHANNEL_WIDTH_80: 608 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 609 val32 &= 0xFCEFCF00; 610 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); 611 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 612 613 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 614 615 if (rfe_option == 2) { 616 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); 617 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); 618 } 619 break; 620 case RTW_CHANNEL_WIDTH_5: 621 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 622 val32 &= 0xEFEEFE00; 623 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); 624 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 625 626 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 627 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 628 break; 629 case RTW_CHANNEL_WIDTH_10: 630 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 631 val32 &= 0xEFFEFF00; 632 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); 633 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 634 635 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 636 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 637 break; 638 } 639 } 640 641 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 642 u8 primary_chan_idx) 643 { 644 struct rtw_efuse *efuse = &rtwdev->efuse; 645 const struct rtw8822b_rfe_info *rfe_info; 646 647 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 648 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 649 return; 650 651 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 652 653 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 654 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 655 rtw8822b_set_channel_rf(rtwdev, channel, bw); 656 rtw8822b_set_channel_rxdfir(rtwdev, bw); 657 rtw8822b_toggle_igi(rtwdev); 658 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info); 659 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel); 660 } 661 662 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 663 u8 rx_path, bool is_tx2_path) 664 { 665 struct rtw_efuse *efuse = &rtwdev->efuse; 666 const struct rtw8822b_rfe_info *rfe_info; 667 u8 ch = rtwdev->hal.current_channel; 668 u8 tx_path_sel, rx_path_sel; 669 int counter; 670 671 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 672 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 673 return; 674 675 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 676 677 if ((tx_path | rx_path) & BB_PATH_A) 678 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); 679 else 680 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); 681 682 if ((tx_path | rx_path) & BB_PATH_B) 683 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); 684 else 685 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); 686 687 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); 688 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); 689 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); 690 691 if (tx_path & BB_PATH_A) { 692 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); 693 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); 694 } else if (tx_path & BB_PATH_B) { 695 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); 696 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); 697 } 698 699 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B) 700 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); 701 else 702 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); 703 704 tx_path_sel = (tx_path << 4) | tx_path; 705 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel); 706 707 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) { 708 if (is_tx2_path || rtwdev->mp_mode) { 709 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); 710 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); 711 } 712 } 713 714 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); 715 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); 716 717 if (rx_path & BB_PATH_A) 718 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); 719 else if (rx_path & BB_PATH_B) 720 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); 721 722 rx_path_sel = (rx_path << 4) | rx_path; 723 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); 724 725 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 726 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); 727 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); 728 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); 729 } else { 730 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); 731 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); 732 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); 733 } 734 735 for (counter = 100; counter > 0; counter--) { 736 u32 rf_reg33; 737 738 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 739 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 740 741 udelay(2); 742 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); 743 744 if (rf_reg33 == 0x00001) 745 break; 746 } 747 748 if (WARN(counter <= 0, "write RF mode table fail\n")) 749 return; 750 751 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 752 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 753 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); 754 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); 755 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 756 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 757 758 rtw8822b_toggle_igi(rtwdev); 759 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info); 760 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch); 761 } 762 763 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 764 struct rtw_rx_pkt_stat *pkt_stat) 765 { 766 s8 min_rx_power = -120; 767 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 768 769 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110; 770 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 771 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 772 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 773 min_rx_power); 774 } 775 776 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 777 struct rtw_rx_pkt_stat *pkt_stat) 778 { 779 u8 rxsc, bw; 780 s8 min_rx_power = -120; 781 782 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 783 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 784 else 785 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 786 787 if (rxsc >= 1 && rxsc <= 8) 788 bw = RTW_CHANNEL_WIDTH_20; 789 else if (rxsc >= 9 && rxsc <= 12) 790 bw = RTW_CHANNEL_WIDTH_40; 791 else if (rxsc >= 13) 792 bw = RTW_CHANNEL_WIDTH_80; 793 else 794 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 795 796 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 797 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 798 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 799 pkt_stat->bw = bw; 800 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 801 pkt_stat->rx_power[RF_PATH_B], 802 min_rx_power); 803 } 804 805 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 806 struct rtw_rx_pkt_stat *pkt_stat) 807 { 808 u8 page; 809 810 page = *phy_status & 0xf; 811 812 switch (page) { 813 case 0: 814 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 815 break; 816 case 1: 817 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 818 break; 819 default: 820 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 821 return; 822 } 823 } 824 825 static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 826 struct rtw_rx_pkt_stat *pkt_stat, 827 struct ieee80211_rx_status *rx_status) 828 { 829 struct ieee80211_hdr *hdr; 830 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 831 u8 *phy_status = NULL; 832 833 memset(pkt_stat, 0, sizeof(*pkt_stat)); 834 835 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 836 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 837 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 838 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc); 839 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 840 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 841 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 842 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 843 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 844 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 845 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 846 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 847 848 /* drv_info_sz is in unit of 8-bytes */ 849 pkt_stat->drv_info_sz *= 8; 850 851 /* c2h cmd pkt's rx/phy status is not interested */ 852 if (pkt_stat->is_c2h) 853 return; 854 855 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 856 pkt_stat->drv_info_sz); 857 if (pkt_stat->phy_status) { 858 phy_status = rx_desc + desc_sz + pkt_stat->shift; 859 query_phy_status(rtwdev, phy_status, pkt_stat); 860 } 861 862 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 863 } 864 865 static void 866 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 867 { 868 struct rtw_hal *hal = &rtwdev->hal; 869 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 870 static u32 phy_pwr_idx; 871 u8 rate, rate_idx, pwr_index, shift; 872 int j; 873 874 for (j = 0; j < rtw_rate_size[rs]; j++) { 875 rate = rtw_rate_section[rs][j]; 876 pwr_index = hal->tx_pwr_tbl[path][rate]; 877 shift = rate & 0x3; 878 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 879 if (shift == 0x3) { 880 rate_idx = rate & 0xfc; 881 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 882 phy_pwr_idx); 883 phy_pwr_idx = 0; 884 } 885 } 886 } 887 888 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev) 889 { 890 struct rtw_hal *hal = &rtwdev->hal; 891 int rs, path; 892 893 for (path = 0; path < hal->rf_path_num; path++) { 894 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 895 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs); 896 } 897 } 898 899 static bool rtw8822b_check_rf_path(u8 antenna) 900 { 901 switch (antenna) { 902 case BB_PATH_A: 903 case BB_PATH_B: 904 case BB_PATH_AB: 905 return true; 906 default: 907 return false; 908 } 909 } 910 911 static void rtw8822b_set_antenna(struct rtw_dev *rtwdev, u8 antenna_tx, 912 u8 antenna_rx) 913 { 914 struct rtw_hal *hal = &rtwdev->hal; 915 916 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", 917 antenna_tx, antenna_rx); 918 919 if (!rtw8822b_check_rf_path(antenna_tx)) { 920 rtw_info(rtwdev, "unsupport tx path, set to default path ab\n"); 921 antenna_tx = BB_PATH_AB; 922 } 923 if (!rtw8822b_check_rf_path(antenna_rx)) { 924 rtw_info(rtwdev, "unsupport rx path, set to default path ab\n"); 925 antenna_rx = BB_PATH_AB; 926 } 927 hal->antenna_tx = antenna_tx; 928 hal->antenna_rx = antenna_rx; 929 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 930 } 931 932 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 933 { 934 u8 ldo_pwr; 935 936 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 937 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 938 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 939 } 940 941 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev) 942 { 943 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 944 u32 cck_enable; 945 u32 cck_fa_cnt; 946 u32 ofdm_fa_cnt; 947 u32 crc32_cnt; 948 949 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); 950 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); 951 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); 952 953 dm_info->cck_fa_cnt = cck_fa_cnt; 954 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 955 dm_info->total_fa_cnt = ofdm_fa_cnt; 956 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 957 958 crc32_cnt = rtw_read32(rtwdev, 0xf04); 959 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 960 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 961 crc32_cnt = rtw_read32(rtwdev, 0xf14); 962 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 963 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 964 crc32_cnt = rtw_read32(rtwdev, 0xf10); 965 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 966 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 967 crc32_cnt = rtw_read32(rtwdev, 0xf0c); 968 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 969 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 970 971 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); 972 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); 973 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); 974 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); 975 rtw_write32_set(rtwdev, 0xb58, BIT(0)); 976 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); 977 } 978 979 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev) 980 { 981 static int do_iqk_cnt; 982 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 983 u32 rf_reg, iqk_fail_mask; 984 int counter; 985 bool reload; 986 987 rtw_fw_do_iqk(rtwdev, ¶); 988 989 for (counter = 0; counter < 300; counter++) { 990 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 991 if (rf_reg == 0xabcde) 992 break; 993 msleep(20); 994 } 995 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 996 997 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 998 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 999 rtw_dbg(rtwdev, RTW_DBG_PHY, 1000 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 1001 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 1002 } 1003 1004 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev) 1005 { 1006 /* enable TBTT nterrupt */ 1007 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1008 1009 /* BT report packet sample rate */ 1010 /* 0x790[5:0]=0x5 */ 1011 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 1012 1013 /* enable BT counter statistics */ 1014 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1015 1016 /* enable PTA (3-wire function form BT side) */ 1017 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1018 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 1019 1020 /* enable PTA (tx/rx signal form WiFi side) */ 1021 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1022 /* wl tx signal to PTA not case EDCCA */ 1023 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 1024 /* GNT_BT=1 while select both */ 1025 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 1026 } 1027 1028 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev, 1029 u8 ctrl_type, u8 pos_type) 1030 { 1031 struct rtw_coex *coex = &rtwdev->coex; 1032 struct rtw_coex_dm *coex_dm = &coex->dm; 1033 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1034 bool polarity_inverse; 1035 u8 regval = 0; 1036 1037 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status) 1038 return; 1039 1040 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type; 1041 1042 if (coex_rfe->ant_switch_diversity && 1043 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 1044 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 1045 1046 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 1047 1048 switch (ctrl_type) { 1049 default: 1050 case COEX_SWITCH_CTRL_BY_BBSW: 1051 /* 0x4c[23] = 0 */ 1052 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1053 /* 0x4c[24] = 1 */ 1054 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1055 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1056 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); 1057 1058 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 1059 if (coex_rfe->rfe_module_type != 0x4 && 1060 coex_rfe->rfe_module_type != 0x2) 1061 regval = 0x3; 1062 else 1063 regval = (!polarity_inverse ? 0x2 : 0x1); 1064 } else if (pos_type == COEX_SWITCH_TO_WLG) { 1065 regval = (!polarity_inverse ? 0x2 : 0x1); 1066 } else { 1067 regval = (!polarity_inverse ? 0x1 : 0x2); 1068 } 1069 1070 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1071 break; 1072 case COEX_SWITCH_CTRL_BY_PTA: 1073 /* 0x4c[23] = 0 */ 1074 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1075 /* 0x4c[24] = 1 */ 1076 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1077 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1078 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); 1079 1080 regval = (!polarity_inverse ? 0x2 : 0x1); 1081 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1082 break; 1083 case COEX_SWITCH_CTRL_BY_ANTDIV: 1084 /* 0x4c[23] = 0 */ 1085 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1086 /* 0x4c[24] = 1 */ 1087 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1088 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); 1089 break; 1090 case COEX_SWITCH_CTRL_BY_MAC: 1091 /* 0x4c[23] = 1 */ 1092 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); 1093 1094 regval = (!polarity_inverse ? 0x0 : 0x1); 1095 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); 1096 break; 1097 case COEX_SWITCH_CTRL_BY_FW: 1098 /* 0x4c[23] = 0 */ 1099 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1100 /* 0x4c[24] = 1 */ 1101 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1102 break; 1103 case COEX_SWITCH_CTRL_BY_BT: 1104 /* 0x4c[23] = 0 */ 1105 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1106 /* 0x4c[24] = 0 */ 1107 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); 1108 break; 1109 } 1110 } 1111 1112 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1113 { 1114 } 1115 1116 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1117 { 1118 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 1119 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 1120 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 1121 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 1122 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 1123 } 1124 1125 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1126 { 1127 struct rtw_coex *coex = &rtwdev->coex; 1128 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1129 struct rtw_efuse *efuse = &rtwdev->efuse; 1130 bool is_ext_fem = false; 1131 1132 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1133 coex_rfe->ant_switch_polarity = 0; 1134 coex_rfe->ant_switch_diversity = false; 1135 if (coex_rfe->rfe_module_type == 0x12 || 1136 coex_rfe->rfe_module_type == 0x15 || 1137 coex_rfe->rfe_module_type == 0x16) 1138 coex_rfe->ant_switch_exist = false; 1139 else 1140 coex_rfe->ant_switch_exist = true; 1141 1142 if (coex_rfe->rfe_module_type == 2 || 1143 coex_rfe->rfe_module_type == 4) { 1144 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true); 1145 is_ext_fem = true; 1146 } else { 1147 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false); 1148 } 1149 1150 coex_rfe->wlg_at_btg = false; 1151 1152 if (efuse->share_ant && 1153 coex_rfe->ant_switch_exist && !is_ext_fem) 1154 coex_rfe->ant_switch_with_bt = true; 1155 else 1156 coex_rfe->ant_switch_with_bt = false; 1157 1158 /* Ext switch buffer mux */ 1159 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); 1160 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); 1161 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); 1162 1163 /* Disable LTE Coex Function in WiFi side */ 1164 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); 1165 1166 /* BTC_CTT_WL_VS_LTE */ 1167 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1168 1169 /* BTC_CTT_BT_VS_LTE */ 1170 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1171 } 1172 1173 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1174 { 1175 struct rtw_coex *coex = &rtwdev->coex; 1176 struct rtw_coex_dm *coex_dm = &coex->dm; 1177 static const u16 reg_addr[] = {0xc58, 0xe58}; 1178 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; 1179 u8 i, pwr; 1180 1181 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1182 return; 1183 1184 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1185 1186 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1187 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1188 1189 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1190 1191 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) 1192 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); 1193 } 1194 1195 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1196 { 1197 struct rtw_coex *coex = &rtwdev->coex; 1198 struct rtw_coex_dm *coex_dm = &coex->dm; 1199 /* WL Rx Low gain on */ 1200 static const u32 wl_rx_low_gain_on[] = { 1201 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 1202 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 1203 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 1204 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 1205 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 1206 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 1207 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 1208 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, 1209 0x007e0403 1210 }; 1211 1212 /* WL Rx Low gain off */ 1213 static const u32 wl_rx_low_gain_off[] = { 1214 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 1215 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 1216 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 1217 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 1218 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 1219 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 1220 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 1221 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, 1222 0x007e0403 1223 }; 1224 u8 i; 1225 1226 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1227 return; 1228 1229 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1230 1231 if (coex_dm->cur_wl_rx_low_gain_en) { 1232 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1233 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]); 1234 1235 /* set Rx filter corner RCK offset */ 1236 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); 1237 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); 1238 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); 1239 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); 1240 } else { 1241 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1242 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); 1243 1244 /* set Rx filter corner RCK offset */ 1245 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); 1246 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); 1247 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); 1248 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); 1249 } 1250 } 1251 1252 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = { 1253 {0x0086, 1254 RTW_PWR_CUT_ALL_MSK, 1255 RTW_PWR_INTF_SDIO_MSK, 1256 RTW_PWR_ADDR_SDIO, 1257 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1258 {0x0086, 1259 RTW_PWR_CUT_ALL_MSK, 1260 RTW_PWR_INTF_SDIO_MSK, 1261 RTW_PWR_ADDR_SDIO, 1262 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1263 {0x004A, 1264 RTW_PWR_CUT_ALL_MSK, 1265 RTW_PWR_INTF_USB_MSK, 1266 RTW_PWR_ADDR_MAC, 1267 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1268 {0x0005, 1269 RTW_PWR_CUT_ALL_MSK, 1270 RTW_PWR_INTF_ALL_MSK, 1271 RTW_PWR_ADDR_MAC, 1272 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1273 {0x0300, 1274 RTW_PWR_CUT_ALL_MSK, 1275 RTW_PWR_INTF_PCI_MSK, 1276 RTW_PWR_ADDR_MAC, 1277 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1278 {0x0301, 1279 RTW_PWR_CUT_ALL_MSK, 1280 RTW_PWR_INTF_PCI_MSK, 1281 RTW_PWR_ADDR_MAC, 1282 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1283 {0xFFFF, 1284 RTW_PWR_CUT_ALL_MSK, 1285 RTW_PWR_INTF_ALL_MSK, 1286 0, 1287 RTW_PWR_CMD_END, 0, 0}, 1288 }; 1289 1290 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = { 1291 {0x0012, 1292 RTW_PWR_CUT_ALL_MSK, 1293 RTW_PWR_INTF_ALL_MSK, 1294 RTW_PWR_ADDR_MAC, 1295 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1296 {0x0012, 1297 RTW_PWR_CUT_ALL_MSK, 1298 RTW_PWR_INTF_ALL_MSK, 1299 RTW_PWR_ADDR_MAC, 1300 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1301 {0x0020, 1302 RTW_PWR_CUT_ALL_MSK, 1303 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1304 RTW_PWR_ADDR_MAC, 1305 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1306 {0x0001, 1307 RTW_PWR_CUT_ALL_MSK, 1308 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1309 RTW_PWR_ADDR_MAC, 1310 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1311 {0x0000, 1312 RTW_PWR_CUT_ALL_MSK, 1313 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1314 RTW_PWR_ADDR_MAC, 1315 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1316 {0x0005, 1317 RTW_PWR_CUT_ALL_MSK, 1318 RTW_PWR_INTF_ALL_MSK, 1319 RTW_PWR_ADDR_MAC, 1320 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1321 {0x0075, 1322 RTW_PWR_CUT_ALL_MSK, 1323 RTW_PWR_INTF_PCI_MSK, 1324 RTW_PWR_ADDR_MAC, 1325 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1326 {0x0006, 1327 RTW_PWR_CUT_ALL_MSK, 1328 RTW_PWR_INTF_ALL_MSK, 1329 RTW_PWR_ADDR_MAC, 1330 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1331 {0x0075, 1332 RTW_PWR_CUT_ALL_MSK, 1333 RTW_PWR_INTF_PCI_MSK, 1334 RTW_PWR_ADDR_MAC, 1335 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1336 {0xFF1A, 1337 RTW_PWR_CUT_ALL_MSK, 1338 RTW_PWR_INTF_USB_MSK, 1339 RTW_PWR_ADDR_MAC, 1340 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1341 {0x0006, 1342 RTW_PWR_CUT_ALL_MSK, 1343 RTW_PWR_INTF_ALL_MSK, 1344 RTW_PWR_ADDR_MAC, 1345 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1346 {0x0005, 1347 RTW_PWR_CUT_ALL_MSK, 1348 RTW_PWR_INTF_ALL_MSK, 1349 RTW_PWR_ADDR_MAC, 1350 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1351 {0x0005, 1352 RTW_PWR_CUT_ALL_MSK, 1353 RTW_PWR_INTF_ALL_MSK, 1354 RTW_PWR_ADDR_MAC, 1355 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1356 {0x10C3, 1357 RTW_PWR_CUT_ALL_MSK, 1358 RTW_PWR_INTF_USB_MSK, 1359 RTW_PWR_ADDR_MAC, 1360 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1361 {0x0005, 1362 RTW_PWR_CUT_ALL_MSK, 1363 RTW_PWR_INTF_ALL_MSK, 1364 RTW_PWR_ADDR_MAC, 1365 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1366 {0x0005, 1367 RTW_PWR_CUT_ALL_MSK, 1368 RTW_PWR_INTF_ALL_MSK, 1369 RTW_PWR_ADDR_MAC, 1370 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1371 {0x0020, 1372 RTW_PWR_CUT_ALL_MSK, 1373 RTW_PWR_INTF_ALL_MSK, 1374 RTW_PWR_ADDR_MAC, 1375 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1376 {0x10A8, 1377 RTW_PWR_CUT_C_MSK, 1378 RTW_PWR_INTF_ALL_MSK, 1379 RTW_PWR_ADDR_MAC, 1380 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1381 {0x10A9, 1382 RTW_PWR_CUT_C_MSK, 1383 RTW_PWR_INTF_ALL_MSK, 1384 RTW_PWR_ADDR_MAC, 1385 RTW_PWR_CMD_WRITE, 0xFF, 0xef}, 1386 {0x10AA, 1387 RTW_PWR_CUT_C_MSK, 1388 RTW_PWR_INTF_ALL_MSK, 1389 RTW_PWR_ADDR_MAC, 1390 RTW_PWR_CMD_WRITE, 0xFF, 0x0c}, 1391 {0x0068, 1392 RTW_PWR_CUT_C_MSK, 1393 RTW_PWR_INTF_SDIO_MSK, 1394 RTW_PWR_ADDR_MAC, 1395 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1396 {0x0029, 1397 RTW_PWR_CUT_ALL_MSK, 1398 RTW_PWR_INTF_ALL_MSK, 1399 RTW_PWR_ADDR_MAC, 1400 RTW_PWR_CMD_WRITE, 0xFF, 0xF9}, 1401 {0x0024, 1402 RTW_PWR_CUT_ALL_MSK, 1403 RTW_PWR_INTF_ALL_MSK, 1404 RTW_PWR_ADDR_MAC, 1405 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1406 {0x0074, 1407 RTW_PWR_CUT_ALL_MSK, 1408 RTW_PWR_INTF_PCI_MSK, 1409 RTW_PWR_ADDR_MAC, 1410 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1411 {0x00AF, 1412 RTW_PWR_CUT_ALL_MSK, 1413 RTW_PWR_INTF_ALL_MSK, 1414 RTW_PWR_ADDR_MAC, 1415 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1416 {0xFFFF, 1417 RTW_PWR_CUT_ALL_MSK, 1418 RTW_PWR_INTF_ALL_MSK, 1419 0, 1420 RTW_PWR_CMD_END, 0, 0}, 1421 }; 1422 1423 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = { 1424 {0x0003, 1425 RTW_PWR_CUT_ALL_MSK, 1426 RTW_PWR_INTF_SDIO_MSK, 1427 RTW_PWR_ADDR_MAC, 1428 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1429 {0x0093, 1430 RTW_PWR_CUT_ALL_MSK, 1431 RTW_PWR_INTF_ALL_MSK, 1432 RTW_PWR_ADDR_MAC, 1433 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1434 {0x001F, 1435 RTW_PWR_CUT_ALL_MSK, 1436 RTW_PWR_INTF_ALL_MSK, 1437 RTW_PWR_ADDR_MAC, 1438 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1439 {0x00EF, 1440 RTW_PWR_CUT_ALL_MSK, 1441 RTW_PWR_INTF_ALL_MSK, 1442 RTW_PWR_ADDR_MAC, 1443 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1444 {0xFF1A, 1445 RTW_PWR_CUT_ALL_MSK, 1446 RTW_PWR_INTF_USB_MSK, 1447 RTW_PWR_ADDR_MAC, 1448 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 1449 {0x0049, 1450 RTW_PWR_CUT_ALL_MSK, 1451 RTW_PWR_INTF_ALL_MSK, 1452 RTW_PWR_ADDR_MAC, 1453 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1454 {0x0006, 1455 RTW_PWR_CUT_ALL_MSK, 1456 RTW_PWR_INTF_ALL_MSK, 1457 RTW_PWR_ADDR_MAC, 1458 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1459 {0x0002, 1460 RTW_PWR_CUT_ALL_MSK, 1461 RTW_PWR_INTF_ALL_MSK, 1462 RTW_PWR_ADDR_MAC, 1463 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1464 {0x10C3, 1465 RTW_PWR_CUT_ALL_MSK, 1466 RTW_PWR_INTF_USB_MSK, 1467 RTW_PWR_ADDR_MAC, 1468 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1469 {0x0005, 1470 RTW_PWR_CUT_ALL_MSK, 1471 RTW_PWR_INTF_ALL_MSK, 1472 RTW_PWR_ADDR_MAC, 1473 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1474 {0x0005, 1475 RTW_PWR_CUT_ALL_MSK, 1476 RTW_PWR_INTF_ALL_MSK, 1477 RTW_PWR_ADDR_MAC, 1478 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1479 {0x0020, 1480 RTW_PWR_CUT_ALL_MSK, 1481 RTW_PWR_INTF_ALL_MSK, 1482 RTW_PWR_ADDR_MAC, 1483 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1484 {0x0000, 1485 RTW_PWR_CUT_ALL_MSK, 1486 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1487 RTW_PWR_ADDR_MAC, 1488 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1489 {0xFFFF, 1490 RTW_PWR_CUT_ALL_MSK, 1491 RTW_PWR_INTF_ALL_MSK, 1492 0, 1493 RTW_PWR_CMD_END, 0, 0}, 1494 }; 1495 1496 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = { 1497 {0x0005, 1498 RTW_PWR_CUT_ALL_MSK, 1499 RTW_PWR_INTF_SDIO_MSK, 1500 RTW_PWR_ADDR_MAC, 1501 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1502 {0x0007, 1503 RTW_PWR_CUT_ALL_MSK, 1504 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1505 RTW_PWR_ADDR_MAC, 1506 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1507 {0x0067, 1508 RTW_PWR_CUT_ALL_MSK, 1509 RTW_PWR_INTF_ALL_MSK, 1510 RTW_PWR_ADDR_MAC, 1511 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1512 {0x0005, 1513 RTW_PWR_CUT_ALL_MSK, 1514 RTW_PWR_INTF_PCI_MSK, 1515 RTW_PWR_ADDR_MAC, 1516 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1517 {0x004A, 1518 RTW_PWR_CUT_ALL_MSK, 1519 RTW_PWR_INTF_USB_MSK, 1520 RTW_PWR_ADDR_MAC, 1521 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1522 {0x0067, 1523 RTW_PWR_CUT_ALL_MSK, 1524 RTW_PWR_INTF_SDIO_MSK, 1525 RTW_PWR_ADDR_MAC, 1526 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1527 {0x0067, 1528 RTW_PWR_CUT_ALL_MSK, 1529 RTW_PWR_INTF_SDIO_MSK, 1530 RTW_PWR_ADDR_MAC, 1531 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1532 {0x004F, 1533 RTW_PWR_CUT_ALL_MSK, 1534 RTW_PWR_INTF_SDIO_MSK, 1535 RTW_PWR_ADDR_MAC, 1536 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1537 {0x0067, 1538 RTW_PWR_CUT_ALL_MSK, 1539 RTW_PWR_INTF_SDIO_MSK, 1540 RTW_PWR_ADDR_MAC, 1541 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1542 {0x0046, 1543 RTW_PWR_CUT_ALL_MSK, 1544 RTW_PWR_INTF_SDIO_MSK, 1545 RTW_PWR_ADDR_MAC, 1546 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1547 {0x0067, 1548 RTW_PWR_CUT_ALL_MSK, 1549 RTW_PWR_INTF_SDIO_MSK, 1550 RTW_PWR_ADDR_MAC, 1551 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1552 {0x0046, 1553 RTW_PWR_CUT_ALL_MSK, 1554 RTW_PWR_INTF_SDIO_MSK, 1555 RTW_PWR_ADDR_MAC, 1556 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1557 {0x0062, 1558 RTW_PWR_CUT_ALL_MSK, 1559 RTW_PWR_INTF_SDIO_MSK, 1560 RTW_PWR_ADDR_MAC, 1561 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1562 {0x0081, 1563 RTW_PWR_CUT_ALL_MSK, 1564 RTW_PWR_INTF_ALL_MSK, 1565 RTW_PWR_ADDR_MAC, 1566 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1567 {0x0005, 1568 RTW_PWR_CUT_ALL_MSK, 1569 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1570 RTW_PWR_ADDR_MAC, 1571 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1572 {0x0086, 1573 RTW_PWR_CUT_ALL_MSK, 1574 RTW_PWR_INTF_SDIO_MSK, 1575 RTW_PWR_ADDR_SDIO, 1576 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1577 {0x0086, 1578 RTW_PWR_CUT_ALL_MSK, 1579 RTW_PWR_INTF_SDIO_MSK, 1580 RTW_PWR_ADDR_SDIO, 1581 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1582 {0x0090, 1583 RTW_PWR_CUT_ALL_MSK, 1584 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1585 RTW_PWR_ADDR_MAC, 1586 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1587 {0x0044, 1588 RTW_PWR_CUT_ALL_MSK, 1589 RTW_PWR_INTF_SDIO_MSK, 1590 RTW_PWR_ADDR_SDIO, 1591 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1592 {0x0040, 1593 RTW_PWR_CUT_ALL_MSK, 1594 RTW_PWR_INTF_SDIO_MSK, 1595 RTW_PWR_ADDR_SDIO, 1596 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1597 {0x0041, 1598 RTW_PWR_CUT_ALL_MSK, 1599 RTW_PWR_INTF_SDIO_MSK, 1600 RTW_PWR_ADDR_SDIO, 1601 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1602 {0x0042, 1603 RTW_PWR_CUT_ALL_MSK, 1604 RTW_PWR_INTF_SDIO_MSK, 1605 RTW_PWR_ADDR_SDIO, 1606 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1607 {0xFFFF, 1608 RTW_PWR_CUT_ALL_MSK, 1609 RTW_PWR_INTF_ALL_MSK, 1610 0, 1611 RTW_PWR_CMD_END, 0, 0}, 1612 }; 1613 1614 static struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = { 1615 trans_carddis_to_cardemu_8822b, 1616 trans_cardemu_to_act_8822b, 1617 NULL 1618 }; 1619 1620 static struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = { 1621 trans_act_to_cardemu_8822b, 1622 trans_cardemu_to_carddis_8822b, 1623 NULL 1624 }; 1625 1626 static struct rtw_intf_phy_para usb2_param_8822b[] = { 1627 {0xFFFF, 0x00, 1628 RTW_IP_SEL_PHY, 1629 RTW_INTF_PHY_CUT_ALL, 1630 RTW_INTF_PHY_PLATFORM_ALL}, 1631 }; 1632 1633 static struct rtw_intf_phy_para usb3_param_8822b[] = { 1634 {0x0001, 0xA841, 1635 RTW_IP_SEL_PHY, 1636 RTW_INTF_PHY_CUT_D, 1637 RTW_INTF_PHY_PLATFORM_ALL}, 1638 {0xFFFF, 0x0000, 1639 RTW_IP_SEL_PHY, 1640 RTW_INTF_PHY_CUT_ALL, 1641 RTW_INTF_PHY_PLATFORM_ALL}, 1642 }; 1643 1644 static struct rtw_intf_phy_para pcie_gen1_param_8822b[] = { 1645 {0x0001, 0xA841, 1646 RTW_IP_SEL_PHY, 1647 RTW_INTF_PHY_CUT_C, 1648 RTW_INTF_PHY_PLATFORM_ALL}, 1649 {0x0002, 0x60C6, 1650 RTW_IP_SEL_PHY, 1651 RTW_INTF_PHY_CUT_C, 1652 RTW_INTF_PHY_PLATFORM_ALL}, 1653 {0x0008, 0x3596, 1654 RTW_IP_SEL_PHY, 1655 RTW_INTF_PHY_CUT_C, 1656 RTW_INTF_PHY_PLATFORM_ALL}, 1657 {0x0009, 0x321C, 1658 RTW_IP_SEL_PHY, 1659 RTW_INTF_PHY_CUT_C, 1660 RTW_INTF_PHY_PLATFORM_ALL}, 1661 {0x000A, 0x9623, 1662 RTW_IP_SEL_PHY, 1663 RTW_INTF_PHY_CUT_C, 1664 RTW_INTF_PHY_PLATFORM_ALL}, 1665 {0x0020, 0x94FF, 1666 RTW_IP_SEL_PHY, 1667 RTW_INTF_PHY_CUT_C, 1668 RTW_INTF_PHY_PLATFORM_ALL}, 1669 {0x0021, 0xFFCF, 1670 RTW_IP_SEL_PHY, 1671 RTW_INTF_PHY_CUT_C, 1672 RTW_INTF_PHY_PLATFORM_ALL}, 1673 {0x0026, 0xC006, 1674 RTW_IP_SEL_PHY, 1675 RTW_INTF_PHY_CUT_C, 1676 RTW_INTF_PHY_PLATFORM_ALL}, 1677 {0x0029, 0xFF0E, 1678 RTW_IP_SEL_PHY, 1679 RTW_INTF_PHY_CUT_C, 1680 RTW_INTF_PHY_PLATFORM_ALL}, 1681 {0x002A, 0x1840, 1682 RTW_IP_SEL_PHY, 1683 RTW_INTF_PHY_CUT_C, 1684 RTW_INTF_PHY_PLATFORM_ALL}, 1685 {0xFFFF, 0x0000, 1686 RTW_IP_SEL_PHY, 1687 RTW_INTF_PHY_CUT_ALL, 1688 RTW_INTF_PHY_PLATFORM_ALL}, 1689 }; 1690 1691 static struct rtw_intf_phy_para pcie_gen2_param_8822b[] = { 1692 {0x0001, 0xA841, 1693 RTW_IP_SEL_PHY, 1694 RTW_INTF_PHY_CUT_C, 1695 RTW_INTF_PHY_PLATFORM_ALL}, 1696 {0x0002, 0x60C6, 1697 RTW_IP_SEL_PHY, 1698 RTW_INTF_PHY_CUT_C, 1699 RTW_INTF_PHY_PLATFORM_ALL}, 1700 {0x0008, 0x3597, 1701 RTW_IP_SEL_PHY, 1702 RTW_INTF_PHY_CUT_C, 1703 RTW_INTF_PHY_PLATFORM_ALL}, 1704 {0x0009, 0x321C, 1705 RTW_IP_SEL_PHY, 1706 RTW_INTF_PHY_CUT_C, 1707 RTW_INTF_PHY_PLATFORM_ALL}, 1708 {0x000A, 0x9623, 1709 RTW_IP_SEL_PHY, 1710 RTW_INTF_PHY_CUT_C, 1711 RTW_INTF_PHY_PLATFORM_ALL}, 1712 {0x0020, 0x94FF, 1713 RTW_IP_SEL_PHY, 1714 RTW_INTF_PHY_CUT_C, 1715 RTW_INTF_PHY_PLATFORM_ALL}, 1716 {0x0021, 0xFFCF, 1717 RTW_IP_SEL_PHY, 1718 RTW_INTF_PHY_CUT_C, 1719 RTW_INTF_PHY_PLATFORM_ALL}, 1720 {0x0026, 0xC006, 1721 RTW_IP_SEL_PHY, 1722 RTW_INTF_PHY_CUT_C, 1723 RTW_INTF_PHY_PLATFORM_ALL}, 1724 {0x0029, 0xFF0E, 1725 RTW_IP_SEL_PHY, 1726 RTW_INTF_PHY_CUT_C, 1727 RTW_INTF_PHY_PLATFORM_ALL}, 1728 {0x002A, 0x3040, 1729 RTW_IP_SEL_PHY, 1730 RTW_INTF_PHY_CUT_C, 1731 RTW_INTF_PHY_PLATFORM_ALL}, 1732 {0xFFFF, 0x0000, 1733 RTW_IP_SEL_PHY, 1734 RTW_INTF_PHY_CUT_ALL, 1735 RTW_INTF_PHY_PLATFORM_ALL}, 1736 }; 1737 1738 static struct rtw_intf_phy_para_table phy_para_table_8822b = { 1739 .usb2_para = usb2_param_8822b, 1740 .usb3_para = usb3_param_8822b, 1741 .gen1_para = pcie_gen1_param_8822b, 1742 .gen2_para = pcie_gen2_param_8822b, 1743 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b), 1744 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b), 1745 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b), 1746 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b), 1747 }; 1748 1749 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = { 1750 [2] = RTW_DEF_RFE(8822b, 2, 2), 1751 [5] = RTW_DEF_RFE(8822b, 5, 5), 1752 }; 1753 1754 static struct rtw_hw_reg rtw8822b_dig[] = { 1755 [0] = { .addr = 0xc50, .mask = 0x7f }, 1756 [1] = { .addr = 0xe50, .mask = 0x7f }, 1757 }; 1758 1759 static struct rtw_page_table page_table_8822b[] = { 1760 {64, 64, 64, 64, 1}, 1761 {64, 64, 64, 64, 1}, 1762 {64, 64, 0, 0, 1}, 1763 {64, 64, 64, 0, 1}, 1764 {64, 64, 64, 64, 1}, 1765 }; 1766 1767 static struct rtw_rqpn rqpn_table_8822b[] = { 1768 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1769 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1770 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1771 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1772 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1773 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1774 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1775 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1776 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1777 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1778 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1779 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1780 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1781 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1782 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1783 }; 1784 1785 static struct rtw_chip_ops rtw8822b_ops = { 1786 .phy_set_param = rtw8822b_phy_set_param, 1787 .read_efuse = rtw8822b_read_efuse, 1788 .query_rx_desc = rtw8822b_query_rx_desc, 1789 .set_channel = rtw8822b_set_channel, 1790 .mac_init = rtw8822b_mac_init, 1791 .read_rf = rtw_phy_read_rf, 1792 .write_rf = rtw_phy_write_rf_reg_sipi, 1793 .set_tx_power_index = rtw8822b_set_tx_power_index, 1794 .set_antenna = rtw8822b_set_antenna, 1795 .cfg_ldo25 = rtw8822b_cfg_ldo25, 1796 .false_alarm_statistics = rtw8822b_false_alarm_statistics, 1797 .do_iqk = rtw8822b_do_iqk, 1798 1799 .coex_set_init = rtw8822b_coex_cfg_init, 1800 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch, 1801 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix, 1802 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug, 1803 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type, 1804 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power, 1805 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain, 1806 }; 1807 1808 /* Shared-Antenna Coex Table */ 1809 static const struct coex_table_para table_sant_8822b[] = { 1810 {0xffffffff, 0xffffffff}, /* case-0 */ 1811 {0x55555555, 0x55555555}, 1812 {0x66555555, 0x66555555}, 1813 {0xaaaaaaaa, 0xaaaaaaaa}, 1814 {0x5a5a5a5a, 0x5a5a5a5a}, 1815 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1816 {0x6a5a6a5a, 0xaaaaaaaa}, 1817 {0x6a5a56aa, 0x6a5a56aa}, 1818 {0x6a5a5a5a, 0x6a5a5a5a}, 1819 {0x66555555, 0x5a5a5a5a}, 1820 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1821 {0x66555555, 0xfafafafa}, 1822 {0x66555555, 0x6a5a5aaa}, 1823 {0x66555555, 0x5aaa5aaa}, 1824 {0x66555555, 0xaaaa5aaa}, 1825 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1826 {0xffff55ff, 0xfafafafa}, 1827 {0xffff55ff, 0x6afa5afa}, 1828 {0xaaffffaa, 0xfafafafa}, 1829 {0xaa5555aa, 0x5a5a5a5a}, 1830 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1831 {0xaa5555aa, 0xaaaaaaaa}, 1832 {0xffffffff, 0x5a5a5a5a}, 1833 {0xffffffff, 0x6a5a5a5a}, 1834 {0xffffffff, 0x55555555}, 1835 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 1836 {0x55555555, 0x5a5a5a5a}, 1837 {0x55555555, 0xaaaaaaaa}, 1838 {0x55555555, 0x6a5a6a5a}, 1839 {0x66556655, 0x66556655} 1840 }; 1841 1842 /* Non-Shared-Antenna Coex Table */ 1843 static const struct coex_table_para table_nsant_8822b[] = { 1844 {0xffffffff, 0xffffffff}, /* case-100 */ 1845 {0x55555555, 0x55555555}, 1846 {0x66555555, 0x66555555}, 1847 {0xaaaaaaaa, 0xaaaaaaaa}, 1848 {0x5a5a5a5a, 0x5a5a5a5a}, 1849 {0xfafafafa, 0xfafafafa}, /* case-105 */ 1850 {0x5afa5afa, 0x5afa5afa}, 1851 {0x55555555, 0xfafafafa}, 1852 {0x66555555, 0xfafafafa}, 1853 {0x66555555, 0x5a5a5a5a}, 1854 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1855 {0x66555555, 0xaaaaaaaa}, 1856 {0xffff55ff, 0xfafafafa}, 1857 {0xffff55ff, 0x5afa5afa}, 1858 {0xffff55ff, 0xaaaaaaaa}, 1859 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 1860 {0xaaffffaa, 0x5afa5afa}, 1861 {0xaaffffaa, 0xaaaaaaaa}, 1862 {0xffffffff, 0xfafafafa}, 1863 {0xffffffff, 0x5afa5afa}, 1864 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1865 {0x55ff55ff, 0x5afa5afa}, 1866 {0x55ff55ff, 0xaaaaaaaa}, 1867 {0x55ff55ff, 0x55ff55ff} 1868 }; 1869 1870 /* Shared-Antenna TDMA */ 1871 static const struct coex_tdma_para tdma_sant_8822b[] = { 1872 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1873 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1874 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1875 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1876 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1877 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 1878 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1879 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1880 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1881 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1882 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1883 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1884 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1885 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1886 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1887 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1888 { {0x51, 0x45, 0x03, 0x10, 0x10} }, 1889 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1890 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1891 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1892 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1893 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1894 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 1895 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1896 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 1897 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1898 { {0x51, 0x08, 0x03, 0x10, 0x50} } 1899 }; 1900 1901 /* Non-Shared-Antenna TDMA */ 1902 static const struct coex_tdma_para tdma_nsant_8822b[] = { 1903 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 1904 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1905 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1906 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1907 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1908 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1909 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1910 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1911 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1912 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1913 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1914 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1915 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1916 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1917 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1918 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1919 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1920 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1921 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1922 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1923 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ 1924 }; 1925 1926 /* rssi in percentage % (dbm = % - 100) */ 1927 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30}; 1928 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30}; 1929 static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} }; 1930 1931 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1932 static const struct coex_rf_para rf_para_tx_8822b[] = { 1933 {0, 0, false, 7}, /* for normal */ 1934 {0, 16, false, 7}, /* for WL-CPT */ 1935 {4, 0, true, 1}, 1936 {3, 6, true, 1}, 1937 {2, 9, true, 1}, 1938 {1, 13, true, 1} 1939 }; 1940 1941 static const struct coex_rf_para rf_para_rx_8822b[] = { 1942 {0, 0, false, 7}, /* for normal */ 1943 {0, 16, false, 7}, /* for WL-CPT */ 1944 {4, 0, true, 1}, 1945 {3, 6, true, 1}, 1946 {2, 9, true, 1}, 1947 {1, 13, true, 1} 1948 }; 1949 1950 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b)); 1951 1952 struct rtw_chip_info rtw8822b_hw_spec = { 1953 .ops = &rtw8822b_ops, 1954 .id = RTW_CHIP_TYPE_8822B, 1955 .fw_name = "rtw88/rtw8822b_fw.bin", 1956 .tx_pkt_desc_sz = 48, 1957 .tx_buf_desc_sz = 16, 1958 .rx_pkt_desc_sz = 24, 1959 .rx_buf_desc_sz = 8, 1960 .phy_efuse_size = 1024, 1961 .log_efuse_size = 768, 1962 .ptct_efuse_size = 96, 1963 .txff_size = 262144, 1964 .rxff_size = 24576, 1965 .txgi_factor = 1, 1966 .is_pwr_by_rate_dec = true, 1967 .max_power_index = 0x3f, 1968 .csi_buf_pg_num = 0, 1969 .band = RTW_BAND_2G | RTW_BAND_5G, 1970 .page_size = 128, 1971 .dig_min = 0x1c, 1972 .ht_supported = true, 1973 .vht_supported = true, 1974 .sys_func_en = 0xDC, 1975 .pwr_on_seq = card_enable_flow_8822b, 1976 .pwr_off_seq = card_disable_flow_8822b, 1977 .page_table = page_table_8822b, 1978 .rqpn_table = rqpn_table_8822b, 1979 .intf_table = &phy_para_table_8822b, 1980 .dig = rtw8822b_dig, 1981 .rf_base_addr = {0x2800, 0x2c00}, 1982 .rf_sipi_addr = {0xc90, 0xe90}, 1983 .mac_tbl = &rtw8822b_mac_tbl, 1984 .agc_tbl = &rtw8822b_agc_tbl, 1985 .bb_tbl = &rtw8822b_bb_tbl, 1986 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl}, 1987 .rfe_defs = rtw8822b_rfe_defs, 1988 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs), 1989 1990 .coex_para_ver = 0x19062706, 1991 .bt_desired_ver = 0x6, 1992 .scbd_support = true, 1993 .new_scbd10_def = false, 1994 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1995 .bt_rssi_type = COEX_BTRSSI_RATIO, 1996 .ant_isolation = 15, 1997 .rssi_tolerance = 2, 1998 .wl_rssi_step = wl_rssi_step_8822b, 1999 .bt_rssi_step = bt_rssi_step_8822b, 2000 .table_sant_num = ARRAY_SIZE(table_sant_8822b), 2001 .table_sant = table_sant_8822b, 2002 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b), 2003 .table_nsant = table_nsant_8822b, 2004 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b), 2005 .tdma_sant = tdma_sant_8822b, 2006 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b), 2007 .tdma_nsant = tdma_nsant_8822b, 2008 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b), 2009 .wl_rf_para_tx = rf_para_tx_8822b, 2010 .wl_rf_para_rx = rf_para_rx_8822b, 2011 .bt_afh_span_bw20 = 0x24, 2012 .bt_afh_span_bw40 = 0x36, 2013 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b), 2014 .afh_5g = afh_5g_8822b, 2015 }; 2016 EXPORT_SYMBOL(rtw8822b_hw_spec); 2017 2018 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin"); 2019