1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8822b.h" 12 #include "rtw8822b_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 18 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 19 u8 rx_path, bool is_tx2_path); 20 21 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse, 22 struct rtw8822b_efuse *map) 23 { 24 ether_addr_copy(efuse->addr, map->e.mac_addr); 25 } 26 27 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 28 { 29 struct rtw_efuse *efuse = &rtwdev->efuse; 30 struct rtw8822b_efuse *map; 31 int i; 32 33 map = (struct rtw8822b_efuse *)log_map; 34 35 efuse->rfe_option = map->rfe_option; 36 efuse->rf_board_option = map->rf_board_option; 37 efuse->crystal_cap = map->xtal_k; 38 efuse->pa_type_2g = map->pa_type; 39 efuse->pa_type_5g = map->pa_type; 40 efuse->lna_type_2g = map->lna_type_2g[0]; 41 efuse->lna_type_5g = map->lna_type_5g[0]; 42 efuse->channel_plan = map->channel_plan; 43 efuse->country_code[0] = map->country_code[0]; 44 efuse->country_code[1] = map->country_code[1]; 45 efuse->bt_setting = map->rf_bt_setting; 46 efuse->regd = map->rf_board_option & 0x7; 47 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; 48 efuse->thermal_meter_k = map->thermal_meter; 49 50 for (i = 0; i < 4; i++) 51 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 52 53 switch (rtw_hci_type(rtwdev)) { 54 case RTW_HCI_TYPE_PCIE: 55 rtw8822be_efuse_parsing(efuse, map); 56 break; 57 default: 58 /* unsupported now */ 59 return -ENOTSUPP; 60 } 61 62 return 0; 63 } 64 65 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev) 66 { 67 /* chip top mux */ 68 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); 69 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); 70 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); 71 72 /* from s0 or s1 */ 73 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); 74 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); 75 76 /* input or output */ 77 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); 78 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); 79 } 80 81 #define RTW_TXSCALE_SIZE 37 82 static const u32 rtw8822b_txscale_tbl[RTW_TXSCALE_SIZE] = { 83 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 84 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 85 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 86 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 87 }; 88 89 static const u8 rtw8822b_get_swing_index(struct rtw_dev *rtwdev) 90 { 91 u8 i = 0; 92 u32 swing, table_value; 93 94 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); 95 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { 96 table_value = rtw8822b_txscale_tbl[i]; 97 if (swing == table_value) 98 break; 99 } 100 101 return i; 102 } 103 104 static void rtw8822b_pwrtrack_init(struct rtw_dev *rtwdev) 105 { 106 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 107 u8 swing_idx = rtw8822b_get_swing_index(rtwdev); 108 u8 path; 109 110 if (swing_idx >= RTW_TXSCALE_SIZE) 111 dm_info->default_ofdm_index = 24; 112 else 113 dm_info->default_ofdm_index = swing_idx; 114 115 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 116 ewma_thermal_init(&dm_info->avg_thermal[path]); 117 dm_info->delta_power_index[path] = 0; 118 } 119 dm_info->pwr_trk_triggered = false; 120 dm_info->pwr_trk_init_trigger = true; 121 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 122 } 123 124 static void rtw8822b_phy_bf_init(struct rtw_dev *rtwdev) 125 { 126 rtw_bf_phy_init(rtwdev); 127 /* Grouping bitmap parameters */ 128 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 129 } 130 131 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev) 132 { 133 struct rtw_hal *hal = &rtwdev->hal; 134 u8 crystal_cap; 135 bool is_tx2_path; 136 137 /* power on BB/RF domain */ 138 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 139 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 140 rtw_write8_set(rtwdev, REG_RF_CTRL, 141 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 142 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 143 144 /* pre init before header files config */ 145 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 146 147 rtw_phy_load_tables(rtwdev); 148 149 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 150 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); 151 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); 152 153 /* post init after header files config */ 154 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 155 156 is_tx2_path = false; 157 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 158 is_tx2_path); 159 rtw_phy_init(rtwdev); 160 161 rtw8822b_phy_rfe_init(rtwdev); 162 rtw8822b_pwrtrack_init(rtwdev); 163 164 rtw8822b_phy_bf_init(rtwdev); 165 } 166 167 #define WLAN_SLOT_TIME 0x09 168 #define WLAN_PIFS_TIME 0x19 169 #define WLAN_SIFS_CCK_CONT_TX 0xA 170 #define WLAN_SIFS_OFDM_CONT_TX 0xE 171 #define WLAN_SIFS_CCK_TRX 0x10 172 #define WLAN_SIFS_OFDM_TRX 0x10 173 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ 174 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ 175 #define WLAN_RDG_NAV 0x05 176 #define WLAN_TXOP_NAV 0x1B 177 #define WLAN_CCK_RX_TSF 0x30 178 #define WLAN_OFDM_RX_TSF 0x30 179 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 180 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 181 #define WLAN_DRV_EARLY_INT 0x04 182 #define WLAN_BCN_DMA_TIME 0x02 183 184 #define WLAN_RX_FILTER0 0x0FFFFFFF 185 #define WLAN_RX_FILTER2 0xFFFF 186 #define WLAN_RCR_CFG 0xE400220E 187 #define WLAN_RXPKT_MAX_SZ 12288 188 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 189 190 #define WLAN_AMPDU_MAX_TIME 0x70 191 #define WLAN_RTS_LEN_TH 0xFF 192 #define WLAN_RTS_TX_TIME_TH 0x08 193 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 194 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 195 #define FAST_EDCA_VO_TH 0x06 196 #define FAST_EDCA_VI_TH 0x06 197 #define FAST_EDCA_BE_TH 0x06 198 #define FAST_EDCA_BK_TH 0x06 199 #define WLAN_BAR_RETRY_LIMIT 0x01 200 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 201 202 #define WLAN_TX_FUNC_CFG1 0x30 203 #define WLAN_TX_FUNC_CFG2 0x30 204 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 205 #define WLAN_MAC_OPT_LB_FUNC1 0x80 206 #define WLAN_MAC_OPT_FUNC2 0x30810041 207 208 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 209 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 210 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 211 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 212 213 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 214 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 215 216 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 217 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 218 219 static int rtw8822b_mac_init(struct rtw_dev *rtwdev) 220 { 221 u32 value32; 222 223 /* protocol configuration */ 224 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD); 225 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 226 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 227 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 228 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 229 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 230 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 231 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 232 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 233 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 234 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 235 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 236 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 237 /* EDCA configuration */ 238 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 239 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 240 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 241 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 242 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 243 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 244 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 245 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 246 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 247 /* Set beacon cotnrol - enable TSF and other related functions */ 248 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 249 /* Set send beacon related registers */ 250 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 251 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 252 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 253 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 254 /* WMAC configuration */ 255 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 256 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 257 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 258 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 259 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 260 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 261 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 262 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 263 264 return 0; 265 } 266 267 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel) 268 { 269 struct rtw_hal *hal = &rtwdev->hal; 270 271 if (IS_CH_2G_BAND(channel)) { 272 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); 273 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 274 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); 275 } else { 276 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); 277 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 278 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); 279 } 280 281 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 282 283 if (hal->antenna_rx == BB_PATH_AB || 284 hal->antenna_tx == BB_PATH_AB) { 285 /* 2TX or 2RX */ 286 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 287 } else if (hal->antenna_rx == hal->antenna_tx) { 288 /* TXA+RXA or TXB+RXB */ 289 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 290 } else { 291 /* TXB+RXA or TXA+RXB */ 292 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 293 } 294 } 295 296 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel) 297 { 298 struct rtw_hal *hal = &rtwdev->hal; 299 300 if (IS_CH_2G_BAND(channel)) { 301 /* signal source */ 302 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); 303 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 304 } else { 305 /* signal source */ 306 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); 307 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 308 } 309 310 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 311 312 if (IS_CH_2G_BAND(channel)) { 313 if (hal->antenna_rx == BB_PATH_AB || 314 hal->antenna_tx == BB_PATH_AB) { 315 /* 2TX or 2RX */ 316 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 317 } else if (hal->antenna_rx == hal->antenna_tx) { 318 /* TXA+RXA or TXB+RXB */ 319 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 320 } else { 321 /* TXB+RXA or TXA+RXB */ 322 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 323 } 324 } else { 325 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); 326 } 327 } 328 329 enum { 330 CCUT_IDX_1R_2G, 331 CCUT_IDX_2R_2G, 332 CCUT_IDX_1R_5G, 333 CCUT_IDX_2R_5G, 334 CCUT_IDX_NR, 335 }; 336 337 struct cca_ccut { 338 u32 reg82c[CCUT_IDX_NR]; 339 u32 reg830[CCUT_IDX_NR]; 340 u32 reg838[CCUT_IDX_NR]; 341 }; 342 343 static const struct cca_ccut cca_ifem_ccut = { 344 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ 345 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 346 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/ 347 }; 348 349 static const struct cca_ccut cca_efem_ccut = { 350 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ 351 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/ 352 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ 353 }; 354 355 static const struct cca_ccut cca_ifem_ccut_ext = { 356 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ 357 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 358 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/ 359 }; 360 361 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col, 362 u32 *reg82c, u32 *reg830, u32 *reg838) 363 { 364 *reg82c = cca_ccut->reg82c[col]; 365 *reg830 = cca_ccut->reg830[col]; 366 *reg838 = cca_ccut->reg838[col]; 367 } 368 369 struct rtw8822b_rfe_info { 370 const struct cca_ccut *cca_ccut_2g; 371 const struct cca_ccut *cca_ccut_5g; 372 enum rtw_rfe_fem fem; 373 bool ifem_ext; 374 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel); 375 }; 376 377 #define I2GE5G_CCUT(set_ch) { \ 378 .cca_ccut_2g = &cca_ifem_ccut, \ 379 .cca_ccut_5g = &cca_efem_ccut, \ 380 .fem = RTW_RFE_IFEM2G_EFEM5G, \ 381 .ifem_ext = false, \ 382 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 383 } 384 #define IFEM_EXT_CCUT(set_ch) { \ 385 .cca_ccut_2g = &cca_ifem_ccut_ext, \ 386 .cca_ccut_5g = &cca_ifem_ccut_ext, \ 387 .fem = RTW_RFE_IFEM, \ 388 .ifem_ext = true, \ 389 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 390 } 391 392 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = { 393 [2] = I2GE5G_CCUT(efem), 394 [3] = IFEM_EXT_CCUT(ifem), 395 [5] = IFEM_EXT_CCUT(ifem), 396 }; 397 398 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw, 399 const struct rtw8822b_rfe_info *rfe_info) 400 { 401 struct rtw_hal *hal = &rtwdev->hal; 402 struct rtw_efuse *efuse = &rtwdev->efuse; 403 const struct cca_ccut *cca_ccut; 404 u8 col; 405 u32 reg82c, reg830, reg838; 406 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; 407 408 if (IS_CH_2G_BAND(channel)) { 409 cca_ccut = rfe_info->cca_ccut_2g; 410 411 if (hal->antenna_rx == BB_PATH_A || 412 hal->antenna_rx == BB_PATH_B) 413 col = CCUT_IDX_1R_2G; 414 else 415 col = CCUT_IDX_2R_2G; 416 } else { 417 cca_ccut = rfe_info->cca_ccut_5g; 418 419 if (hal->antenna_rx == BB_PATH_A || 420 hal->antenna_rx == BB_PATH_B) 421 col = CCUT_IDX_1R_5G; 422 else 423 col = CCUT_IDX_2R_5G; 424 } 425 426 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838); 427 428 switch (rfe_info->fem) { 429 case RTW_RFE_IFEM: 430 default: 431 is_ifem_cca = true; 432 if (rfe_info->ifem_ext) 433 is_rfe_type = true; 434 break; 435 case RTW_RFE_EFEM: 436 is_efem_cca = true; 437 break; 438 case RTW_RFE_IFEM2G_EFEM5G: 439 if (IS_CH_2G_BAND(channel)) 440 is_ifem_cca = true; 441 else 442 is_efem_cca = true; 443 break; 444 } 445 446 if (is_ifem_cca) { 447 if ((hal->cut_version == RTW_CHIP_VER_CUT_B && 448 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) && 449 bw == RTW_CHANNEL_WIDTH_40) || 450 (!is_rfe_type && col == CCUT_IDX_2R_5G && 451 bw == RTW_CHANNEL_WIDTH_40) || 452 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G)) 453 reg830 = 0x79a0ea28; 454 } 455 456 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c); 457 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830); 458 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838); 459 460 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B)) 461 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); 462 463 if (bw == RTW_CHANNEL_WIDTH_20 && IS_CH_5G_BAND_MID(channel)) 464 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); 465 } 466 467 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 468 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; 469 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 470 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 471 0x6, 0x5, 0x0, 0x0, 0x7}; 472 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 473 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; 474 475 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 476 { 477 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 478 #define RF18_BAND_2G (0) 479 #define RF18_BAND_5G (BIT(16) | BIT(8)) 480 #define RF18_CHANNEL_MASK (MASKBYTE0) 481 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 482 #define RF18_RFSI_GE_CH80 (BIT(17)) 483 #define RF18_RFSI_GT_CH144 (BIT(18)) 484 #define RF18_BW_MASK (BIT(11) | BIT(10)) 485 #define RF18_BW_20M (BIT(11) | BIT(10)) 486 #define RF18_BW_40M (BIT(11)) 487 #define RF18_BW_80M (BIT(10)) 488 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) 489 490 struct rtw_hal *hal = &rtwdev->hal; 491 u32 rf_reg18, rf_reg_be; 492 493 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 494 495 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 496 RF18_BW_MASK); 497 498 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 499 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 500 if (channel > 144) 501 rf_reg18 |= RF18_RFSI_GT_CH144; 502 else if (channel >= 80) 503 rf_reg18 |= RF18_RFSI_GE_CH80; 504 505 switch (bw) { 506 case RTW_CHANNEL_WIDTH_5: 507 case RTW_CHANNEL_WIDTH_10: 508 case RTW_CHANNEL_WIDTH_20: 509 default: 510 rf_reg18 |= RF18_BW_20M; 511 break; 512 case RTW_CHANNEL_WIDTH_40: 513 rf_reg18 |= RF18_BW_40M; 514 break; 515 case RTW_CHANNEL_WIDTH_80: 516 rf_reg18 |= RF18_BW_80M; 517 break; 518 } 519 520 if (IS_CH_2G_BAND(channel)) 521 rf_reg_be = 0x0; 522 else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 523 rf_reg_be = low_band[(channel - 36) >> 1]; 524 else if (IS_CH_5G_BAND_3(channel)) 525 rf_reg_be = middle_band[(channel - 100) >> 1]; 526 else if (IS_CH_5G_BAND_4(channel)) 527 rf_reg_be = high_band[(channel - 149) >> 1]; 528 else 529 goto err; 530 531 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be); 532 533 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ 534 if (channel == 144) 535 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); 536 else 537 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); 538 539 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 540 if (hal->rf_type > RF_1T1R) 541 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); 542 543 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 544 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 545 546 return; 547 548 err: 549 WARN_ON(1); 550 } 551 552 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev) 553 { 554 struct rtw_hal *hal = &rtwdev->hal; 555 u32 igi; 556 557 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); 558 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); 559 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); 560 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); 561 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); 562 563 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); 564 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 565 hal->antenna_rx | (hal->antenna_rx << 4)); 566 } 567 568 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 569 { 570 if (bw == RTW_CHANNEL_WIDTH_40) { 571 /* RX DFIR for BW40 */ 572 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); 573 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); 574 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 575 } else if (bw == RTW_CHANNEL_WIDTH_80) { 576 /* RX DFIR for BW80 */ 577 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 578 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 579 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 580 } else { 581 /* RX DFIR for BW20, BW10 and BW5*/ 582 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 583 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 584 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 585 } 586 } 587 588 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 589 u8 primary_ch_idx) 590 { 591 struct rtw_efuse *efuse = &rtwdev->efuse; 592 u8 rfe_option = efuse->rfe_option; 593 u32 val32; 594 595 if (IS_CH_2G_BAND(channel)) { 596 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 597 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 598 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 599 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 600 601 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); 602 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 603 if (channel == 14) { 604 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); 605 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 606 } else { 607 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); 608 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); 609 } 610 611 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); 612 } else if (IS_CH_5G_BAND(channel)) { 613 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 614 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 615 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 616 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); 617 618 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 619 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); 620 else if (IS_CH_5G_BAND_3(channel)) 621 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); 622 else if (IS_CH_5G_BAND_4(channel)) 623 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); 624 625 if (IS_CH_5G_BAND_1(channel)) 626 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 627 else if (IS_CH_5G_BAND_2(channel)) 628 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 629 else if (channel >= 100 && channel <= 116) 630 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 631 else if (channel >= 118 && channel <= 177) 632 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 633 634 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); 635 } 636 637 switch (bw) { 638 case RTW_CHANNEL_WIDTH_20: 639 default: 640 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 641 val32 &= 0xFFCFFC00; 642 val32 |= (RTW_CHANNEL_WIDTH_20); 643 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 644 645 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 646 break; 647 case RTW_CHANNEL_WIDTH_40: 648 if (primary_ch_idx == RTW_SC_20_UPPER) 649 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 650 else 651 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 652 653 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 654 val32 &= 0xFF3FF300; 655 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); 656 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 657 658 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 659 break; 660 case RTW_CHANNEL_WIDTH_80: 661 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 662 val32 &= 0xFCEFCF00; 663 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); 664 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 665 666 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 667 668 if (rfe_option == 2 || rfe_option == 3) { 669 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); 670 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); 671 } 672 break; 673 case RTW_CHANNEL_WIDTH_5: 674 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 675 val32 &= 0xEFEEFE00; 676 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); 677 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 678 679 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 680 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 681 break; 682 case RTW_CHANNEL_WIDTH_10: 683 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 684 val32 &= 0xEFFEFF00; 685 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); 686 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 687 688 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 689 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 690 break; 691 } 692 } 693 694 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 695 u8 primary_chan_idx) 696 { 697 struct rtw_efuse *efuse = &rtwdev->efuse; 698 const struct rtw8822b_rfe_info *rfe_info; 699 700 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 701 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 702 return; 703 704 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 705 706 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 707 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 708 rtw8822b_set_channel_rf(rtwdev, channel, bw); 709 rtw8822b_set_channel_rxdfir(rtwdev, bw); 710 rtw8822b_toggle_igi(rtwdev); 711 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info); 712 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel); 713 } 714 715 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 716 u8 rx_path, bool is_tx2_path) 717 { 718 struct rtw_efuse *efuse = &rtwdev->efuse; 719 const struct rtw8822b_rfe_info *rfe_info; 720 u8 ch = rtwdev->hal.current_channel; 721 u8 tx_path_sel, rx_path_sel; 722 int counter; 723 724 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 725 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 726 return; 727 728 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 729 730 if ((tx_path | rx_path) & BB_PATH_A) 731 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); 732 else 733 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); 734 735 if ((tx_path | rx_path) & BB_PATH_B) 736 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); 737 else 738 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); 739 740 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); 741 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); 742 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); 743 744 if (tx_path & BB_PATH_A) { 745 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); 746 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); 747 } else if (tx_path & BB_PATH_B) { 748 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); 749 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); 750 } 751 752 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B) 753 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); 754 else 755 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); 756 757 tx_path_sel = (tx_path << 4) | tx_path; 758 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel); 759 760 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) { 761 if (is_tx2_path || rtwdev->mp_mode) { 762 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); 763 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); 764 } 765 } 766 767 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); 768 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); 769 770 if (rx_path & BB_PATH_A) 771 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); 772 else if (rx_path & BB_PATH_B) 773 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); 774 775 rx_path_sel = (rx_path << 4) | rx_path; 776 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); 777 778 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 779 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); 780 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); 781 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); 782 } else { 783 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); 784 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); 785 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); 786 } 787 788 for (counter = 100; counter > 0; counter--) { 789 u32 rf_reg33; 790 791 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 792 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 793 794 udelay(2); 795 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); 796 797 if (rf_reg33 == 0x00001) 798 break; 799 } 800 801 if (WARN(counter <= 0, "write RF mode table fail\n")) 802 return; 803 804 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 805 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 806 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); 807 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); 808 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 809 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 810 811 rtw8822b_toggle_igi(rtwdev); 812 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info); 813 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch); 814 } 815 816 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 817 struct rtw_rx_pkt_stat *pkt_stat) 818 { 819 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 820 s8 min_rx_power = -120; 821 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 822 823 /* 8822B uses only 1 antenna to RX CCK rates */ 824 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110; 825 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 826 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 827 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 828 min_rx_power); 829 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 830 } 831 832 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 833 struct rtw_rx_pkt_stat *pkt_stat) 834 { 835 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 836 u8 rxsc, bw; 837 s8 min_rx_power = -120; 838 s8 rx_evm; 839 u8 evm_dbm = 0; 840 u8 rssi; 841 int path; 842 843 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 844 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 845 else 846 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 847 848 if (rxsc >= 1 && rxsc <= 8) 849 bw = RTW_CHANNEL_WIDTH_20; 850 else if (rxsc >= 9 && rxsc <= 12) 851 bw = RTW_CHANNEL_WIDTH_40; 852 else if (rxsc >= 13) 853 bw = RTW_CHANNEL_WIDTH_80; 854 else 855 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 856 857 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 858 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 859 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 860 pkt_stat->bw = bw; 861 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 862 pkt_stat->rx_power[RF_PATH_B], 863 min_rx_power); 864 865 dm_info->curr_rx_rate = pkt_stat->rate; 866 867 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 868 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 869 870 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 871 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 872 873 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 874 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 875 876 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 877 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 878 dm_info->rssi[path] = rssi; 879 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 880 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 881 882 rx_evm = pkt_stat->rx_evm[path]; 883 884 if (rx_evm < 0) { 885 if (rx_evm == S8_MIN) 886 evm_dbm = 0; 887 else 888 evm_dbm = ((u8)-rx_evm >> 1); 889 } 890 dm_info->rx_evm_dbm[path] = evm_dbm; 891 } 892 } 893 894 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 895 struct rtw_rx_pkt_stat *pkt_stat) 896 { 897 u8 page; 898 899 page = *phy_status & 0xf; 900 901 switch (page) { 902 case 0: 903 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 904 break; 905 case 1: 906 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 907 break; 908 default: 909 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 910 return; 911 } 912 } 913 914 static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 915 struct rtw_rx_pkt_stat *pkt_stat, 916 struct ieee80211_rx_status *rx_status) 917 { 918 struct ieee80211_hdr *hdr; 919 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 920 u8 *phy_status = NULL; 921 922 memset(pkt_stat, 0, sizeof(*pkt_stat)); 923 924 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 925 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 926 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 927 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 928 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 929 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 930 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 931 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 932 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 933 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 934 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 935 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 936 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 937 938 /* drv_info_sz is in unit of 8-bytes */ 939 pkt_stat->drv_info_sz *= 8; 940 941 /* c2h cmd pkt's rx/phy status is not interested */ 942 if (pkt_stat->is_c2h) 943 return; 944 945 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 946 pkt_stat->drv_info_sz); 947 if (pkt_stat->phy_status) { 948 phy_status = rx_desc + desc_sz + pkt_stat->shift; 949 query_phy_status(rtwdev, phy_status, pkt_stat); 950 } 951 952 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 953 } 954 955 static void 956 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 957 { 958 struct rtw_hal *hal = &rtwdev->hal; 959 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 960 static u32 phy_pwr_idx; 961 u8 rate, rate_idx, pwr_index, shift; 962 int j; 963 964 for (j = 0; j < rtw_rate_size[rs]; j++) { 965 rate = rtw_rate_section[rs][j]; 966 pwr_index = hal->tx_pwr_tbl[path][rate]; 967 shift = rate & 0x3; 968 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 969 if (shift == 0x3) { 970 rate_idx = rate & 0xfc; 971 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 972 phy_pwr_idx); 973 phy_pwr_idx = 0; 974 } 975 } 976 } 977 978 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev) 979 { 980 struct rtw_hal *hal = &rtwdev->hal; 981 int rs, path; 982 983 for (path = 0; path < hal->rf_path_num; path++) { 984 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 985 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs); 986 } 987 } 988 989 static bool rtw8822b_check_rf_path(u8 antenna) 990 { 991 switch (antenna) { 992 case BB_PATH_A: 993 case BB_PATH_B: 994 case BB_PATH_AB: 995 return true; 996 default: 997 return false; 998 } 999 } 1000 1001 static int rtw8822b_set_antenna(struct rtw_dev *rtwdev, 1002 u32 antenna_tx, 1003 u32 antenna_rx) 1004 { 1005 struct rtw_hal *hal = &rtwdev->hal; 1006 1007 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", 1008 antenna_tx, antenna_rx); 1009 1010 if (!rtw8822b_check_rf_path(antenna_tx)) { 1011 rtw_info(rtwdev, "unsupport tx path 0x%x\n", antenna_tx); 1012 return -EINVAL; 1013 } 1014 1015 if (!rtw8822b_check_rf_path(antenna_rx)) { 1016 rtw_info(rtwdev, "unsupport rx path 0x%x\n", antenna_rx); 1017 return -EINVAL; 1018 } 1019 1020 hal->antenna_tx = antenna_tx; 1021 hal->antenna_rx = antenna_rx; 1022 1023 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 1024 1025 return 0; 1026 } 1027 1028 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1029 { 1030 u8 ldo_pwr; 1031 1032 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 1033 ldo_pwr = enable ? ldo_pwr | BIT_LDO25_EN : ldo_pwr & ~BIT_LDO25_EN; 1034 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 1035 } 1036 1037 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev) 1038 { 1039 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1040 u32 cck_enable; 1041 u32 cck_fa_cnt; 1042 u32 ofdm_fa_cnt; 1043 u32 crc32_cnt; 1044 u32 cca32_cnt; 1045 1046 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); 1047 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); 1048 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); 1049 1050 dm_info->cck_fa_cnt = cck_fa_cnt; 1051 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1052 dm_info->total_fa_cnt = ofdm_fa_cnt; 1053 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 1054 1055 crc32_cnt = rtw_read32(rtwdev, 0xf04); 1056 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 1057 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1058 crc32_cnt = rtw_read32(rtwdev, 0xf14); 1059 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 1060 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1061 crc32_cnt = rtw_read32(rtwdev, 0xf10); 1062 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 1063 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1064 crc32_cnt = rtw_read32(rtwdev, 0xf0c); 1065 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 1066 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1067 1068 cca32_cnt = rtw_read32(rtwdev, 0xf08); 1069 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 1070 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 1071 if (cck_enable) { 1072 cca32_cnt = rtw_read32(rtwdev, 0xfcc); 1073 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 1074 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 1075 } 1076 1077 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); 1078 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); 1079 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); 1080 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); 1081 rtw_write32_set(rtwdev, 0xb58, BIT(0)); 1082 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); 1083 } 1084 1085 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev) 1086 { 1087 static int do_iqk_cnt; 1088 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 1089 u32 rf_reg, iqk_fail_mask; 1090 int counter; 1091 bool reload; 1092 1093 rtw_fw_do_iqk(rtwdev, ¶); 1094 1095 for (counter = 0; counter < 300; counter++) { 1096 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 1097 if (rf_reg == 0xabcde) 1098 break; 1099 msleep(20); 1100 } 1101 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 1102 1103 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 1104 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 1105 rtw_dbg(rtwdev, RTW_DBG_PHY, 1106 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 1107 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 1108 } 1109 1110 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev) 1111 { 1112 rtw8822b_do_iqk(rtwdev); 1113 } 1114 1115 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev) 1116 { 1117 /* enable TBTT nterrupt */ 1118 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1119 1120 /* BT report packet sample rate */ 1121 /* 0x790[5:0]=0x5 */ 1122 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 1123 1124 /* enable BT counter statistics */ 1125 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1126 1127 /* enable PTA (3-wire function form BT side) */ 1128 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1129 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 1130 1131 /* enable PTA (tx/rx signal form WiFi side) */ 1132 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1133 /* wl tx signal to PTA not case EDCCA */ 1134 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 1135 /* GNT_BT=1 while select both */ 1136 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 1137 } 1138 1139 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev, 1140 u8 ctrl_type, u8 pos_type) 1141 { 1142 struct rtw_coex *coex = &rtwdev->coex; 1143 struct rtw_coex_dm *coex_dm = &coex->dm; 1144 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1145 bool polarity_inverse; 1146 u8 regval = 0; 1147 1148 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status) 1149 return; 1150 1151 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type; 1152 1153 if (coex_rfe->ant_switch_diversity && 1154 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 1155 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 1156 1157 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 1158 1159 switch (ctrl_type) { 1160 default: 1161 case COEX_SWITCH_CTRL_BY_BBSW: 1162 /* 0x4c[23] = 0 */ 1163 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1164 /* 0x4c[24] = 1 */ 1165 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1166 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1167 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); 1168 1169 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 1170 if (coex_rfe->rfe_module_type != 0x4 && 1171 coex_rfe->rfe_module_type != 0x2) 1172 regval = 0x3; 1173 else 1174 regval = (!polarity_inverse ? 0x2 : 0x1); 1175 } else if (pos_type == COEX_SWITCH_TO_WLG) { 1176 regval = (!polarity_inverse ? 0x2 : 0x1); 1177 } else { 1178 regval = (!polarity_inverse ? 0x1 : 0x2); 1179 } 1180 1181 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1182 break; 1183 case COEX_SWITCH_CTRL_BY_PTA: 1184 /* 0x4c[23] = 0 */ 1185 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1186 /* 0x4c[24] = 1 */ 1187 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1188 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1189 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); 1190 1191 regval = (!polarity_inverse ? 0x2 : 0x1); 1192 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1193 break; 1194 case COEX_SWITCH_CTRL_BY_ANTDIV: 1195 /* 0x4c[23] = 0 */ 1196 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1197 /* 0x4c[24] = 1 */ 1198 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1199 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); 1200 break; 1201 case COEX_SWITCH_CTRL_BY_MAC: 1202 /* 0x4c[23] = 1 */ 1203 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); 1204 1205 regval = (!polarity_inverse ? 0x0 : 0x1); 1206 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); 1207 break; 1208 case COEX_SWITCH_CTRL_BY_FW: 1209 /* 0x4c[23] = 0 */ 1210 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1211 /* 0x4c[24] = 1 */ 1212 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1213 break; 1214 case COEX_SWITCH_CTRL_BY_BT: 1215 /* 0x4c[23] = 0 */ 1216 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1217 /* 0x4c[24] = 0 */ 1218 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); 1219 break; 1220 } 1221 } 1222 1223 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1224 { 1225 } 1226 1227 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1228 { 1229 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 1230 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 1231 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 1232 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 1233 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 1234 } 1235 1236 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1237 { 1238 struct rtw_coex *coex = &rtwdev->coex; 1239 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1240 struct rtw_efuse *efuse = &rtwdev->efuse; 1241 bool is_ext_fem = false; 1242 1243 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1244 coex_rfe->ant_switch_polarity = 0; 1245 coex_rfe->ant_switch_diversity = false; 1246 if (coex_rfe->rfe_module_type == 0x12 || 1247 coex_rfe->rfe_module_type == 0x15 || 1248 coex_rfe->rfe_module_type == 0x16) 1249 coex_rfe->ant_switch_exist = false; 1250 else 1251 coex_rfe->ant_switch_exist = true; 1252 1253 if (coex_rfe->rfe_module_type == 2 || 1254 coex_rfe->rfe_module_type == 4) { 1255 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true); 1256 is_ext_fem = true; 1257 } else { 1258 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false); 1259 } 1260 1261 coex_rfe->wlg_at_btg = false; 1262 1263 if (efuse->share_ant && 1264 coex_rfe->ant_switch_exist && !is_ext_fem) 1265 coex_rfe->ant_switch_with_bt = true; 1266 else 1267 coex_rfe->ant_switch_with_bt = false; 1268 1269 /* Ext switch buffer mux */ 1270 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); 1271 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); 1272 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); 1273 1274 /* Disable LTE Coex Function in WiFi side */ 1275 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); 1276 1277 /* BTC_CTT_WL_VS_LTE */ 1278 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1279 1280 /* BTC_CTT_BT_VS_LTE */ 1281 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1282 } 1283 1284 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1285 { 1286 struct rtw_coex *coex = &rtwdev->coex; 1287 struct rtw_coex_dm *coex_dm = &coex->dm; 1288 static const u16 reg_addr[] = {0xc58, 0xe58}; 1289 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; 1290 u8 i, pwr; 1291 1292 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1293 return; 1294 1295 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1296 1297 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1298 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1299 1300 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1301 1302 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) 1303 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); 1304 } 1305 1306 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1307 { 1308 struct rtw_coex *coex = &rtwdev->coex; 1309 struct rtw_coex_dm *coex_dm = &coex->dm; 1310 /* WL Rx Low gain on */ 1311 static const u32 wl_rx_low_gain_on[] = { 1312 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 1313 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 1314 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 1315 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 1316 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 1317 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 1318 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 1319 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, 1320 0x007e0403 1321 }; 1322 1323 /* WL Rx Low gain off */ 1324 static const u32 wl_rx_low_gain_off[] = { 1325 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 1326 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 1327 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 1328 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 1329 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 1330 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 1331 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 1332 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, 1333 0x007e0403 1334 }; 1335 u8 i; 1336 1337 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1338 return; 1339 1340 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1341 1342 if (coex_dm->cur_wl_rx_low_gain_en) { 1343 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1344 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]); 1345 1346 /* set Rx filter corner RCK offset */ 1347 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); 1348 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); 1349 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); 1350 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); 1351 } else { 1352 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1353 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); 1354 1355 /* set Rx filter corner RCK offset */ 1356 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); 1357 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); 1358 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); 1359 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); 1360 } 1361 } 1362 1363 static void rtw8822b_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path, 1364 u8 tx_pwr_idx_offset, 1365 s8 *txagc_idx, u8 *swing_idx) 1366 { 1367 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1368 s8 delta_pwr_idx = dm_info->delta_power_index[path]; 1369 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 1370 u8 swing_lower_bound = 0; 1371 u8 max_tx_pwr_idx_offset = 0xf; 1372 s8 agc_index = 0; 1373 u8 swing_index = dm_info->default_ofdm_index; 1374 1375 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset); 1376 1377 if (delta_pwr_idx >= 0) { 1378 if (delta_pwr_idx <= tx_pwr_idx_offset) { 1379 agc_index = delta_pwr_idx; 1380 swing_index = dm_info->default_ofdm_index; 1381 } else if (delta_pwr_idx > tx_pwr_idx_offset) { 1382 agc_index = tx_pwr_idx_offset; 1383 swing_index = dm_info->default_ofdm_index + 1384 delta_pwr_idx - tx_pwr_idx_offset; 1385 swing_index = min_t(u8, swing_index, swing_upper_bound); 1386 } 1387 } else { 1388 if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) 1389 swing_index = 1390 dm_info->default_ofdm_index + delta_pwr_idx; 1391 else 1392 swing_index = swing_lower_bound; 1393 swing_index = max_t(u8, swing_index, swing_lower_bound); 1394 1395 agc_index = 0; 1396 } 1397 1398 if (swing_index >= RTW_TXSCALE_SIZE) { 1399 rtw_warn(rtwdev, "swing index overflow\n"); 1400 swing_index = RTW_TXSCALE_SIZE - 1; 1401 } 1402 *txagc_idx = agc_index; 1403 *swing_idx = swing_index; 1404 } 1405 1406 static void rtw8822b_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path, 1407 u8 pwr_idx_offset) 1408 { 1409 s8 txagc_idx; 1410 u8 swing_idx; 1411 u32 reg1, reg2; 1412 1413 if (path == RF_PATH_A) { 1414 reg1 = 0xc94; 1415 reg2 = 0xc1c; 1416 } else if (path == RF_PATH_B) { 1417 reg1 = 0xe94; 1418 reg2 = 0xe1c; 1419 } else { 1420 return; 1421 } 1422 1423 rtw8822b_txagc_swing_offset(rtwdev, path, pwr_idx_offset, 1424 &txagc_idx, &swing_idx); 1425 rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx); 1426 rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21), 1427 rtw8822b_txscale_tbl[swing_idx]); 1428 } 1429 1430 static void rtw8822b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1431 { 1432 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1433 u8 pwr_idx_offset, tx_pwr_idx; 1434 u8 channel = rtwdev->hal.current_channel; 1435 u8 band_width = rtwdev->hal.current_band_width; 1436 u8 regd = rtwdev->regd.txpwr_regd; 1437 u8 tx_rate = dm_info->tx_rate; 1438 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1439 1440 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate, 1441 band_width, channel, regd); 1442 1443 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1444 1445 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1446 1447 rtw8822b_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset); 1448 } 1449 1450 static void rtw8822b_phy_pwrtrack_path(struct rtw_dev *rtwdev, 1451 struct rtw_swing_table *swing_table, 1452 u8 path) 1453 { 1454 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1455 u8 power_idx_cur, power_idx_last; 1456 u8 delta; 1457 1458 /* 8822B only has one thermal meter at PATH A */ 1459 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1460 1461 power_idx_last = dm_info->delta_power_index[path]; 1462 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, 1463 path, RF_PATH_A, delta); 1464 1465 /* if delta of power indexes are the same, just skip */ 1466 if (power_idx_cur == power_idx_last) 1467 return; 1468 1469 dm_info->delta_power_index[path] = power_idx_cur; 1470 rtw8822b_pwrtrack_set(rtwdev, path); 1471 } 1472 1473 static void rtw8822b_phy_pwrtrack(struct rtw_dev *rtwdev) 1474 { 1475 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1476 struct rtw_swing_table swing_table; 1477 u8 thermal_value, path; 1478 1479 rtw_phy_config_swing_table(rtwdev, &swing_table); 1480 1481 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) 1482 return; 1483 1484 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1485 1486 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1487 1488 if (dm_info->pwr_trk_init_trigger) 1489 dm_info->pwr_trk_init_trigger = false; 1490 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1491 RF_PATH_A)) 1492 goto iqk; 1493 1494 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 1495 rtw8822b_phy_pwrtrack_path(rtwdev, &swing_table, path); 1496 1497 iqk: 1498 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1499 rtw8822b_do_iqk(rtwdev); 1500 } 1501 1502 static void rtw8822b_pwr_track(struct rtw_dev *rtwdev) 1503 { 1504 struct rtw_efuse *efuse = &rtwdev->efuse; 1505 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1506 1507 if (efuse->power_track_type != 0) 1508 return; 1509 1510 if (!dm_info->pwr_trk_triggered) { 1511 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1512 GENMASK(17, 16), 0x03); 1513 dm_info->pwr_trk_triggered = true; 1514 return; 1515 } 1516 1517 rtw8822b_phy_pwrtrack(rtwdev); 1518 dm_info->pwr_trk_triggered = false; 1519 } 1520 1521 static void rtw8822b_bf_config_bfee_su(struct rtw_dev *rtwdev, 1522 struct rtw_vif *vif, 1523 struct rtw_bfee *bfee, bool enable) 1524 { 1525 if (enable) 1526 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1527 else 1528 rtw_bf_remove_bfee_su(rtwdev, bfee); 1529 } 1530 1531 static void rtw8822b_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1532 struct rtw_vif *vif, 1533 struct rtw_bfee *bfee, bool enable) 1534 { 1535 if (enable) 1536 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1537 else 1538 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1539 } 1540 1541 static void rtw8822b_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1542 struct rtw_bfee *bfee, bool enable) 1543 { 1544 if (bfee->role == RTW_BFEE_SU) 1545 rtw8822b_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1546 else if (bfee->role == RTW_BFEE_MU) 1547 rtw8822b_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1548 else 1549 rtw_warn(rtwdev, "wrong bfee role\n"); 1550 } 1551 1552 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = { 1553 {0x0086, 1554 RTW_PWR_CUT_ALL_MSK, 1555 RTW_PWR_INTF_SDIO_MSK, 1556 RTW_PWR_ADDR_SDIO, 1557 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1558 {0x0086, 1559 RTW_PWR_CUT_ALL_MSK, 1560 RTW_PWR_INTF_SDIO_MSK, 1561 RTW_PWR_ADDR_SDIO, 1562 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1563 {0x004A, 1564 RTW_PWR_CUT_ALL_MSK, 1565 RTW_PWR_INTF_USB_MSK, 1566 RTW_PWR_ADDR_MAC, 1567 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1568 {0x0005, 1569 RTW_PWR_CUT_ALL_MSK, 1570 RTW_PWR_INTF_ALL_MSK, 1571 RTW_PWR_ADDR_MAC, 1572 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1573 {0x0300, 1574 RTW_PWR_CUT_ALL_MSK, 1575 RTW_PWR_INTF_PCI_MSK, 1576 RTW_PWR_ADDR_MAC, 1577 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1578 {0x0301, 1579 RTW_PWR_CUT_ALL_MSK, 1580 RTW_PWR_INTF_PCI_MSK, 1581 RTW_PWR_ADDR_MAC, 1582 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1583 {0xFFFF, 1584 RTW_PWR_CUT_ALL_MSK, 1585 RTW_PWR_INTF_ALL_MSK, 1586 0, 1587 RTW_PWR_CMD_END, 0, 0}, 1588 }; 1589 1590 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = { 1591 {0x0012, 1592 RTW_PWR_CUT_ALL_MSK, 1593 RTW_PWR_INTF_ALL_MSK, 1594 RTW_PWR_ADDR_MAC, 1595 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1596 {0x0012, 1597 RTW_PWR_CUT_ALL_MSK, 1598 RTW_PWR_INTF_ALL_MSK, 1599 RTW_PWR_ADDR_MAC, 1600 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1601 {0x0020, 1602 RTW_PWR_CUT_ALL_MSK, 1603 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1604 RTW_PWR_ADDR_MAC, 1605 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1606 {0x0001, 1607 RTW_PWR_CUT_ALL_MSK, 1608 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1609 RTW_PWR_ADDR_MAC, 1610 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1611 {0x0000, 1612 RTW_PWR_CUT_ALL_MSK, 1613 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1614 RTW_PWR_ADDR_MAC, 1615 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1616 {0x0005, 1617 RTW_PWR_CUT_ALL_MSK, 1618 RTW_PWR_INTF_ALL_MSK, 1619 RTW_PWR_ADDR_MAC, 1620 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1621 {0x0075, 1622 RTW_PWR_CUT_ALL_MSK, 1623 RTW_PWR_INTF_PCI_MSK, 1624 RTW_PWR_ADDR_MAC, 1625 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1626 {0x0006, 1627 RTW_PWR_CUT_ALL_MSK, 1628 RTW_PWR_INTF_ALL_MSK, 1629 RTW_PWR_ADDR_MAC, 1630 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1631 {0x0075, 1632 RTW_PWR_CUT_ALL_MSK, 1633 RTW_PWR_INTF_PCI_MSK, 1634 RTW_PWR_ADDR_MAC, 1635 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1636 {0xFF1A, 1637 RTW_PWR_CUT_ALL_MSK, 1638 RTW_PWR_INTF_USB_MSK, 1639 RTW_PWR_ADDR_MAC, 1640 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1641 {0x0006, 1642 RTW_PWR_CUT_ALL_MSK, 1643 RTW_PWR_INTF_ALL_MSK, 1644 RTW_PWR_ADDR_MAC, 1645 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1646 {0x0005, 1647 RTW_PWR_CUT_ALL_MSK, 1648 RTW_PWR_INTF_ALL_MSK, 1649 RTW_PWR_ADDR_MAC, 1650 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1651 {0x0005, 1652 RTW_PWR_CUT_ALL_MSK, 1653 RTW_PWR_INTF_ALL_MSK, 1654 RTW_PWR_ADDR_MAC, 1655 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1656 {0x10C3, 1657 RTW_PWR_CUT_ALL_MSK, 1658 RTW_PWR_INTF_USB_MSK, 1659 RTW_PWR_ADDR_MAC, 1660 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1661 {0x0005, 1662 RTW_PWR_CUT_ALL_MSK, 1663 RTW_PWR_INTF_ALL_MSK, 1664 RTW_PWR_ADDR_MAC, 1665 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1666 {0x0005, 1667 RTW_PWR_CUT_ALL_MSK, 1668 RTW_PWR_INTF_ALL_MSK, 1669 RTW_PWR_ADDR_MAC, 1670 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1671 {0x0020, 1672 RTW_PWR_CUT_ALL_MSK, 1673 RTW_PWR_INTF_ALL_MSK, 1674 RTW_PWR_ADDR_MAC, 1675 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1676 {0x10A8, 1677 RTW_PWR_CUT_C_MSK, 1678 RTW_PWR_INTF_ALL_MSK, 1679 RTW_PWR_ADDR_MAC, 1680 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1681 {0x10A9, 1682 RTW_PWR_CUT_C_MSK, 1683 RTW_PWR_INTF_ALL_MSK, 1684 RTW_PWR_ADDR_MAC, 1685 RTW_PWR_CMD_WRITE, 0xFF, 0xef}, 1686 {0x10AA, 1687 RTW_PWR_CUT_C_MSK, 1688 RTW_PWR_INTF_ALL_MSK, 1689 RTW_PWR_ADDR_MAC, 1690 RTW_PWR_CMD_WRITE, 0xFF, 0x0c}, 1691 {0x0068, 1692 RTW_PWR_CUT_C_MSK, 1693 RTW_PWR_INTF_SDIO_MSK, 1694 RTW_PWR_ADDR_MAC, 1695 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1696 {0x0029, 1697 RTW_PWR_CUT_ALL_MSK, 1698 RTW_PWR_INTF_ALL_MSK, 1699 RTW_PWR_ADDR_MAC, 1700 RTW_PWR_CMD_WRITE, 0xFF, 0xF9}, 1701 {0x0024, 1702 RTW_PWR_CUT_ALL_MSK, 1703 RTW_PWR_INTF_ALL_MSK, 1704 RTW_PWR_ADDR_MAC, 1705 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1706 {0x0074, 1707 RTW_PWR_CUT_ALL_MSK, 1708 RTW_PWR_INTF_PCI_MSK, 1709 RTW_PWR_ADDR_MAC, 1710 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1711 {0x00AF, 1712 RTW_PWR_CUT_ALL_MSK, 1713 RTW_PWR_INTF_ALL_MSK, 1714 RTW_PWR_ADDR_MAC, 1715 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1716 {0xFFFF, 1717 RTW_PWR_CUT_ALL_MSK, 1718 RTW_PWR_INTF_ALL_MSK, 1719 0, 1720 RTW_PWR_CMD_END, 0, 0}, 1721 }; 1722 1723 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = { 1724 {0x0003, 1725 RTW_PWR_CUT_ALL_MSK, 1726 RTW_PWR_INTF_SDIO_MSK, 1727 RTW_PWR_ADDR_MAC, 1728 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1729 {0x0093, 1730 RTW_PWR_CUT_ALL_MSK, 1731 RTW_PWR_INTF_ALL_MSK, 1732 RTW_PWR_ADDR_MAC, 1733 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1734 {0x001F, 1735 RTW_PWR_CUT_ALL_MSK, 1736 RTW_PWR_INTF_ALL_MSK, 1737 RTW_PWR_ADDR_MAC, 1738 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1739 {0x00EF, 1740 RTW_PWR_CUT_ALL_MSK, 1741 RTW_PWR_INTF_ALL_MSK, 1742 RTW_PWR_ADDR_MAC, 1743 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1744 {0xFF1A, 1745 RTW_PWR_CUT_ALL_MSK, 1746 RTW_PWR_INTF_USB_MSK, 1747 RTW_PWR_ADDR_MAC, 1748 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 1749 {0x0049, 1750 RTW_PWR_CUT_ALL_MSK, 1751 RTW_PWR_INTF_ALL_MSK, 1752 RTW_PWR_ADDR_MAC, 1753 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1754 {0x0006, 1755 RTW_PWR_CUT_ALL_MSK, 1756 RTW_PWR_INTF_ALL_MSK, 1757 RTW_PWR_ADDR_MAC, 1758 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1759 {0x0002, 1760 RTW_PWR_CUT_ALL_MSK, 1761 RTW_PWR_INTF_ALL_MSK, 1762 RTW_PWR_ADDR_MAC, 1763 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1764 {0x10C3, 1765 RTW_PWR_CUT_ALL_MSK, 1766 RTW_PWR_INTF_USB_MSK, 1767 RTW_PWR_ADDR_MAC, 1768 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1769 {0x0005, 1770 RTW_PWR_CUT_ALL_MSK, 1771 RTW_PWR_INTF_ALL_MSK, 1772 RTW_PWR_ADDR_MAC, 1773 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1774 {0x0005, 1775 RTW_PWR_CUT_ALL_MSK, 1776 RTW_PWR_INTF_ALL_MSK, 1777 RTW_PWR_ADDR_MAC, 1778 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1779 {0x0020, 1780 RTW_PWR_CUT_ALL_MSK, 1781 RTW_PWR_INTF_ALL_MSK, 1782 RTW_PWR_ADDR_MAC, 1783 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1784 {0x0000, 1785 RTW_PWR_CUT_ALL_MSK, 1786 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1787 RTW_PWR_ADDR_MAC, 1788 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1789 {0xFFFF, 1790 RTW_PWR_CUT_ALL_MSK, 1791 RTW_PWR_INTF_ALL_MSK, 1792 0, 1793 RTW_PWR_CMD_END, 0, 0}, 1794 }; 1795 1796 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = { 1797 {0x0005, 1798 RTW_PWR_CUT_ALL_MSK, 1799 RTW_PWR_INTF_SDIO_MSK, 1800 RTW_PWR_ADDR_MAC, 1801 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1802 {0x0007, 1803 RTW_PWR_CUT_ALL_MSK, 1804 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1805 RTW_PWR_ADDR_MAC, 1806 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1807 {0x0067, 1808 RTW_PWR_CUT_ALL_MSK, 1809 RTW_PWR_INTF_ALL_MSK, 1810 RTW_PWR_ADDR_MAC, 1811 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1812 {0x0005, 1813 RTW_PWR_CUT_ALL_MSK, 1814 RTW_PWR_INTF_PCI_MSK, 1815 RTW_PWR_ADDR_MAC, 1816 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1817 {0x004A, 1818 RTW_PWR_CUT_ALL_MSK, 1819 RTW_PWR_INTF_USB_MSK, 1820 RTW_PWR_ADDR_MAC, 1821 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1822 {0x0067, 1823 RTW_PWR_CUT_ALL_MSK, 1824 RTW_PWR_INTF_SDIO_MSK, 1825 RTW_PWR_ADDR_MAC, 1826 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1827 {0x0067, 1828 RTW_PWR_CUT_ALL_MSK, 1829 RTW_PWR_INTF_SDIO_MSK, 1830 RTW_PWR_ADDR_MAC, 1831 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1832 {0x004F, 1833 RTW_PWR_CUT_ALL_MSK, 1834 RTW_PWR_INTF_SDIO_MSK, 1835 RTW_PWR_ADDR_MAC, 1836 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1837 {0x0067, 1838 RTW_PWR_CUT_ALL_MSK, 1839 RTW_PWR_INTF_SDIO_MSK, 1840 RTW_PWR_ADDR_MAC, 1841 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1842 {0x0046, 1843 RTW_PWR_CUT_ALL_MSK, 1844 RTW_PWR_INTF_SDIO_MSK, 1845 RTW_PWR_ADDR_MAC, 1846 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1847 {0x0067, 1848 RTW_PWR_CUT_ALL_MSK, 1849 RTW_PWR_INTF_SDIO_MSK, 1850 RTW_PWR_ADDR_MAC, 1851 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1852 {0x0046, 1853 RTW_PWR_CUT_ALL_MSK, 1854 RTW_PWR_INTF_SDIO_MSK, 1855 RTW_PWR_ADDR_MAC, 1856 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1857 {0x0062, 1858 RTW_PWR_CUT_ALL_MSK, 1859 RTW_PWR_INTF_SDIO_MSK, 1860 RTW_PWR_ADDR_MAC, 1861 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1862 {0x0081, 1863 RTW_PWR_CUT_ALL_MSK, 1864 RTW_PWR_INTF_ALL_MSK, 1865 RTW_PWR_ADDR_MAC, 1866 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1867 {0x0005, 1868 RTW_PWR_CUT_ALL_MSK, 1869 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1870 RTW_PWR_ADDR_MAC, 1871 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1872 {0x0086, 1873 RTW_PWR_CUT_ALL_MSK, 1874 RTW_PWR_INTF_SDIO_MSK, 1875 RTW_PWR_ADDR_SDIO, 1876 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1877 {0x0086, 1878 RTW_PWR_CUT_ALL_MSK, 1879 RTW_PWR_INTF_SDIO_MSK, 1880 RTW_PWR_ADDR_SDIO, 1881 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1882 {0x0090, 1883 RTW_PWR_CUT_ALL_MSK, 1884 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1885 RTW_PWR_ADDR_MAC, 1886 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1887 {0x0044, 1888 RTW_PWR_CUT_ALL_MSK, 1889 RTW_PWR_INTF_SDIO_MSK, 1890 RTW_PWR_ADDR_SDIO, 1891 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1892 {0x0040, 1893 RTW_PWR_CUT_ALL_MSK, 1894 RTW_PWR_INTF_SDIO_MSK, 1895 RTW_PWR_ADDR_SDIO, 1896 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1897 {0x0041, 1898 RTW_PWR_CUT_ALL_MSK, 1899 RTW_PWR_INTF_SDIO_MSK, 1900 RTW_PWR_ADDR_SDIO, 1901 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1902 {0x0042, 1903 RTW_PWR_CUT_ALL_MSK, 1904 RTW_PWR_INTF_SDIO_MSK, 1905 RTW_PWR_ADDR_SDIO, 1906 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1907 {0xFFFF, 1908 RTW_PWR_CUT_ALL_MSK, 1909 RTW_PWR_INTF_ALL_MSK, 1910 0, 1911 RTW_PWR_CMD_END, 0, 0}, 1912 }; 1913 1914 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = { 1915 trans_carddis_to_cardemu_8822b, 1916 trans_cardemu_to_act_8822b, 1917 NULL 1918 }; 1919 1920 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = { 1921 trans_act_to_cardemu_8822b, 1922 trans_cardemu_to_carddis_8822b, 1923 NULL 1924 }; 1925 1926 static const struct rtw_intf_phy_para usb2_param_8822b[] = { 1927 {0xFFFF, 0x00, 1928 RTW_IP_SEL_PHY, 1929 RTW_INTF_PHY_CUT_ALL, 1930 RTW_INTF_PHY_PLATFORM_ALL}, 1931 }; 1932 1933 static const struct rtw_intf_phy_para usb3_param_8822b[] = { 1934 {0x0001, 0xA841, 1935 RTW_IP_SEL_PHY, 1936 RTW_INTF_PHY_CUT_D, 1937 RTW_INTF_PHY_PLATFORM_ALL}, 1938 {0xFFFF, 0x0000, 1939 RTW_IP_SEL_PHY, 1940 RTW_INTF_PHY_CUT_ALL, 1941 RTW_INTF_PHY_PLATFORM_ALL}, 1942 }; 1943 1944 static const struct rtw_intf_phy_para pcie_gen1_param_8822b[] = { 1945 {0x0001, 0xA841, 1946 RTW_IP_SEL_PHY, 1947 RTW_INTF_PHY_CUT_C, 1948 RTW_INTF_PHY_PLATFORM_ALL}, 1949 {0x0002, 0x60C6, 1950 RTW_IP_SEL_PHY, 1951 RTW_INTF_PHY_CUT_C, 1952 RTW_INTF_PHY_PLATFORM_ALL}, 1953 {0x0008, 0x3596, 1954 RTW_IP_SEL_PHY, 1955 RTW_INTF_PHY_CUT_C, 1956 RTW_INTF_PHY_PLATFORM_ALL}, 1957 {0x0009, 0x321C, 1958 RTW_IP_SEL_PHY, 1959 RTW_INTF_PHY_CUT_C, 1960 RTW_INTF_PHY_PLATFORM_ALL}, 1961 {0x000A, 0x9623, 1962 RTW_IP_SEL_PHY, 1963 RTW_INTF_PHY_CUT_C, 1964 RTW_INTF_PHY_PLATFORM_ALL}, 1965 {0x0020, 0x94FF, 1966 RTW_IP_SEL_PHY, 1967 RTW_INTF_PHY_CUT_C, 1968 RTW_INTF_PHY_PLATFORM_ALL}, 1969 {0x0021, 0xFFCF, 1970 RTW_IP_SEL_PHY, 1971 RTW_INTF_PHY_CUT_C, 1972 RTW_INTF_PHY_PLATFORM_ALL}, 1973 {0x0026, 0xC006, 1974 RTW_IP_SEL_PHY, 1975 RTW_INTF_PHY_CUT_C, 1976 RTW_INTF_PHY_PLATFORM_ALL}, 1977 {0x0029, 0xFF0E, 1978 RTW_IP_SEL_PHY, 1979 RTW_INTF_PHY_CUT_C, 1980 RTW_INTF_PHY_PLATFORM_ALL}, 1981 {0x002A, 0x1840, 1982 RTW_IP_SEL_PHY, 1983 RTW_INTF_PHY_CUT_C, 1984 RTW_INTF_PHY_PLATFORM_ALL}, 1985 {0xFFFF, 0x0000, 1986 RTW_IP_SEL_PHY, 1987 RTW_INTF_PHY_CUT_ALL, 1988 RTW_INTF_PHY_PLATFORM_ALL}, 1989 }; 1990 1991 static const struct rtw_intf_phy_para pcie_gen2_param_8822b[] = { 1992 {0x0001, 0xA841, 1993 RTW_IP_SEL_PHY, 1994 RTW_INTF_PHY_CUT_C, 1995 RTW_INTF_PHY_PLATFORM_ALL}, 1996 {0x0002, 0x60C6, 1997 RTW_IP_SEL_PHY, 1998 RTW_INTF_PHY_CUT_C, 1999 RTW_INTF_PHY_PLATFORM_ALL}, 2000 {0x0008, 0x3597, 2001 RTW_IP_SEL_PHY, 2002 RTW_INTF_PHY_CUT_C, 2003 RTW_INTF_PHY_PLATFORM_ALL}, 2004 {0x0009, 0x321C, 2005 RTW_IP_SEL_PHY, 2006 RTW_INTF_PHY_CUT_C, 2007 RTW_INTF_PHY_PLATFORM_ALL}, 2008 {0x000A, 0x9623, 2009 RTW_IP_SEL_PHY, 2010 RTW_INTF_PHY_CUT_C, 2011 RTW_INTF_PHY_PLATFORM_ALL}, 2012 {0x0020, 0x94FF, 2013 RTW_IP_SEL_PHY, 2014 RTW_INTF_PHY_CUT_C, 2015 RTW_INTF_PHY_PLATFORM_ALL}, 2016 {0x0021, 0xFFCF, 2017 RTW_IP_SEL_PHY, 2018 RTW_INTF_PHY_CUT_C, 2019 RTW_INTF_PHY_PLATFORM_ALL}, 2020 {0x0026, 0xC006, 2021 RTW_IP_SEL_PHY, 2022 RTW_INTF_PHY_CUT_C, 2023 RTW_INTF_PHY_PLATFORM_ALL}, 2024 {0x0029, 0xFF0E, 2025 RTW_IP_SEL_PHY, 2026 RTW_INTF_PHY_CUT_C, 2027 RTW_INTF_PHY_PLATFORM_ALL}, 2028 {0x002A, 0x3040, 2029 RTW_IP_SEL_PHY, 2030 RTW_INTF_PHY_CUT_C, 2031 RTW_INTF_PHY_PLATFORM_ALL}, 2032 {0xFFFF, 0x0000, 2033 RTW_IP_SEL_PHY, 2034 RTW_INTF_PHY_CUT_ALL, 2035 RTW_INTF_PHY_PLATFORM_ALL}, 2036 }; 2037 2038 static const struct rtw_intf_phy_para_table phy_para_table_8822b = { 2039 .usb2_para = usb2_param_8822b, 2040 .usb3_para = usb3_param_8822b, 2041 .gen1_para = pcie_gen1_param_8822b, 2042 .gen2_para = pcie_gen2_param_8822b, 2043 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b), 2044 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b), 2045 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b), 2046 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b), 2047 }; 2048 2049 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = { 2050 [2] = RTW_DEF_RFE(8822b, 2, 2), 2051 [3] = RTW_DEF_RFE(8822b, 3, 0), 2052 [5] = RTW_DEF_RFE(8822b, 5, 5), 2053 }; 2054 2055 static const struct rtw_hw_reg rtw8822b_dig[] = { 2056 [0] = { .addr = 0xc50, .mask = 0x7f }, 2057 [1] = { .addr = 0xe50, .mask = 0x7f }, 2058 }; 2059 2060 static const struct rtw_page_table page_table_8822b[] = { 2061 {64, 64, 64, 64, 1}, 2062 {64, 64, 64, 64, 1}, 2063 {64, 64, 0, 0, 1}, 2064 {64, 64, 64, 0, 1}, 2065 {64, 64, 64, 64, 1}, 2066 }; 2067 2068 static const struct rtw_rqpn rqpn_table_8822b[] = { 2069 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2070 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2071 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2072 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2073 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2074 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2075 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2076 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2077 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2078 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2079 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2080 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2081 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2082 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2083 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2084 }; 2085 2086 static struct rtw_chip_ops rtw8822b_ops = { 2087 .phy_set_param = rtw8822b_phy_set_param, 2088 .read_efuse = rtw8822b_read_efuse, 2089 .query_rx_desc = rtw8822b_query_rx_desc, 2090 .set_channel = rtw8822b_set_channel, 2091 .mac_init = rtw8822b_mac_init, 2092 .read_rf = rtw_phy_read_rf, 2093 .write_rf = rtw_phy_write_rf_reg_sipi, 2094 .set_tx_power_index = rtw8822b_set_tx_power_index, 2095 .set_antenna = rtw8822b_set_antenna, 2096 .cfg_ldo25 = rtw8822b_cfg_ldo25, 2097 .false_alarm_statistics = rtw8822b_false_alarm_statistics, 2098 .phy_calibration = rtw8822b_phy_calibration, 2099 .pwr_track = rtw8822b_pwr_track, 2100 .config_bfee = rtw8822b_bf_config_bfee, 2101 .set_gid_table = rtw_bf_set_gid_table, 2102 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 2103 2104 .coex_set_init = rtw8822b_coex_cfg_init, 2105 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch, 2106 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix, 2107 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug, 2108 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type, 2109 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power, 2110 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain, 2111 }; 2112 2113 /* Shared-Antenna Coex Table */ 2114 static const struct coex_table_para table_sant_8822b[] = { 2115 {0xffffffff, 0xffffffff}, /* case-0 */ 2116 {0x55555555, 0x55555555}, 2117 {0x66555555, 0x66555555}, 2118 {0xaaaaaaaa, 0xaaaaaaaa}, 2119 {0x5a5a5a5a, 0x5a5a5a5a}, 2120 {0xfafafafa, 0xfafafafa}, /* case-5 */ 2121 {0x6a5a6a5a, 0xaaaaaaaa}, 2122 {0x6a5a56aa, 0x6a5a56aa}, 2123 {0x6a5a5a5a, 0x6a5a5a5a}, 2124 {0x66555555, 0x5a5a5a5a}, 2125 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 2126 {0x66555555, 0xfafafafa}, 2127 {0x66555555, 0x6a5a5aaa}, 2128 {0x66555555, 0x5aaa5aaa}, 2129 {0x66555555, 0xaaaa5aaa}, 2130 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 2131 {0xffff55ff, 0xfafafafa}, 2132 {0xffff55ff, 0x6afa5afa}, 2133 {0xaaffffaa, 0xfafafafa}, 2134 {0xaa5555aa, 0x5a5a5a5a}, 2135 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 2136 {0xaa5555aa, 0xaaaaaaaa}, 2137 {0xffffffff, 0x5a5a5a5a}, 2138 {0xffffffff, 0x6a5a5a5a}, 2139 {0xffffffff, 0x55555555}, 2140 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 2141 {0x55555555, 0x5a5a5a5a}, 2142 {0x55555555, 0xaaaaaaaa}, 2143 {0x55555555, 0x6a5a6a5a}, 2144 {0x66556655, 0x66556655} 2145 }; 2146 2147 /* Non-Shared-Antenna Coex Table */ 2148 static const struct coex_table_para table_nsant_8822b[] = { 2149 {0xffffffff, 0xffffffff}, /* case-100 */ 2150 {0x55555555, 0x55555555}, 2151 {0x66555555, 0x66555555}, 2152 {0xaaaaaaaa, 0xaaaaaaaa}, 2153 {0x5a5a5a5a, 0x5a5a5a5a}, 2154 {0xfafafafa, 0xfafafafa}, /* case-105 */ 2155 {0x5afa5afa, 0x5afa5afa}, 2156 {0x55555555, 0xfafafafa}, 2157 {0x66555555, 0xfafafafa}, 2158 {0x66555555, 0x5a5a5a5a}, 2159 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 2160 {0x66555555, 0xaaaaaaaa}, 2161 {0xffff55ff, 0xfafafafa}, 2162 {0xffff55ff, 0x5afa5afa}, 2163 {0xffff55ff, 0xaaaaaaaa}, 2164 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 2165 {0xaaffffaa, 0x5afa5afa}, 2166 {0xaaffffaa, 0xaaaaaaaa}, 2167 {0xffffffff, 0xfafafafa}, 2168 {0xffffffff, 0x5afa5afa}, 2169 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 2170 {0x55ff55ff, 0x5afa5afa}, 2171 {0x55ff55ff, 0xaaaaaaaa}, 2172 {0x55ff55ff, 0x55ff55ff} 2173 }; 2174 2175 /* Shared-Antenna TDMA */ 2176 static const struct coex_tdma_para tdma_sant_8822b[] = { 2177 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2178 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 2179 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2180 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2181 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2182 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2183 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2184 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2185 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2186 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2187 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2188 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2189 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2190 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2191 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2192 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 2193 { {0x51, 0x45, 0x03, 0x10, 0x10} }, 2194 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2195 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2196 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2197 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 2198 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2199 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2200 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2201 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 2202 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 2203 { {0x51, 0x08, 0x03, 0x10, 0x50} } 2204 }; 2205 2206 /* Non-Shared-Antenna TDMA */ 2207 static const struct coex_tdma_para tdma_nsant_8822b[] = { 2208 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 2209 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 2210 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2211 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2212 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2213 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2214 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2215 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2216 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2217 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2218 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2219 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2220 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2221 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2222 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2223 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2224 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2225 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2226 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2227 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2228 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ 2229 }; 2230 2231 /* rssi in percentage % (dbm = % - 100) */ 2232 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30}; 2233 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30}; 2234 static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} }; 2235 2236 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2237 static const struct coex_rf_para rf_para_tx_8822b[] = { 2238 {0, 0, false, 7}, /* for normal */ 2239 {0, 16, false, 7}, /* for WL-CPT */ 2240 {4, 0, true, 1}, 2241 {3, 6, true, 1}, 2242 {2, 9, true, 1}, 2243 {1, 13, true, 1} 2244 }; 2245 2246 static const struct coex_rf_para rf_para_rx_8822b[] = { 2247 {0, 0, false, 7}, /* for normal */ 2248 {0, 16, false, 7}, /* for WL-CPT */ 2249 {4, 0, true, 1}, 2250 {3, 6, true, 1}, 2251 {2, 9, true, 1}, 2252 {1, 13, true, 1} 2253 }; 2254 2255 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b)); 2256 2257 static const u8 2258 rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2259 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2260 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2261 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2262 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2263 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2264 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2265 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2266 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2267 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2268 }; 2269 2270 static const u8 2271 rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2272 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2273 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2274 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2275 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2276 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2277 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2278 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2279 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2280 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2281 }; 2282 2283 static const u8 2284 rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2285 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2286 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2287 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2288 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2289 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2290 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2291 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2292 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2293 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2294 }; 2295 2296 static const u8 2297 rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2298 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2299 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2300 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2301 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2302 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2303 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2304 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2305 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2306 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2307 }; 2308 2309 static const u8 rtw8822b_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 2310 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2311 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2312 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2313 }; 2314 2315 static const u8 rtw8822b_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 2316 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2317 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2318 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2319 }; 2320 2321 static const u8 rtw8822b_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 2322 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2323 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2324 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2325 }; 2326 2327 static const u8 rtw8822b_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 2328 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2329 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2330 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2331 }; 2332 2333 static const u8 rtw8822b_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 2334 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2335 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2336 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2337 }; 2338 2339 static const u8 rtw8822b_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 2340 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2341 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2342 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2343 }; 2344 2345 static const u8 rtw8822b_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 2346 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2347 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2348 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2349 }; 2350 2351 static const u8 rtw8822b_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 2352 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2353 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2354 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2355 }; 2356 2357 static const struct rtw_pwr_track_tbl rtw8822b_rtw_pwr_track_tbl = { 2358 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 2359 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 2360 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 2361 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 2362 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 2363 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 2364 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 2365 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 2366 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 2367 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 2368 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 2369 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 2370 .pwrtrk_2gb_n = rtw8822b_pwrtrk_2gb_n, 2371 .pwrtrk_2gb_p = rtw8822b_pwrtrk_2gb_p, 2372 .pwrtrk_2ga_n = rtw8822b_pwrtrk_2ga_n, 2373 .pwrtrk_2ga_p = rtw8822b_pwrtrk_2ga_p, 2374 .pwrtrk_2g_cckb_n = rtw8822b_pwrtrk_2g_cck_b_n, 2375 .pwrtrk_2g_cckb_p = rtw8822b_pwrtrk_2g_cck_b_p, 2376 .pwrtrk_2g_ccka_n = rtw8822b_pwrtrk_2g_cck_a_n, 2377 .pwrtrk_2g_ccka_p = rtw8822b_pwrtrk_2g_cck_a_p, 2378 }; 2379 2380 static const struct rtw_reg_domain coex_info_hw_regs_8822b[] = { 2381 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2382 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2383 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2384 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2385 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2386 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8}, 2387 {0, 0, RTW_REG_DOMAIN_NL}, 2388 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2389 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2390 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2391 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2392 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2393 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2394 {0, 0, RTW_REG_DOMAIN_NL}, 2395 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 2396 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 2397 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2398 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2399 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 2400 {0, 0, RTW_REG_DOMAIN_NL}, 2401 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2402 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2403 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2404 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2405 }; 2406 2407 struct rtw_chip_info rtw8822b_hw_spec = { 2408 .ops = &rtw8822b_ops, 2409 .id = RTW_CHIP_TYPE_8822B, 2410 .fw_name = "rtw88/rtw8822b_fw.bin", 2411 .tx_pkt_desc_sz = 48, 2412 .tx_buf_desc_sz = 16, 2413 .rx_pkt_desc_sz = 24, 2414 .rx_buf_desc_sz = 8, 2415 .phy_efuse_size = 1024, 2416 .log_efuse_size = 768, 2417 .ptct_efuse_size = 96, 2418 .txff_size = 262144, 2419 .rxff_size = 24576, 2420 .txgi_factor = 1, 2421 .is_pwr_by_rate_dec = true, 2422 .max_power_index = 0x3f, 2423 .csi_buf_pg_num = 0, 2424 .band = RTW_BAND_2G | RTW_BAND_5G, 2425 .page_size = 128, 2426 .dig_min = 0x1c, 2427 .ht_supported = true, 2428 .vht_supported = true, 2429 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 2430 .sys_func_en = 0xDC, 2431 .pwr_on_seq = card_enable_flow_8822b, 2432 .pwr_off_seq = card_disable_flow_8822b, 2433 .page_table = page_table_8822b, 2434 .rqpn_table = rqpn_table_8822b, 2435 .intf_table = &phy_para_table_8822b, 2436 .dig = rtw8822b_dig, 2437 .rf_base_addr = {0x2800, 0x2c00}, 2438 .rf_sipi_addr = {0xc90, 0xe90}, 2439 .mac_tbl = &rtw8822b_mac_tbl, 2440 .agc_tbl = &rtw8822b_agc_tbl, 2441 .bb_tbl = &rtw8822b_bb_tbl, 2442 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl}, 2443 .rfe_defs = rtw8822b_rfe_defs, 2444 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs), 2445 .pwr_track_tbl = &rtw8822b_rtw_pwr_track_tbl, 2446 .iqk_threshold = 8, 2447 .bfer_su_max_num = 2, 2448 .bfer_mu_max_num = 1, 2449 2450 .coex_para_ver = 0x19062706, 2451 .bt_desired_ver = 0x6, 2452 .scbd_support = true, 2453 .new_scbd10_def = false, 2454 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2455 .bt_rssi_type = COEX_BTRSSI_RATIO, 2456 .ant_isolation = 15, 2457 .rssi_tolerance = 2, 2458 .wl_rssi_step = wl_rssi_step_8822b, 2459 .bt_rssi_step = bt_rssi_step_8822b, 2460 .table_sant_num = ARRAY_SIZE(table_sant_8822b), 2461 .table_sant = table_sant_8822b, 2462 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b), 2463 .table_nsant = table_nsant_8822b, 2464 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b), 2465 .tdma_sant = tdma_sant_8822b, 2466 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b), 2467 .tdma_nsant = tdma_nsant_8822b, 2468 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b), 2469 .wl_rf_para_tx = rf_para_tx_8822b, 2470 .wl_rf_para_rx = rf_para_rx_8822b, 2471 .bt_afh_span_bw20 = 0x24, 2472 .bt_afh_span_bw40 = 0x36, 2473 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b), 2474 .afh_5g = afh_5g_8822b, 2475 2476 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822b), 2477 .coex_info_hw_regs = coex_info_hw_regs_8822b, 2478 }; 2479 EXPORT_SYMBOL(rtw8822b_hw_spec); 2480 2481 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin"); 2482