1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822b.h" 13 #include "rtw8822b_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "bf.h" 18 #include "regd.h" 19 20 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 21 u8 rx_path, bool is_tx2_path); 22 23 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8822b_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static void rtw8822bu_efuse_parsing(struct rtw_efuse *efuse, 30 struct rtw8822b_efuse *map) 31 { 32 ether_addr_copy(efuse->addr, map->u.mac_addr); 33 } 34 35 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 36 { 37 struct rtw_efuse *efuse = &rtwdev->efuse; 38 struct rtw8822b_efuse *map; 39 int i; 40 41 map = (struct rtw8822b_efuse *)log_map; 42 43 efuse->rfe_option = map->rfe_option; 44 efuse->rf_board_option = map->rf_board_option; 45 efuse->crystal_cap = map->xtal_k; 46 efuse->pa_type_2g = map->pa_type; 47 efuse->pa_type_5g = map->pa_type; 48 efuse->lna_type_2g = map->lna_type_2g[0]; 49 efuse->lna_type_5g = map->lna_type_5g[0]; 50 efuse->channel_plan = map->channel_plan; 51 efuse->country_code[0] = map->country_code[0]; 52 efuse->country_code[1] = map->country_code[1]; 53 efuse->bt_setting = map->rf_bt_setting; 54 efuse->regd = map->rf_board_option & 0x7; 55 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; 56 efuse->thermal_meter_k = map->thermal_meter; 57 58 for (i = 0; i < 4; i++) 59 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 60 61 switch (rtw_hci_type(rtwdev)) { 62 case RTW_HCI_TYPE_PCIE: 63 rtw8822be_efuse_parsing(efuse, map); 64 break; 65 case RTW_HCI_TYPE_USB: 66 rtw8822bu_efuse_parsing(efuse, map); 67 break; 68 default: 69 /* unsupported now */ 70 return -ENOTSUPP; 71 } 72 73 return 0; 74 } 75 76 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev) 77 { 78 /* chip top mux */ 79 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); 80 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); 81 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); 82 83 /* from s0 or s1 */ 84 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); 85 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); 86 87 /* input or output */ 88 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); 89 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); 90 } 91 92 #define RTW_TXSCALE_SIZE 37 93 static const u32 rtw8822b_txscale_tbl[RTW_TXSCALE_SIZE] = { 94 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 95 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 96 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 97 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 98 }; 99 100 static u8 rtw8822b_get_swing_index(struct rtw_dev *rtwdev) 101 { 102 u8 i = 0; 103 u32 swing, table_value; 104 105 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); 106 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { 107 table_value = rtw8822b_txscale_tbl[i]; 108 if (swing == table_value) 109 break; 110 } 111 112 return i; 113 } 114 115 static void rtw8822b_pwrtrack_init(struct rtw_dev *rtwdev) 116 { 117 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 118 u8 swing_idx = rtw8822b_get_swing_index(rtwdev); 119 u8 path; 120 121 if (swing_idx >= RTW_TXSCALE_SIZE) 122 dm_info->default_ofdm_index = 24; 123 else 124 dm_info->default_ofdm_index = swing_idx; 125 126 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 127 ewma_thermal_init(&dm_info->avg_thermal[path]); 128 dm_info->delta_power_index[path] = 0; 129 } 130 dm_info->pwr_trk_triggered = false; 131 dm_info->pwr_trk_init_trigger = true; 132 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 133 } 134 135 static void rtw8822b_phy_bf_init(struct rtw_dev *rtwdev) 136 { 137 rtw_bf_phy_init(rtwdev); 138 /* Grouping bitmap parameters */ 139 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 140 } 141 142 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev) 143 { 144 struct rtw_hal *hal = &rtwdev->hal; 145 u8 crystal_cap; 146 bool is_tx2_path; 147 148 /* power on BB/RF domain */ 149 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 150 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 151 rtw_write8_set(rtwdev, REG_RF_CTRL, 152 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 153 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 154 155 /* pre init before header files config */ 156 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 157 158 rtw_phy_load_tables(rtwdev); 159 160 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 161 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); 162 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); 163 164 /* post init after header files config */ 165 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 166 167 is_tx2_path = false; 168 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 169 is_tx2_path); 170 rtw_phy_init(rtwdev); 171 172 rtw8822b_phy_rfe_init(rtwdev); 173 rtw8822b_pwrtrack_init(rtwdev); 174 175 rtw8822b_phy_bf_init(rtwdev); 176 } 177 178 #define WLAN_SLOT_TIME 0x09 179 #define WLAN_PIFS_TIME 0x19 180 #define WLAN_SIFS_CCK_CONT_TX 0xA 181 #define WLAN_SIFS_OFDM_CONT_TX 0xE 182 #define WLAN_SIFS_CCK_TRX 0x10 183 #define WLAN_SIFS_OFDM_TRX 0x10 184 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ 185 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ 186 #define WLAN_RDG_NAV 0x05 187 #define WLAN_TXOP_NAV 0x1B 188 #define WLAN_CCK_RX_TSF 0x30 189 #define WLAN_OFDM_RX_TSF 0x30 190 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 191 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 192 #define WLAN_DRV_EARLY_INT 0x04 193 #define WLAN_BCN_DMA_TIME 0x02 194 195 #define WLAN_RX_FILTER0 0x0FFFFFFF 196 #define WLAN_RX_FILTER2 0xFFFF 197 #define WLAN_RCR_CFG 0xE400220E 198 #define WLAN_RXPKT_MAX_SZ 12288 199 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 200 201 #define WLAN_AMPDU_MAX_TIME 0x70 202 #define WLAN_RTS_LEN_TH 0xFF 203 #define WLAN_RTS_TX_TIME_TH 0x08 204 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 205 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 206 #define FAST_EDCA_VO_TH 0x06 207 #define FAST_EDCA_VI_TH 0x06 208 #define FAST_EDCA_BE_TH 0x06 209 #define FAST_EDCA_BK_TH 0x06 210 #define WLAN_BAR_RETRY_LIMIT 0x01 211 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 212 213 #define WLAN_TX_FUNC_CFG1 0x30 214 #define WLAN_TX_FUNC_CFG2 0x30 215 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 216 #define WLAN_MAC_OPT_LB_FUNC1 0x80 217 #define WLAN_MAC_OPT_FUNC2 0xb0810041 218 219 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 220 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 221 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 222 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 223 224 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 225 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 226 227 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 228 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 229 230 static int rtw8822b_mac_init(struct rtw_dev *rtwdev) 231 { 232 u32 value32; 233 234 /* protocol configuration */ 235 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD); 236 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 237 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 238 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 239 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 240 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 241 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 242 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 243 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 244 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 245 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 246 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 247 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 248 /* EDCA configuration */ 249 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 250 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 251 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 252 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 253 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 254 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 255 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 256 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 257 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 258 /* Set beacon cotnrol - enable TSF and other related functions */ 259 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 260 /* Set send beacon related registers */ 261 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 262 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 263 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 264 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 265 /* WMAC configuration */ 266 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 267 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 268 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 269 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 270 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 271 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 272 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 273 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 274 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 275 BIT_DIS_CHK_VHTSIGB_CRC); 276 277 return 0; 278 } 279 280 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel) 281 { 282 struct rtw_hal *hal = &rtwdev->hal; 283 284 if (IS_CH_2G_BAND(channel)) { 285 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); 286 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 287 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); 288 } else { 289 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); 290 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 291 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); 292 } 293 294 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 295 296 if (hal->antenna_rx == BB_PATH_AB || 297 hal->antenna_tx == BB_PATH_AB) { 298 /* 2TX or 2RX */ 299 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 300 } else if (hal->antenna_rx == hal->antenna_tx) { 301 /* TXA+RXA or TXB+RXB */ 302 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 303 } else { 304 /* TXB+RXA or TXA+RXB */ 305 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 306 } 307 } 308 309 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel) 310 { 311 struct rtw_hal *hal = &rtwdev->hal; 312 313 if (IS_CH_2G_BAND(channel)) { 314 /* signal source */ 315 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); 316 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 317 } else { 318 /* signal source */ 319 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); 320 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 321 } 322 323 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 324 325 if (IS_CH_2G_BAND(channel)) { 326 if (hal->antenna_rx == BB_PATH_AB || 327 hal->antenna_tx == BB_PATH_AB) { 328 /* 2TX or 2RX */ 329 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 330 } else if (hal->antenna_rx == hal->antenna_tx) { 331 /* TXA+RXA or TXB+RXB */ 332 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 333 } else { 334 /* TXB+RXA or TXA+RXB */ 335 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 336 } 337 } else { 338 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); 339 } 340 } 341 342 enum { 343 CCUT_IDX_1R_2G, 344 CCUT_IDX_2R_2G, 345 CCUT_IDX_1R_5G, 346 CCUT_IDX_2R_5G, 347 CCUT_IDX_NR, 348 }; 349 350 struct cca_ccut { 351 u32 reg82c[CCUT_IDX_NR]; 352 u32 reg830[CCUT_IDX_NR]; 353 u32 reg838[CCUT_IDX_NR]; 354 }; 355 356 static const struct cca_ccut cca_ifem_ccut = { 357 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ 358 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 359 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/ 360 }; 361 362 static const struct cca_ccut cca_efem_ccut = { 363 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ 364 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/ 365 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ 366 }; 367 368 static const struct cca_ccut cca_ifem_ccut_ext = { 369 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ 370 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 371 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/ 372 }; 373 374 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col, 375 u32 *reg82c, u32 *reg830, u32 *reg838) 376 { 377 *reg82c = cca_ccut->reg82c[col]; 378 *reg830 = cca_ccut->reg830[col]; 379 *reg838 = cca_ccut->reg838[col]; 380 } 381 382 struct rtw8822b_rfe_info { 383 const struct cca_ccut *cca_ccut_2g; 384 const struct cca_ccut *cca_ccut_5g; 385 enum rtw_rfe_fem fem; 386 bool ifem_ext; 387 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel); 388 }; 389 390 #define I2GE5G_CCUT(set_ch) { \ 391 .cca_ccut_2g = &cca_ifem_ccut, \ 392 .cca_ccut_5g = &cca_efem_ccut, \ 393 .fem = RTW_RFE_IFEM2G_EFEM5G, \ 394 .ifem_ext = false, \ 395 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 396 } 397 #define IFEM_EXT_CCUT(set_ch) { \ 398 .cca_ccut_2g = &cca_ifem_ccut_ext, \ 399 .cca_ccut_5g = &cca_ifem_ccut_ext, \ 400 .fem = RTW_RFE_IFEM, \ 401 .ifem_ext = true, \ 402 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 403 } 404 405 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = { 406 [2] = I2GE5G_CCUT(efem), 407 [3] = IFEM_EXT_CCUT(ifem), 408 [5] = IFEM_EXT_CCUT(ifem), 409 }; 410 411 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw, 412 const struct rtw8822b_rfe_info *rfe_info) 413 { 414 struct rtw_hal *hal = &rtwdev->hal; 415 struct rtw_efuse *efuse = &rtwdev->efuse; 416 const struct cca_ccut *cca_ccut; 417 u8 col; 418 u32 reg82c, reg830, reg838; 419 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; 420 421 if (IS_CH_2G_BAND(channel)) { 422 cca_ccut = rfe_info->cca_ccut_2g; 423 424 if (hal->antenna_rx == BB_PATH_A || 425 hal->antenna_rx == BB_PATH_B) 426 col = CCUT_IDX_1R_2G; 427 else 428 col = CCUT_IDX_2R_2G; 429 } else { 430 cca_ccut = rfe_info->cca_ccut_5g; 431 432 if (hal->antenna_rx == BB_PATH_A || 433 hal->antenna_rx == BB_PATH_B) 434 col = CCUT_IDX_1R_5G; 435 else 436 col = CCUT_IDX_2R_5G; 437 } 438 439 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838); 440 441 switch (rfe_info->fem) { 442 case RTW_RFE_IFEM: 443 default: 444 is_ifem_cca = true; 445 if (rfe_info->ifem_ext) 446 is_rfe_type = true; 447 break; 448 case RTW_RFE_EFEM: 449 is_efem_cca = true; 450 break; 451 case RTW_RFE_IFEM2G_EFEM5G: 452 if (IS_CH_2G_BAND(channel)) 453 is_ifem_cca = true; 454 else 455 is_efem_cca = true; 456 break; 457 } 458 459 if (is_ifem_cca) { 460 if ((hal->cut_version == RTW_CHIP_VER_CUT_B && 461 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) && 462 bw == RTW_CHANNEL_WIDTH_40) || 463 (!is_rfe_type && col == CCUT_IDX_2R_5G && 464 bw == RTW_CHANNEL_WIDTH_40) || 465 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G)) 466 reg830 = 0x79a0ea28; 467 } 468 469 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c); 470 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830); 471 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838); 472 473 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B)) 474 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); 475 476 if (bw == RTW_CHANNEL_WIDTH_20 && IS_CH_5G_BAND_MID(channel)) 477 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); 478 } 479 480 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 481 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; 482 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 483 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 484 0x6, 0x5, 0x0, 0x0, 0x7}; 485 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 486 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; 487 488 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 489 { 490 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 491 #define RF18_BAND_2G (0) 492 #define RF18_BAND_5G (BIT(16) | BIT(8)) 493 #define RF18_CHANNEL_MASK (MASKBYTE0) 494 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 495 #define RF18_RFSI_GE_CH80 (BIT(17)) 496 #define RF18_RFSI_GT_CH144 (BIT(18)) 497 #define RF18_BW_MASK (BIT(11) | BIT(10)) 498 #define RF18_BW_20M (BIT(11) | BIT(10)) 499 #define RF18_BW_40M (BIT(11)) 500 #define RF18_BW_80M (BIT(10)) 501 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) 502 503 struct rtw_hal *hal = &rtwdev->hal; 504 u32 rf_reg18, rf_reg_be; 505 506 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 507 508 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 509 RF18_BW_MASK); 510 511 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 512 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 513 if (channel > 144) 514 rf_reg18 |= RF18_RFSI_GT_CH144; 515 else if (channel >= 80) 516 rf_reg18 |= RF18_RFSI_GE_CH80; 517 518 switch (bw) { 519 case RTW_CHANNEL_WIDTH_5: 520 case RTW_CHANNEL_WIDTH_10: 521 case RTW_CHANNEL_WIDTH_20: 522 default: 523 rf_reg18 |= RF18_BW_20M; 524 break; 525 case RTW_CHANNEL_WIDTH_40: 526 rf_reg18 |= RF18_BW_40M; 527 break; 528 case RTW_CHANNEL_WIDTH_80: 529 rf_reg18 |= RF18_BW_80M; 530 break; 531 } 532 533 if (IS_CH_2G_BAND(channel)) 534 rf_reg_be = 0x0; 535 else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 536 rf_reg_be = low_band[(channel - 36) >> 1]; 537 else if (IS_CH_5G_BAND_3(channel)) 538 rf_reg_be = middle_band[(channel - 100) >> 1]; 539 else if (IS_CH_5G_BAND_4(channel)) 540 rf_reg_be = high_band[(channel - 149) >> 1]; 541 else 542 goto err; 543 544 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be); 545 546 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ 547 if (channel == 144) 548 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); 549 else 550 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); 551 552 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 553 if (hal->rf_type > RF_1T1R) 554 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); 555 556 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 557 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 558 559 return; 560 561 err: 562 WARN_ON(1); 563 } 564 565 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev) 566 { 567 struct rtw_hal *hal = &rtwdev->hal; 568 u32 igi; 569 570 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); 571 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); 572 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); 573 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); 574 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); 575 576 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); 577 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 578 hal->antenna_rx | (hal->antenna_rx << 4)); 579 } 580 581 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 582 { 583 if (bw == RTW_CHANNEL_WIDTH_40) { 584 /* RX DFIR for BW40 */ 585 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); 586 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); 587 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 588 } else if (bw == RTW_CHANNEL_WIDTH_80) { 589 /* RX DFIR for BW80 */ 590 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 591 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 592 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 593 } else { 594 /* RX DFIR for BW20, BW10 and BW5*/ 595 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 596 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 597 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 598 } 599 } 600 601 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 602 u8 primary_ch_idx) 603 { 604 struct rtw_efuse *efuse = &rtwdev->efuse; 605 u8 rfe_option = efuse->rfe_option; 606 u32 val32; 607 608 if (IS_CH_2G_BAND(channel)) { 609 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 610 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 611 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 612 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 613 614 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); 615 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 616 if (channel == 14) { 617 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); 618 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 619 } else { 620 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); 621 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); 622 } 623 624 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); 625 } else if (IS_CH_5G_BAND(channel)) { 626 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 627 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 628 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 629 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); 630 631 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 632 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); 633 else if (IS_CH_5G_BAND_3(channel)) 634 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); 635 else if (IS_CH_5G_BAND_4(channel)) 636 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); 637 638 if (IS_CH_5G_BAND_1(channel)) 639 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 640 else if (IS_CH_5G_BAND_2(channel)) 641 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 642 else if (channel >= 100 && channel <= 116) 643 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 644 else if (channel >= 118 && channel <= 177) 645 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 646 647 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); 648 } 649 650 switch (bw) { 651 case RTW_CHANNEL_WIDTH_20: 652 default: 653 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 654 val32 &= 0xFFCFFC00; 655 val32 |= (RTW_CHANNEL_WIDTH_20); 656 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 657 658 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 659 break; 660 case RTW_CHANNEL_WIDTH_40: 661 if (primary_ch_idx == RTW_SC_20_UPPER) 662 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 663 else 664 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 665 666 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 667 val32 &= 0xFF3FF300; 668 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); 669 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 670 671 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 672 break; 673 case RTW_CHANNEL_WIDTH_80: 674 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 675 val32 &= 0xFCEFCF00; 676 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); 677 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 678 679 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 680 681 if (rfe_option == 2 || rfe_option == 3) { 682 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); 683 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); 684 } 685 break; 686 case RTW_CHANNEL_WIDTH_5: 687 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 688 val32 &= 0xEFEEFE00; 689 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); 690 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 691 692 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 694 break; 695 case RTW_CHANNEL_WIDTH_10: 696 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 697 val32 &= 0xEFFEFF00; 698 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); 699 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 700 701 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 702 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 703 break; 704 } 705 } 706 707 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 708 u8 primary_chan_idx) 709 { 710 struct rtw_efuse *efuse = &rtwdev->efuse; 711 const struct rtw8822b_rfe_info *rfe_info; 712 713 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 714 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 715 return; 716 717 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 718 719 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 720 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 721 rtw8822b_set_channel_rf(rtwdev, channel, bw); 722 rtw8822b_set_channel_rxdfir(rtwdev, bw); 723 rtw8822b_toggle_igi(rtwdev); 724 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info); 725 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel); 726 } 727 728 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 729 u8 rx_path, bool is_tx2_path) 730 { 731 struct rtw_efuse *efuse = &rtwdev->efuse; 732 const struct rtw8822b_rfe_info *rfe_info; 733 u8 ch = rtwdev->hal.current_channel; 734 u8 tx_path_sel, rx_path_sel; 735 int counter; 736 737 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 738 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 739 return; 740 741 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 742 743 if ((tx_path | rx_path) & BB_PATH_A) 744 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); 745 else 746 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); 747 748 if ((tx_path | rx_path) & BB_PATH_B) 749 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); 750 else 751 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); 752 753 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); 754 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); 755 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); 756 757 if (tx_path & BB_PATH_A) { 758 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); 759 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); 760 } else if (tx_path & BB_PATH_B) { 761 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); 762 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); 763 } 764 765 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B) 766 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); 767 else 768 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); 769 770 tx_path_sel = (tx_path << 4) | tx_path; 771 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel); 772 773 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) { 774 if (is_tx2_path || rtwdev->mp_mode) { 775 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); 776 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); 777 } 778 } 779 780 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); 781 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); 782 783 if (rx_path & BB_PATH_A) 784 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); 785 else if (rx_path & BB_PATH_B) 786 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); 787 788 rx_path_sel = (rx_path << 4) | rx_path; 789 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); 790 791 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 792 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); 793 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); 794 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); 795 } else { 796 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); 797 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); 798 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); 799 } 800 801 for (counter = 100; counter > 0; counter--) { 802 u32 rf_reg33; 803 804 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 805 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 806 807 udelay(2); 808 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); 809 810 if (rf_reg33 == 0x00001) 811 break; 812 } 813 814 if (WARN(counter <= 0, "write RF mode table fail\n")) 815 return; 816 817 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 818 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 819 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); 820 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); 821 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 822 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 823 824 rtw8822b_toggle_igi(rtwdev); 825 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info); 826 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch); 827 } 828 829 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 830 struct rtw_rx_pkt_stat *pkt_stat) 831 { 832 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 833 s8 min_rx_power = -120; 834 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 835 836 /* 8822B uses only 1 antenna to RX CCK rates */ 837 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110; 838 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 839 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 840 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 841 min_rx_power); 842 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 843 } 844 845 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 846 struct rtw_rx_pkt_stat *pkt_stat) 847 { 848 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 849 u8 rxsc, bw; 850 s8 min_rx_power = -120; 851 s8 rx_evm; 852 u8 evm_dbm = 0; 853 u8 rssi; 854 int path; 855 856 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 857 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 858 else 859 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 860 861 if (rxsc >= 1 && rxsc <= 8) 862 bw = RTW_CHANNEL_WIDTH_20; 863 else if (rxsc >= 9 && rxsc <= 12) 864 bw = RTW_CHANNEL_WIDTH_40; 865 else if (rxsc >= 13) 866 bw = RTW_CHANNEL_WIDTH_80; 867 else 868 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 869 870 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 871 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 872 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 873 pkt_stat->bw = bw; 874 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 875 pkt_stat->rx_power[RF_PATH_B], 876 min_rx_power); 877 878 dm_info->curr_rx_rate = pkt_stat->rate; 879 880 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 881 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 882 883 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 884 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 885 886 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 887 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 888 889 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 890 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 891 dm_info->rssi[path] = rssi; 892 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 893 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 894 895 rx_evm = pkt_stat->rx_evm[path]; 896 897 if (rx_evm < 0) { 898 if (rx_evm == S8_MIN) 899 evm_dbm = 0; 900 else 901 evm_dbm = ((u8)-rx_evm >> 1); 902 } 903 dm_info->rx_evm_dbm[path] = evm_dbm; 904 } 905 } 906 907 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 908 struct rtw_rx_pkt_stat *pkt_stat) 909 { 910 u8 page; 911 912 page = *phy_status & 0xf; 913 914 switch (page) { 915 case 0: 916 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 917 break; 918 case 1: 919 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 920 break; 921 default: 922 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 923 return; 924 } 925 } 926 927 static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 928 struct rtw_rx_pkt_stat *pkt_stat, 929 struct ieee80211_rx_status *rx_status) 930 { 931 struct ieee80211_hdr *hdr; 932 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 933 u8 *phy_status = NULL; 934 935 memset(pkt_stat, 0, sizeof(*pkt_stat)); 936 937 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 938 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 939 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 940 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 941 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 942 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 943 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 944 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 945 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 946 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 947 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 948 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 949 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 950 951 /* drv_info_sz is in unit of 8-bytes */ 952 pkt_stat->drv_info_sz *= 8; 953 954 /* c2h cmd pkt's rx/phy status is not interested */ 955 if (pkt_stat->is_c2h) 956 return; 957 958 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 959 pkt_stat->drv_info_sz); 960 if (pkt_stat->phy_status) { 961 phy_status = rx_desc + desc_sz + pkt_stat->shift; 962 query_phy_status(rtwdev, phy_status, pkt_stat); 963 } 964 965 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 966 } 967 968 static void 969 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 970 { 971 struct rtw_hal *hal = &rtwdev->hal; 972 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 973 static u32 phy_pwr_idx; 974 u8 rate, rate_idx, pwr_index, shift; 975 int j; 976 977 for (j = 0; j < rtw_rate_size[rs]; j++) { 978 rate = rtw_rate_section[rs][j]; 979 pwr_index = hal->tx_pwr_tbl[path][rate]; 980 shift = rate & 0x3; 981 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 982 if (shift == 0x3) { 983 rate_idx = rate & 0xfc; 984 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 985 phy_pwr_idx); 986 phy_pwr_idx = 0; 987 } 988 } 989 } 990 991 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev) 992 { 993 struct rtw_hal *hal = &rtwdev->hal; 994 int rs, path; 995 996 for (path = 0; path < hal->rf_path_num; path++) { 997 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 998 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs); 999 } 1000 } 1001 1002 static bool rtw8822b_check_rf_path(u8 antenna) 1003 { 1004 switch (antenna) { 1005 case BB_PATH_A: 1006 case BB_PATH_B: 1007 case BB_PATH_AB: 1008 return true; 1009 default: 1010 return false; 1011 } 1012 } 1013 1014 static int rtw8822b_set_antenna(struct rtw_dev *rtwdev, 1015 u32 antenna_tx, 1016 u32 antenna_rx) 1017 { 1018 struct rtw_hal *hal = &rtwdev->hal; 1019 1020 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", 1021 antenna_tx, antenna_rx); 1022 1023 if (!rtw8822b_check_rf_path(antenna_tx)) { 1024 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 1025 return -EINVAL; 1026 } 1027 1028 if (!rtw8822b_check_rf_path(antenna_rx)) { 1029 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 1030 return -EINVAL; 1031 } 1032 1033 hal->antenna_tx = antenna_tx; 1034 hal->antenna_rx = antenna_rx; 1035 1036 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 1037 1038 return 0; 1039 } 1040 1041 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1042 { 1043 u8 ldo_pwr; 1044 1045 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 1046 ldo_pwr = enable ? ldo_pwr | BIT_LDO25_EN : ldo_pwr & ~BIT_LDO25_EN; 1047 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 1048 } 1049 1050 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev) 1051 { 1052 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1053 u32 cck_enable; 1054 u32 cck_fa_cnt; 1055 u32 ofdm_fa_cnt; 1056 u32 crc32_cnt; 1057 u32 cca32_cnt; 1058 1059 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); 1060 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); 1061 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); 1062 1063 dm_info->cck_fa_cnt = cck_fa_cnt; 1064 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1065 dm_info->total_fa_cnt = ofdm_fa_cnt; 1066 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 1067 1068 crc32_cnt = rtw_read32(rtwdev, 0xf04); 1069 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 1070 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1071 crc32_cnt = rtw_read32(rtwdev, 0xf14); 1072 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 1073 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1074 crc32_cnt = rtw_read32(rtwdev, 0xf10); 1075 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 1076 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1077 crc32_cnt = rtw_read32(rtwdev, 0xf0c); 1078 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 1079 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1080 1081 cca32_cnt = rtw_read32(rtwdev, 0xf08); 1082 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 1083 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 1084 if (cck_enable) { 1085 cca32_cnt = rtw_read32(rtwdev, 0xfcc); 1086 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 1087 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 1088 } 1089 1090 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); 1091 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); 1092 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); 1093 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); 1094 rtw_write32_set(rtwdev, 0xb58, BIT(0)); 1095 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); 1096 } 1097 1098 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev) 1099 { 1100 static int do_iqk_cnt; 1101 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 1102 u32 rf_reg, iqk_fail_mask; 1103 int counter; 1104 bool reload; 1105 1106 rtw_fw_do_iqk(rtwdev, ¶); 1107 1108 for (counter = 0; counter < 300; counter++) { 1109 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 1110 if (rf_reg == 0xabcde) 1111 break; 1112 msleep(20); 1113 } 1114 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 1115 1116 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 1117 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 1118 rtw_dbg(rtwdev, RTW_DBG_PHY, 1119 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 1120 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 1121 } 1122 1123 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev) 1124 { 1125 rtw8822b_do_iqk(rtwdev); 1126 } 1127 1128 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev) 1129 { 1130 /* enable TBTT nterrupt */ 1131 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1132 1133 /* BT report packet sample rate */ 1134 /* 0x790[5:0]=0x5 */ 1135 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 1136 1137 /* enable BT counter statistics */ 1138 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1139 1140 /* enable PTA (3-wire function form BT side) */ 1141 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1142 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 1143 1144 /* enable PTA (tx/rx signal form WiFi side) */ 1145 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1146 /* wl tx signal to PTA not case EDCCA */ 1147 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 1148 /* GNT_BT=1 while select both */ 1149 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 1150 } 1151 1152 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev, 1153 u8 ctrl_type, u8 pos_type) 1154 { 1155 struct rtw_coex *coex = &rtwdev->coex; 1156 struct rtw_coex_dm *coex_dm = &coex->dm; 1157 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1158 bool polarity_inverse; 1159 u8 regval = 0; 1160 1161 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status) 1162 return; 1163 1164 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type; 1165 1166 if (coex_rfe->ant_switch_diversity && 1167 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 1168 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 1169 1170 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 1171 1172 switch (ctrl_type) { 1173 default: 1174 case COEX_SWITCH_CTRL_BY_BBSW: 1175 /* 0x4c[23] = 0 */ 1176 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1177 /* 0x4c[24] = 1 */ 1178 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1179 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1180 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); 1181 1182 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 1183 if (coex_rfe->rfe_module_type != 0x4 && 1184 coex_rfe->rfe_module_type != 0x2) 1185 regval = 0x3; 1186 else 1187 regval = (!polarity_inverse ? 0x2 : 0x1); 1188 } else if (pos_type == COEX_SWITCH_TO_WLG) { 1189 regval = (!polarity_inverse ? 0x2 : 0x1); 1190 } else { 1191 regval = (!polarity_inverse ? 0x1 : 0x2); 1192 } 1193 1194 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1195 break; 1196 case COEX_SWITCH_CTRL_BY_PTA: 1197 /* 0x4c[23] = 0 */ 1198 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1199 /* 0x4c[24] = 1 */ 1200 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1201 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1202 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); 1203 1204 regval = (!polarity_inverse ? 0x2 : 0x1); 1205 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1206 break; 1207 case COEX_SWITCH_CTRL_BY_ANTDIV: 1208 /* 0x4c[23] = 0 */ 1209 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1210 /* 0x4c[24] = 1 */ 1211 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1212 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); 1213 break; 1214 case COEX_SWITCH_CTRL_BY_MAC: 1215 /* 0x4c[23] = 1 */ 1216 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); 1217 1218 regval = (!polarity_inverse ? 0x0 : 0x1); 1219 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); 1220 break; 1221 case COEX_SWITCH_CTRL_BY_FW: 1222 /* 0x4c[23] = 0 */ 1223 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1224 /* 0x4c[24] = 1 */ 1225 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1226 break; 1227 case COEX_SWITCH_CTRL_BY_BT: 1228 /* 0x4c[23] = 0 */ 1229 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1230 /* 0x4c[24] = 0 */ 1231 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); 1232 break; 1233 } 1234 } 1235 1236 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1237 { 1238 } 1239 1240 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1241 { 1242 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 1243 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 1244 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 1245 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 1246 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 1247 } 1248 1249 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1250 { 1251 struct rtw_coex *coex = &rtwdev->coex; 1252 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1253 struct rtw_efuse *efuse = &rtwdev->efuse; 1254 bool is_ext_fem = false; 1255 1256 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1257 coex_rfe->ant_switch_polarity = 0; 1258 coex_rfe->ant_switch_diversity = false; 1259 if (coex_rfe->rfe_module_type == 0x12 || 1260 coex_rfe->rfe_module_type == 0x15 || 1261 coex_rfe->rfe_module_type == 0x16) 1262 coex_rfe->ant_switch_exist = false; 1263 else 1264 coex_rfe->ant_switch_exist = true; 1265 1266 if (coex_rfe->rfe_module_type == 2 || 1267 coex_rfe->rfe_module_type == 4) { 1268 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true); 1269 is_ext_fem = true; 1270 } else { 1271 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false); 1272 } 1273 1274 coex_rfe->wlg_at_btg = false; 1275 1276 if (efuse->share_ant && 1277 coex_rfe->ant_switch_exist && !is_ext_fem) 1278 coex_rfe->ant_switch_with_bt = true; 1279 else 1280 coex_rfe->ant_switch_with_bt = false; 1281 1282 /* Ext switch buffer mux */ 1283 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); 1284 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); 1285 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); 1286 1287 /* Disable LTE Coex Function in WiFi side */ 1288 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); 1289 1290 /* BTC_CTT_WL_VS_LTE */ 1291 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1292 1293 /* BTC_CTT_BT_VS_LTE */ 1294 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1295 } 1296 1297 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1298 { 1299 struct rtw_coex *coex = &rtwdev->coex; 1300 struct rtw_coex_dm *coex_dm = &coex->dm; 1301 static const u16 reg_addr[] = {0xc58, 0xe58}; 1302 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; 1303 u8 i, pwr; 1304 1305 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1306 return; 1307 1308 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1309 1310 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1311 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1312 1313 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1314 1315 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) 1316 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); 1317 } 1318 1319 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1320 { 1321 struct rtw_coex *coex = &rtwdev->coex; 1322 struct rtw_coex_dm *coex_dm = &coex->dm; 1323 /* WL Rx Low gain on */ 1324 static const u32 wl_rx_low_gain_on[] = { 1325 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 1326 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 1327 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 1328 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 1329 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 1330 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 1331 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 1332 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, 1333 0x007e0403 1334 }; 1335 1336 /* WL Rx Low gain off */ 1337 static const u32 wl_rx_low_gain_off[] = { 1338 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 1339 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 1340 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 1341 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 1342 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 1343 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 1344 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 1345 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, 1346 0x007e0403 1347 }; 1348 u8 i; 1349 1350 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1351 return; 1352 1353 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1354 1355 if (coex_dm->cur_wl_rx_low_gain_en) { 1356 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); 1357 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1358 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]); 1359 1360 /* set Rx filter corner RCK offset */ 1361 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); 1362 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); 1363 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); 1364 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); 1365 } else { 1366 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); 1367 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1368 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); 1369 1370 /* set Rx filter corner RCK offset */ 1371 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); 1372 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); 1373 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); 1374 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); 1375 } 1376 } 1377 1378 static void rtw8822b_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path, 1379 u8 tx_pwr_idx_offset, 1380 s8 *txagc_idx, u8 *swing_idx) 1381 { 1382 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1383 s8 delta_pwr_idx = dm_info->delta_power_index[path]; 1384 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 1385 u8 swing_lower_bound = 0; 1386 u8 max_tx_pwr_idx_offset = 0xf; 1387 s8 agc_index = 0; 1388 u8 swing_index = dm_info->default_ofdm_index; 1389 1390 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset); 1391 1392 if (delta_pwr_idx >= 0) { 1393 if (delta_pwr_idx <= tx_pwr_idx_offset) { 1394 agc_index = delta_pwr_idx; 1395 swing_index = dm_info->default_ofdm_index; 1396 } else if (delta_pwr_idx > tx_pwr_idx_offset) { 1397 agc_index = tx_pwr_idx_offset; 1398 swing_index = dm_info->default_ofdm_index + 1399 delta_pwr_idx - tx_pwr_idx_offset; 1400 swing_index = min_t(u8, swing_index, swing_upper_bound); 1401 } 1402 } else { 1403 if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) 1404 swing_index = 1405 dm_info->default_ofdm_index + delta_pwr_idx; 1406 else 1407 swing_index = swing_lower_bound; 1408 swing_index = max_t(u8, swing_index, swing_lower_bound); 1409 1410 agc_index = 0; 1411 } 1412 1413 if (swing_index >= RTW_TXSCALE_SIZE) { 1414 rtw_warn(rtwdev, "swing index overflow\n"); 1415 swing_index = RTW_TXSCALE_SIZE - 1; 1416 } 1417 *txagc_idx = agc_index; 1418 *swing_idx = swing_index; 1419 } 1420 1421 static void rtw8822b_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path, 1422 u8 pwr_idx_offset) 1423 { 1424 s8 txagc_idx; 1425 u8 swing_idx; 1426 u32 reg1, reg2; 1427 1428 if (path == RF_PATH_A) { 1429 reg1 = 0xc94; 1430 reg2 = 0xc1c; 1431 } else if (path == RF_PATH_B) { 1432 reg1 = 0xe94; 1433 reg2 = 0xe1c; 1434 } else { 1435 return; 1436 } 1437 1438 rtw8822b_txagc_swing_offset(rtwdev, path, pwr_idx_offset, 1439 &txagc_idx, &swing_idx); 1440 rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx); 1441 rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21), 1442 rtw8822b_txscale_tbl[swing_idx]); 1443 } 1444 1445 static void rtw8822b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1446 { 1447 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1448 u8 pwr_idx_offset, tx_pwr_idx; 1449 u8 channel = rtwdev->hal.current_channel; 1450 u8 band_width = rtwdev->hal.current_band_width; 1451 u8 regd = rtw_regd_get(rtwdev); 1452 u8 tx_rate = dm_info->tx_rate; 1453 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1454 1455 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate, 1456 band_width, channel, regd); 1457 1458 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1459 1460 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1461 1462 rtw8822b_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset); 1463 } 1464 1465 static void rtw8822b_phy_pwrtrack_path(struct rtw_dev *rtwdev, 1466 struct rtw_swing_table *swing_table, 1467 u8 path) 1468 { 1469 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1470 u8 power_idx_cur, power_idx_last; 1471 u8 delta; 1472 1473 /* 8822B only has one thermal meter at PATH A */ 1474 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1475 1476 power_idx_last = dm_info->delta_power_index[path]; 1477 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, 1478 path, RF_PATH_A, delta); 1479 1480 /* if delta of power indexes are the same, just skip */ 1481 if (power_idx_cur == power_idx_last) 1482 return; 1483 1484 dm_info->delta_power_index[path] = power_idx_cur; 1485 rtw8822b_pwrtrack_set(rtwdev, path); 1486 } 1487 1488 static void rtw8822b_phy_pwrtrack(struct rtw_dev *rtwdev) 1489 { 1490 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1491 struct rtw_swing_table swing_table; 1492 u8 thermal_value, path; 1493 1494 rtw_phy_config_swing_table(rtwdev, &swing_table); 1495 1496 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) 1497 return; 1498 1499 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1500 1501 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1502 1503 if (dm_info->pwr_trk_init_trigger) 1504 dm_info->pwr_trk_init_trigger = false; 1505 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1506 RF_PATH_A)) 1507 goto iqk; 1508 1509 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 1510 rtw8822b_phy_pwrtrack_path(rtwdev, &swing_table, path); 1511 1512 iqk: 1513 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1514 rtw8822b_do_iqk(rtwdev); 1515 } 1516 1517 static void rtw8822b_pwr_track(struct rtw_dev *rtwdev) 1518 { 1519 struct rtw_efuse *efuse = &rtwdev->efuse; 1520 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1521 1522 if (efuse->power_track_type != 0) 1523 return; 1524 1525 if (!dm_info->pwr_trk_triggered) { 1526 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1527 GENMASK(17, 16), 0x03); 1528 dm_info->pwr_trk_triggered = true; 1529 return; 1530 } 1531 1532 rtw8822b_phy_pwrtrack(rtwdev); 1533 dm_info->pwr_trk_triggered = false; 1534 } 1535 1536 static void rtw8822b_bf_config_bfee_su(struct rtw_dev *rtwdev, 1537 struct rtw_vif *vif, 1538 struct rtw_bfee *bfee, bool enable) 1539 { 1540 if (enable) 1541 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1542 else 1543 rtw_bf_remove_bfee_su(rtwdev, bfee); 1544 } 1545 1546 static void rtw8822b_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1547 struct rtw_vif *vif, 1548 struct rtw_bfee *bfee, bool enable) 1549 { 1550 if (enable) 1551 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1552 else 1553 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1554 } 1555 1556 static void rtw8822b_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1557 struct rtw_bfee *bfee, bool enable) 1558 { 1559 if (bfee->role == RTW_BFEE_SU) 1560 rtw8822b_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1561 else if (bfee->role == RTW_BFEE_MU) 1562 rtw8822b_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1563 else 1564 rtw_warn(rtwdev, "wrong bfee role\n"); 1565 } 1566 1567 static void rtw8822b_adaptivity_init(struct rtw_dev *rtwdev) 1568 { 1569 rtw_phy_set_edcca_th(rtwdev, RTW8822B_EDCCA_MAX, RTW8822B_EDCCA_MAX); 1570 1571 /* mac edcca state setting */ 1572 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA); 1573 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN); 1574 rtw_write32_mask(rtwdev, REG_EDCCA_SOURCE, BIT_SOURCE_OPTION, 1575 RTW8822B_EDCCA_SRC_DEF); 1576 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0); 1577 1578 /* edcca decision opt */ 1579 rtw_write32_set(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION); 1580 } 1581 1582 static void rtw8822b_adaptivity(struct rtw_dev *rtwdev) 1583 { 1584 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1585 s8 l2h, h2l; 1586 u8 igi; 1587 1588 igi = dm_info->igi_history[0]; 1589 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) { 1590 l2h = max_t(s8, igi + EDCCA_IGI_L2H_DIFF, EDCCA_TH_L2H_LB); 1591 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL; 1592 } else { 1593 l2h = min_t(s8, igi, dm_info->l2h_th_ini); 1594 h2l = l2h - EDCCA_L2H_H2L_DIFF; 1595 } 1596 1597 rtw_phy_set_edcca_th(rtwdev, l2h, h2l); 1598 } 1599 1600 static void rtw8822b_fill_txdesc_checksum(struct rtw_dev *rtwdev, 1601 struct rtw_tx_pkt_info *pkt_info, 1602 u8 *txdesc) 1603 { 1604 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ 1605 1606 fill_txdesc_checksum_common(txdesc, words); 1607 } 1608 1609 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = { 1610 {0x0086, 1611 RTW_PWR_CUT_ALL_MSK, 1612 RTW_PWR_INTF_SDIO_MSK, 1613 RTW_PWR_ADDR_SDIO, 1614 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1615 {0x0086, 1616 RTW_PWR_CUT_ALL_MSK, 1617 RTW_PWR_INTF_SDIO_MSK, 1618 RTW_PWR_ADDR_SDIO, 1619 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1620 {0x004A, 1621 RTW_PWR_CUT_ALL_MSK, 1622 RTW_PWR_INTF_USB_MSK, 1623 RTW_PWR_ADDR_MAC, 1624 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1625 {0x0005, 1626 RTW_PWR_CUT_ALL_MSK, 1627 RTW_PWR_INTF_ALL_MSK, 1628 RTW_PWR_ADDR_MAC, 1629 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1630 {0x0300, 1631 RTW_PWR_CUT_ALL_MSK, 1632 RTW_PWR_INTF_PCI_MSK, 1633 RTW_PWR_ADDR_MAC, 1634 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1635 {0x0301, 1636 RTW_PWR_CUT_ALL_MSK, 1637 RTW_PWR_INTF_PCI_MSK, 1638 RTW_PWR_ADDR_MAC, 1639 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1640 {0xFFFF, 1641 RTW_PWR_CUT_ALL_MSK, 1642 RTW_PWR_INTF_ALL_MSK, 1643 0, 1644 RTW_PWR_CMD_END, 0, 0}, 1645 }; 1646 1647 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = { 1648 {0x0012, 1649 RTW_PWR_CUT_ALL_MSK, 1650 RTW_PWR_INTF_ALL_MSK, 1651 RTW_PWR_ADDR_MAC, 1652 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1653 {0x0012, 1654 RTW_PWR_CUT_ALL_MSK, 1655 RTW_PWR_INTF_ALL_MSK, 1656 RTW_PWR_ADDR_MAC, 1657 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1658 {0x0020, 1659 RTW_PWR_CUT_ALL_MSK, 1660 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1661 RTW_PWR_ADDR_MAC, 1662 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1663 {0x0001, 1664 RTW_PWR_CUT_ALL_MSK, 1665 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1666 RTW_PWR_ADDR_MAC, 1667 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1668 {0x0000, 1669 RTW_PWR_CUT_ALL_MSK, 1670 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1671 RTW_PWR_ADDR_MAC, 1672 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1673 {0x0005, 1674 RTW_PWR_CUT_ALL_MSK, 1675 RTW_PWR_INTF_ALL_MSK, 1676 RTW_PWR_ADDR_MAC, 1677 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1678 {0x0075, 1679 RTW_PWR_CUT_ALL_MSK, 1680 RTW_PWR_INTF_PCI_MSK, 1681 RTW_PWR_ADDR_MAC, 1682 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1683 {0x0006, 1684 RTW_PWR_CUT_ALL_MSK, 1685 RTW_PWR_INTF_ALL_MSK, 1686 RTW_PWR_ADDR_MAC, 1687 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1688 {0x0075, 1689 RTW_PWR_CUT_ALL_MSK, 1690 RTW_PWR_INTF_PCI_MSK, 1691 RTW_PWR_ADDR_MAC, 1692 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1693 {0xFF1A, 1694 RTW_PWR_CUT_ALL_MSK, 1695 RTW_PWR_INTF_USB_MSK, 1696 RTW_PWR_ADDR_MAC, 1697 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1698 {0x0006, 1699 RTW_PWR_CUT_ALL_MSK, 1700 RTW_PWR_INTF_ALL_MSK, 1701 RTW_PWR_ADDR_MAC, 1702 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1703 {0x0005, 1704 RTW_PWR_CUT_ALL_MSK, 1705 RTW_PWR_INTF_ALL_MSK, 1706 RTW_PWR_ADDR_MAC, 1707 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1708 {0x0005, 1709 RTW_PWR_CUT_ALL_MSK, 1710 RTW_PWR_INTF_ALL_MSK, 1711 RTW_PWR_ADDR_MAC, 1712 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1713 {0x10C3, 1714 RTW_PWR_CUT_ALL_MSK, 1715 RTW_PWR_INTF_USB_MSK, 1716 RTW_PWR_ADDR_MAC, 1717 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1718 {0x0005, 1719 RTW_PWR_CUT_ALL_MSK, 1720 RTW_PWR_INTF_ALL_MSK, 1721 RTW_PWR_ADDR_MAC, 1722 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1723 {0x0005, 1724 RTW_PWR_CUT_ALL_MSK, 1725 RTW_PWR_INTF_ALL_MSK, 1726 RTW_PWR_ADDR_MAC, 1727 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1728 {0x0020, 1729 RTW_PWR_CUT_ALL_MSK, 1730 RTW_PWR_INTF_ALL_MSK, 1731 RTW_PWR_ADDR_MAC, 1732 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1733 {0x10A8, 1734 RTW_PWR_CUT_C_MSK, 1735 RTW_PWR_INTF_ALL_MSK, 1736 RTW_PWR_ADDR_MAC, 1737 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1738 {0x10A9, 1739 RTW_PWR_CUT_C_MSK, 1740 RTW_PWR_INTF_ALL_MSK, 1741 RTW_PWR_ADDR_MAC, 1742 RTW_PWR_CMD_WRITE, 0xFF, 0xef}, 1743 {0x10AA, 1744 RTW_PWR_CUT_C_MSK, 1745 RTW_PWR_INTF_ALL_MSK, 1746 RTW_PWR_ADDR_MAC, 1747 RTW_PWR_CMD_WRITE, 0xFF, 0x0c}, 1748 {0x0068, 1749 RTW_PWR_CUT_C_MSK, 1750 RTW_PWR_INTF_SDIO_MSK, 1751 RTW_PWR_ADDR_MAC, 1752 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1753 {0x0029, 1754 RTW_PWR_CUT_ALL_MSK, 1755 RTW_PWR_INTF_ALL_MSK, 1756 RTW_PWR_ADDR_MAC, 1757 RTW_PWR_CMD_WRITE, 0xFF, 0xF9}, 1758 {0x0024, 1759 RTW_PWR_CUT_ALL_MSK, 1760 RTW_PWR_INTF_ALL_MSK, 1761 RTW_PWR_ADDR_MAC, 1762 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1763 {0x0074, 1764 RTW_PWR_CUT_ALL_MSK, 1765 RTW_PWR_INTF_PCI_MSK, 1766 RTW_PWR_ADDR_MAC, 1767 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1768 {0x00AF, 1769 RTW_PWR_CUT_ALL_MSK, 1770 RTW_PWR_INTF_ALL_MSK, 1771 RTW_PWR_ADDR_MAC, 1772 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1773 {0xFFFF, 1774 RTW_PWR_CUT_ALL_MSK, 1775 RTW_PWR_INTF_ALL_MSK, 1776 0, 1777 RTW_PWR_CMD_END, 0, 0}, 1778 }; 1779 1780 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = { 1781 {0x0003, 1782 RTW_PWR_CUT_ALL_MSK, 1783 RTW_PWR_INTF_SDIO_MSK, 1784 RTW_PWR_ADDR_MAC, 1785 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1786 {0x0093, 1787 RTW_PWR_CUT_ALL_MSK, 1788 RTW_PWR_INTF_ALL_MSK, 1789 RTW_PWR_ADDR_MAC, 1790 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1791 {0x001F, 1792 RTW_PWR_CUT_ALL_MSK, 1793 RTW_PWR_INTF_ALL_MSK, 1794 RTW_PWR_ADDR_MAC, 1795 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1796 {0x00EF, 1797 RTW_PWR_CUT_ALL_MSK, 1798 RTW_PWR_INTF_ALL_MSK, 1799 RTW_PWR_ADDR_MAC, 1800 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1801 {0xFF1A, 1802 RTW_PWR_CUT_ALL_MSK, 1803 RTW_PWR_INTF_USB_MSK, 1804 RTW_PWR_ADDR_MAC, 1805 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 1806 {0x0049, 1807 RTW_PWR_CUT_ALL_MSK, 1808 RTW_PWR_INTF_ALL_MSK, 1809 RTW_PWR_ADDR_MAC, 1810 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1811 {0x0006, 1812 RTW_PWR_CUT_ALL_MSK, 1813 RTW_PWR_INTF_ALL_MSK, 1814 RTW_PWR_ADDR_MAC, 1815 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1816 {0x0002, 1817 RTW_PWR_CUT_ALL_MSK, 1818 RTW_PWR_INTF_ALL_MSK, 1819 RTW_PWR_ADDR_MAC, 1820 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1821 {0x10C3, 1822 RTW_PWR_CUT_ALL_MSK, 1823 RTW_PWR_INTF_USB_MSK, 1824 RTW_PWR_ADDR_MAC, 1825 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1826 {0x0005, 1827 RTW_PWR_CUT_ALL_MSK, 1828 RTW_PWR_INTF_ALL_MSK, 1829 RTW_PWR_ADDR_MAC, 1830 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1831 {0x0005, 1832 RTW_PWR_CUT_ALL_MSK, 1833 RTW_PWR_INTF_ALL_MSK, 1834 RTW_PWR_ADDR_MAC, 1835 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1836 {0x0020, 1837 RTW_PWR_CUT_ALL_MSK, 1838 RTW_PWR_INTF_ALL_MSK, 1839 RTW_PWR_ADDR_MAC, 1840 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1841 {0x0000, 1842 RTW_PWR_CUT_ALL_MSK, 1843 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1844 RTW_PWR_ADDR_MAC, 1845 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1846 {0xFFFF, 1847 RTW_PWR_CUT_ALL_MSK, 1848 RTW_PWR_INTF_ALL_MSK, 1849 0, 1850 RTW_PWR_CMD_END, 0, 0}, 1851 }; 1852 1853 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = { 1854 {0x0005, 1855 RTW_PWR_CUT_ALL_MSK, 1856 RTW_PWR_INTF_SDIO_MSK, 1857 RTW_PWR_ADDR_MAC, 1858 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1859 {0x0007, 1860 RTW_PWR_CUT_ALL_MSK, 1861 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1862 RTW_PWR_ADDR_MAC, 1863 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1864 {0x0067, 1865 RTW_PWR_CUT_ALL_MSK, 1866 RTW_PWR_INTF_ALL_MSK, 1867 RTW_PWR_ADDR_MAC, 1868 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1869 {0x0005, 1870 RTW_PWR_CUT_ALL_MSK, 1871 RTW_PWR_INTF_PCI_MSK, 1872 RTW_PWR_ADDR_MAC, 1873 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1874 {0x004A, 1875 RTW_PWR_CUT_ALL_MSK, 1876 RTW_PWR_INTF_USB_MSK, 1877 RTW_PWR_ADDR_MAC, 1878 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1879 {0x0067, 1880 RTW_PWR_CUT_ALL_MSK, 1881 RTW_PWR_INTF_SDIO_MSK, 1882 RTW_PWR_ADDR_MAC, 1883 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1884 {0x0067, 1885 RTW_PWR_CUT_ALL_MSK, 1886 RTW_PWR_INTF_SDIO_MSK, 1887 RTW_PWR_ADDR_MAC, 1888 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1889 {0x004F, 1890 RTW_PWR_CUT_ALL_MSK, 1891 RTW_PWR_INTF_SDIO_MSK, 1892 RTW_PWR_ADDR_MAC, 1893 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1894 {0x0067, 1895 RTW_PWR_CUT_ALL_MSK, 1896 RTW_PWR_INTF_SDIO_MSK, 1897 RTW_PWR_ADDR_MAC, 1898 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1899 {0x0046, 1900 RTW_PWR_CUT_ALL_MSK, 1901 RTW_PWR_INTF_SDIO_MSK, 1902 RTW_PWR_ADDR_MAC, 1903 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1904 {0x0067, 1905 RTW_PWR_CUT_ALL_MSK, 1906 RTW_PWR_INTF_SDIO_MSK, 1907 RTW_PWR_ADDR_MAC, 1908 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1909 {0x0046, 1910 RTW_PWR_CUT_ALL_MSK, 1911 RTW_PWR_INTF_SDIO_MSK, 1912 RTW_PWR_ADDR_MAC, 1913 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1914 {0x0062, 1915 RTW_PWR_CUT_ALL_MSK, 1916 RTW_PWR_INTF_SDIO_MSK, 1917 RTW_PWR_ADDR_MAC, 1918 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1919 {0x0081, 1920 RTW_PWR_CUT_ALL_MSK, 1921 RTW_PWR_INTF_ALL_MSK, 1922 RTW_PWR_ADDR_MAC, 1923 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1924 {0x0005, 1925 RTW_PWR_CUT_ALL_MSK, 1926 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1927 RTW_PWR_ADDR_MAC, 1928 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1929 {0x0086, 1930 RTW_PWR_CUT_ALL_MSK, 1931 RTW_PWR_INTF_SDIO_MSK, 1932 RTW_PWR_ADDR_SDIO, 1933 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1934 {0x0086, 1935 RTW_PWR_CUT_ALL_MSK, 1936 RTW_PWR_INTF_SDIO_MSK, 1937 RTW_PWR_ADDR_SDIO, 1938 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1939 {0x0090, 1940 RTW_PWR_CUT_ALL_MSK, 1941 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1942 RTW_PWR_ADDR_MAC, 1943 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1944 {0x0044, 1945 RTW_PWR_CUT_ALL_MSK, 1946 RTW_PWR_INTF_SDIO_MSK, 1947 RTW_PWR_ADDR_SDIO, 1948 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1949 {0x0040, 1950 RTW_PWR_CUT_ALL_MSK, 1951 RTW_PWR_INTF_SDIO_MSK, 1952 RTW_PWR_ADDR_SDIO, 1953 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1954 {0x0041, 1955 RTW_PWR_CUT_ALL_MSK, 1956 RTW_PWR_INTF_SDIO_MSK, 1957 RTW_PWR_ADDR_SDIO, 1958 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1959 {0x0042, 1960 RTW_PWR_CUT_ALL_MSK, 1961 RTW_PWR_INTF_SDIO_MSK, 1962 RTW_PWR_ADDR_SDIO, 1963 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1964 {0xFFFF, 1965 RTW_PWR_CUT_ALL_MSK, 1966 RTW_PWR_INTF_ALL_MSK, 1967 0, 1968 RTW_PWR_CMD_END, 0, 0}, 1969 }; 1970 1971 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = { 1972 trans_carddis_to_cardemu_8822b, 1973 trans_cardemu_to_act_8822b, 1974 NULL 1975 }; 1976 1977 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = { 1978 trans_act_to_cardemu_8822b, 1979 trans_cardemu_to_carddis_8822b, 1980 NULL 1981 }; 1982 1983 static const struct rtw_intf_phy_para usb2_param_8822b[] = { 1984 {0xFFFF, 0x00, 1985 RTW_IP_SEL_PHY, 1986 RTW_INTF_PHY_CUT_ALL, 1987 RTW_INTF_PHY_PLATFORM_ALL}, 1988 }; 1989 1990 static const struct rtw_intf_phy_para usb3_param_8822b[] = { 1991 {0x0001, 0xA841, 1992 RTW_IP_SEL_PHY, 1993 RTW_INTF_PHY_CUT_D, 1994 RTW_INTF_PHY_PLATFORM_ALL}, 1995 {0xFFFF, 0x0000, 1996 RTW_IP_SEL_PHY, 1997 RTW_INTF_PHY_CUT_ALL, 1998 RTW_INTF_PHY_PLATFORM_ALL}, 1999 }; 2000 2001 static const struct rtw_intf_phy_para pcie_gen1_param_8822b[] = { 2002 {0x0001, 0xA841, 2003 RTW_IP_SEL_PHY, 2004 RTW_INTF_PHY_CUT_C, 2005 RTW_INTF_PHY_PLATFORM_ALL}, 2006 {0x0002, 0x60C6, 2007 RTW_IP_SEL_PHY, 2008 RTW_INTF_PHY_CUT_C, 2009 RTW_INTF_PHY_PLATFORM_ALL}, 2010 {0x0008, 0x3596, 2011 RTW_IP_SEL_PHY, 2012 RTW_INTF_PHY_CUT_C, 2013 RTW_INTF_PHY_PLATFORM_ALL}, 2014 {0x0009, 0x321C, 2015 RTW_IP_SEL_PHY, 2016 RTW_INTF_PHY_CUT_C, 2017 RTW_INTF_PHY_PLATFORM_ALL}, 2018 {0x000A, 0x9623, 2019 RTW_IP_SEL_PHY, 2020 RTW_INTF_PHY_CUT_C, 2021 RTW_INTF_PHY_PLATFORM_ALL}, 2022 {0x0020, 0x94FF, 2023 RTW_IP_SEL_PHY, 2024 RTW_INTF_PHY_CUT_C, 2025 RTW_INTF_PHY_PLATFORM_ALL}, 2026 {0x0021, 0xFFCF, 2027 RTW_IP_SEL_PHY, 2028 RTW_INTF_PHY_CUT_C, 2029 RTW_INTF_PHY_PLATFORM_ALL}, 2030 {0x0026, 0xC006, 2031 RTW_IP_SEL_PHY, 2032 RTW_INTF_PHY_CUT_C, 2033 RTW_INTF_PHY_PLATFORM_ALL}, 2034 {0x0029, 0xFF0E, 2035 RTW_IP_SEL_PHY, 2036 RTW_INTF_PHY_CUT_C, 2037 RTW_INTF_PHY_PLATFORM_ALL}, 2038 {0x002A, 0x1840, 2039 RTW_IP_SEL_PHY, 2040 RTW_INTF_PHY_CUT_C, 2041 RTW_INTF_PHY_PLATFORM_ALL}, 2042 {0xFFFF, 0x0000, 2043 RTW_IP_SEL_PHY, 2044 RTW_INTF_PHY_CUT_ALL, 2045 RTW_INTF_PHY_PLATFORM_ALL}, 2046 }; 2047 2048 static const struct rtw_intf_phy_para pcie_gen2_param_8822b[] = { 2049 {0x0001, 0xA841, 2050 RTW_IP_SEL_PHY, 2051 RTW_INTF_PHY_CUT_C, 2052 RTW_INTF_PHY_PLATFORM_ALL}, 2053 {0x0002, 0x60C6, 2054 RTW_IP_SEL_PHY, 2055 RTW_INTF_PHY_CUT_C, 2056 RTW_INTF_PHY_PLATFORM_ALL}, 2057 {0x0008, 0x3597, 2058 RTW_IP_SEL_PHY, 2059 RTW_INTF_PHY_CUT_C, 2060 RTW_INTF_PHY_PLATFORM_ALL}, 2061 {0x0009, 0x321C, 2062 RTW_IP_SEL_PHY, 2063 RTW_INTF_PHY_CUT_C, 2064 RTW_INTF_PHY_PLATFORM_ALL}, 2065 {0x000A, 0x9623, 2066 RTW_IP_SEL_PHY, 2067 RTW_INTF_PHY_CUT_C, 2068 RTW_INTF_PHY_PLATFORM_ALL}, 2069 {0x0020, 0x94FF, 2070 RTW_IP_SEL_PHY, 2071 RTW_INTF_PHY_CUT_C, 2072 RTW_INTF_PHY_PLATFORM_ALL}, 2073 {0x0021, 0xFFCF, 2074 RTW_IP_SEL_PHY, 2075 RTW_INTF_PHY_CUT_C, 2076 RTW_INTF_PHY_PLATFORM_ALL}, 2077 {0x0026, 0xC006, 2078 RTW_IP_SEL_PHY, 2079 RTW_INTF_PHY_CUT_C, 2080 RTW_INTF_PHY_PLATFORM_ALL}, 2081 {0x0029, 0xFF0E, 2082 RTW_IP_SEL_PHY, 2083 RTW_INTF_PHY_CUT_C, 2084 RTW_INTF_PHY_PLATFORM_ALL}, 2085 {0x002A, 0x3040, 2086 RTW_IP_SEL_PHY, 2087 RTW_INTF_PHY_CUT_C, 2088 RTW_INTF_PHY_PLATFORM_ALL}, 2089 {0xFFFF, 0x0000, 2090 RTW_IP_SEL_PHY, 2091 RTW_INTF_PHY_CUT_ALL, 2092 RTW_INTF_PHY_PLATFORM_ALL}, 2093 }; 2094 2095 static const struct rtw_intf_phy_para_table phy_para_table_8822b = { 2096 .usb2_para = usb2_param_8822b, 2097 .usb3_para = usb3_param_8822b, 2098 .gen1_para = pcie_gen1_param_8822b, 2099 .gen2_para = pcie_gen2_param_8822b, 2100 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b), 2101 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b), 2102 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b), 2103 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b), 2104 }; 2105 2106 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = { 2107 [2] = RTW_DEF_RFE(8822b, 2, 2), 2108 [3] = RTW_DEF_RFE(8822b, 3, 0), 2109 [5] = RTW_DEF_RFE(8822b, 5, 5), 2110 }; 2111 2112 static const struct rtw_hw_reg rtw8822b_dig[] = { 2113 [0] = { .addr = 0xc50, .mask = 0x7f }, 2114 [1] = { .addr = 0xe50, .mask = 0x7f }, 2115 }; 2116 2117 static const struct rtw_ltecoex_addr rtw8822b_ltecoex_addr = { 2118 .ctrl = LTECOEX_ACCESS_CTRL, 2119 .wdata = LTECOEX_WRITE_DATA, 2120 .rdata = LTECOEX_READ_DATA, 2121 }; 2122 2123 static const struct rtw_page_table page_table_8822b[] = { 2124 {64, 64, 64, 64, 1}, 2125 {64, 64, 64, 64, 1}, 2126 {64, 64, 0, 0, 1}, 2127 {64, 64, 64, 0, 1}, 2128 {64, 64, 64, 64, 1}, 2129 }; 2130 2131 static const struct rtw_rqpn rqpn_table_8822b[] = { 2132 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2133 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2134 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2135 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2136 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2137 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2138 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2139 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2140 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2141 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2142 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2143 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2144 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2145 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2146 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2147 }; 2148 2149 static struct rtw_prioq_addrs prioq_addrs_8822b = { 2150 .prio[RTW_DMA_MAPPING_EXTRA] = { 2151 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 2152 }, 2153 .prio[RTW_DMA_MAPPING_LOW] = { 2154 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 2155 }, 2156 .prio[RTW_DMA_MAPPING_NORMAL] = { 2157 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 2158 }, 2159 .prio[RTW_DMA_MAPPING_HIGH] = { 2160 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 2161 }, 2162 .wsize = true, 2163 }; 2164 2165 static struct rtw_chip_ops rtw8822b_ops = { 2166 .phy_set_param = rtw8822b_phy_set_param, 2167 .read_efuse = rtw8822b_read_efuse, 2168 .query_rx_desc = rtw8822b_query_rx_desc, 2169 .set_channel = rtw8822b_set_channel, 2170 .mac_init = rtw8822b_mac_init, 2171 .read_rf = rtw_phy_read_rf, 2172 .write_rf = rtw_phy_write_rf_reg_sipi, 2173 .set_tx_power_index = rtw8822b_set_tx_power_index, 2174 .set_antenna = rtw8822b_set_antenna, 2175 .cfg_ldo25 = rtw8822b_cfg_ldo25, 2176 .false_alarm_statistics = rtw8822b_false_alarm_statistics, 2177 .phy_calibration = rtw8822b_phy_calibration, 2178 .pwr_track = rtw8822b_pwr_track, 2179 .config_bfee = rtw8822b_bf_config_bfee, 2180 .set_gid_table = rtw_bf_set_gid_table, 2181 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 2182 .adaptivity_init = rtw8822b_adaptivity_init, 2183 .adaptivity = rtw8822b_adaptivity, 2184 .fill_txdesc_checksum = rtw8822b_fill_txdesc_checksum, 2185 2186 .coex_set_init = rtw8822b_coex_cfg_init, 2187 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch, 2188 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix, 2189 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug, 2190 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type, 2191 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power, 2192 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain, 2193 }; 2194 2195 /* Shared-Antenna Coex Table */ 2196 static const struct coex_table_para table_sant_8822b[] = { 2197 {0xffffffff, 0xffffffff}, /* case-0 */ 2198 {0x55555555, 0x55555555}, 2199 {0x66555555, 0x66555555}, 2200 {0xaaaaaaaa, 0xaaaaaaaa}, 2201 {0x5a5a5a5a, 0x5a5a5a5a}, 2202 {0xfafafafa, 0xfafafafa}, /* case-5 */ 2203 {0x6a5a5555, 0xaaaaaaaa}, 2204 {0x6a5a56aa, 0x6a5a56aa}, 2205 {0x6a5a5a5a, 0x6a5a5a5a}, 2206 {0x66555555, 0x5a5a5a5a}, 2207 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 2208 {0x66555555, 0xfafafafa}, 2209 {0x66555555, 0x5a5a5aaa}, 2210 {0x66555555, 0x6aaa5aaa}, 2211 {0x66555555, 0xaaaa5aaa}, 2212 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 2213 {0xffff55ff, 0xfafafafa}, 2214 {0xffff55ff, 0x6afa5afa}, 2215 {0xaaffffaa, 0xfafafafa}, 2216 {0xaa5555aa, 0x5a5a5a5a}, 2217 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 2218 {0xaa5555aa, 0xaaaaaaaa}, 2219 {0xffffffff, 0x5a5a5a5a}, 2220 {0xffffffff, 0x5a5a5a5a}, 2221 {0xffffffff, 0x55555555}, 2222 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 2223 {0x55555555, 0x5a5a5a5a}, 2224 {0x55555555, 0xaaaaaaaa}, 2225 {0x55555555, 0x6a5a6a5a}, 2226 {0x66556655, 0x66556655}, 2227 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 2228 {0xffffffff, 0x5aaa5aaa}, 2229 {0x56555555, 0x5a5a5aaa}, 2230 }; 2231 2232 /* Non-Shared-Antenna Coex Table */ 2233 static const struct coex_table_para table_nsant_8822b[] = { 2234 {0xffffffff, 0xffffffff}, /* case-100 */ 2235 {0x55555555, 0x55555555}, 2236 {0x66555555, 0x66555555}, 2237 {0xaaaaaaaa, 0xaaaaaaaa}, 2238 {0x5a5a5a5a, 0x5a5a5a5a}, 2239 {0xfafafafa, 0xfafafafa}, /* case-105 */ 2240 {0x5afa5afa, 0x5afa5afa}, 2241 {0x55555555, 0xfafafafa}, 2242 {0x66555555, 0xfafafafa}, 2243 {0x66555555, 0x5a5a5a5a}, 2244 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 2245 {0x66555555, 0xaaaaaaaa}, 2246 {0xffff55ff, 0xfafafafa}, 2247 {0xffff55ff, 0x5afa5afa}, 2248 {0xffff55ff, 0xaaaaaaaa}, 2249 {0xffff55ff, 0xffff55ff}, /* case-115 */ 2250 {0xaaffffaa, 0x5afa5afa}, 2251 {0xaaffffaa, 0xaaaaaaaa}, 2252 {0xffffffff, 0xfafafafa}, 2253 {0xffffffff, 0x5afa5afa}, 2254 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 2255 {0x55ff55ff, 0x5afa5afa}, 2256 {0x55ff55ff, 0xaaaaaaaa}, 2257 {0x55ff55ff, 0x55ff55ff} 2258 }; 2259 2260 /* Shared-Antenna TDMA */ 2261 static const struct coex_tdma_para tdma_sant_8822b[] = { 2262 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2263 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 2264 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2265 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2266 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2267 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2268 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2269 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2270 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2271 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2272 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2273 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2274 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2275 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2276 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2277 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 2278 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2279 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2280 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2281 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2282 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 2283 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2284 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2285 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2286 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 2287 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 2288 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 2289 { {0x61, 0x08, 0x03, 0x11, 0x11} } 2290 }; 2291 2292 /* Non-Shared-Antenna TDMA */ 2293 static const struct coex_tdma_para tdma_nsant_8822b[] = { 2294 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 2295 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */ 2296 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2297 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2298 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2299 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2300 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2301 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2302 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2303 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2304 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2305 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2306 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2307 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2308 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2309 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2310 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2311 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2312 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2313 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2314 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 2315 { {0x51, 0x08, 0x03, 0x10, 0x50} } 2316 }; 2317 2318 /* rssi in percentage % (dbm = % - 100) */ 2319 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30}; 2320 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30}; 2321 2322 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2323 static const struct coex_rf_para rf_para_tx_8822b[] = { 2324 {0, 0, false, 7}, /* for normal */ 2325 {0, 16, false, 7}, /* for WL-CPT */ 2326 {4, 0, true, 1}, 2327 {3, 6, true, 1}, 2328 {2, 9, true, 1}, 2329 {1, 13, true, 1} 2330 }; 2331 2332 static const struct coex_rf_para rf_para_rx_8822b[] = { 2333 {0, 0, false, 7}, /* for normal */ 2334 {0, 16, false, 7}, /* for WL-CPT */ 2335 {4, 0, true, 1}, 2336 {3, 6, true, 1}, 2337 {2, 9, true, 1}, 2338 {1, 13, true, 1} 2339 }; 2340 2341 static const struct coex_5g_afh_map afh_5g_8822b[] = { 2342 {120, 2, 4}, 2343 {124, 8, 8}, 2344 {128, 17, 8}, 2345 {132, 26, 10}, 2346 {136, 34, 8}, 2347 {140, 42, 10}, 2348 {144, 51, 8}, 2349 {149, 62, 8}, 2350 {153, 71, 10}, 2351 {157, 77, 4}, 2352 {118, 2, 4}, 2353 {126, 12, 16}, 2354 {134, 29, 16}, 2355 {142, 46, 16}, 2356 {151, 66, 16}, 2357 {159, 76, 4}, 2358 {122, 10, 20}, 2359 {138, 37, 34}, 2360 {155, 68, 20} 2361 }; 2362 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b)); 2363 2364 static const u8 2365 rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2366 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2367 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2368 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2369 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2370 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2371 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2372 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2373 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2374 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2375 }; 2376 2377 static const u8 2378 rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2379 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2380 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2381 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2382 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2383 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2384 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2385 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2386 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2387 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2388 }; 2389 2390 static const u8 2391 rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2392 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2393 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2394 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2395 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2396 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2397 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2398 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2399 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2400 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2401 }; 2402 2403 static const u8 2404 rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2405 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2406 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2407 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2408 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2409 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2410 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2411 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2412 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2413 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2414 }; 2415 2416 static const u8 rtw8822b_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 2417 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2418 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2419 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2420 }; 2421 2422 static const u8 rtw8822b_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 2423 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2424 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2425 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2426 }; 2427 2428 static const u8 rtw8822b_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 2429 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2430 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2431 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2432 }; 2433 2434 static const u8 rtw8822b_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 2435 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2436 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2437 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2438 }; 2439 2440 static const u8 rtw8822b_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 2441 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2442 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2443 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2444 }; 2445 2446 static const u8 rtw8822b_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 2447 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2448 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2449 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2450 }; 2451 2452 static const u8 rtw8822b_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 2453 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2454 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2455 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2456 }; 2457 2458 static const u8 rtw8822b_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 2459 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2460 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2461 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2462 }; 2463 2464 static const struct rtw_pwr_track_tbl rtw8822b_rtw_pwr_track_tbl = { 2465 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 2466 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 2467 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 2468 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 2469 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 2470 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 2471 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 2472 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 2473 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 2474 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 2475 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 2476 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 2477 .pwrtrk_2gb_n = rtw8822b_pwrtrk_2gb_n, 2478 .pwrtrk_2gb_p = rtw8822b_pwrtrk_2gb_p, 2479 .pwrtrk_2ga_n = rtw8822b_pwrtrk_2ga_n, 2480 .pwrtrk_2ga_p = rtw8822b_pwrtrk_2ga_p, 2481 .pwrtrk_2g_cckb_n = rtw8822b_pwrtrk_2g_cck_b_n, 2482 .pwrtrk_2g_cckb_p = rtw8822b_pwrtrk_2g_cck_b_p, 2483 .pwrtrk_2g_ccka_n = rtw8822b_pwrtrk_2g_cck_a_n, 2484 .pwrtrk_2g_ccka_p = rtw8822b_pwrtrk_2g_cck_a_p, 2485 }; 2486 2487 static const struct rtw_reg_domain coex_info_hw_regs_8822b[] = { 2488 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2489 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2490 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2491 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2492 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2493 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8}, 2494 {0, 0, RTW_REG_DOMAIN_NL}, 2495 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2496 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2497 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2498 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2499 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2500 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2501 {0, 0, RTW_REG_DOMAIN_NL}, 2502 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 2503 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 2504 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2505 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2506 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 2507 {0, 0, RTW_REG_DOMAIN_NL}, 2508 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2509 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2510 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2511 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2512 }; 2513 2514 static struct rtw_hw_reg_offset rtw8822b_edcca_th[] = { 2515 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0}, 2516 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0}, 2517 }; 2518 2519 const struct rtw_chip_info rtw8822b_hw_spec = { 2520 .ops = &rtw8822b_ops, 2521 .id = RTW_CHIP_TYPE_8822B, 2522 .fw_name = "rtw88/rtw8822b_fw.bin", 2523 .wlan_cpu = RTW_WCPU_11AC, 2524 .tx_pkt_desc_sz = 48, 2525 .tx_buf_desc_sz = 16, 2526 .rx_pkt_desc_sz = 24, 2527 .rx_buf_desc_sz = 8, 2528 .phy_efuse_size = 1024, 2529 .log_efuse_size = 768, 2530 .ptct_efuse_size = 96, 2531 .txff_size = 262144, 2532 .rxff_size = 24576, 2533 .fw_rxff_size = 12288, 2534 .txgi_factor = 1, 2535 .is_pwr_by_rate_dec = true, 2536 .max_power_index = 0x3f, 2537 .csi_buf_pg_num = 0, 2538 .band = RTW_BAND_2G | RTW_BAND_5G, 2539 .page_size = TX_PAGE_SIZE, 2540 .dig_min = 0x1c, 2541 .ht_supported = true, 2542 .vht_supported = true, 2543 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 2544 .sys_func_en = 0xDC, 2545 .pwr_on_seq = card_enable_flow_8822b, 2546 .pwr_off_seq = card_disable_flow_8822b, 2547 .page_table = page_table_8822b, 2548 .rqpn_table = rqpn_table_8822b, 2549 .prioq_addrs = &prioq_addrs_8822b, 2550 .intf_table = &phy_para_table_8822b, 2551 .dig = rtw8822b_dig, 2552 .dig_cck = NULL, 2553 .rf_base_addr = {0x2800, 0x2c00}, 2554 .rf_sipi_addr = {0xc90, 0xe90}, 2555 .ltecoex_addr = &rtw8822b_ltecoex_addr, 2556 .mac_tbl = &rtw8822b_mac_tbl, 2557 .agc_tbl = &rtw8822b_agc_tbl, 2558 .bb_tbl = &rtw8822b_bb_tbl, 2559 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl}, 2560 .rfe_defs = rtw8822b_rfe_defs, 2561 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs), 2562 .pwr_track_tbl = &rtw8822b_rtw_pwr_track_tbl, 2563 .iqk_threshold = 8, 2564 .bfer_su_max_num = 2, 2565 .bfer_mu_max_num = 1, 2566 .rx_ldpc = true, 2567 .edcca_th = rtw8822b_edcca_th, 2568 .l2h_th_ini_cs = 10 + EDCCA_IGI_BASE, 2569 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE, 2570 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 2571 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2572 2573 .coex_para_ver = 0x20070206, 2574 .bt_desired_ver = 0x6, 2575 .scbd_support = true, 2576 .new_scbd10_def = false, 2577 .ble_hid_profile_support = false, 2578 .wl_mimo_ps_support = false, 2579 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2580 .bt_rssi_type = COEX_BTRSSI_RATIO, 2581 .ant_isolation = 15, 2582 .rssi_tolerance = 2, 2583 .wl_rssi_step = wl_rssi_step_8822b, 2584 .bt_rssi_step = bt_rssi_step_8822b, 2585 .table_sant_num = ARRAY_SIZE(table_sant_8822b), 2586 .table_sant = table_sant_8822b, 2587 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b), 2588 .table_nsant = table_nsant_8822b, 2589 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b), 2590 .tdma_sant = tdma_sant_8822b, 2591 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b), 2592 .tdma_nsant = tdma_nsant_8822b, 2593 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b), 2594 .wl_rf_para_tx = rf_para_tx_8822b, 2595 .wl_rf_para_rx = rf_para_rx_8822b, 2596 .bt_afh_span_bw20 = 0x24, 2597 .bt_afh_span_bw40 = 0x36, 2598 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b), 2599 .afh_5g = afh_5g_8822b, 2600 2601 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822b), 2602 .coex_info_hw_regs = coex_info_hw_regs_8822b, 2603 2604 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 2605 }; 2606 EXPORT_SYMBOL(rtw8822b_hw_spec); 2607 2608 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin"); 2609 2610 MODULE_AUTHOR("Realtek Corporation"); 2611 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822b driver"); 2612 MODULE_LICENSE("Dual BSD/GPL"); 2613