1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTW8821C_H__
6 #define __RTW8821C_H__
7 
8 #include <asm/byteorder.h>
9 
10 #define RCR_VHT_ACK		BIT(26)
11 
12 struct rtw8821ce_efuse {
13 	u8 mac_addr[ETH_ALEN];		/* 0xd0 */
14 	u8 vender_id[2];
15 	u8 device_id[2];
16 	u8 sub_vender_id[2];
17 	u8 sub_device_id[2];
18 	u8 pmc[2];
19 	u8 exp_device_cap[2];
20 	u8 msi_cap;
21 	u8 ltr_cap;			/* 0xe3 */
22 	u8 exp_link_control[2];
23 	u8 link_cap[4];
24 	u8 link_control[2];
25 	u8 serial_number[8];
26 	u8 res0:2;			/* 0xf4 */
27 	u8 ltr_en:1;
28 	u8 res1:2;
29 	u8 obff:2;
30 	u8 res2:3;
31 	u8 obff_cap:2;
32 	u8 res3:4;
33 	u8 res4[3];
34 	u8 class_code[3];
35 	u8 pci_pm_L1_2_supp:1;
36 	u8 pci_pm_L1_1_supp:1;
37 	u8 aspm_pm_L1_2_supp:1;
38 	u8 aspm_pm_L1_1_supp:1;
39 	u8 L1_pm_substates_supp:1;
40 	u8 res5:3;
41 	u8 port_common_mode_restore_time;
42 	u8 port_t_power_on_scale:2;
43 	u8 res6:1;
44 	u8 port_t_power_on_value:5;
45 	u8 res7;
46 };
47 
48 struct rtw8821c_efuse {
49 	__le16 rtl_id;
50 	u8 res0[0x0e];
51 
52 	/* power index for four RF paths */
53 	struct rtw_txpwr_idx txpwr_idx_table[4];
54 
55 	u8 channel_plan;		/* 0xb8 */
56 	u8 xtal_k;
57 	u8 thermal_meter;
58 	u8 iqk_lck;
59 	u8 pa_type;			/* 0xbc */
60 	u8 lna_type_2g[2];		/* 0xbd */
61 	u8 lna_type_5g[2];
62 	u8 rf_board_option;
63 	u8 rf_feature_option;
64 	u8 rf_bt_setting;
65 	u8 eeprom_version;
66 	u8 eeprom_customer_id;
67 	u8 tx_bb_swing_setting_2g;
68 	u8 tx_bb_swing_setting_5g;
69 	u8 tx_pwr_calibrate_rate;
70 	u8 rf_antenna_option;		/* 0xc9 */
71 	u8 rfe_option;
72 	u8 country_code[2];
73 	u8 res[3];
74 	union {
75 		struct rtw8821ce_efuse e;
76 	};
77 };
78 
79 static inline void
80 _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
81 {
82 	/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
83 	rtw_write32_mask(rtwdev, addr, mask, data);
84 	rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
85 }
86 
87 #define rtw_write32s_mask(rtwdev, addr, mask, data)			       \
88 	do {								       \
89 		BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00);	       \
90 									       \
91 		_rtw_write32s_mask(rtwdev, addr, mask, data);		       \
92 	} while (0)
93 
94 #define BIT_FEN_PCIEA BIT(6)
95 #define WLAN_SLOT_TIME		0x09
96 #define WLAN_PIFS_TIME		0x19
97 #define WLAN_SIFS_CCK_CONT_TX	0xA
98 #define WLAN_SIFS_OFDM_CONT_TX	0xE
99 #define WLAN_SIFS_CCK_TRX	0x10
100 #define WLAN_SIFS_OFDM_TRX	0x10
101 #define WLAN_VO_TXOP_LIMIT	0x186
102 #define WLAN_VI_TXOP_LIMIT	0x3BC
103 #define WLAN_RDG_NAV		0x05
104 #define WLAN_TXOP_NAV		0x1B
105 #define WLAN_CCK_RX_TSF		0x30
106 #define WLAN_OFDM_RX_TSF	0x30
107 #define WLAN_TBTT_PROHIBIT	0x04
108 #define WLAN_TBTT_HOLD_TIME	0x064
109 #define WLAN_DRV_EARLY_INT	0x04
110 #define WLAN_BCN_DMA_TIME	0x02
111 
112 #define WLAN_RX_FILTER0		0x0FFFFFFF
113 #define WLAN_RX_FILTER2		0xFFFF
114 #define WLAN_RCR_CFG		0xE400220E
115 #define WLAN_RXPKT_MAX_SZ	12288
116 #define WLAN_RXPKT_MAX_SZ_512	(WLAN_RXPKT_MAX_SZ >> 9)
117 
118 #define WLAN_AMPDU_MAX_TIME		0x70
119 #define WLAN_RTS_LEN_TH			0xFF
120 #define WLAN_RTS_TX_TIME_TH		0x08
121 #define WLAN_MAX_AGG_PKT_LIMIT		0x20
122 #define WLAN_RTS_MAX_AGG_PKT_LIMIT	0x20
123 #define FAST_EDCA_VO_TH		0x06
124 #define FAST_EDCA_VI_TH		0x06
125 #define FAST_EDCA_BE_TH		0x06
126 #define FAST_EDCA_BK_TH		0x06
127 #define WLAN_BAR_RETRY_LIMIT		0x01
128 #define WLAN_RA_TRY_RATE_AGG_LIMIT	0x08
129 
130 #define WLAN_TX_FUNC_CFG1		0x30
131 #define WLAN_TX_FUNC_CFG2		0x30
132 #define WLAN_MAC_OPT_NORM_FUNC1		0x98
133 #define WLAN_MAC_OPT_LB_FUNC1		0x80
134 #define WLAN_MAC_OPT_FUNC2		0xb0810041
135 
136 #define WLAN_SIFS_CFG	(WLAN_SIFS_CCK_CONT_TX | \
137 			(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
138 			(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
139 			(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
140 
141 #define WLAN_TBTT_TIME	(WLAN_TBTT_PROHIBIT |\
142 			(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
143 
144 #define WLAN_NAV_CFG		(WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
145 #define WLAN_RX_TSF_CFG		(WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
146 #define WLAN_PRE_TXCNT_TIME_TH		0x1E4
147 
148 /* phy status page0 */
149 #define GET_PHY_STAT_P0_PWDB(phy_stat)                                         \
150 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
151 #define GET_PHY_STAT_P0_VGA(phy_stat)                                          \
152 	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8))
153 #define GET_PHY_STAT_P0_LNA_L(phy_stat)                                        \
154 	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13))
155 #define GET_PHY_STAT_P0_LNA_H(phy_stat)                                        \
156 	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23))
157 #define BIT_LNA_H_MASK BIT(3)
158 #define BIT_LNA_L_MASK GENMASK(2, 0)
159 
160 /* phy status page1 */
161 #define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
162 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
163 #define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
164 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
165 #define GET_PHY_STAT_P1_RF_MODE(phy_stat)                                      \
166 	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
167 #define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
168 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
169 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
170 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
171 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat)                                      \
172 	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
173 #define GET_PHY_STAT_P1_RXEVM_B(phy_stat)                                      \
174 	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
175 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat)                                 \
176 	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
177 #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat)                                 \
178 	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
179 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat)                                      \
180 	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
181 #define GET_PHY_STAT_P1_RXSNR_B(phy_stat)                                      \
182 	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
183 
184 #define REG_SYS_CTRL	0x000
185 #define BIT_FEN_EN	BIT(26)
186 #define REG_INIRTS_RATE_SEL 0x0480
187 #define REG_HTSTFWT	0x800
188 #define REG_RXPSEL	0x808
189 #define BIT_RX_PSEL_RST		(BIT(28) | BIT(29))
190 #define REG_TXPSEL	0x80c
191 #define REG_RXCCAMSK	0x814
192 #define REG_CCASEL	0x82c
193 #define REG_PDMFTH	0x830
194 #define REG_CCA2ND	0x838
195 #define REG_L1WT	0x83c
196 #define REG_L1PKWT	0x840
197 #define REG_MRC		0x850
198 #define REG_CLKTRK	0x860
199 #define REG_ADCCLK	0x8ac
200 #define REG_ADC160	0x8c4
201 #define REG_ADC40	0x8c8
202 #define REG_CHFIR	0x8f0
203 #define REG_CDDTXP	0x93c
204 #define REG_TXPSEL1	0x940
205 #define REG_ACBB0	0x948
206 #define REG_ACBBRXFIR	0x94c
207 #define REG_ACGG2TBL	0x958
208 #define REG_FAS		0x9a4
209 #define REG_RXSB	0xa00
210 #define REG_ADCINI	0xa04
211 #define REG_PWRTH	0xa08
212 #define REG_TXSF2	0xa24
213 #define REG_TXSF6	0xa28
214 #define REG_FA_CCK	0xa5c
215 #define REG_RXDESC	0xa2c
216 #define REG_ENTXCCK	0xa80
217 #define BTG_LNA		0xfc84
218 #define WLG_LNA		0x7532
219 #define REG_ENRXCCA	0xa84
220 #define BTG_CCA		0x0e
221 #define WLG_CCA		0x12
222 #define REG_PWRTH2	0xaa8
223 #define REG_CSRATIO	0xaaa
224 #define REG_TXFILTER	0xaac
225 #define REG_CNTRST	0xb58
226 #define REG_AGCTR_A	0xc08
227 #define REG_TXSCALE_A	0xc1c
228 #define REG_TXDFIR	0xc20
229 #define REG_RXIGI_A	0xc50
230 #define REG_TXAGCIDX	0xc94
231 #define REG_TRSW	0xca0
232 #define REG_RFESEL0	0xcb0
233 #define REG_RFESEL8	0xcb4
234 #define REG_RFECTL	0xcb8
235 #define B_BTG_SWITCH	BIT(16)
236 #define B_CTRL_SWITCH	BIT(18)
237 #define B_WL_SWITCH	(BIT(20) | BIT(22))
238 #define B_WLG_SWITCH	BIT(21)
239 #define B_WLA_SWITCH	BIT(23)
240 #define REG_RFEINV	0xcbc
241 #define REG_AGCTR_B	0xe08
242 #define REG_RXIGI_B	0xe50
243 #define REG_CRC_CCK	0xf04
244 #define REG_CRC_OFDM	0xf14
245 #define REG_CRC_HT	0xf10
246 #define REG_CRC_VHT	0xf0c
247 #define REG_CCA_OFDM	0xf08
248 #define REG_FA_OFDM	0xf48
249 #define REG_CCA_CCK	0xfcc
250 #define REG_DMEM_CTRL	0x1080
251 #define BIT_WL_RST	BIT(16)
252 #define REG_ANTWT	0x1904
253 #define REG_IQKFAILMSK	0x1bf0
254 #define BIT_MASK_R_RFE_SEL_15	GENMASK(31, 28)
255 #define BIT_SDIO_INT BIT(18)
256 #define BT_CNT_ENABLE	0x1
257 #define BIT_BCN_QUEUE	BIT(3)
258 #define BCN_PRI_EN	0x1
259 #define PTA_CTRL_PIN	0x66
260 #define DPDT_CTRL_PIN	0x77
261 #define ANTDIC_CTRL_PIN	0x88
262 #define REG_CTRL_TYPE	0x67
263 #define BIT_CTRL_TYPE1	BIT(5)
264 #define BIT_CTRL_TYPE2	BIT(4)
265 #define CTRL_TYPE_MASK	GENMASK(15, 8)
266 
267 #define RF18_BAND_MASK		(BIT(16) | BIT(9) | BIT(8))
268 #define RF18_BAND_2G		(0)
269 #define RF18_BAND_5G		(BIT(16) | BIT(8))
270 #define RF18_CHANNEL_MASK	(MASKBYTE0)
271 #define RF18_RFSI_MASK		(BIT(18) | BIT(17))
272 #define RF18_RFSI_GE		(BIT(17))
273 #define RF18_RFSI_GT		(BIT(18))
274 #define RF18_BW_MASK		(BIT(11) | BIT(10))
275 #define RF18_BW_20M		(BIT(11) | BIT(10))
276 #define RF18_BW_40M		(BIT(11))
277 #define RF18_BW_80M		(BIT(10))
278 
279 #endif
280