1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 #include "regd.h" 18 19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; 20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, 21 -20, -24, -28, -31, -34, -37, -40, -44}; 22 23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8821c_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 enum rtw8821ce_rf_set { 30 SWITCH_TO_BTG, 31 SWITCH_TO_WLG, 32 SWITCH_TO_WLA, 33 SWITCH_TO_BT, 34 }; 35 36 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 37 { 38 struct rtw_efuse *efuse = &rtwdev->efuse; 39 struct rtw8821c_efuse *map; 40 int i; 41 42 map = (struct rtw8821c_efuse *)log_map; 43 44 efuse->rfe_option = map->rfe_option; 45 efuse->rf_board_option = map->rf_board_option; 46 efuse->crystal_cap = map->xtal_k; 47 efuse->pa_type_2g = map->pa_type; 48 efuse->pa_type_5g = map->pa_type; 49 efuse->lna_type_2g = map->lna_type_2g[0]; 50 efuse->lna_type_5g = map->lna_type_5g[0]; 51 efuse->channel_plan = map->channel_plan; 52 efuse->country_code[0] = map->country_code[0]; 53 efuse->country_code[1] = map->country_code[1]; 54 efuse->bt_setting = map->rf_bt_setting; 55 efuse->regd = map->rf_board_option & 0x7; 56 efuse->thermal_meter[0] = map->thermal_meter; 57 efuse->thermal_meter_k = map->thermal_meter; 58 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 59 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 60 61 for (i = 0; i < 4; i++) 62 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 63 64 switch (rtw_hci_type(rtwdev)) { 65 case RTW_HCI_TYPE_PCIE: 66 rtw8821ce_efuse_parsing(efuse, map); 67 break; 68 default: 69 /* unsupported now */ 70 return -ENOTSUPP; 71 } 72 73 return 0; 74 } 75 76 static const u32 rtw8821c_txscale_tbl[] = { 77 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 78 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 79 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 80 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 81 }; 82 83 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 84 { 85 u8 i = 0; 86 u32 swing, table_value; 87 88 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 89 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 90 table_value = rtw8821c_txscale_tbl[i]; 91 if (swing == table_value) 92 break; 93 } 94 95 return i; 96 } 97 98 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 99 { 100 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 101 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 102 103 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 104 dm_info->default_ofdm_index = 24; 105 else 106 dm_info->default_ofdm_index = swing_idx; 107 108 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 109 dm_info->delta_power_index[RF_PATH_A] = 0; 110 dm_info->delta_power_index_last[RF_PATH_A] = 0; 111 dm_info->pwr_trk_triggered = false; 112 dm_info->pwr_trk_init_trigger = true; 113 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 114 } 115 116 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 117 { 118 rtw_bf_phy_init(rtwdev); 119 /* Grouping bitmap parameters */ 120 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 121 } 122 123 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 124 { 125 u8 crystal_cap, val; 126 127 /* power on BB/RF domain */ 128 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 129 val |= BIT_FEN_PCIEA; 130 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 131 132 /* toggle BB reset */ 133 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 134 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 135 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 136 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 137 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 138 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 139 140 rtw_write8(rtwdev, REG_RF_CTRL, 141 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 142 usleep_range(10, 11); 143 rtw_write8(rtwdev, REG_WLRF1 + 3, 144 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 145 usleep_range(10, 11); 146 147 /* pre init before header files config */ 148 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 149 150 rtw_phy_load_tables(rtwdev); 151 152 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 153 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 154 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 155 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 156 157 /* post init after header files config */ 158 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 159 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 160 rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 161 rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 162 163 rtw_phy_init(rtwdev); 164 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 165 166 rtw8821c_pwrtrack_init(rtwdev); 167 168 rtw8821c_phy_bf_init(rtwdev); 169 } 170 171 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 172 { 173 u32 value32; 174 u16 pre_txcnt; 175 176 /* protocol configuration */ 177 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 178 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 179 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 180 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 181 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 182 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 183 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 184 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 185 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 186 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 187 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 188 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 189 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 190 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 191 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 192 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 193 194 /* EDCA configuration */ 195 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 196 rtw_write16(rtwdev, REG_TXPAUSE, 0); 197 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 198 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 199 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 200 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 201 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 202 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 203 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 204 205 /* Set beacon cotnrol - enable TSF and other related functions */ 206 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 207 208 /* Set send beacon related registers */ 209 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 210 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 211 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 212 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 213 214 /* WMAC configuration */ 215 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 216 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 217 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 218 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 219 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 220 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 221 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 222 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 223 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6)); 224 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 225 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 226 227 return 0; 228 } 229 230 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 231 { 232 u8 ldo_pwr; 233 234 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 235 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 236 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 237 } 238 239 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) 240 { 241 u32 reg; 242 243 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST); 244 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN); 245 246 reg = rtw_read32(rtwdev, REG_RFECTL); 247 switch (rf_set) { 248 case SWITCH_TO_BTG: 249 reg |= B_BTG_SWITCH; 250 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH | 251 B_WLA_SWITCH); 252 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); 253 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); 254 break; 255 case SWITCH_TO_WLG: 256 reg |= B_WL_SWITCH | B_WLG_SWITCH; 257 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH); 258 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); 259 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); 260 break; 261 case SWITCH_TO_WLA: 262 reg |= B_WL_SWITCH | B_WLA_SWITCH; 263 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH); 264 break; 265 case SWITCH_TO_BT: 266 default: 267 break; 268 } 269 270 rtw_write32(rtwdev, REG_RFECTL, reg); 271 } 272 273 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 274 { 275 u32 rf_reg18; 276 277 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 278 279 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 280 RF18_BW_MASK); 281 282 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 283 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 284 285 if (channel >= 100 && channel <= 140) 286 rf_reg18 |= RF18_RFSI_GE; 287 else if (channel > 140) 288 rf_reg18 |= RF18_RFSI_GT; 289 290 switch (bw) { 291 case RTW_CHANNEL_WIDTH_5: 292 case RTW_CHANNEL_WIDTH_10: 293 case RTW_CHANNEL_WIDTH_20: 294 default: 295 rf_reg18 |= RF18_BW_20M; 296 break; 297 case RTW_CHANNEL_WIDTH_40: 298 rf_reg18 |= RF18_BW_40M; 299 break; 300 case RTW_CHANNEL_WIDTH_80: 301 rf_reg18 |= RF18_BW_80M; 302 break; 303 } 304 305 if (channel <= 14) { 306 if (rtwdev->efuse.rfe_option == 0) 307 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG); 308 else if (rtwdev->efuse.rfe_option == 2) 309 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG); 310 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 311 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 312 } else { 313 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA); 314 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 315 } 316 317 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 318 319 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 320 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 321 } 322 323 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 324 { 325 if (bw == RTW_CHANNEL_WIDTH_40) { 326 /* RX DFIR for BW40 */ 327 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 328 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 329 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 330 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 331 } else if (bw == RTW_CHANNEL_WIDTH_80) { 332 /* RX DFIR for BW80 */ 333 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 334 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 335 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 336 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 337 } else { 338 /* RX DFIR for BW20, BW10 and BW5 */ 339 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 340 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 341 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 342 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 343 } 344 } 345 346 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 347 u8 primary_ch_idx) 348 { 349 u32 val32; 350 351 if (channel <= 14) { 352 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 353 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 354 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 355 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 356 357 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 358 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 359 if (channel == 14) { 360 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 361 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 362 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 363 } else { 364 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 365 rtwdev->chip->ch_param[0]); 366 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 367 rtwdev->chip->ch_param[1] & MASKLWORD); 368 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 369 rtwdev->chip->ch_param[2]); 370 } 371 } else if (channel > 35) { 372 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 373 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 374 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 375 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 376 377 if (channel >= 36 && channel <= 64) 378 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 379 else if (channel >= 100 && channel <= 144) 380 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 381 else if (channel >= 149) 382 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 383 384 if (channel >= 36 && channel <= 48) 385 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 386 else if (channel >= 52 && channel <= 64) 387 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 388 else if (channel >= 100 && channel <= 116) 389 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 390 else if (channel >= 118 && channel <= 177) 391 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 392 } 393 394 switch (bw) { 395 case RTW_CHANNEL_WIDTH_20: 396 default: 397 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 398 val32 &= 0xffcffc00; 399 val32 |= 0x10010000; 400 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 401 402 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 403 break; 404 case RTW_CHANNEL_WIDTH_40: 405 if (primary_ch_idx == 1) 406 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 407 else 408 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 409 410 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 411 val32 &= 0xff3ff300; 412 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 413 RTW_CHANNEL_WIDTH_40; 414 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 415 416 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 417 break; 418 case RTW_CHANNEL_WIDTH_80: 419 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 420 val32 &= 0xfcffcf00; 421 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 422 RTW_CHANNEL_WIDTH_80; 423 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 424 425 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 426 break; 427 case RTW_CHANNEL_WIDTH_5: 428 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 429 val32 &= 0xefcefc00; 430 val32 |= 0x200240; 431 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 432 433 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 434 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 435 break; 436 case RTW_CHANNEL_WIDTH_10: 437 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 438 val32 &= 0xefcefc00; 439 val32 |= 0x300380; 440 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 441 442 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 443 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 444 break; 445 } 446 } 447 448 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 449 { 450 struct rtw_efuse efuse = rtwdev->efuse; 451 u8 tx_bb_swing; 452 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 453 454 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 455 efuse.tx_bb_swing_setting_5g; 456 if (tx_bb_swing > 9) 457 tx_bb_swing = 0; 458 459 return swing2setting[(tx_bb_swing / 3)]; 460 } 461 462 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 463 u8 bw, u8 primary_ch_idx) 464 { 465 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 466 rtw8821c_get_bb_swing(rtwdev, channel)); 467 rtw8821c_pwrtrack_init(rtwdev); 468 } 469 470 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 471 u8 primary_chan_idx) 472 { 473 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 474 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 475 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 476 rtw8821c_set_channel_rf(rtwdev, channel, bw); 477 rtw8821c_set_channel_rxdfir(rtwdev, bw); 478 } 479 480 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 481 { 482 struct rtw_efuse *efuse = &rtwdev->efuse; 483 const s8 *lna_gain_table; 484 int lna_gain_table_size; 485 s8 rx_pwr_all = 0; 486 s8 lna_gain = 0; 487 488 if (efuse->rfe_option == 0) { 489 lna_gain_table = lna_gain_table_0; 490 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0); 491 } else { 492 lna_gain_table = lna_gain_table_1; 493 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1); 494 } 495 496 if (lna_idx >= lna_gain_table_size) { 497 rtw_info(rtwdev, "incorrect lna index (%d)\n", lna_idx); 498 return -120; 499 } 500 501 lna_gain = lna_gain_table[lna_idx]; 502 rx_pwr_all = lna_gain - 2 * vga_idx; 503 504 return rx_pwr_all; 505 } 506 507 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 508 struct rtw_rx_pkt_stat *pkt_stat) 509 { 510 s8 rx_power; 511 u8 lna_idx = 0; 512 u8 vga_idx = 0; 513 514 vga_idx = GET_PHY_STAT_P0_VGA(phy_status); 515 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) | 516 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status)); 517 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 518 519 pkt_stat->rx_power[RF_PATH_A] = rx_power; 520 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 521 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 522 pkt_stat->signal_power = rx_power; 523 } 524 525 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 526 struct rtw_rx_pkt_stat *pkt_stat) 527 { 528 u8 rxsc, bw; 529 s8 min_rx_power = -120; 530 531 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 532 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 533 else 534 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 535 536 if (rxsc >= 1 && rxsc <= 8) 537 bw = RTW_CHANNEL_WIDTH_20; 538 else if (rxsc >= 9 && rxsc <= 12) 539 bw = RTW_CHANNEL_WIDTH_40; 540 else if (rxsc >= 13) 541 bw = RTW_CHANNEL_WIDTH_80; 542 else 543 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 544 545 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 546 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 547 pkt_stat->bw = bw; 548 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 549 min_rx_power); 550 } 551 552 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 553 struct rtw_rx_pkt_stat *pkt_stat) 554 { 555 u8 page; 556 557 page = *phy_status & 0xf; 558 559 switch (page) { 560 case 0: 561 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 562 break; 563 case 1: 564 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 565 break; 566 default: 567 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 568 return; 569 } 570 } 571 572 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 573 struct rtw_rx_pkt_stat *pkt_stat, 574 struct ieee80211_rx_status *rx_status) 575 { 576 struct ieee80211_hdr *hdr; 577 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 578 u8 *phy_status = NULL; 579 580 memset(pkt_stat, 0, sizeof(*pkt_stat)); 581 582 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 583 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 584 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 585 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 586 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 587 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 588 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 589 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 590 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 591 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 592 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 593 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 594 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 595 596 /* drv_info_sz is in unit of 8-bytes */ 597 pkt_stat->drv_info_sz *= 8; 598 599 /* c2h cmd pkt's rx/phy status is not interested */ 600 if (pkt_stat->is_c2h) 601 return; 602 603 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 604 pkt_stat->drv_info_sz); 605 if (pkt_stat->phy_status) { 606 phy_status = rx_desc + desc_sz + pkt_stat->shift; 607 query_phy_status(rtwdev, phy_status, pkt_stat); 608 } 609 610 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 611 } 612 613 static void 614 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 615 { 616 struct rtw_hal *hal = &rtwdev->hal; 617 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 618 static u32 phy_pwr_idx; 619 u8 rate, rate_idx, pwr_index, shift; 620 int j; 621 622 for (j = 0; j < rtw_rate_size[rs]; j++) { 623 rate = rtw_rate_section[rs][j]; 624 pwr_index = hal->tx_pwr_tbl[path][rate]; 625 shift = rate & 0x3; 626 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 627 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 628 rate_idx = rate & 0xfc; 629 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 630 phy_pwr_idx); 631 phy_pwr_idx = 0; 632 } 633 } 634 } 635 636 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 637 { 638 struct rtw_hal *hal = &rtwdev->hal; 639 int rs, path; 640 641 for (path = 0; path < hal->rf_path_num; path++) { 642 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 643 if (rs == RTW_RATE_SECTION_HT_2S || 644 rs == RTW_RATE_SECTION_VHT_2S) 645 continue; 646 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 647 } 648 } 649 } 650 651 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 652 { 653 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 654 u32 cck_enable; 655 u32 cck_fa_cnt; 656 u32 ofdm_fa_cnt; 657 u32 crc32_cnt; 658 u32 cca32_cnt; 659 660 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 661 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 662 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 663 664 dm_info->cck_fa_cnt = cck_fa_cnt; 665 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 666 if (cck_enable) 667 dm_info->total_fa_cnt += cck_fa_cnt; 668 dm_info->total_fa_cnt = ofdm_fa_cnt; 669 670 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 671 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 672 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 673 674 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 675 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 676 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 677 678 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 679 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 680 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 681 682 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 683 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 684 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 685 686 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 687 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 688 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 689 if (cck_enable) { 690 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 691 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 692 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 693 } 694 695 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 696 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 697 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 698 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 699 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 700 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 701 } 702 703 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 704 { 705 static int do_iqk_cnt; 706 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 707 u32 rf_reg, iqk_fail_mask; 708 int counter; 709 bool reload; 710 711 if (rtw_is_assoc(rtwdev)) 712 para.segment_iqk = 1; 713 714 rtw_fw_do_iqk(rtwdev, ¶); 715 716 for (counter = 0; counter < 300; counter++) { 717 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 718 if (rf_reg == 0xabcde) 719 break; 720 msleep(20); 721 } 722 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 723 724 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 725 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 726 rtw_dbg(rtwdev, RTW_DBG_PHY, 727 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 728 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 729 } 730 731 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 732 { 733 rtw8821c_do_iqk(rtwdev); 734 } 735 736 /* for coex */ 737 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 738 { 739 /* enable TBTT nterrupt */ 740 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 741 742 /* BT report packet sample rate */ 743 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 744 745 /* enable BT counter statistics */ 746 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 747 748 /* enable PTA (3-wire function form BT side) */ 749 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 750 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 751 752 /* enable PTA (tx/rx signal form WiFi side) */ 753 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 754 /* wl tx signal to PTA not case EDCCA */ 755 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 756 /* GNT_BT=1 while select both */ 757 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 758 759 /* beacon queue always hi-pri */ 760 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 761 BCN_PRI_EN); 762 } 763 764 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 765 u8 pos_type) 766 { 767 struct rtw_coex *coex = &rtwdev->coex; 768 struct rtw_coex_dm *coex_dm = &coex->dm; 769 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 770 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 771 bool polarity_inverse; 772 u8 regval = 0; 773 774 if (switch_status == coex_dm->cur_switch_status) 775 return; 776 777 coex_dm->cur_switch_status = switch_status; 778 779 if (coex_rfe->ant_switch_diversity && 780 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 781 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 782 783 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 784 785 switch (ctrl_type) { 786 default: 787 case COEX_SWITCH_CTRL_BY_BBSW: 788 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 789 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 790 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 791 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 792 DPDT_CTRL_PIN); 793 794 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 795 if (coex_rfe->rfe_module_type != 0x4 && 796 coex_rfe->rfe_module_type != 0x2) 797 regval = 0x3; 798 else 799 regval = (!polarity_inverse ? 0x2 : 0x1); 800 } else if (pos_type == COEX_SWITCH_TO_WLG) { 801 regval = (!polarity_inverse ? 0x2 : 0x1); 802 } else { 803 regval = (!polarity_inverse ? 0x1 : 0x2); 804 } 805 806 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 807 regval); 808 break; 809 case COEX_SWITCH_CTRL_BY_PTA: 810 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 811 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 812 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 813 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 814 PTA_CTRL_PIN); 815 816 regval = (!polarity_inverse ? 0x2 : 0x1); 817 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 818 regval); 819 break; 820 case COEX_SWITCH_CTRL_BY_ANTDIV: 821 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 822 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 823 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 824 ANTDIC_CTRL_PIN); 825 break; 826 case COEX_SWITCH_CTRL_BY_MAC: 827 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 828 829 regval = (!polarity_inverse ? 0x0 : 0x1); 830 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 831 regval); 832 break; 833 case COEX_SWITCH_CTRL_BY_FW: 834 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 835 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 836 break; 837 case COEX_SWITCH_CTRL_BY_BT: 838 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 839 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 840 break; 841 } 842 843 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 844 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 845 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 846 } else { 847 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 848 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 849 } 850 } 851 852 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 853 {} 854 855 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 856 { 857 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 858 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 859 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 860 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 861 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 862 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 863 } 864 865 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 866 { 867 struct rtw_coex *coex = &rtwdev->coex; 868 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 869 struct rtw_efuse *efuse = &rtwdev->efuse; 870 871 coex_rfe->rfe_module_type = efuse->rfe_option; 872 coex_rfe->ant_switch_polarity = 0; 873 coex_rfe->ant_switch_exist = true; 874 coex_rfe->wlg_at_btg = false; 875 876 switch (coex_rfe->rfe_module_type) { 877 case 0: 878 case 8: 879 case 1: 880 case 9: /* 1-Ant, Main, WLG */ 881 default: /* 2-Ant, DPDT, WLG */ 882 break; 883 case 2: 884 case 10: /* 1-Ant, Main, BTG */ 885 case 7: 886 case 15: /* 2-Ant, DPDT, BTG */ 887 coex_rfe->wlg_at_btg = true; 888 break; 889 case 3: 890 case 11: /* 1-Ant, Aux, WLG */ 891 coex_rfe->ant_switch_polarity = 1; 892 break; 893 case 4: 894 case 12: /* 1-Ant, Aux, BTG */ 895 coex_rfe->wlg_at_btg = true; 896 coex_rfe->ant_switch_polarity = 1; 897 break; 898 case 5: 899 case 13: /* 2-Ant, no switch, WLG */ 900 case 6: 901 case 14: /* 2-Ant, no antenna switch, WLG */ 902 coex_rfe->ant_switch_exist = false; 903 break; 904 } 905 } 906 907 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 908 { 909 struct rtw_coex *coex = &rtwdev->coex; 910 struct rtw_coex_dm *coex_dm = &coex->dm; 911 struct rtw_efuse *efuse = &rtwdev->efuse; 912 bool share_ant = efuse->share_ant; 913 914 if (share_ant) 915 return; 916 917 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 918 return; 919 920 coex_dm->cur_wl_pwr_lvl = wl_pwr; 921 } 922 923 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 924 {} 925 926 static void 927 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 928 s8 pwr_idx_offset_lower, 929 s8 *txagc_idx, u8 *swing_idx) 930 { 931 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 932 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 933 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 934 u8 swing_lower_bound = 0; 935 u8 max_pwr_idx_offset = 0xf; 936 s8 agc_index = 0; 937 u8 swing_index = dm_info->default_ofdm_index; 938 939 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 940 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 941 942 if (delta_pwr_idx >= 0) { 943 if (delta_pwr_idx <= pwr_idx_offset) { 944 agc_index = delta_pwr_idx; 945 swing_index = dm_info->default_ofdm_index; 946 } else if (delta_pwr_idx > pwr_idx_offset) { 947 agc_index = pwr_idx_offset; 948 swing_index = dm_info->default_ofdm_index + 949 delta_pwr_idx - pwr_idx_offset; 950 swing_index = min_t(u8, swing_index, swing_upper_bound); 951 } 952 } else if (delta_pwr_idx < 0) { 953 if (delta_pwr_idx >= pwr_idx_offset_lower) { 954 agc_index = delta_pwr_idx; 955 swing_index = dm_info->default_ofdm_index; 956 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 957 if (dm_info->default_ofdm_index > 958 (pwr_idx_offset_lower - delta_pwr_idx)) 959 swing_index = dm_info->default_ofdm_index + 960 delta_pwr_idx - pwr_idx_offset_lower; 961 else 962 swing_index = swing_lower_bound; 963 964 agc_index = pwr_idx_offset_lower; 965 } 966 } 967 968 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 969 rtw_warn(rtwdev, "swing index overflow\n"); 970 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 971 } 972 973 *txagc_idx = agc_index; 974 *swing_idx = swing_index; 975 } 976 977 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 978 s8 pwr_idx_offset_lower) 979 { 980 s8 txagc_idx; 981 u8 swing_idx; 982 983 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 984 &txagc_idx, &swing_idx); 985 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 986 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 987 rtw8821c_txscale_tbl[swing_idx]); 988 } 989 990 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 991 { 992 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 993 u8 pwr_idx_offset, tx_pwr_idx; 994 s8 pwr_idx_offset_lower; 995 u8 channel = rtwdev->hal.current_channel; 996 u8 band_width = rtwdev->hal.current_band_width; 997 u8 regd = rtw_regd_get(rtwdev); 998 u8 tx_rate = dm_info->tx_rate; 999 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1000 1001 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 1002 band_width, channel, regd); 1003 1004 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1005 1006 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1007 pwr_idx_offset_lower = 0 - tx_pwr_idx; 1008 1009 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 1010 } 1011 1012 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 1013 { 1014 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1015 struct rtw_swing_table swing_table; 1016 u8 thermal_value, delta; 1017 1018 rtw_phy_config_swing_table(rtwdev, &swing_table); 1019 1020 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1021 return; 1022 1023 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1024 1025 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1026 1027 if (dm_info->pwr_trk_init_trigger) 1028 dm_info->pwr_trk_init_trigger = false; 1029 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1030 RF_PATH_A)) 1031 goto iqk; 1032 1033 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1034 1035 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1036 1037 dm_info->delta_power_index[RF_PATH_A] = 1038 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 1039 RF_PATH_A, delta); 1040 if (dm_info->delta_power_index[RF_PATH_A] == 1041 dm_info->delta_power_index_last[RF_PATH_A]) 1042 goto iqk; 1043 else 1044 dm_info->delta_power_index_last[RF_PATH_A] = 1045 dm_info->delta_power_index[RF_PATH_A]; 1046 rtw8821c_pwrtrack_set(rtwdev); 1047 1048 iqk: 1049 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1050 rtw8821c_do_iqk(rtwdev); 1051 } 1052 1053 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 1054 { 1055 struct rtw_efuse *efuse = &rtwdev->efuse; 1056 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1057 1058 if (efuse->power_track_type != 0) 1059 return; 1060 1061 if (!dm_info->pwr_trk_triggered) { 1062 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1063 GENMASK(17, 16), 0x03); 1064 dm_info->pwr_trk_triggered = true; 1065 return; 1066 } 1067 1068 rtw8821c_phy_pwrtrack(rtwdev); 1069 dm_info->pwr_trk_triggered = false; 1070 } 1071 1072 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 1073 struct rtw_vif *vif, 1074 struct rtw_bfee *bfee, bool enable) 1075 { 1076 if (enable) 1077 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1078 else 1079 rtw_bf_remove_bfee_su(rtwdev, bfee); 1080 } 1081 1082 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1083 struct rtw_vif *vif, 1084 struct rtw_bfee *bfee, bool enable) 1085 { 1086 if (enable) 1087 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1088 else 1089 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1090 } 1091 1092 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1093 struct rtw_bfee *bfee, bool enable) 1094 { 1095 if (bfee->role == RTW_BFEE_SU) 1096 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1097 else if (bfee->role == RTW_BFEE_MU) 1098 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1099 else 1100 rtw_warn(rtwdev, "wrong bfee role\n"); 1101 } 1102 1103 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1104 { 1105 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1106 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1107 u8 cck_n_rx; 1108 1109 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1110 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1111 1112 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1113 return; 1114 1115 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1116 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1117 rtw_dbg(rtwdev, RTW_DBG_PHY, 1118 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1119 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1120 dm_info->cck_pd_default + new_lvl * 2, 1121 pd[new_lvl], dm_info->cck_fa_avg); 1122 1123 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1124 1125 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1126 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1127 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1128 dm_info->cck_pd_default + new_lvl * 2); 1129 } 1130 1131 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1132 {0x0086, 1133 RTW_PWR_CUT_ALL_MSK, 1134 RTW_PWR_INTF_SDIO_MSK, 1135 RTW_PWR_ADDR_SDIO, 1136 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1137 {0x0086, 1138 RTW_PWR_CUT_ALL_MSK, 1139 RTW_PWR_INTF_SDIO_MSK, 1140 RTW_PWR_ADDR_SDIO, 1141 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1142 {0x004A, 1143 RTW_PWR_CUT_ALL_MSK, 1144 RTW_PWR_INTF_USB_MSK, 1145 RTW_PWR_ADDR_MAC, 1146 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1147 {0x0005, 1148 RTW_PWR_CUT_ALL_MSK, 1149 RTW_PWR_INTF_ALL_MSK, 1150 RTW_PWR_ADDR_MAC, 1151 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1152 {0x0300, 1153 RTW_PWR_CUT_ALL_MSK, 1154 RTW_PWR_INTF_PCI_MSK, 1155 RTW_PWR_ADDR_MAC, 1156 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1157 {0x0301, 1158 RTW_PWR_CUT_ALL_MSK, 1159 RTW_PWR_INTF_PCI_MSK, 1160 RTW_PWR_ADDR_MAC, 1161 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1162 {0xFFFF, 1163 RTW_PWR_CUT_ALL_MSK, 1164 RTW_PWR_INTF_ALL_MSK, 1165 0, 1166 RTW_PWR_CMD_END, 0, 0}, 1167 }; 1168 1169 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1170 {0x0020, 1171 RTW_PWR_CUT_ALL_MSK, 1172 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1173 RTW_PWR_ADDR_MAC, 1174 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1175 {0x0001, 1176 RTW_PWR_CUT_ALL_MSK, 1177 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1178 RTW_PWR_ADDR_MAC, 1179 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1180 {0x0000, 1181 RTW_PWR_CUT_ALL_MSK, 1182 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1183 RTW_PWR_ADDR_MAC, 1184 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1185 {0x0005, 1186 RTW_PWR_CUT_ALL_MSK, 1187 RTW_PWR_INTF_ALL_MSK, 1188 RTW_PWR_ADDR_MAC, 1189 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1190 {0x0075, 1191 RTW_PWR_CUT_ALL_MSK, 1192 RTW_PWR_INTF_PCI_MSK, 1193 RTW_PWR_ADDR_MAC, 1194 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1195 {0x0006, 1196 RTW_PWR_CUT_ALL_MSK, 1197 RTW_PWR_INTF_ALL_MSK, 1198 RTW_PWR_ADDR_MAC, 1199 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1200 {0x0075, 1201 RTW_PWR_CUT_ALL_MSK, 1202 RTW_PWR_INTF_PCI_MSK, 1203 RTW_PWR_ADDR_MAC, 1204 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1205 {0x0006, 1206 RTW_PWR_CUT_ALL_MSK, 1207 RTW_PWR_INTF_ALL_MSK, 1208 RTW_PWR_ADDR_MAC, 1209 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1210 {0x0005, 1211 RTW_PWR_CUT_ALL_MSK, 1212 RTW_PWR_INTF_ALL_MSK, 1213 RTW_PWR_ADDR_MAC, 1214 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1215 {0x0005, 1216 RTW_PWR_CUT_ALL_MSK, 1217 RTW_PWR_INTF_ALL_MSK, 1218 RTW_PWR_ADDR_MAC, 1219 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1220 {0x10C3, 1221 RTW_PWR_CUT_ALL_MSK, 1222 RTW_PWR_INTF_USB_MSK, 1223 RTW_PWR_ADDR_MAC, 1224 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1225 {0x0005, 1226 RTW_PWR_CUT_ALL_MSK, 1227 RTW_PWR_INTF_ALL_MSK, 1228 RTW_PWR_ADDR_MAC, 1229 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1230 {0x0005, 1231 RTW_PWR_CUT_ALL_MSK, 1232 RTW_PWR_INTF_ALL_MSK, 1233 RTW_PWR_ADDR_MAC, 1234 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1235 {0x0020, 1236 RTW_PWR_CUT_ALL_MSK, 1237 RTW_PWR_INTF_ALL_MSK, 1238 RTW_PWR_ADDR_MAC, 1239 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1240 {0x0074, 1241 RTW_PWR_CUT_ALL_MSK, 1242 RTW_PWR_INTF_PCI_MSK, 1243 RTW_PWR_ADDR_MAC, 1244 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1245 {0x0022, 1246 RTW_PWR_CUT_ALL_MSK, 1247 RTW_PWR_INTF_PCI_MSK, 1248 RTW_PWR_ADDR_MAC, 1249 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1250 {0x0062, 1251 RTW_PWR_CUT_ALL_MSK, 1252 RTW_PWR_INTF_PCI_MSK, 1253 RTW_PWR_ADDR_MAC, 1254 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1255 (BIT(7) | BIT(6) | BIT(5))}, 1256 {0x0061, 1257 RTW_PWR_CUT_ALL_MSK, 1258 RTW_PWR_INTF_PCI_MSK, 1259 RTW_PWR_ADDR_MAC, 1260 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1261 {0x007C, 1262 RTW_PWR_CUT_ALL_MSK, 1263 RTW_PWR_INTF_ALL_MSK, 1264 RTW_PWR_ADDR_MAC, 1265 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1266 {0xFFFF, 1267 RTW_PWR_CUT_ALL_MSK, 1268 RTW_PWR_INTF_ALL_MSK, 1269 0, 1270 RTW_PWR_CMD_END, 0, 0}, 1271 }; 1272 1273 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1274 {0x0093, 1275 RTW_PWR_CUT_ALL_MSK, 1276 RTW_PWR_INTF_ALL_MSK, 1277 RTW_PWR_ADDR_MAC, 1278 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1279 {0x001F, 1280 RTW_PWR_CUT_ALL_MSK, 1281 RTW_PWR_INTF_ALL_MSK, 1282 RTW_PWR_ADDR_MAC, 1283 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1284 {0x0049, 1285 RTW_PWR_CUT_ALL_MSK, 1286 RTW_PWR_INTF_ALL_MSK, 1287 RTW_PWR_ADDR_MAC, 1288 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1289 {0x0006, 1290 RTW_PWR_CUT_ALL_MSK, 1291 RTW_PWR_INTF_ALL_MSK, 1292 RTW_PWR_ADDR_MAC, 1293 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1294 {0x0002, 1295 RTW_PWR_CUT_ALL_MSK, 1296 RTW_PWR_INTF_ALL_MSK, 1297 RTW_PWR_ADDR_MAC, 1298 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1299 {0x10C3, 1300 RTW_PWR_CUT_ALL_MSK, 1301 RTW_PWR_INTF_USB_MSK, 1302 RTW_PWR_ADDR_MAC, 1303 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1304 {0x0005, 1305 RTW_PWR_CUT_ALL_MSK, 1306 RTW_PWR_INTF_ALL_MSK, 1307 RTW_PWR_ADDR_MAC, 1308 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1309 {0x0005, 1310 RTW_PWR_CUT_ALL_MSK, 1311 RTW_PWR_INTF_ALL_MSK, 1312 RTW_PWR_ADDR_MAC, 1313 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1314 {0x0020, 1315 RTW_PWR_CUT_ALL_MSK, 1316 RTW_PWR_INTF_ALL_MSK, 1317 RTW_PWR_ADDR_MAC, 1318 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1319 {0x0000, 1320 RTW_PWR_CUT_ALL_MSK, 1321 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1322 RTW_PWR_ADDR_MAC, 1323 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1324 {0xFFFF, 1325 RTW_PWR_CUT_ALL_MSK, 1326 RTW_PWR_INTF_ALL_MSK, 1327 0, 1328 RTW_PWR_CMD_END, 0, 0}, 1329 }; 1330 1331 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1332 {0x0007, 1333 RTW_PWR_CUT_ALL_MSK, 1334 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1335 RTW_PWR_ADDR_MAC, 1336 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1337 {0x0067, 1338 RTW_PWR_CUT_ALL_MSK, 1339 RTW_PWR_INTF_ALL_MSK, 1340 RTW_PWR_ADDR_MAC, 1341 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1342 {0x0005, 1343 RTW_PWR_CUT_ALL_MSK, 1344 RTW_PWR_INTF_PCI_MSK, 1345 RTW_PWR_ADDR_MAC, 1346 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1347 {0x004A, 1348 RTW_PWR_CUT_ALL_MSK, 1349 RTW_PWR_INTF_USB_MSK, 1350 RTW_PWR_ADDR_MAC, 1351 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1352 {0x0067, 1353 RTW_PWR_CUT_ALL_MSK, 1354 RTW_PWR_INTF_SDIO_MSK, 1355 RTW_PWR_ADDR_MAC, 1356 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1357 {0x0067, 1358 RTW_PWR_CUT_ALL_MSK, 1359 RTW_PWR_INTF_SDIO_MSK, 1360 RTW_PWR_ADDR_MAC, 1361 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1362 {0x004F, 1363 RTW_PWR_CUT_ALL_MSK, 1364 RTW_PWR_INTF_SDIO_MSK, 1365 RTW_PWR_ADDR_MAC, 1366 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1367 {0x0067, 1368 RTW_PWR_CUT_ALL_MSK, 1369 RTW_PWR_INTF_SDIO_MSK, 1370 RTW_PWR_ADDR_MAC, 1371 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1372 {0x0046, 1373 RTW_PWR_CUT_ALL_MSK, 1374 RTW_PWR_INTF_SDIO_MSK, 1375 RTW_PWR_ADDR_MAC, 1376 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1377 {0x0067, 1378 RTW_PWR_CUT_ALL_MSK, 1379 RTW_PWR_INTF_SDIO_MSK, 1380 RTW_PWR_ADDR_MAC, 1381 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1382 {0x0046, 1383 RTW_PWR_CUT_ALL_MSK, 1384 RTW_PWR_INTF_SDIO_MSK, 1385 RTW_PWR_ADDR_MAC, 1386 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1387 {0x0062, 1388 RTW_PWR_CUT_ALL_MSK, 1389 RTW_PWR_INTF_SDIO_MSK, 1390 RTW_PWR_ADDR_MAC, 1391 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1392 {0x0081, 1393 RTW_PWR_CUT_ALL_MSK, 1394 RTW_PWR_INTF_ALL_MSK, 1395 RTW_PWR_ADDR_MAC, 1396 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1397 {0x0005, 1398 RTW_PWR_CUT_ALL_MSK, 1399 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1400 RTW_PWR_ADDR_MAC, 1401 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1402 {0x0086, 1403 RTW_PWR_CUT_ALL_MSK, 1404 RTW_PWR_INTF_SDIO_MSK, 1405 RTW_PWR_ADDR_SDIO, 1406 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1407 {0x0086, 1408 RTW_PWR_CUT_ALL_MSK, 1409 RTW_PWR_INTF_SDIO_MSK, 1410 RTW_PWR_ADDR_SDIO, 1411 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1412 {0x0090, 1413 RTW_PWR_CUT_ALL_MSK, 1414 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1415 RTW_PWR_ADDR_MAC, 1416 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1417 {0x0044, 1418 RTW_PWR_CUT_ALL_MSK, 1419 RTW_PWR_INTF_SDIO_MSK, 1420 RTW_PWR_ADDR_SDIO, 1421 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1422 {0x0040, 1423 RTW_PWR_CUT_ALL_MSK, 1424 RTW_PWR_INTF_SDIO_MSK, 1425 RTW_PWR_ADDR_SDIO, 1426 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1427 {0x0041, 1428 RTW_PWR_CUT_ALL_MSK, 1429 RTW_PWR_INTF_SDIO_MSK, 1430 RTW_PWR_ADDR_SDIO, 1431 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1432 {0x0042, 1433 RTW_PWR_CUT_ALL_MSK, 1434 RTW_PWR_INTF_SDIO_MSK, 1435 RTW_PWR_ADDR_SDIO, 1436 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1437 {0xFFFF, 1438 RTW_PWR_CUT_ALL_MSK, 1439 RTW_PWR_INTF_ALL_MSK, 1440 0, 1441 RTW_PWR_CMD_END, 0, 0}, 1442 }; 1443 1444 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1445 trans_carddis_to_cardemu_8821c, 1446 trans_cardemu_to_act_8821c, 1447 NULL 1448 }; 1449 1450 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1451 trans_act_to_cardemu_8821c, 1452 trans_cardemu_to_carddis_8821c, 1453 NULL 1454 }; 1455 1456 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1457 {0xFFFF, 0x00, 1458 RTW_IP_SEL_PHY, 1459 RTW_INTF_PHY_CUT_ALL, 1460 RTW_INTF_PHY_PLATFORM_ALL}, 1461 }; 1462 1463 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1464 {0xFFFF, 0x0000, 1465 RTW_IP_SEL_PHY, 1466 RTW_INTF_PHY_CUT_ALL, 1467 RTW_INTF_PHY_PLATFORM_ALL}, 1468 }; 1469 1470 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1471 {0x0009, 0x6380, 1472 RTW_IP_SEL_PHY, 1473 RTW_INTF_PHY_CUT_ALL, 1474 RTW_INTF_PHY_PLATFORM_ALL}, 1475 {0xFFFF, 0x0000, 1476 RTW_IP_SEL_PHY, 1477 RTW_INTF_PHY_CUT_ALL, 1478 RTW_INTF_PHY_PLATFORM_ALL}, 1479 }; 1480 1481 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1482 {0xFFFF, 0x0000, 1483 RTW_IP_SEL_PHY, 1484 RTW_INTF_PHY_CUT_ALL, 1485 RTW_INTF_PHY_PLATFORM_ALL}, 1486 }; 1487 1488 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1489 .usb2_para = usb2_param_8821c, 1490 .usb3_para = usb3_param_8821c, 1491 .gen1_para = pcie_gen1_param_8821c, 1492 .gen2_para = pcie_gen2_param_8821c, 1493 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1494 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1495 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1496 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1497 }; 1498 1499 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1500 [0] = RTW_DEF_RFE(8821c, 0, 0), 1501 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1502 }; 1503 1504 static struct rtw_hw_reg rtw8821c_dig[] = { 1505 [0] = { .addr = 0xc50, .mask = 0x7f }, 1506 }; 1507 1508 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1509 .ctrl = LTECOEX_ACCESS_CTRL, 1510 .wdata = LTECOEX_WRITE_DATA, 1511 .rdata = LTECOEX_READ_DATA, 1512 }; 1513 1514 static struct rtw_page_table page_table_8821c[] = { 1515 /* not sure what [0] stands for */ 1516 {16, 16, 16, 14, 1}, 1517 {16, 16, 16, 14, 1}, 1518 {16, 16, 0, 0, 1}, 1519 {16, 16, 16, 0, 1}, 1520 {16, 16, 16, 14, 1}, 1521 }; 1522 1523 static struct rtw_rqpn rqpn_table_8821c[] = { 1524 /* not sure what [0] stands for */ 1525 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1526 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1527 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1528 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1529 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1530 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1531 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1532 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1533 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1534 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1535 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1536 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1537 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1538 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1539 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1540 }; 1541 1542 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1543 .prio[RTW_DMA_MAPPING_EXTRA] = { 1544 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1545 }, 1546 .prio[RTW_DMA_MAPPING_LOW] = { 1547 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1548 }, 1549 .prio[RTW_DMA_MAPPING_NORMAL] = { 1550 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1551 }, 1552 .prio[RTW_DMA_MAPPING_HIGH] = { 1553 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1554 }, 1555 .wsize = true, 1556 }; 1557 1558 static struct rtw_chip_ops rtw8821c_ops = { 1559 .phy_set_param = rtw8821c_phy_set_param, 1560 .read_efuse = rtw8821c_read_efuse, 1561 .query_rx_desc = rtw8821c_query_rx_desc, 1562 .set_channel = rtw8821c_set_channel, 1563 .mac_init = rtw8821c_mac_init, 1564 .read_rf = rtw_phy_read_rf, 1565 .write_rf = rtw_phy_write_rf_reg_sipi, 1566 .set_antenna = NULL, 1567 .set_tx_power_index = rtw8821c_set_tx_power_index, 1568 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1569 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1570 .phy_calibration = rtw8821c_phy_calibration, 1571 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1572 .pwr_track = rtw8821c_pwr_track, 1573 .config_bfee = rtw8821c_bf_config_bfee, 1574 .set_gid_table = rtw_bf_set_gid_table, 1575 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1576 1577 .coex_set_init = rtw8821c_coex_cfg_init, 1578 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1579 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1580 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1581 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1582 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1583 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1584 }; 1585 1586 /* rssi in percentage % (dbm = % - 100) */ 1587 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1588 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1589 1590 /* Shared-Antenna Coex Table */ 1591 static const struct coex_table_para table_sant_8821c[] = { 1592 {0x55555555, 0x55555555}, /* case-0 */ 1593 {0x55555555, 0x55555555}, 1594 {0x66555555, 0x66555555}, 1595 {0xaaaaaaaa, 0xaaaaaaaa}, 1596 {0x5a5a5a5a, 0x5a5a5a5a}, 1597 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1598 {0x6a5a5555, 0xaaaaaaaa}, 1599 {0x6a5a56aa, 0x6a5a56aa}, 1600 {0x6a5a5a5a, 0x6a5a5a5a}, 1601 {0x66555555, 0x5a5a5a5a}, 1602 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1603 {0x66555555, 0xaaaaaaaa}, 1604 {0x66555555, 0x6a5a5aaa}, 1605 {0x66555555, 0x6aaa6aaa}, 1606 {0x66555555, 0x6a5a5aaa}, 1607 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1608 {0xffff55ff, 0xfafafafa}, 1609 {0xffff55ff, 0x6afa5afa}, 1610 {0xaaffffaa, 0xfafafafa}, 1611 {0xaa5555aa, 0x5a5a5a5a}, 1612 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1613 {0xaa5555aa, 0xaaaaaaaa}, 1614 {0xffffffff, 0x55555555}, 1615 {0xffffffff, 0x5a5a5a5a}, 1616 {0xffffffff, 0x5a5a5a5a}, 1617 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1618 {0x55555555, 0x5a5a5a5a}, 1619 {0x55555555, 0xaaaaaaaa}, 1620 {0x66555555, 0x6a5a6a5a}, 1621 {0x66556655, 0x66556655}, 1622 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1623 {0xffffffff, 0x5aaa5aaa}, 1624 {0x56555555, 0x5a5a5aaa} 1625 }; 1626 1627 /* Non-Shared-Antenna Coex Table */ 1628 static const struct coex_table_para table_nsant_8821c[] = { 1629 {0xffffffff, 0xffffffff}, /* case-100 */ 1630 {0xffff55ff, 0xfafafafa}, 1631 {0x66555555, 0x66555555}, 1632 {0xaaaaaaaa, 0xaaaaaaaa}, 1633 {0x5a5a5a5a, 0x5a5a5a5a}, 1634 {0xffffffff, 0xffffffff}, /* case-105 */ 1635 {0x5afa5afa, 0x5afa5afa}, 1636 {0x55555555, 0xfafafafa}, 1637 {0x66555555, 0xfafafafa}, 1638 {0x66555555, 0x5a5a5a5a}, 1639 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1640 {0x66555555, 0xaaaaaaaa}, 1641 {0xffff55ff, 0xfafafafa}, 1642 {0xffff55ff, 0x5afa5afa}, 1643 {0xffff55ff, 0xaaaaaaaa}, 1644 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1645 {0xaaffffaa, 0x5afa5afa}, 1646 {0xaaffffaa, 0xaaaaaaaa}, 1647 {0xffffffff, 0xfafafafa}, 1648 {0xffff55ff, 0xfafafafa}, 1649 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1650 {0xffff55ff, 0x5afa5afa}, 1651 {0xffff55ff, 0x5afa5afa}, 1652 {0x55ff55ff, 0x55ff55ff} 1653 }; 1654 1655 /* Shared-Antenna TDMA */ 1656 static const struct coex_tdma_para tdma_sant_8821c[] = { 1657 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1658 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1659 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1660 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1661 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1662 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1663 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1664 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1665 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1666 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1667 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1668 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1669 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1670 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1671 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1672 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1673 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1674 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1675 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1676 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1677 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1678 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1679 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1680 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1681 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1682 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1683 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1684 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1685 }; 1686 1687 /* Non-Shared-Antenna TDMA */ 1688 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1689 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1690 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1691 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1692 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1693 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1694 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1695 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1696 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1697 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1698 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1699 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1700 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1701 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1702 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1703 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1704 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1705 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1706 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1707 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1708 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1709 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1710 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1711 }; 1712 1713 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1714 1715 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1716 static const struct coex_rf_para rf_para_tx_8821c[] = { 1717 {0, 0, false, 7}, /* for normal */ 1718 {0, 20, false, 7}, /* for WL-CPT */ 1719 {8, 17, true, 4}, 1720 {7, 18, true, 4}, 1721 {6, 19, true, 4}, 1722 {5, 20, true, 4} 1723 }; 1724 1725 static const struct coex_rf_para rf_para_rx_8821c[] = { 1726 {0, 0, false, 7}, /* for normal */ 1727 {0, 20, false, 7}, /* for WL-CPT */ 1728 {3, 24, true, 5}, 1729 {2, 26, true, 5}, 1730 {1, 27, true, 5}, 1731 {0, 28, true, 5} 1732 }; 1733 1734 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1735 1736 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1737 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1738 11, 11, 12, 12, 12, 12, 12}, 1739 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1740 11, 12, 12, 12, 12, 12, 12, 12}, 1741 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1742 11, 12, 12, 12, 12, 12, 12}, 1743 }; 1744 1745 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1746 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1747 12, 12, 12, 12, 12, 12, 12}, 1748 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1749 12, 12, 12, 12, 12, 12, 12, 12}, 1750 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1751 11, 12, 12, 12, 12, 12, 12, 12}, 1752 }; 1753 1754 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1755 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1756 11, 11, 12, 12, 12, 12, 12}, 1757 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1758 11, 12, 12, 12, 12, 12, 12, 12}, 1759 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1760 11, 12, 12, 12, 12, 12, 12}, 1761 }; 1762 1763 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1764 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1765 12, 12, 12, 12, 12, 12, 12}, 1766 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1767 12, 12, 12, 12, 12, 12, 12, 12}, 1768 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1769 11, 12, 12, 12, 12, 12, 12, 12}, 1770 }; 1771 1772 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1773 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1774 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1775 }; 1776 1777 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1778 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1779 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1780 }; 1781 1782 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1783 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1784 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1785 }; 1786 1787 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1788 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1789 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1790 }; 1791 1792 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1793 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1794 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1795 }; 1796 1797 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1798 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1799 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1800 }; 1801 1802 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1803 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1804 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1805 }; 1806 1807 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1808 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1809 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1810 }; 1811 1812 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1813 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1814 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1815 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1816 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1817 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1818 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1819 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1820 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1821 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1822 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1823 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1824 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1825 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1826 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1827 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1828 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1829 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1830 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1831 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1832 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1833 }; 1834 1835 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1836 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1837 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1838 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1839 {0, 0, RTW_REG_DOMAIN_NL}, 1840 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1841 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1842 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1843 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1844 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1845 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1846 {0, 0, RTW_REG_DOMAIN_NL}, 1847 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1848 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1849 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1850 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1851 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1852 {0, 0, RTW_REG_DOMAIN_NL}, 1853 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1854 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1855 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1856 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1857 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1858 }; 1859 1860 struct rtw_chip_info rtw8821c_hw_spec = { 1861 .ops = &rtw8821c_ops, 1862 .id = RTW_CHIP_TYPE_8821C, 1863 .fw_name = "rtw88/rtw8821c_fw.bin", 1864 .wlan_cpu = RTW_WCPU_11AC, 1865 .tx_pkt_desc_sz = 48, 1866 .tx_buf_desc_sz = 16, 1867 .rx_pkt_desc_sz = 24, 1868 .rx_buf_desc_sz = 8, 1869 .phy_efuse_size = 512, 1870 .log_efuse_size = 512, 1871 .ptct_efuse_size = 96, 1872 .txff_size = 65536, 1873 .rxff_size = 16384, 1874 .txgi_factor = 1, 1875 .is_pwr_by_rate_dec = true, 1876 .max_power_index = 0x3f, 1877 .csi_buf_pg_num = 0, 1878 .band = RTW_BAND_2G | RTW_BAND_5G, 1879 .page_size = 128, 1880 .dig_min = 0x1c, 1881 .ht_supported = true, 1882 .vht_supported = true, 1883 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1884 .sys_func_en = 0xD8, 1885 .pwr_on_seq = card_enable_flow_8821c, 1886 .pwr_off_seq = card_disable_flow_8821c, 1887 .page_table = page_table_8821c, 1888 .rqpn_table = rqpn_table_8821c, 1889 .prioq_addrs = &prioq_addrs_8821c, 1890 .intf_table = &phy_para_table_8821c, 1891 .dig = rtw8821c_dig, 1892 .rf_base_addr = {0x2800, 0x2c00}, 1893 .rf_sipi_addr = {0xc90, 0xe90}, 1894 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1895 .mac_tbl = &rtw8821c_mac_tbl, 1896 .agc_tbl = &rtw8821c_agc_tbl, 1897 .bb_tbl = &rtw8821c_bb_tbl, 1898 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1899 .rfe_defs = rtw8821c_rfe_defs, 1900 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1901 .rx_ldpc = false, 1902 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1903 .iqk_threshold = 8, 1904 .bfer_su_max_num = 2, 1905 .bfer_mu_max_num = 1, 1906 1907 .coex_para_ver = 0x19092746, 1908 .bt_desired_ver = 0x46, 1909 .scbd_support = true, 1910 .new_scbd10_def = false, 1911 .ble_hid_profile_support = false, 1912 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1913 .bt_rssi_type = COEX_BTRSSI_RATIO, 1914 .ant_isolation = 15, 1915 .rssi_tolerance = 2, 1916 .wl_rssi_step = wl_rssi_step_8821c, 1917 .bt_rssi_step = bt_rssi_step_8821c, 1918 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 1919 .table_sant = table_sant_8821c, 1920 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 1921 .table_nsant = table_nsant_8821c, 1922 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 1923 .tdma_sant = tdma_sant_8821c, 1924 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 1925 .tdma_nsant = tdma_nsant_8821c, 1926 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 1927 .wl_rf_para_tx = rf_para_tx_8821c, 1928 .wl_rf_para_rx = rf_para_rx_8821c, 1929 .bt_afh_span_bw20 = 0x24, 1930 .bt_afh_span_bw40 = 0x36, 1931 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 1932 .afh_5g = afh_5g_8821c, 1933 1934 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 1935 .coex_info_hw_regs = coex_info_hw_regs_8821c, 1936 }; 1937 EXPORT_SYMBOL(rtw8821c_hw_spec); 1938 1939 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 1940 1941 MODULE_AUTHOR("Realtek Corporation"); 1942 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 1943 MODULE_LICENSE("Dual BSD/GPL"); 1944