1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 #include "regd.h" 18 19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; 20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, 21 -20, -24, -28, -31, -34, -37, -40, -44}; 22 23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8821c_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse, 30 struct rtw8821c_efuse *map) 31 { 32 ether_addr_copy(efuse->addr, map->u.mac_addr); 33 } 34 35 static void rtw8821cs_efuse_parsing(struct rtw_efuse *efuse, 36 struct rtw8821c_efuse *map) 37 { 38 ether_addr_copy(efuse->addr, map->s.mac_addr); 39 } 40 41 enum rtw8821ce_rf_set { 42 SWITCH_TO_BTG, 43 SWITCH_TO_WLG, 44 SWITCH_TO_WLA, 45 SWITCH_TO_BT, 46 }; 47 48 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 49 { 50 struct rtw_hal *hal = &rtwdev->hal; 51 struct rtw_efuse *efuse = &rtwdev->efuse; 52 struct rtw8821c_efuse *map; 53 int i; 54 55 map = (struct rtw8821c_efuse *)log_map; 56 57 efuse->rfe_option = map->rfe_option & 0x1f; 58 efuse->rf_board_option = map->rf_board_option; 59 efuse->crystal_cap = map->xtal_k; 60 efuse->pa_type_2g = map->pa_type; 61 efuse->pa_type_5g = map->pa_type; 62 efuse->lna_type_2g = map->lna_type_2g[0]; 63 efuse->lna_type_5g = map->lna_type_5g[0]; 64 efuse->channel_plan = map->channel_plan; 65 efuse->country_code[0] = map->country_code[0]; 66 efuse->country_code[1] = map->country_code[1]; 67 efuse->bt_setting = map->rf_bt_setting; 68 efuse->regd = map->rf_board_option & 0x7; 69 efuse->thermal_meter[0] = map->thermal_meter; 70 efuse->thermal_meter_k = map->thermal_meter; 71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 73 74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; 75 76 switch (efuse->rfe_option) { 77 case 0x2: 78 case 0x4: 79 case 0x7: 80 case 0xa: 81 case 0xc: 82 case 0xf: 83 hal->rfe_btg = true; 84 break; 85 } 86 87 for (i = 0; i < 4; i++) 88 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 89 90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) 91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; 92 93 switch (rtw_hci_type(rtwdev)) { 94 case RTW_HCI_TYPE_PCIE: 95 rtw8821ce_efuse_parsing(efuse, map); 96 break; 97 case RTW_HCI_TYPE_USB: 98 rtw8821cu_efuse_parsing(efuse, map); 99 break; 100 case RTW_HCI_TYPE_SDIO: 101 rtw8821cs_efuse_parsing(efuse, map); 102 break; 103 default: 104 /* unsupported now */ 105 return -ENOTSUPP; 106 } 107 108 return 0; 109 } 110 111 static const u32 rtw8821c_txscale_tbl[] = { 112 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 113 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 114 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 115 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 116 }; 117 118 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 119 { 120 u8 i = 0; 121 u32 swing, table_value; 122 123 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 124 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 125 table_value = rtw8821c_txscale_tbl[i]; 126 if (swing == table_value) 127 break; 128 } 129 130 return i; 131 } 132 133 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 134 { 135 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 136 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 137 138 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 139 dm_info->default_ofdm_index = 24; 140 else 141 dm_info->default_ofdm_index = swing_idx; 142 143 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 144 dm_info->delta_power_index[RF_PATH_A] = 0; 145 dm_info->delta_power_index_last[RF_PATH_A] = 0; 146 dm_info->pwr_trk_triggered = false; 147 dm_info->pwr_trk_init_trigger = true; 148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 149 } 150 151 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 152 { 153 rtw_bf_phy_init(rtwdev); 154 /* Grouping bitmap parameters */ 155 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 156 } 157 158 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 159 { 160 struct rtw_hal *hal = &rtwdev->hal; 161 u8 crystal_cap, val; 162 163 /* power on BB/RF domain */ 164 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 165 val |= BIT_FEN_PCIEA; 166 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 167 168 /* toggle BB reset */ 169 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 170 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 171 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 172 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 173 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 174 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 175 176 rtw_write8(rtwdev, REG_RF_CTRL, 177 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 178 usleep_range(10, 11); 179 rtw_write8(rtwdev, REG_WLRF1 + 3, 180 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 181 usleep_range(10, 11); 182 183 /* pre init before header files config */ 184 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 185 186 rtw_phy_load_tables(rtwdev); 187 188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 192 193 /* post init after header files config */ 194 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 198 199 rtw_phy_init(rtwdev); 200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 201 202 rtw8821c_pwrtrack_init(rtwdev); 203 204 rtw8821c_phy_bf_init(rtwdev); 205 } 206 207 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 208 { 209 u32 value32; 210 u16 pre_txcnt; 211 212 /* protocol configuration */ 213 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 214 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 215 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 216 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 217 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 218 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 219 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 220 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 221 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 222 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 223 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 224 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 225 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 226 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 227 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 229 230 /* EDCA configuration */ 231 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 232 rtw_write16(rtwdev, REG_TXPAUSE, 0); 233 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 234 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 235 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 236 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 237 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 238 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 239 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 240 241 /* Set beacon cotnrol - enable TSF and other related functions */ 242 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 243 244 /* Set send beacon related registers */ 245 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 246 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 247 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 248 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 249 250 /* WMAC configuration */ 251 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 252 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 253 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 254 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 255 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 256 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 257 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 259 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 260 BIT_DIS_CHK_VHTSIGB_CRC); 261 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 262 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 263 264 return 0; 265 } 266 267 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 268 { 269 u8 ldo_pwr; 270 271 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 273 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 274 } 275 276 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) 277 { 278 u32 reg; 279 280 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST); 281 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN); 282 283 reg = rtw_read32(rtwdev, REG_RFECTL); 284 switch (rf_set) { 285 case SWITCH_TO_BTG: 286 reg |= B_BTG_SWITCH; 287 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH | 288 B_WLA_SWITCH); 289 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); 290 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); 291 break; 292 case SWITCH_TO_WLG: 293 reg |= B_WL_SWITCH | B_WLG_SWITCH; 294 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH); 295 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); 296 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); 297 break; 298 case SWITCH_TO_WLA: 299 reg |= B_WL_SWITCH | B_WLA_SWITCH; 300 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH); 301 break; 302 case SWITCH_TO_BT: 303 default: 304 break; 305 } 306 307 rtw_write32(rtwdev, REG_RFECTL, reg); 308 } 309 310 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 311 { 312 struct rtw_hal *hal = &rtwdev->hal; 313 u32 rf_reg18; 314 315 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 316 317 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 318 RF18_BW_MASK); 319 320 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 321 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 322 323 if (channel >= 100 && channel <= 140) 324 rf_reg18 |= RF18_RFSI_GE; 325 else if (channel > 140) 326 rf_reg18 |= RF18_RFSI_GT; 327 328 switch (bw) { 329 case RTW_CHANNEL_WIDTH_5: 330 case RTW_CHANNEL_WIDTH_10: 331 case RTW_CHANNEL_WIDTH_20: 332 default: 333 rf_reg18 |= RF18_BW_20M; 334 break; 335 case RTW_CHANNEL_WIDTH_40: 336 rf_reg18 |= RF18_BW_40M; 337 break; 338 case RTW_CHANNEL_WIDTH_80: 339 rf_reg18 |= RF18_BW_80M; 340 break; 341 } 342 343 if (channel <= 14) { 344 if (hal->rfe_btg) 345 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG); 346 else 347 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG); 348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 349 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 350 } else { 351 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA); 352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 353 } 354 355 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 356 357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 359 } 360 361 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 362 { 363 if (bw == RTW_CHANNEL_WIDTH_40) { 364 /* RX DFIR for BW40 */ 365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 369 } else if (bw == RTW_CHANNEL_WIDTH_80) { 370 /* RX DFIR for BW80 */ 371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 375 } else { 376 /* RX DFIR for BW20, BW10 and BW5 */ 377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 381 } 382 } 383 384 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 385 u8 primary_ch_idx) 386 { 387 struct rtw_hal *hal = &rtwdev->hal; 388 u32 val32; 389 390 if (channel <= 14) { 391 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 392 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 393 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 394 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 395 396 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 397 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 398 if (channel == 14) { 399 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 400 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 401 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 402 } else { 403 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 404 hal->ch_param[0]); 405 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 406 hal->ch_param[1] & MASKLWORD); 407 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 408 hal->ch_param[2]); 409 } 410 } else if (channel > 35) { 411 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 412 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 413 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 414 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 415 416 if (channel >= 36 && channel <= 64) 417 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 418 else if (channel >= 100 && channel <= 144) 419 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 420 else if (channel >= 149) 421 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 422 423 if (channel >= 36 && channel <= 48) 424 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 425 else if (channel >= 52 && channel <= 64) 426 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 427 else if (channel >= 100 && channel <= 116) 428 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 429 else if (channel >= 118 && channel <= 177) 430 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 431 } 432 433 switch (bw) { 434 case RTW_CHANNEL_WIDTH_20: 435 default: 436 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 437 val32 &= 0xffcffc00; 438 val32 |= 0x10010000; 439 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 440 441 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 442 break; 443 case RTW_CHANNEL_WIDTH_40: 444 if (primary_ch_idx == 1) 445 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 446 else 447 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 448 449 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 450 val32 &= 0xff3ff300; 451 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 452 RTW_CHANNEL_WIDTH_40; 453 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 454 455 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 456 break; 457 case RTW_CHANNEL_WIDTH_80: 458 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 459 val32 &= 0xfcffcf00; 460 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 461 RTW_CHANNEL_WIDTH_80; 462 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 463 464 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 465 break; 466 case RTW_CHANNEL_WIDTH_5: 467 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 468 val32 &= 0xefcefc00; 469 val32 |= 0x200240; 470 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 471 472 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 473 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 474 break; 475 case RTW_CHANNEL_WIDTH_10: 476 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 477 val32 &= 0xefcefc00; 478 val32 |= 0x300380; 479 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 480 481 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 482 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 483 break; 484 } 485 } 486 487 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 488 { 489 struct rtw_efuse efuse = rtwdev->efuse; 490 u8 tx_bb_swing; 491 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 492 493 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 494 efuse.tx_bb_swing_setting_5g; 495 if (tx_bb_swing > 9) 496 tx_bb_swing = 0; 497 498 return swing2setting[(tx_bb_swing / 3)]; 499 } 500 501 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 502 u8 bw, u8 primary_ch_idx) 503 { 504 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 505 rtw8821c_get_bb_swing(rtwdev, channel)); 506 rtw8821c_pwrtrack_init(rtwdev); 507 } 508 509 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 510 u8 primary_chan_idx) 511 { 512 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 513 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 514 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 515 rtw8821c_set_channel_rf(rtwdev, channel, bw); 516 rtw8821c_set_channel_rxdfir(rtwdev, bw); 517 } 518 519 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 520 { 521 struct rtw_efuse *efuse = &rtwdev->efuse; 522 const s8 *lna_gain_table; 523 int lna_gain_table_size; 524 s8 rx_pwr_all = 0; 525 s8 lna_gain = 0; 526 527 if (efuse->rfe_option == 0) { 528 lna_gain_table = lna_gain_table_0; 529 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0); 530 } else { 531 lna_gain_table = lna_gain_table_1; 532 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1); 533 } 534 535 if (lna_idx >= lna_gain_table_size) { 536 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 537 return -120; 538 } 539 540 lna_gain = lna_gain_table[lna_idx]; 541 rx_pwr_all = lna_gain - 2 * vga_idx; 542 543 return rx_pwr_all; 544 } 545 546 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 547 struct rtw_rx_pkt_stat *pkt_stat) 548 { 549 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 550 s8 rx_power; 551 u8 lna_idx = 0; 552 u8 vga_idx = 0; 553 554 vga_idx = GET_PHY_STAT_P0_VGA(phy_status); 555 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) | 556 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status)); 557 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 558 559 pkt_stat->rx_power[RF_PATH_A] = rx_power; 560 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 561 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 562 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 563 pkt_stat->signal_power = rx_power; 564 } 565 566 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 567 struct rtw_rx_pkt_stat *pkt_stat) 568 { 569 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 570 u8 rxsc, bw; 571 s8 min_rx_power = -120; 572 573 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 574 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 575 else 576 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 577 578 if (rxsc >= 1 && rxsc <= 8) 579 bw = RTW_CHANNEL_WIDTH_20; 580 else if (rxsc >= 9 && rxsc <= 12) 581 bw = RTW_CHANNEL_WIDTH_40; 582 else if (rxsc >= 13) 583 bw = RTW_CHANNEL_WIDTH_80; 584 else 585 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 586 587 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 588 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 589 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 590 pkt_stat->bw = bw; 591 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 592 min_rx_power); 593 } 594 595 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 596 struct rtw_rx_pkt_stat *pkt_stat) 597 { 598 u8 page; 599 600 page = *phy_status & 0xf; 601 602 switch (page) { 603 case 0: 604 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 605 break; 606 case 1: 607 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 608 break; 609 default: 610 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 611 return; 612 } 613 } 614 615 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 616 struct rtw_rx_pkt_stat *pkt_stat, 617 struct ieee80211_rx_status *rx_status) 618 { 619 struct ieee80211_hdr *hdr; 620 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 621 u8 *phy_status = NULL; 622 623 memset(pkt_stat, 0, sizeof(*pkt_stat)); 624 625 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 626 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 627 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 628 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 629 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 630 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 631 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 632 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 633 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 634 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 635 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 636 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 637 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 638 639 /* drv_info_sz is in unit of 8-bytes */ 640 pkt_stat->drv_info_sz *= 8; 641 642 /* c2h cmd pkt's rx/phy status is not interested */ 643 if (pkt_stat->is_c2h) 644 return; 645 646 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 647 pkt_stat->drv_info_sz); 648 if (pkt_stat->phy_status) { 649 phy_status = rx_desc + desc_sz + pkt_stat->shift; 650 query_phy_status(rtwdev, phy_status, pkt_stat); 651 } 652 653 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 654 } 655 656 static void 657 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 658 { 659 struct rtw_hal *hal = &rtwdev->hal; 660 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 661 static u32 phy_pwr_idx; 662 u8 rate, rate_idx, pwr_index, shift; 663 int j; 664 665 for (j = 0; j < rtw_rate_size[rs]; j++) { 666 rate = rtw_rate_section[rs][j]; 667 pwr_index = hal->tx_pwr_tbl[path][rate]; 668 shift = rate & 0x3; 669 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 670 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 671 rate_idx = rate & 0xfc; 672 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 673 phy_pwr_idx); 674 phy_pwr_idx = 0; 675 } 676 } 677 } 678 679 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 680 { 681 struct rtw_hal *hal = &rtwdev->hal; 682 int rs, path; 683 684 for (path = 0; path < hal->rf_path_num; path++) { 685 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 686 if (rs == RTW_RATE_SECTION_HT_2S || 687 rs == RTW_RATE_SECTION_VHT_2S) 688 continue; 689 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 690 } 691 } 692 } 693 694 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 695 { 696 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 697 u32 cck_enable; 698 u32 cck_fa_cnt; 699 u32 ofdm_fa_cnt; 700 u32 crc32_cnt; 701 u32 cca32_cnt; 702 703 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 704 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 705 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 706 707 dm_info->cck_fa_cnt = cck_fa_cnt; 708 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 709 dm_info->total_fa_cnt = ofdm_fa_cnt; 710 if (cck_enable) 711 dm_info->total_fa_cnt += cck_fa_cnt; 712 713 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 714 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 715 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 716 717 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 718 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 719 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 720 721 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 722 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 723 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 724 725 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 726 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 727 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 728 729 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 730 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 731 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 732 if (cck_enable) { 733 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 734 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 735 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 736 } 737 738 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 739 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 740 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 741 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 742 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 743 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 744 } 745 746 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 747 { 748 static int do_iqk_cnt; 749 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 750 u32 rf_reg, iqk_fail_mask; 751 int counter; 752 bool reload; 753 754 if (rtw_is_assoc(rtwdev)) 755 para.segment_iqk = 1; 756 757 rtw_fw_do_iqk(rtwdev, ¶); 758 759 for (counter = 0; counter < 300; counter++) { 760 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 761 if (rf_reg == 0xabcde) 762 break; 763 msleep(20); 764 } 765 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 766 767 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 768 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 769 rtw_dbg(rtwdev, RTW_DBG_PHY, 770 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 771 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 772 } 773 774 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 775 { 776 rtw8821c_do_iqk(rtwdev); 777 } 778 779 /* for coex */ 780 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 781 { 782 /* enable TBTT nterrupt */ 783 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 784 785 /* BT report packet sample rate */ 786 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 787 788 /* enable BT counter statistics */ 789 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 790 791 /* enable PTA (3-wire function form BT side) */ 792 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 793 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 794 795 /* enable PTA (tx/rx signal form WiFi side) */ 796 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 797 /* wl tx signal to PTA not case EDCCA */ 798 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 799 /* GNT_BT=1 while select both */ 800 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 801 802 /* beacon queue always hi-pri */ 803 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 804 BCN_PRI_EN); 805 } 806 807 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 808 u8 pos_type) 809 { 810 struct rtw_coex *coex = &rtwdev->coex; 811 struct rtw_coex_dm *coex_dm = &coex->dm; 812 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 813 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 814 bool polarity_inverse; 815 u8 regval = 0; 816 817 if (switch_status == coex_dm->cur_switch_status) 818 return; 819 820 if (coex_rfe->wlg_at_btg) { 821 ctrl_type = COEX_SWITCH_CTRL_BY_BBSW; 822 823 if (coex_rfe->ant_switch_polarity) 824 pos_type = COEX_SWITCH_TO_WLA; 825 else 826 pos_type = COEX_SWITCH_TO_WLG_BT; 827 } 828 829 coex_dm->cur_switch_status = switch_status; 830 831 if (coex_rfe->ant_switch_diversity && 832 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 833 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 834 835 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 836 837 switch (ctrl_type) { 838 default: 839 case COEX_SWITCH_CTRL_BY_BBSW: 840 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 841 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 842 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 843 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 844 DPDT_CTRL_PIN); 845 846 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 847 if (coex_rfe->rfe_module_type != 0x4 && 848 coex_rfe->rfe_module_type != 0x2) 849 regval = 0x3; 850 else 851 regval = (!polarity_inverse ? 0x2 : 0x1); 852 } else if (pos_type == COEX_SWITCH_TO_WLG) { 853 regval = (!polarity_inverse ? 0x2 : 0x1); 854 } else { 855 regval = (!polarity_inverse ? 0x1 : 0x2); 856 } 857 858 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 859 regval); 860 break; 861 case COEX_SWITCH_CTRL_BY_PTA: 862 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 863 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 864 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 865 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 866 PTA_CTRL_PIN); 867 868 regval = (!polarity_inverse ? 0x2 : 0x1); 869 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 870 regval); 871 break; 872 case COEX_SWITCH_CTRL_BY_ANTDIV: 873 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 874 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 875 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 876 ANTDIC_CTRL_PIN); 877 break; 878 case COEX_SWITCH_CTRL_BY_MAC: 879 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 880 881 regval = (!polarity_inverse ? 0x0 : 0x1); 882 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 883 regval); 884 break; 885 case COEX_SWITCH_CTRL_BY_FW: 886 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 887 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 888 break; 889 case COEX_SWITCH_CTRL_BY_BT: 890 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 891 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 892 break; 893 } 894 895 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 896 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 897 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 898 } else { 899 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 900 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 901 } 902 } 903 904 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 905 {} 906 907 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 908 { 909 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 910 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 911 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 912 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 913 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 914 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 915 } 916 917 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 918 { 919 struct rtw_coex *coex = &rtwdev->coex; 920 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 921 struct rtw_efuse *efuse = &rtwdev->efuse; 922 923 coex_rfe->rfe_module_type = efuse->rfe_option; 924 coex_rfe->ant_switch_polarity = 0; 925 coex_rfe->ant_switch_exist = true; 926 coex_rfe->wlg_at_btg = false; 927 928 switch (coex_rfe->rfe_module_type) { 929 case 0: 930 case 8: 931 case 1: 932 case 9: /* 1-Ant, Main, WLG */ 933 default: /* 2-Ant, DPDT, WLG */ 934 break; 935 case 2: 936 case 10: /* 1-Ant, Main, BTG */ 937 case 7: 938 case 15: /* 2-Ant, DPDT, BTG */ 939 coex_rfe->wlg_at_btg = true; 940 break; 941 case 3: 942 case 11: /* 1-Ant, Aux, WLG */ 943 coex_rfe->ant_switch_polarity = 1; 944 break; 945 case 4: 946 case 12: /* 1-Ant, Aux, BTG */ 947 coex_rfe->wlg_at_btg = true; 948 coex_rfe->ant_switch_polarity = 1; 949 break; 950 case 5: 951 case 13: /* 2-Ant, no switch, WLG */ 952 case 6: 953 case 14: /* 2-Ant, no antenna switch, WLG */ 954 coex_rfe->ant_switch_exist = false; 955 break; 956 } 957 } 958 959 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 960 { 961 struct rtw_coex *coex = &rtwdev->coex; 962 struct rtw_coex_dm *coex_dm = &coex->dm; 963 struct rtw_efuse *efuse = &rtwdev->efuse; 964 bool share_ant = efuse->share_ant; 965 966 if (share_ant) 967 return; 968 969 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 970 return; 971 972 coex_dm->cur_wl_pwr_lvl = wl_pwr; 973 } 974 975 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 976 {} 977 978 static void 979 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 980 s8 pwr_idx_offset_lower, 981 s8 *txagc_idx, u8 *swing_idx) 982 { 983 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 984 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 985 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 986 u8 swing_lower_bound = 0; 987 u8 max_pwr_idx_offset = 0xf; 988 s8 agc_index = 0; 989 u8 swing_index = dm_info->default_ofdm_index; 990 991 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 992 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 993 994 if (delta_pwr_idx >= 0) { 995 if (delta_pwr_idx <= pwr_idx_offset) { 996 agc_index = delta_pwr_idx; 997 swing_index = dm_info->default_ofdm_index; 998 } else if (delta_pwr_idx > pwr_idx_offset) { 999 agc_index = pwr_idx_offset; 1000 swing_index = dm_info->default_ofdm_index + 1001 delta_pwr_idx - pwr_idx_offset; 1002 swing_index = min_t(u8, swing_index, swing_upper_bound); 1003 } 1004 } else if (delta_pwr_idx < 0) { 1005 if (delta_pwr_idx >= pwr_idx_offset_lower) { 1006 agc_index = delta_pwr_idx; 1007 swing_index = dm_info->default_ofdm_index; 1008 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 1009 if (dm_info->default_ofdm_index > 1010 (pwr_idx_offset_lower - delta_pwr_idx)) 1011 swing_index = dm_info->default_ofdm_index + 1012 delta_pwr_idx - pwr_idx_offset_lower; 1013 else 1014 swing_index = swing_lower_bound; 1015 1016 agc_index = pwr_idx_offset_lower; 1017 } 1018 } 1019 1020 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 1021 rtw_warn(rtwdev, "swing index overflow\n"); 1022 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 1023 } 1024 1025 *txagc_idx = agc_index; 1026 *swing_idx = swing_index; 1027 } 1028 1029 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 1030 s8 pwr_idx_offset_lower) 1031 { 1032 s8 txagc_idx; 1033 u8 swing_idx; 1034 1035 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 1036 &txagc_idx, &swing_idx); 1037 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 1038 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 1039 rtw8821c_txscale_tbl[swing_idx]); 1040 } 1041 1042 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 1043 { 1044 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1045 u8 pwr_idx_offset, tx_pwr_idx; 1046 s8 pwr_idx_offset_lower; 1047 u8 channel = rtwdev->hal.current_channel; 1048 u8 band_width = rtwdev->hal.current_band_width; 1049 u8 regd = rtw_regd_get(rtwdev); 1050 u8 tx_rate = dm_info->tx_rate; 1051 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1052 1053 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 1054 band_width, channel, regd); 1055 1056 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1057 1058 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1059 pwr_idx_offset_lower = 0 - tx_pwr_idx; 1060 1061 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 1062 } 1063 1064 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 1065 { 1066 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1067 struct rtw_swing_table swing_table; 1068 u8 thermal_value, delta; 1069 1070 rtw_phy_config_swing_table(rtwdev, &swing_table); 1071 1072 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1073 return; 1074 1075 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1076 1077 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1078 1079 if (dm_info->pwr_trk_init_trigger) 1080 dm_info->pwr_trk_init_trigger = false; 1081 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1082 RF_PATH_A)) 1083 goto iqk; 1084 1085 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1086 1087 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1088 1089 dm_info->delta_power_index[RF_PATH_A] = 1090 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 1091 RF_PATH_A, delta); 1092 if (dm_info->delta_power_index[RF_PATH_A] == 1093 dm_info->delta_power_index_last[RF_PATH_A]) 1094 goto iqk; 1095 else 1096 dm_info->delta_power_index_last[RF_PATH_A] = 1097 dm_info->delta_power_index[RF_PATH_A]; 1098 rtw8821c_pwrtrack_set(rtwdev); 1099 1100 iqk: 1101 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1102 rtw8821c_do_iqk(rtwdev); 1103 } 1104 1105 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 1106 { 1107 struct rtw_efuse *efuse = &rtwdev->efuse; 1108 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1109 1110 if (efuse->power_track_type != 0) 1111 return; 1112 1113 if (!dm_info->pwr_trk_triggered) { 1114 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1115 GENMASK(17, 16), 0x03); 1116 dm_info->pwr_trk_triggered = true; 1117 return; 1118 } 1119 1120 rtw8821c_phy_pwrtrack(rtwdev); 1121 dm_info->pwr_trk_triggered = false; 1122 } 1123 1124 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 1125 struct rtw_vif *vif, 1126 struct rtw_bfee *bfee, bool enable) 1127 { 1128 if (enable) 1129 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1130 else 1131 rtw_bf_remove_bfee_su(rtwdev, bfee); 1132 } 1133 1134 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1135 struct rtw_vif *vif, 1136 struct rtw_bfee *bfee, bool enable) 1137 { 1138 if (enable) 1139 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1140 else 1141 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1142 } 1143 1144 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1145 struct rtw_bfee *bfee, bool enable) 1146 { 1147 if (bfee->role == RTW_BFEE_SU) 1148 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1149 else if (bfee->role == RTW_BFEE_MU) 1150 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1151 else 1152 rtw_warn(rtwdev, "wrong bfee role\n"); 1153 } 1154 1155 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1156 { 1157 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1158 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1159 u8 cck_n_rx; 1160 1161 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1162 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1163 1164 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1165 return; 1166 1167 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1168 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1169 rtw_dbg(rtwdev, RTW_DBG_PHY, 1170 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1171 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1172 dm_info->cck_pd_default + new_lvl * 2, 1173 pd[new_lvl], dm_info->cck_fa_avg); 1174 1175 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1176 1177 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1178 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1179 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1180 dm_info->cck_pd_default + new_lvl * 2); 1181 } 1182 1183 static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev, 1184 struct rtw_tx_pkt_info *pkt_info, 1185 u8 *txdesc) 1186 { 1187 fill_txdesc_checksum_common(txdesc, 16); 1188 } 1189 1190 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1191 {0x0086, 1192 RTW_PWR_CUT_ALL_MSK, 1193 RTW_PWR_INTF_SDIO_MSK, 1194 RTW_PWR_ADDR_SDIO, 1195 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1196 {0x0086, 1197 RTW_PWR_CUT_ALL_MSK, 1198 RTW_PWR_INTF_SDIO_MSK, 1199 RTW_PWR_ADDR_SDIO, 1200 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1201 {0x004A, 1202 RTW_PWR_CUT_ALL_MSK, 1203 RTW_PWR_INTF_USB_MSK, 1204 RTW_PWR_ADDR_MAC, 1205 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1206 {0x0005, 1207 RTW_PWR_CUT_ALL_MSK, 1208 RTW_PWR_INTF_ALL_MSK, 1209 RTW_PWR_ADDR_MAC, 1210 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1211 {0x0300, 1212 RTW_PWR_CUT_ALL_MSK, 1213 RTW_PWR_INTF_PCI_MSK, 1214 RTW_PWR_ADDR_MAC, 1215 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1216 {0x0301, 1217 RTW_PWR_CUT_ALL_MSK, 1218 RTW_PWR_INTF_PCI_MSK, 1219 RTW_PWR_ADDR_MAC, 1220 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1221 {0xFFFF, 1222 RTW_PWR_CUT_ALL_MSK, 1223 RTW_PWR_INTF_ALL_MSK, 1224 0, 1225 RTW_PWR_CMD_END, 0, 0}, 1226 }; 1227 1228 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1229 {0x0020, 1230 RTW_PWR_CUT_ALL_MSK, 1231 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1232 RTW_PWR_ADDR_MAC, 1233 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1234 {0x0001, 1235 RTW_PWR_CUT_ALL_MSK, 1236 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1237 RTW_PWR_ADDR_MAC, 1238 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1239 {0x0000, 1240 RTW_PWR_CUT_ALL_MSK, 1241 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1242 RTW_PWR_ADDR_MAC, 1243 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1244 {0x0005, 1245 RTW_PWR_CUT_ALL_MSK, 1246 RTW_PWR_INTF_ALL_MSK, 1247 RTW_PWR_ADDR_MAC, 1248 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1249 {0x0075, 1250 RTW_PWR_CUT_ALL_MSK, 1251 RTW_PWR_INTF_PCI_MSK, 1252 RTW_PWR_ADDR_MAC, 1253 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1254 {0x0006, 1255 RTW_PWR_CUT_ALL_MSK, 1256 RTW_PWR_INTF_ALL_MSK, 1257 RTW_PWR_ADDR_MAC, 1258 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1259 {0x0075, 1260 RTW_PWR_CUT_ALL_MSK, 1261 RTW_PWR_INTF_PCI_MSK, 1262 RTW_PWR_ADDR_MAC, 1263 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1264 {0x0006, 1265 RTW_PWR_CUT_ALL_MSK, 1266 RTW_PWR_INTF_ALL_MSK, 1267 RTW_PWR_ADDR_MAC, 1268 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1269 {0x0005, 1270 RTW_PWR_CUT_ALL_MSK, 1271 RTW_PWR_INTF_ALL_MSK, 1272 RTW_PWR_ADDR_MAC, 1273 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1274 {0x0005, 1275 RTW_PWR_CUT_ALL_MSK, 1276 RTW_PWR_INTF_ALL_MSK, 1277 RTW_PWR_ADDR_MAC, 1278 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1279 {0x10C3, 1280 RTW_PWR_CUT_ALL_MSK, 1281 RTW_PWR_INTF_USB_MSK, 1282 RTW_PWR_ADDR_MAC, 1283 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1284 {0x0005, 1285 RTW_PWR_CUT_ALL_MSK, 1286 RTW_PWR_INTF_ALL_MSK, 1287 RTW_PWR_ADDR_MAC, 1288 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1289 {0x0005, 1290 RTW_PWR_CUT_ALL_MSK, 1291 RTW_PWR_INTF_ALL_MSK, 1292 RTW_PWR_ADDR_MAC, 1293 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1294 {0x0020, 1295 RTW_PWR_CUT_ALL_MSK, 1296 RTW_PWR_INTF_ALL_MSK, 1297 RTW_PWR_ADDR_MAC, 1298 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1299 {0x0074, 1300 RTW_PWR_CUT_ALL_MSK, 1301 RTW_PWR_INTF_PCI_MSK, 1302 RTW_PWR_ADDR_MAC, 1303 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1304 {0x0022, 1305 RTW_PWR_CUT_ALL_MSK, 1306 RTW_PWR_INTF_PCI_MSK, 1307 RTW_PWR_ADDR_MAC, 1308 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1309 {0x0062, 1310 RTW_PWR_CUT_ALL_MSK, 1311 RTW_PWR_INTF_PCI_MSK, 1312 RTW_PWR_ADDR_MAC, 1313 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1314 (BIT(7) | BIT(6) | BIT(5))}, 1315 {0x0061, 1316 RTW_PWR_CUT_ALL_MSK, 1317 RTW_PWR_INTF_PCI_MSK, 1318 RTW_PWR_ADDR_MAC, 1319 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1320 {0x007C, 1321 RTW_PWR_CUT_ALL_MSK, 1322 RTW_PWR_INTF_ALL_MSK, 1323 RTW_PWR_ADDR_MAC, 1324 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1325 {0xFFFF, 1326 RTW_PWR_CUT_ALL_MSK, 1327 RTW_PWR_INTF_ALL_MSK, 1328 0, 1329 RTW_PWR_CMD_END, 0, 0}, 1330 }; 1331 1332 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1333 {0x0093, 1334 RTW_PWR_CUT_ALL_MSK, 1335 RTW_PWR_INTF_ALL_MSK, 1336 RTW_PWR_ADDR_MAC, 1337 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1338 {0x001F, 1339 RTW_PWR_CUT_ALL_MSK, 1340 RTW_PWR_INTF_ALL_MSK, 1341 RTW_PWR_ADDR_MAC, 1342 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1343 {0x0049, 1344 RTW_PWR_CUT_ALL_MSK, 1345 RTW_PWR_INTF_ALL_MSK, 1346 RTW_PWR_ADDR_MAC, 1347 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1348 {0x0006, 1349 RTW_PWR_CUT_ALL_MSK, 1350 RTW_PWR_INTF_ALL_MSK, 1351 RTW_PWR_ADDR_MAC, 1352 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1353 {0x0002, 1354 RTW_PWR_CUT_ALL_MSK, 1355 RTW_PWR_INTF_ALL_MSK, 1356 RTW_PWR_ADDR_MAC, 1357 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1358 {0x10C3, 1359 RTW_PWR_CUT_ALL_MSK, 1360 RTW_PWR_INTF_USB_MSK, 1361 RTW_PWR_ADDR_MAC, 1362 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1363 {0x0005, 1364 RTW_PWR_CUT_ALL_MSK, 1365 RTW_PWR_INTF_ALL_MSK, 1366 RTW_PWR_ADDR_MAC, 1367 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1368 {0x0005, 1369 RTW_PWR_CUT_ALL_MSK, 1370 RTW_PWR_INTF_ALL_MSK, 1371 RTW_PWR_ADDR_MAC, 1372 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1373 {0x0020, 1374 RTW_PWR_CUT_ALL_MSK, 1375 RTW_PWR_INTF_ALL_MSK, 1376 RTW_PWR_ADDR_MAC, 1377 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1378 {0x0000, 1379 RTW_PWR_CUT_ALL_MSK, 1380 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1381 RTW_PWR_ADDR_MAC, 1382 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1383 {0xFFFF, 1384 RTW_PWR_CUT_ALL_MSK, 1385 RTW_PWR_INTF_ALL_MSK, 1386 0, 1387 RTW_PWR_CMD_END, 0, 0}, 1388 }; 1389 1390 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1391 {0x0007, 1392 RTW_PWR_CUT_ALL_MSK, 1393 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1394 RTW_PWR_ADDR_MAC, 1395 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1396 {0x0067, 1397 RTW_PWR_CUT_ALL_MSK, 1398 RTW_PWR_INTF_ALL_MSK, 1399 RTW_PWR_ADDR_MAC, 1400 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1401 {0x0005, 1402 RTW_PWR_CUT_ALL_MSK, 1403 RTW_PWR_INTF_PCI_MSK, 1404 RTW_PWR_ADDR_MAC, 1405 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1406 {0x004A, 1407 RTW_PWR_CUT_ALL_MSK, 1408 RTW_PWR_INTF_USB_MSK, 1409 RTW_PWR_ADDR_MAC, 1410 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1411 {0x0067, 1412 RTW_PWR_CUT_ALL_MSK, 1413 RTW_PWR_INTF_SDIO_MSK, 1414 RTW_PWR_ADDR_MAC, 1415 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1416 {0x0067, 1417 RTW_PWR_CUT_ALL_MSK, 1418 RTW_PWR_INTF_SDIO_MSK, 1419 RTW_PWR_ADDR_MAC, 1420 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1421 {0x004F, 1422 RTW_PWR_CUT_ALL_MSK, 1423 RTW_PWR_INTF_SDIO_MSK, 1424 RTW_PWR_ADDR_MAC, 1425 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1426 {0x0067, 1427 RTW_PWR_CUT_ALL_MSK, 1428 RTW_PWR_INTF_SDIO_MSK, 1429 RTW_PWR_ADDR_MAC, 1430 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1431 {0x0046, 1432 RTW_PWR_CUT_ALL_MSK, 1433 RTW_PWR_INTF_SDIO_MSK, 1434 RTW_PWR_ADDR_MAC, 1435 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1436 {0x0067, 1437 RTW_PWR_CUT_ALL_MSK, 1438 RTW_PWR_INTF_SDIO_MSK, 1439 RTW_PWR_ADDR_MAC, 1440 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1441 {0x0046, 1442 RTW_PWR_CUT_ALL_MSK, 1443 RTW_PWR_INTF_SDIO_MSK, 1444 RTW_PWR_ADDR_MAC, 1445 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1446 {0x0062, 1447 RTW_PWR_CUT_ALL_MSK, 1448 RTW_PWR_INTF_SDIO_MSK, 1449 RTW_PWR_ADDR_MAC, 1450 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1451 {0x0081, 1452 RTW_PWR_CUT_ALL_MSK, 1453 RTW_PWR_INTF_ALL_MSK, 1454 RTW_PWR_ADDR_MAC, 1455 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1456 {0x0005, 1457 RTW_PWR_CUT_ALL_MSK, 1458 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1459 RTW_PWR_ADDR_MAC, 1460 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1461 {0x0086, 1462 RTW_PWR_CUT_ALL_MSK, 1463 RTW_PWR_INTF_SDIO_MSK, 1464 RTW_PWR_ADDR_SDIO, 1465 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1466 {0x0086, 1467 RTW_PWR_CUT_ALL_MSK, 1468 RTW_PWR_INTF_SDIO_MSK, 1469 RTW_PWR_ADDR_SDIO, 1470 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1471 {0x0090, 1472 RTW_PWR_CUT_ALL_MSK, 1473 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1474 RTW_PWR_ADDR_MAC, 1475 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1476 {0x0044, 1477 RTW_PWR_CUT_ALL_MSK, 1478 RTW_PWR_INTF_SDIO_MSK, 1479 RTW_PWR_ADDR_SDIO, 1480 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1481 {0x0040, 1482 RTW_PWR_CUT_ALL_MSK, 1483 RTW_PWR_INTF_SDIO_MSK, 1484 RTW_PWR_ADDR_SDIO, 1485 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1486 {0x0041, 1487 RTW_PWR_CUT_ALL_MSK, 1488 RTW_PWR_INTF_SDIO_MSK, 1489 RTW_PWR_ADDR_SDIO, 1490 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1491 {0x0042, 1492 RTW_PWR_CUT_ALL_MSK, 1493 RTW_PWR_INTF_SDIO_MSK, 1494 RTW_PWR_ADDR_SDIO, 1495 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1496 {0xFFFF, 1497 RTW_PWR_CUT_ALL_MSK, 1498 RTW_PWR_INTF_ALL_MSK, 1499 0, 1500 RTW_PWR_CMD_END, 0, 0}, 1501 }; 1502 1503 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1504 trans_carddis_to_cardemu_8821c, 1505 trans_cardemu_to_act_8821c, 1506 NULL 1507 }; 1508 1509 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1510 trans_act_to_cardemu_8821c, 1511 trans_cardemu_to_carddis_8821c, 1512 NULL 1513 }; 1514 1515 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1516 {0xFFFF, 0x00, 1517 RTW_IP_SEL_PHY, 1518 RTW_INTF_PHY_CUT_ALL, 1519 RTW_INTF_PHY_PLATFORM_ALL}, 1520 }; 1521 1522 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1523 {0xFFFF, 0x0000, 1524 RTW_IP_SEL_PHY, 1525 RTW_INTF_PHY_CUT_ALL, 1526 RTW_INTF_PHY_PLATFORM_ALL}, 1527 }; 1528 1529 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1530 {0x0009, 0x6380, 1531 RTW_IP_SEL_PHY, 1532 RTW_INTF_PHY_CUT_ALL, 1533 RTW_INTF_PHY_PLATFORM_ALL}, 1534 {0xFFFF, 0x0000, 1535 RTW_IP_SEL_PHY, 1536 RTW_INTF_PHY_CUT_ALL, 1537 RTW_INTF_PHY_PLATFORM_ALL}, 1538 }; 1539 1540 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1541 {0xFFFF, 0x0000, 1542 RTW_IP_SEL_PHY, 1543 RTW_INTF_PHY_CUT_ALL, 1544 RTW_INTF_PHY_PLATFORM_ALL}, 1545 }; 1546 1547 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1548 .usb2_para = usb2_param_8821c, 1549 .usb3_para = usb3_param_8821c, 1550 .gen1_para = pcie_gen1_param_8821c, 1551 .gen2_para = pcie_gen2_param_8821c, 1552 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1553 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1554 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1555 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1556 }; 1557 1558 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1559 [0] = RTW_DEF_RFE(8821c, 0, 0), 1560 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1561 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1562 [6] = RTW_DEF_RFE(8821c, 0, 0), 1563 }; 1564 1565 static struct rtw_hw_reg rtw8821c_dig[] = { 1566 [0] = { .addr = 0xc50, .mask = 0x7f }, 1567 }; 1568 1569 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1570 .ctrl = LTECOEX_ACCESS_CTRL, 1571 .wdata = LTECOEX_WRITE_DATA, 1572 .rdata = LTECOEX_READ_DATA, 1573 }; 1574 1575 static struct rtw_page_table page_table_8821c[] = { 1576 /* not sure what [0] stands for */ 1577 {16, 16, 16, 14, 1}, 1578 {16, 16, 16, 14, 1}, 1579 {16, 16, 0, 0, 1}, 1580 {16, 16, 16, 0, 1}, 1581 {16, 16, 16, 14, 1}, 1582 }; 1583 1584 static struct rtw_rqpn rqpn_table_8821c[] = { 1585 /* not sure what [0] stands for */ 1586 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1587 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1588 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1589 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1590 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1591 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1592 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1593 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1594 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1595 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1596 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1597 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1598 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1599 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1600 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1601 }; 1602 1603 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1604 .prio[RTW_DMA_MAPPING_EXTRA] = { 1605 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1606 }, 1607 .prio[RTW_DMA_MAPPING_LOW] = { 1608 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1609 }, 1610 .prio[RTW_DMA_MAPPING_NORMAL] = { 1611 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1612 }, 1613 .prio[RTW_DMA_MAPPING_HIGH] = { 1614 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1615 }, 1616 .wsize = true, 1617 }; 1618 1619 static struct rtw_chip_ops rtw8821c_ops = { 1620 .phy_set_param = rtw8821c_phy_set_param, 1621 .read_efuse = rtw8821c_read_efuse, 1622 .query_rx_desc = rtw8821c_query_rx_desc, 1623 .set_channel = rtw8821c_set_channel, 1624 .mac_init = rtw8821c_mac_init, 1625 .read_rf = rtw_phy_read_rf, 1626 .write_rf = rtw_phy_write_rf_reg_sipi, 1627 .set_antenna = NULL, 1628 .set_tx_power_index = rtw8821c_set_tx_power_index, 1629 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1630 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1631 .phy_calibration = rtw8821c_phy_calibration, 1632 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1633 .pwr_track = rtw8821c_pwr_track, 1634 .config_bfee = rtw8821c_bf_config_bfee, 1635 .set_gid_table = rtw_bf_set_gid_table, 1636 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1637 .fill_txdesc_checksum = rtw8821c_fill_txdesc_checksum, 1638 1639 .coex_set_init = rtw8821c_coex_cfg_init, 1640 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1641 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1642 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1643 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1644 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1645 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1646 }; 1647 1648 /* rssi in percentage % (dbm = % - 100) */ 1649 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1650 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1651 1652 /* Shared-Antenna Coex Table */ 1653 static const struct coex_table_para table_sant_8821c[] = { 1654 {0x55555555, 0x55555555}, /* case-0 */ 1655 {0x55555555, 0x55555555}, 1656 {0x66555555, 0x66555555}, 1657 {0xaaaaaaaa, 0xaaaaaaaa}, 1658 {0x5a5a5a5a, 0x5a5a5a5a}, 1659 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1660 {0x6a5a5555, 0xaaaaaaaa}, 1661 {0x6a5a56aa, 0x6a5a56aa}, 1662 {0x6a5a5a5a, 0x6a5a5a5a}, 1663 {0x66555555, 0x5a5a5a5a}, 1664 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1665 {0x66555555, 0xaaaaaaaa}, 1666 {0x66555555, 0x6a5a5aaa}, 1667 {0x66555555, 0x6aaa6aaa}, 1668 {0x66555555, 0x6a5a5aaa}, 1669 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1670 {0xffff55ff, 0xfafafafa}, 1671 {0xffff55ff, 0x6afa5afa}, 1672 {0xaaffffaa, 0xfafafafa}, 1673 {0xaa5555aa, 0x5a5a5a5a}, 1674 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1675 {0xaa5555aa, 0xaaaaaaaa}, 1676 {0xffffffff, 0x55555555}, 1677 {0xffffffff, 0x5a5a5a5a}, 1678 {0xffffffff, 0x5a5a5a5a}, 1679 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1680 {0x55555555, 0x5a5a5a5a}, 1681 {0x55555555, 0xaaaaaaaa}, 1682 {0x66555555, 0x6a5a6a5a}, 1683 {0x66556655, 0x66556655}, 1684 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1685 {0xffffffff, 0x5aaa5aaa}, 1686 {0x56555555, 0x5a5a5aaa} 1687 }; 1688 1689 /* Non-Shared-Antenna Coex Table */ 1690 static const struct coex_table_para table_nsant_8821c[] = { 1691 {0xffffffff, 0xffffffff}, /* case-100 */ 1692 {0xffff55ff, 0xfafafafa}, 1693 {0x66555555, 0x66555555}, 1694 {0xaaaaaaaa, 0xaaaaaaaa}, 1695 {0x5a5a5a5a, 0x5a5a5a5a}, 1696 {0xffffffff, 0xffffffff}, /* case-105 */ 1697 {0x5afa5afa, 0x5afa5afa}, 1698 {0x55555555, 0xfafafafa}, 1699 {0x66555555, 0xfafafafa}, 1700 {0x66555555, 0x5a5a5a5a}, 1701 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1702 {0x66555555, 0xaaaaaaaa}, 1703 {0xffff55ff, 0xfafafafa}, 1704 {0xffff55ff, 0x5afa5afa}, 1705 {0xffff55ff, 0xaaaaaaaa}, 1706 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1707 {0xaaffffaa, 0x5afa5afa}, 1708 {0xaaffffaa, 0xaaaaaaaa}, 1709 {0xffffffff, 0xfafafafa}, 1710 {0xffff55ff, 0xfafafafa}, 1711 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1712 {0xffff55ff, 0x5afa5afa}, 1713 {0xffff55ff, 0x5afa5afa}, 1714 {0x55ff55ff, 0x55ff55ff} 1715 }; 1716 1717 /* Shared-Antenna TDMA */ 1718 static const struct coex_tdma_para tdma_sant_8821c[] = { 1719 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1720 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1721 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1722 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1723 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1724 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1725 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1726 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1727 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1728 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1729 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1730 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1731 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1732 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1733 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1734 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1735 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1736 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1737 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1738 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1739 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1740 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1741 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1742 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1743 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1744 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1745 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1746 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1747 }; 1748 1749 /* Non-Shared-Antenna TDMA */ 1750 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1751 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1752 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1753 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1754 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1755 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1756 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1757 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1758 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1759 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1760 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1761 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1762 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1763 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1764 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1765 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1766 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1767 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1768 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1769 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1770 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1771 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1772 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1773 }; 1774 1775 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1776 1777 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1778 static const struct coex_rf_para rf_para_tx_8821c[] = { 1779 {0, 0, false, 7}, /* for normal */ 1780 {0, 20, false, 7}, /* for WL-CPT */ 1781 {8, 17, true, 4}, 1782 {7, 18, true, 4}, 1783 {6, 19, true, 4}, 1784 {5, 20, true, 4} 1785 }; 1786 1787 static const struct coex_rf_para rf_para_rx_8821c[] = { 1788 {0, 0, false, 7}, /* for normal */ 1789 {0, 20, false, 7}, /* for WL-CPT */ 1790 {3, 24, true, 5}, 1791 {2, 26, true, 5}, 1792 {1, 27, true, 5}, 1793 {0, 28, true, 5} 1794 }; 1795 1796 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1797 1798 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1799 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1800 11, 11, 12, 12, 12, 12, 12}, 1801 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1802 11, 12, 12, 12, 12, 12, 12, 12}, 1803 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1804 11, 12, 12, 12, 12, 12, 12}, 1805 }; 1806 1807 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1808 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1809 12, 12, 12, 12, 12, 12, 12}, 1810 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1811 12, 12, 12, 12, 12, 12, 12, 12}, 1812 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1813 11, 12, 12, 12, 12, 12, 12, 12}, 1814 }; 1815 1816 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1817 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1818 11, 11, 12, 12, 12, 12, 12}, 1819 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1820 11, 12, 12, 12, 12, 12, 12, 12}, 1821 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1822 11, 12, 12, 12, 12, 12, 12}, 1823 }; 1824 1825 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1826 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1827 12, 12, 12, 12, 12, 12, 12}, 1828 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1829 12, 12, 12, 12, 12, 12, 12, 12}, 1830 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1831 11, 12, 12, 12, 12, 12, 12, 12}, 1832 }; 1833 1834 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1835 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1836 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1837 }; 1838 1839 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1840 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1841 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1842 }; 1843 1844 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1845 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1846 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1847 }; 1848 1849 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1850 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1851 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1852 }; 1853 1854 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1855 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1856 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1857 }; 1858 1859 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1860 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1861 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1862 }; 1863 1864 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1865 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1866 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1867 }; 1868 1869 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1870 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1871 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1872 }; 1873 1874 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1875 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1876 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1877 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1878 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1879 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1880 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1881 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1882 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1883 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1884 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1885 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1886 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1887 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1888 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1889 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1890 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1891 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1892 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1893 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1894 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1895 }; 1896 1897 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1898 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1899 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1900 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1901 {0, 0, RTW_REG_DOMAIN_NL}, 1902 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1903 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1904 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1905 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1906 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1907 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1908 {0, 0, RTW_REG_DOMAIN_NL}, 1909 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1910 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1911 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1912 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1913 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1914 {0, 0, RTW_REG_DOMAIN_NL}, 1915 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1916 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1917 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1918 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1919 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1920 }; 1921 1922 const struct rtw_chip_info rtw8821c_hw_spec = { 1923 .ops = &rtw8821c_ops, 1924 .id = RTW_CHIP_TYPE_8821C, 1925 .fw_name = "rtw88/rtw8821c_fw.bin", 1926 .wlan_cpu = RTW_WCPU_11AC, 1927 .tx_pkt_desc_sz = 48, 1928 .tx_buf_desc_sz = 16, 1929 .rx_pkt_desc_sz = 24, 1930 .rx_buf_desc_sz = 8, 1931 .phy_efuse_size = 512, 1932 .log_efuse_size = 512, 1933 .ptct_efuse_size = 96, 1934 .txff_size = 65536, 1935 .rxff_size = 16384, 1936 .rsvd_drv_pg_num = 8, 1937 .txgi_factor = 1, 1938 .is_pwr_by_rate_dec = true, 1939 .max_power_index = 0x3f, 1940 .csi_buf_pg_num = 0, 1941 .band = RTW_BAND_2G | RTW_BAND_5G, 1942 .page_size = TX_PAGE_SIZE, 1943 .dig_min = 0x1c, 1944 .ht_supported = true, 1945 .vht_supported = true, 1946 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1947 .sys_func_en = 0xD8, 1948 .pwr_on_seq = card_enable_flow_8821c, 1949 .pwr_off_seq = card_disable_flow_8821c, 1950 .page_table = page_table_8821c, 1951 .rqpn_table = rqpn_table_8821c, 1952 .prioq_addrs = &prioq_addrs_8821c, 1953 .intf_table = &phy_para_table_8821c, 1954 .dig = rtw8821c_dig, 1955 .rf_base_addr = {0x2800, 0x2c00}, 1956 .rf_sipi_addr = {0xc90, 0xe90}, 1957 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1958 .mac_tbl = &rtw8821c_mac_tbl, 1959 .agc_tbl = &rtw8821c_agc_tbl, 1960 .bb_tbl = &rtw8821c_bb_tbl, 1961 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1962 .rfe_defs = rtw8821c_rfe_defs, 1963 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1964 .rx_ldpc = false, 1965 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1966 .iqk_threshold = 8, 1967 .bfer_su_max_num = 2, 1968 .bfer_mu_max_num = 1, 1969 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 1970 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 1971 1972 .coex_para_ver = 0x19092746, 1973 .bt_desired_ver = 0x46, 1974 .scbd_support = true, 1975 .new_scbd10_def = false, 1976 .ble_hid_profile_support = false, 1977 .wl_mimo_ps_support = false, 1978 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1979 .bt_rssi_type = COEX_BTRSSI_RATIO, 1980 .ant_isolation = 15, 1981 .rssi_tolerance = 2, 1982 .wl_rssi_step = wl_rssi_step_8821c, 1983 .bt_rssi_step = bt_rssi_step_8821c, 1984 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 1985 .table_sant = table_sant_8821c, 1986 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 1987 .table_nsant = table_nsant_8821c, 1988 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 1989 .tdma_sant = tdma_sant_8821c, 1990 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 1991 .tdma_nsant = tdma_nsant_8821c, 1992 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 1993 .wl_rf_para_tx = rf_para_tx_8821c, 1994 .wl_rf_para_rx = rf_para_rx_8821c, 1995 .bt_afh_span_bw20 = 0x24, 1996 .bt_afh_span_bw40 = 0x36, 1997 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 1998 .afh_5g = afh_5g_8821c, 1999 2000 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 2001 .coex_info_hw_regs = coex_info_hw_regs_8821c, 2002 }; 2003 EXPORT_SYMBOL(rtw8821c_hw_spec); 2004 2005 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 2006 2007 MODULE_AUTHOR("Realtek Corporation"); 2008 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 2009 MODULE_LICENSE("Dual BSD/GPL"); 2010