1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #include "main.h"
6 #include "coex.h"
7 #include "fw.h"
8 #include "tx.h"
9 #include "rx.h"
10 #include "phy.h"
11 #include "rtw8821c.h"
12 #include "rtw8821c_table.h"
13 #include "mac.h"
14 #include "reg.h"
15 #include "debug.h"
16 #include "bf.h"
17 
18 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
19 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
20 					-20, -24, -28, -31, -34, -37, -40, -44};
21 
22 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
23 				    struct rtw8821c_efuse *map)
24 {
25 	ether_addr_copy(efuse->addr, map->e.mac_addr);
26 }
27 
28 enum rtw8821ce_rf_set {
29 	SWITCH_TO_BTG,
30 	SWITCH_TO_WLG,
31 	SWITCH_TO_WLA,
32 	SWITCH_TO_BT,
33 };
34 
35 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
36 {
37 	struct rtw_efuse *efuse = &rtwdev->efuse;
38 	struct rtw8821c_efuse *map;
39 	int i;
40 
41 	map = (struct rtw8821c_efuse *)log_map;
42 
43 	efuse->rfe_option = map->rfe_option;
44 	efuse->rf_board_option = map->rf_board_option;
45 	efuse->crystal_cap = map->xtal_k;
46 	efuse->pa_type_2g = map->pa_type;
47 	efuse->pa_type_5g = map->pa_type;
48 	efuse->lna_type_2g = map->lna_type_2g[0];
49 	efuse->lna_type_5g = map->lna_type_5g[0];
50 	efuse->channel_plan = map->channel_plan;
51 	efuse->country_code[0] = map->country_code[0];
52 	efuse->country_code[1] = map->country_code[1];
53 	efuse->bt_setting = map->rf_bt_setting;
54 	efuse->regd = map->rf_board_option & 0x7;
55 	efuse->thermal_meter[0] = map->thermal_meter;
56 	efuse->thermal_meter_k = map->thermal_meter;
57 	efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
58 	efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
59 
60 	for (i = 0; i < 4; i++)
61 		efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
62 
63 	switch (rtw_hci_type(rtwdev)) {
64 	case RTW_HCI_TYPE_PCIE:
65 		rtw8821ce_efuse_parsing(efuse, map);
66 		break;
67 	default:
68 		/* unsupported now */
69 		return -ENOTSUPP;
70 	}
71 
72 	return 0;
73 }
74 
75 static const u32 rtw8821c_txscale_tbl[] = {
76 	0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
77 	0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
78 	0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
79 	0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
80 };
81 
82 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
83 {
84 	u8 i = 0;
85 	u32 swing, table_value;
86 
87 	swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
88 	for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
89 		table_value = rtw8821c_txscale_tbl[i];
90 		if (swing == table_value)
91 			break;
92 	}
93 
94 	return i;
95 }
96 
97 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
98 {
99 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
100 	u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
101 
102 	if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
103 		dm_info->default_ofdm_index = 24;
104 	else
105 		dm_info->default_ofdm_index = swing_idx;
106 
107 	ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
108 	dm_info->delta_power_index[RF_PATH_A] = 0;
109 	dm_info->delta_power_index_last[RF_PATH_A] = 0;
110 	dm_info->pwr_trk_triggered = false;
111 	dm_info->pwr_trk_init_trigger = true;
112 	dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
113 }
114 
115 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
116 {
117 	rtw_bf_phy_init(rtwdev);
118 	/* Grouping bitmap parameters */
119 	rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
120 }
121 
122 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
123 {
124 	u8 crystal_cap, val;
125 
126 	/* power on BB/RF domain */
127 	val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
128 	val |= BIT_FEN_PCIEA;
129 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
130 
131 	/* toggle BB reset */
132 	val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
133 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
134 	val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
135 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
136 	val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
137 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
138 
139 	rtw_write8(rtwdev, REG_RF_CTRL,
140 		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
141 	usleep_range(10, 11);
142 	rtw_write8(rtwdev, REG_WLRF1 + 3,
143 		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
144 	usleep_range(10, 11);
145 
146 	/* pre init before header files config */
147 	rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
148 
149 	rtw_phy_load_tables(rtwdev);
150 
151 	crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
152 	rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
153 	rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
154 	rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
155 
156 	/* post init after header files config */
157 	rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
158 	rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
159 	rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
160 	rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
161 
162 	rtw_phy_init(rtwdev);
163 	rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
164 
165 	rtw8821c_pwrtrack_init(rtwdev);
166 
167 	rtw8821c_phy_bf_init(rtwdev);
168 }
169 
170 static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
171 {
172 	u32 value32;
173 	u16 pre_txcnt;
174 
175 	/* protocol configuration */
176 	rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
177 	rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
178 	pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
179 	rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
180 	rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
181 	value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
182 		  (WLAN_MAX_AGG_PKT_LIMIT << 16) |
183 		  (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
184 	rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
185 	rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
186 		    WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
187 	rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
188 	rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
189 	rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
190 	rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
191 	rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
192 
193 	/* EDCA configuration */
194 	rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
195 	rtw_write16(rtwdev, REG_TXPAUSE, 0);
196 	rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
197 	rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
198 	rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
199 	rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
200 	rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
201 	rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
202 	rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
203 
204 	/* Set beacon cotnrol - enable TSF and other related functions */
205 	rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
206 
207 	/* Set send beacon related registers */
208 	rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
209 	rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
210 	rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
211 	rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
212 
213 	/* WMAC configuration */
214 	rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
215 	rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
216 	rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
217 	rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
218 	rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
219 	rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
220 	rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
221 	rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
222 	rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6));
223 	rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
224 	rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
225 
226 	return 0;
227 }
228 
229 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
230 {
231 	u8 ldo_pwr;
232 
233 	ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
234 	ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
235 	rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
236 }
237 
238 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
239 {
240 	u32 reg;
241 
242 	rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
243 	rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
244 
245 	reg = rtw_read32(rtwdev, REG_RFECTL);
246 	switch (rf_set) {
247 	case SWITCH_TO_BTG:
248 		reg |= B_BTG_SWITCH;
249 		reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH |
250 			 B_WLA_SWITCH);
251 		rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
252 		rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
253 		break;
254 	case SWITCH_TO_WLG:
255 		reg |= B_WL_SWITCH | B_WLG_SWITCH;
256 		reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH);
257 		rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
258 		rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
259 		break;
260 	case SWITCH_TO_WLA:
261 		reg |= B_WL_SWITCH | B_WLA_SWITCH;
262 		reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH);
263 		break;
264 	case SWITCH_TO_BT:
265 	default:
266 		break;
267 	}
268 
269 	rtw_write32(rtwdev, REG_RFECTL, reg);
270 }
271 
272 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
273 {
274 	u32 rf_reg18;
275 
276 	rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
277 
278 	rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
279 		      RF18_BW_MASK);
280 
281 	rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
282 	rf_reg18 |= (channel & RF18_CHANNEL_MASK);
283 
284 	if (channel >= 100 && channel <= 140)
285 		rf_reg18 |= RF18_RFSI_GE;
286 	else if (channel > 140)
287 		rf_reg18 |= RF18_RFSI_GT;
288 
289 	switch (bw) {
290 	case RTW_CHANNEL_WIDTH_5:
291 	case RTW_CHANNEL_WIDTH_10:
292 	case RTW_CHANNEL_WIDTH_20:
293 	default:
294 		rf_reg18 |= RF18_BW_20M;
295 		break;
296 	case RTW_CHANNEL_WIDTH_40:
297 		rf_reg18 |= RF18_BW_40M;
298 		break;
299 	case RTW_CHANNEL_WIDTH_80:
300 		rf_reg18 |= RF18_BW_80M;
301 		break;
302 	}
303 
304 	if (channel <= 14) {
305 		if (rtwdev->efuse.rfe_option == 0)
306 			rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
307 		else if (rtwdev->efuse.rfe_option == 2)
308 			rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
309 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
310 		rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
311 	} else {
312 		rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
313 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
314 	}
315 
316 	rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
317 
318 	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
319 	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
320 }
321 
322 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
323 {
324 	if (bw == RTW_CHANNEL_WIDTH_40) {
325 		/* RX DFIR for BW40 */
326 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
327 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
328 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
329 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
330 	} else if (bw == RTW_CHANNEL_WIDTH_80) {
331 		/* RX DFIR for BW80 */
332 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
333 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
334 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
335 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
336 	} else {
337 		/* RX DFIR for BW20, BW10 and BW5 */
338 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
339 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
340 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
341 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
342 	}
343 }
344 
345 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
346 				    u8 primary_ch_idx)
347 {
348 	u32 val32;
349 
350 	if (channel <= 14) {
351 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
352 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
353 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
354 		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
355 
356 		rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
357 		rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
358 		if (channel == 14) {
359 			rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
360 			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
361 			rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
362 		} else {
363 			rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
364 					 rtwdev->chip->ch_param[0]);
365 			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
366 					 rtwdev->chip->ch_param[1] & MASKLWORD);
367 			rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
368 					 rtwdev->chip->ch_param[2]);
369 		}
370 	} else if (channel > 35) {
371 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
372 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
373 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
374 		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
375 
376 		if (channel >= 36 && channel <= 64)
377 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
378 		else if (channel >= 100 && channel <= 144)
379 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
380 		else if (channel >= 149)
381 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
382 
383 		if (channel >= 36 && channel <= 48)
384 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
385 		else if (channel >= 52 && channel <= 64)
386 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
387 		else if (channel >= 100 && channel <= 116)
388 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
389 		else if (channel >= 118 && channel <= 177)
390 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
391 	}
392 
393 	switch (bw) {
394 	case RTW_CHANNEL_WIDTH_20:
395 	default:
396 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
397 		val32 &= 0xffcffc00;
398 		val32 |= 0x10010000;
399 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
400 
401 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
402 		break;
403 	case RTW_CHANNEL_WIDTH_40:
404 		if (primary_ch_idx == 1)
405 			rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
406 		else
407 			rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
408 
409 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
410 		val32 &= 0xff3ff300;
411 		val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
412 			 RTW_CHANNEL_WIDTH_40;
413 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
414 
415 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
416 		break;
417 	case RTW_CHANNEL_WIDTH_80:
418 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
419 		val32 &= 0xfcffcf00;
420 		val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
421 			 RTW_CHANNEL_WIDTH_80;
422 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
423 
424 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
425 		break;
426 	case RTW_CHANNEL_WIDTH_5:
427 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
428 		val32 &= 0xefcefc00;
429 		val32 |= 0x200240;
430 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
431 
432 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
433 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
434 		break;
435 	case RTW_CHANNEL_WIDTH_10:
436 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
437 		val32 &= 0xefcefc00;
438 		val32 |= 0x300380;
439 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
440 
441 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
442 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
443 		break;
444 	}
445 }
446 
447 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
448 {
449 	struct rtw_efuse efuse = rtwdev->efuse;
450 	u8 tx_bb_swing;
451 	u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
452 
453 	tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
454 				      efuse.tx_bb_swing_setting_5g;
455 	if (tx_bb_swing > 9)
456 		tx_bb_swing = 0;
457 
458 	return swing2setting[(tx_bb_swing / 3)];
459 }
460 
461 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
462 					  u8 bw, u8 primary_ch_idx)
463 {
464 	rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
465 			 rtw8821c_get_bb_swing(rtwdev, channel));
466 	rtw8821c_pwrtrack_init(rtwdev);
467 }
468 
469 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
470 				 u8 primary_chan_idx)
471 {
472 	rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
473 	rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
474 	rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
475 	rtw8821c_set_channel_rf(rtwdev, channel, bw);
476 	rtw8821c_set_channel_rxdfir(rtwdev, bw);
477 }
478 
479 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
480 {
481 	struct rtw_efuse *efuse = &rtwdev->efuse;
482 	const s8 *lna_gain_table;
483 	int lna_gain_table_size;
484 	s8 rx_pwr_all = 0;
485 	s8 lna_gain = 0;
486 
487 	if (efuse->rfe_option == 0) {
488 		lna_gain_table = lna_gain_table_0;
489 		lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0);
490 	} else {
491 		lna_gain_table = lna_gain_table_1;
492 		lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1);
493 	}
494 
495 	if (lna_idx >= lna_gain_table_size) {
496 		rtw_info(rtwdev, "incorrect lna index (%d)\n", lna_idx);
497 		return -120;
498 	}
499 
500 	lna_gain = lna_gain_table[lna_idx];
501 	rx_pwr_all = lna_gain - 2 * vga_idx;
502 
503 	return rx_pwr_all;
504 }
505 
506 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
507 				   struct rtw_rx_pkt_stat *pkt_stat)
508 {
509 	s8 rx_power;
510 	u8 lna_idx = 0;
511 	u8 vga_idx = 0;
512 
513 	vga_idx = GET_PHY_STAT_P0_VGA(phy_status);
514 	lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) |
515 		  FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status));
516 	rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
517 
518 	pkt_stat->rx_power[RF_PATH_A] = rx_power;
519 	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
520 	pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
521 	pkt_stat->signal_power = rx_power;
522 }
523 
524 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
525 				   struct rtw_rx_pkt_stat *pkt_stat)
526 {
527 	u8 rxsc, bw;
528 	s8 min_rx_power = -120;
529 
530 	if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
531 		rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
532 	else
533 		rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
534 
535 	if (rxsc >= 1 && rxsc <= 8)
536 		bw = RTW_CHANNEL_WIDTH_20;
537 	else if (rxsc >= 9 && rxsc <= 12)
538 		bw = RTW_CHANNEL_WIDTH_40;
539 	else if (rxsc >= 13)
540 		bw = RTW_CHANNEL_WIDTH_80;
541 	else
542 		bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
543 
544 	pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
545 	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
546 	pkt_stat->bw = bw;
547 	pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
548 				     min_rx_power);
549 }
550 
551 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
552 			     struct rtw_rx_pkt_stat *pkt_stat)
553 {
554 	u8 page;
555 
556 	page = *phy_status & 0xf;
557 
558 	switch (page) {
559 	case 0:
560 		query_phy_status_page0(rtwdev, phy_status, pkt_stat);
561 		break;
562 	case 1:
563 		query_phy_status_page1(rtwdev, phy_status, pkt_stat);
564 		break;
565 	default:
566 		rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
567 		return;
568 	}
569 }
570 
571 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
572 				   struct rtw_rx_pkt_stat *pkt_stat,
573 				   struct ieee80211_rx_status *rx_status)
574 {
575 	struct ieee80211_hdr *hdr;
576 	u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
577 	u8 *phy_status = NULL;
578 
579 	memset(pkt_stat, 0, sizeof(*pkt_stat));
580 
581 	pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
582 	pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
583 	pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
584 	pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
585 			      GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
586 	pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
587 	pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
588 	pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
589 	pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
590 	pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
591 	pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
592 	pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
593 	pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
594 
595 	/* drv_info_sz is in unit of 8-bytes */
596 	pkt_stat->drv_info_sz *= 8;
597 
598 	/* c2h cmd pkt's rx/phy status is not interested */
599 	if (pkt_stat->is_c2h)
600 		return;
601 
602 	hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
603 				       pkt_stat->drv_info_sz);
604 	if (pkt_stat->phy_status) {
605 		phy_status = rx_desc + desc_sz + pkt_stat->shift;
606 		query_phy_status(rtwdev, phy_status, pkt_stat);
607 	}
608 
609 	rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
610 }
611 
612 static void
613 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
614 {
615 	struct rtw_hal *hal = &rtwdev->hal;
616 	static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
617 	static u32 phy_pwr_idx;
618 	u8 rate, rate_idx, pwr_index, shift;
619 	int j;
620 
621 	for (j = 0; j < rtw_rate_size[rs]; j++) {
622 		rate = rtw_rate_section[rs][j];
623 		pwr_index = hal->tx_pwr_tbl[path][rate];
624 		shift = rate & 0x3;
625 		phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
626 		if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
627 			rate_idx = rate & 0xfc;
628 			rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
629 				    phy_pwr_idx);
630 			phy_pwr_idx = 0;
631 		}
632 	}
633 }
634 
635 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
636 {
637 	struct rtw_hal *hal = &rtwdev->hal;
638 	int rs, path;
639 
640 	for (path = 0; path < hal->rf_path_num; path++) {
641 		for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
642 			if (rs == RTW_RATE_SECTION_HT_2S ||
643 			    rs == RTW_RATE_SECTION_VHT_2S)
644 				continue;
645 			rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs);
646 		}
647 	}
648 }
649 
650 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
651 {
652 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
653 	u32 cck_enable;
654 	u32 cck_fa_cnt;
655 	u32 ofdm_fa_cnt;
656 	u32 crc32_cnt;
657 	u32 cca32_cnt;
658 
659 	cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
660 	cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
661 	ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
662 
663 	dm_info->cck_fa_cnt = cck_fa_cnt;
664 	dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
665 	if (cck_enable)
666 		dm_info->total_fa_cnt += cck_fa_cnt;
667 	dm_info->total_fa_cnt = ofdm_fa_cnt;
668 
669 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
670 	dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
671 	dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
672 
673 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
674 	dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
675 	dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
676 
677 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
678 	dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
679 	dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
680 
681 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
682 	dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
683 	dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
684 
685 	cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
686 	dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
687 	dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
688 	if (cck_enable) {
689 		cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
690 		dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
691 		dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
692 	}
693 
694 	rtw_write32_set(rtwdev, REG_FAS, BIT(17));
695 	rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
696 	rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
697 	rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
698 	rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
699 	rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
700 }
701 
702 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
703 {
704 	static int do_iqk_cnt;
705 	struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
706 	u32 rf_reg, iqk_fail_mask;
707 	int counter;
708 	bool reload;
709 
710 	if (rtw_is_assoc(rtwdev))
711 		para.segment_iqk = 1;
712 
713 	rtw_fw_do_iqk(rtwdev, &para);
714 
715 	for (counter = 0; counter < 300; counter++) {
716 		rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
717 		if (rf_reg == 0xabcde)
718 			break;
719 		msleep(20);
720 	}
721 	rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
722 
723 	reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
724 	iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
725 	rtw_dbg(rtwdev, RTW_DBG_PHY,
726 		"iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
727 		counter, reload, ++do_iqk_cnt, iqk_fail_mask);
728 }
729 
730 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
731 {
732 	rtw8821c_do_iqk(rtwdev);
733 }
734 
735 /* for coex */
736 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
737 {
738 	/* enable TBTT nterrupt */
739 	rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
740 
741 	/* BT report packet sample rate */
742 	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
743 
744 	/* enable BT counter statistics */
745 	rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
746 
747 	/* enable PTA (3-wire function form BT side) */
748 	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
749 	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
750 
751 	/* enable PTA (tx/rx signal form WiFi side) */
752 	rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
753 	/* wl tx signal to PTA not case EDCCA */
754 	rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
755 	/* GNT_BT=1 while select both */
756 	rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
757 
758 	/* beacon queue always hi-pri  */
759 	rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
760 			BCN_PRI_EN);
761 }
762 
763 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
764 					 u8 pos_type)
765 {
766 	struct rtw_coex *coex = &rtwdev->coex;
767 	struct rtw_coex_dm *coex_dm = &coex->dm;
768 	struct rtw_coex_rfe *coex_rfe = &coex->rfe;
769 	u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type;
770 	bool polarity_inverse;
771 	u8 regval = 0;
772 
773 	if (switch_status == coex_dm->cur_switch_status)
774 		return;
775 
776 	coex_dm->cur_switch_status = switch_status;
777 
778 	if (coex_rfe->ant_switch_diversity &&
779 	    ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
780 		ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
781 
782 	polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
783 
784 	switch (ctrl_type) {
785 	default:
786 	case COEX_SWITCH_CTRL_BY_BBSW:
787 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
788 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
789 		/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
790 		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
791 				DPDT_CTRL_PIN);
792 
793 		if (pos_type == COEX_SWITCH_TO_WLG_BT) {
794 			if (coex_rfe->rfe_module_type != 0x4 &&
795 			    coex_rfe->rfe_module_type != 0x2)
796 				regval = 0x3;
797 			else
798 				regval = (!polarity_inverse ? 0x2 : 0x1);
799 		} else if (pos_type == COEX_SWITCH_TO_WLG) {
800 			regval = (!polarity_inverse ? 0x2 : 0x1);
801 		} else {
802 			regval = (!polarity_inverse ? 0x1 : 0x2);
803 		}
804 
805 		rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
806 				 regval);
807 		break;
808 	case COEX_SWITCH_CTRL_BY_PTA:
809 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
810 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
811 		/* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
812 		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
813 				PTA_CTRL_PIN);
814 
815 		regval = (!polarity_inverse ? 0x2 : 0x1);
816 		rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
817 				 regval);
818 		break;
819 	case COEX_SWITCH_CTRL_BY_ANTDIV:
820 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
821 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
822 		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
823 				ANTDIC_CTRL_PIN);
824 		break;
825 	case COEX_SWITCH_CTRL_BY_MAC:
826 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
827 
828 		regval = (!polarity_inverse ? 0x0 : 0x1);
829 		rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
830 				regval);
831 		break;
832 	case COEX_SWITCH_CTRL_BY_FW:
833 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
834 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
835 		break;
836 	case COEX_SWITCH_CTRL_BY_BT:
837 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
838 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
839 		break;
840 	}
841 
842 	if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
843 		rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
844 		rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
845 	} else {
846 		rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
847 		rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
848 	}
849 }
850 
851 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
852 {}
853 
854 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
855 {
856 	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
857 	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
858 	rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
859 	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
860 	rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
861 	rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
862 }
863 
864 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
865 {
866 	struct rtw_coex *coex = &rtwdev->coex;
867 	struct rtw_coex_rfe *coex_rfe = &coex->rfe;
868 	struct rtw_efuse *efuse = &rtwdev->efuse;
869 
870 	coex_rfe->rfe_module_type = efuse->rfe_option;
871 	coex_rfe->ant_switch_polarity = 0;
872 	coex_rfe->ant_switch_exist = true;
873 	coex_rfe->wlg_at_btg = false;
874 
875 	switch (coex_rfe->rfe_module_type) {
876 	case 0:
877 	case 8:
878 	case 1:
879 	case 9:  /* 1-Ant, Main, WLG */
880 	default: /* 2-Ant, DPDT, WLG */
881 		break;
882 	case 2:
883 	case 10: /* 1-Ant, Main, BTG */
884 	case 7:
885 	case 15: /* 2-Ant, DPDT, BTG */
886 		coex_rfe->wlg_at_btg = true;
887 		break;
888 	case 3:
889 	case 11: /* 1-Ant, Aux, WLG */
890 		coex_rfe->ant_switch_polarity = 1;
891 		break;
892 	case 4:
893 	case 12: /* 1-Ant, Aux, BTG */
894 		coex_rfe->wlg_at_btg = true;
895 		coex_rfe->ant_switch_polarity = 1;
896 		break;
897 	case 5:
898 	case 13: /* 2-Ant, no switch, WLG */
899 	case 6:
900 	case 14: /* 2-Ant, no antenna switch, WLG */
901 		coex_rfe->ant_switch_exist = false;
902 		break;
903 	}
904 }
905 
906 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
907 {
908 	struct rtw_coex *coex = &rtwdev->coex;
909 	struct rtw_coex_dm *coex_dm = &coex->dm;
910 	struct rtw_efuse *efuse = &rtwdev->efuse;
911 	bool share_ant = efuse->share_ant;
912 
913 	if (share_ant)
914 		return;
915 
916 	if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
917 		return;
918 
919 	coex_dm->cur_wl_pwr_lvl = wl_pwr;
920 }
921 
922 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
923 {}
924 
925 static void
926 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
927 			    s8 pwr_idx_offset_lower,
928 			    s8 *txagc_idx, u8 *swing_idx)
929 {
930 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
931 	s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
932 	u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
933 	u8 swing_lower_bound = 0;
934 	u8 max_pwr_idx_offset = 0xf;
935 	s8 agc_index = 0;
936 	u8 swing_index = dm_info->default_ofdm_index;
937 
938 	pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset);
939 	pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
940 
941 	if (delta_pwr_idx >= 0) {
942 		if (delta_pwr_idx <= pwr_idx_offset) {
943 			agc_index = delta_pwr_idx;
944 			swing_index = dm_info->default_ofdm_index;
945 		} else if (delta_pwr_idx > pwr_idx_offset) {
946 			agc_index = pwr_idx_offset;
947 			swing_index = dm_info->default_ofdm_index +
948 					delta_pwr_idx - pwr_idx_offset;
949 			swing_index = min_t(u8, swing_index, swing_upper_bound);
950 		}
951 	} else if (delta_pwr_idx < 0) {
952 		if (delta_pwr_idx >= pwr_idx_offset_lower) {
953 			agc_index = delta_pwr_idx;
954 			swing_index = dm_info->default_ofdm_index;
955 		} else if (delta_pwr_idx < pwr_idx_offset_lower) {
956 			if (dm_info->default_ofdm_index >
957 				(pwr_idx_offset_lower - delta_pwr_idx))
958 				swing_index = dm_info->default_ofdm_index +
959 					delta_pwr_idx - pwr_idx_offset_lower;
960 			else
961 				swing_index = swing_lower_bound;
962 
963 			agc_index = pwr_idx_offset_lower;
964 		}
965 	}
966 
967 	if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) {
968 		rtw_warn(rtwdev, "swing index overflow\n");
969 		swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
970 	}
971 
972 	*txagc_idx = agc_index;
973 	*swing_idx = swing_index;
974 }
975 
976 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
977 				      s8 pwr_idx_offset_lower)
978 {
979 	s8 txagc_idx;
980 	u8 swing_idx;
981 
982 	rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
983 				    &txagc_idx, &swing_idx);
984 	rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
985 	rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
986 			 rtw8821c_txscale_tbl[swing_idx]);
987 }
988 
989 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
990 {
991 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
992 	u8 pwr_idx_offset, tx_pwr_idx;
993 	s8 pwr_idx_offset_lower;
994 	u8 channel = rtwdev->hal.current_channel;
995 	u8 band_width = rtwdev->hal.current_band_width;
996 	u8 regd = rtwdev->regd.txpwr_regd;
997 	u8 tx_rate = dm_info->tx_rate;
998 	u8 max_pwr_idx = rtwdev->chip->max_power_index;
999 
1000 	tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
1001 						band_width, channel, regd);
1002 
1003 	tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1004 
1005 	pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1006 	pwr_idx_offset_lower = 0 - tx_pwr_idx;
1007 
1008 	rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
1009 }
1010 
1011 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
1012 {
1013 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1014 	struct rtw_swing_table swing_table;
1015 	u8 thermal_value, delta;
1016 
1017 	rtw_phy_config_swing_table(rtwdev, &swing_table);
1018 
1019 	if (rtwdev->efuse.thermal_meter[0] == 0xff)
1020 		return;
1021 
1022 	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1023 
1024 	rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1025 
1026 	if (dm_info->pwr_trk_init_trigger)
1027 		dm_info->pwr_trk_init_trigger = false;
1028 	else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1029 						   RF_PATH_A))
1030 		goto iqk;
1031 
1032 	delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1033 
1034 	delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1035 
1036 	dm_info->delta_power_index[RF_PATH_A] =
1037 		rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
1038 					    RF_PATH_A, delta);
1039 	if (dm_info->delta_power_index[RF_PATH_A] ==
1040 			dm_info->delta_power_index_last[RF_PATH_A])
1041 		goto iqk;
1042 	else
1043 		dm_info->delta_power_index_last[RF_PATH_A] =
1044 			dm_info->delta_power_index[RF_PATH_A];
1045 	rtw8821c_pwrtrack_set(rtwdev);
1046 
1047 iqk:
1048 	if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1049 		rtw8821c_do_iqk(rtwdev);
1050 }
1051 
1052 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
1053 {
1054 	struct rtw_efuse *efuse = &rtwdev->efuse;
1055 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1056 
1057 	if (efuse->power_track_type != 0)
1058 		return;
1059 
1060 	if (!dm_info->pwr_trk_triggered) {
1061 		rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1062 			     GENMASK(17, 16), 0x03);
1063 		dm_info->pwr_trk_triggered = true;
1064 		return;
1065 	}
1066 
1067 	rtw8821c_phy_pwrtrack(rtwdev);
1068 	dm_info->pwr_trk_triggered = false;
1069 }
1070 
1071 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev,
1072 				       struct rtw_vif *vif,
1073 				       struct rtw_bfee *bfee, bool enable)
1074 {
1075 	if (enable)
1076 		rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1077 	else
1078 		rtw_bf_remove_bfee_su(rtwdev, bfee);
1079 }
1080 
1081 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1082 				       struct rtw_vif *vif,
1083 				       struct rtw_bfee *bfee, bool enable)
1084 {
1085 	if (enable)
1086 		rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1087 	else
1088 		rtw_bf_remove_bfee_mu(rtwdev, bfee);
1089 }
1090 
1091 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1092 				    struct rtw_bfee *bfee, bool enable)
1093 {
1094 	if (bfee->role == RTW_BFEE_SU)
1095 		rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1096 	else if (bfee->role == RTW_BFEE_MU)
1097 		rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1098 	else
1099 		rtw_warn(rtwdev, "wrong bfee role\n");
1100 }
1101 
1102 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1103 {
1104 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1105 	u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1106 	u8 cck_n_rx;
1107 
1108 	rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1109 		dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1110 
1111 	if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1112 		return;
1113 
1114 	cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1115 		    rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1116 	rtw_dbg(rtwdev, RTW_DBG_PHY,
1117 		"is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1118 		rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1119 		dm_info->cck_pd_default + new_lvl * 2,
1120 		pd[new_lvl], dm_info->cck_fa_avg);
1121 
1122 	dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1123 
1124 	dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1125 	rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1126 	rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1127 			 dm_info->cck_pd_default + new_lvl * 2);
1128 }
1129 
1130 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1131 	{0x0086,
1132 	 RTW_PWR_CUT_ALL_MSK,
1133 	 RTW_PWR_INTF_SDIO_MSK,
1134 	 RTW_PWR_ADDR_SDIO,
1135 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1136 	{0x0086,
1137 	 RTW_PWR_CUT_ALL_MSK,
1138 	 RTW_PWR_INTF_SDIO_MSK,
1139 	 RTW_PWR_ADDR_SDIO,
1140 	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1141 	{0x004A,
1142 	 RTW_PWR_CUT_ALL_MSK,
1143 	 RTW_PWR_INTF_USB_MSK,
1144 	 RTW_PWR_ADDR_MAC,
1145 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1146 	{0x0005,
1147 	 RTW_PWR_CUT_ALL_MSK,
1148 	 RTW_PWR_INTF_ALL_MSK,
1149 	 RTW_PWR_ADDR_MAC,
1150 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1151 	{0x0300,
1152 	 RTW_PWR_CUT_ALL_MSK,
1153 	 RTW_PWR_INTF_PCI_MSK,
1154 	 RTW_PWR_ADDR_MAC,
1155 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1156 	{0x0301,
1157 	 RTW_PWR_CUT_ALL_MSK,
1158 	 RTW_PWR_INTF_PCI_MSK,
1159 	 RTW_PWR_ADDR_MAC,
1160 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1161 	{0xFFFF,
1162 	 RTW_PWR_CUT_ALL_MSK,
1163 	 RTW_PWR_INTF_ALL_MSK,
1164 	 0,
1165 	 RTW_PWR_CMD_END, 0, 0},
1166 };
1167 
1168 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
1169 	{0x0020,
1170 	 RTW_PWR_CUT_ALL_MSK,
1171 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1172 	 RTW_PWR_ADDR_MAC,
1173 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1174 	{0x0001,
1175 	 RTW_PWR_CUT_ALL_MSK,
1176 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1177 	 RTW_PWR_ADDR_MAC,
1178 	 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1179 	{0x0000,
1180 	 RTW_PWR_CUT_ALL_MSK,
1181 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1182 	 RTW_PWR_ADDR_MAC,
1183 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1184 	{0x0005,
1185 	 RTW_PWR_CUT_ALL_MSK,
1186 	 RTW_PWR_INTF_ALL_MSK,
1187 	 RTW_PWR_ADDR_MAC,
1188 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1189 	{0x0075,
1190 	 RTW_PWR_CUT_ALL_MSK,
1191 	 RTW_PWR_INTF_PCI_MSK,
1192 	 RTW_PWR_ADDR_MAC,
1193 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1194 	{0x0006,
1195 	 RTW_PWR_CUT_ALL_MSK,
1196 	 RTW_PWR_INTF_ALL_MSK,
1197 	 RTW_PWR_ADDR_MAC,
1198 	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1199 	{0x0075,
1200 	 RTW_PWR_CUT_ALL_MSK,
1201 	 RTW_PWR_INTF_PCI_MSK,
1202 	 RTW_PWR_ADDR_MAC,
1203 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1204 	{0x0006,
1205 	 RTW_PWR_CUT_ALL_MSK,
1206 	 RTW_PWR_INTF_ALL_MSK,
1207 	 RTW_PWR_ADDR_MAC,
1208 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1209 	{0x0005,
1210 	 RTW_PWR_CUT_ALL_MSK,
1211 	 RTW_PWR_INTF_ALL_MSK,
1212 	 RTW_PWR_ADDR_MAC,
1213 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
1214 	{0x0005,
1215 	 RTW_PWR_CUT_ALL_MSK,
1216 	 RTW_PWR_INTF_ALL_MSK,
1217 	 RTW_PWR_ADDR_MAC,
1218 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1219 	{0x10C3,
1220 	 RTW_PWR_CUT_ALL_MSK,
1221 	 RTW_PWR_INTF_USB_MSK,
1222 	 RTW_PWR_ADDR_MAC,
1223 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1224 	{0x0005,
1225 	 RTW_PWR_CUT_ALL_MSK,
1226 	 RTW_PWR_INTF_ALL_MSK,
1227 	 RTW_PWR_ADDR_MAC,
1228 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1229 	{0x0005,
1230 	 RTW_PWR_CUT_ALL_MSK,
1231 	 RTW_PWR_INTF_ALL_MSK,
1232 	 RTW_PWR_ADDR_MAC,
1233 	 RTW_PWR_CMD_POLLING, BIT(0), 0},
1234 	{0x0020,
1235 	 RTW_PWR_CUT_ALL_MSK,
1236 	 RTW_PWR_INTF_ALL_MSK,
1237 	 RTW_PWR_ADDR_MAC,
1238 	 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1239 	{0x0074,
1240 	 RTW_PWR_CUT_ALL_MSK,
1241 	 RTW_PWR_INTF_PCI_MSK,
1242 	 RTW_PWR_ADDR_MAC,
1243 	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1244 	{0x0022,
1245 	 RTW_PWR_CUT_ALL_MSK,
1246 	 RTW_PWR_INTF_PCI_MSK,
1247 	 RTW_PWR_ADDR_MAC,
1248 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1249 	{0x0062,
1250 	 RTW_PWR_CUT_ALL_MSK,
1251 	 RTW_PWR_INTF_PCI_MSK,
1252 	 RTW_PWR_ADDR_MAC,
1253 	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1254 	 (BIT(7) | BIT(6) | BIT(5))},
1255 	{0x0061,
1256 	 RTW_PWR_CUT_ALL_MSK,
1257 	 RTW_PWR_INTF_PCI_MSK,
1258 	 RTW_PWR_ADDR_MAC,
1259 	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1260 	{0x007C,
1261 	 RTW_PWR_CUT_ALL_MSK,
1262 	 RTW_PWR_INTF_ALL_MSK,
1263 	 RTW_PWR_ADDR_MAC,
1264 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1265 	{0xFFFF,
1266 	 RTW_PWR_CUT_ALL_MSK,
1267 	 RTW_PWR_INTF_ALL_MSK,
1268 	 0,
1269 	 RTW_PWR_CMD_END, 0, 0},
1270 };
1271 
1272 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
1273 	{0x0093,
1274 	 RTW_PWR_CUT_ALL_MSK,
1275 	 RTW_PWR_INTF_ALL_MSK,
1276 	 RTW_PWR_ADDR_MAC,
1277 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1278 	{0x001F,
1279 	 RTW_PWR_CUT_ALL_MSK,
1280 	 RTW_PWR_INTF_ALL_MSK,
1281 	 RTW_PWR_ADDR_MAC,
1282 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1283 	{0x0049,
1284 	 RTW_PWR_CUT_ALL_MSK,
1285 	 RTW_PWR_INTF_ALL_MSK,
1286 	 RTW_PWR_ADDR_MAC,
1287 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1288 	{0x0006,
1289 	 RTW_PWR_CUT_ALL_MSK,
1290 	 RTW_PWR_INTF_ALL_MSK,
1291 	 RTW_PWR_ADDR_MAC,
1292 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1293 	{0x0002,
1294 	 RTW_PWR_CUT_ALL_MSK,
1295 	 RTW_PWR_INTF_ALL_MSK,
1296 	 RTW_PWR_ADDR_MAC,
1297 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1298 	{0x10C3,
1299 	 RTW_PWR_CUT_ALL_MSK,
1300 	 RTW_PWR_INTF_USB_MSK,
1301 	 RTW_PWR_ADDR_MAC,
1302 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1303 	{0x0005,
1304 	 RTW_PWR_CUT_ALL_MSK,
1305 	 RTW_PWR_INTF_ALL_MSK,
1306 	 RTW_PWR_ADDR_MAC,
1307 	 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1308 	{0x0005,
1309 	 RTW_PWR_CUT_ALL_MSK,
1310 	 RTW_PWR_INTF_ALL_MSK,
1311 	 RTW_PWR_ADDR_MAC,
1312 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1313 	{0x0020,
1314 	 RTW_PWR_CUT_ALL_MSK,
1315 	 RTW_PWR_INTF_ALL_MSK,
1316 	 RTW_PWR_ADDR_MAC,
1317 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1318 	{0x0000,
1319 	 RTW_PWR_CUT_ALL_MSK,
1320 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1321 	 RTW_PWR_ADDR_MAC,
1322 	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1323 	{0xFFFF,
1324 	 RTW_PWR_CUT_ALL_MSK,
1325 	 RTW_PWR_INTF_ALL_MSK,
1326 	 0,
1327 	 RTW_PWR_CMD_END, 0, 0},
1328 };
1329 
1330 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
1331 	{0x0007,
1332 	 RTW_PWR_CUT_ALL_MSK,
1333 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1334 	 RTW_PWR_ADDR_MAC,
1335 	 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1336 	{0x0067,
1337 	 RTW_PWR_CUT_ALL_MSK,
1338 	 RTW_PWR_INTF_ALL_MSK,
1339 	 RTW_PWR_ADDR_MAC,
1340 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1341 	{0x0005,
1342 	 RTW_PWR_CUT_ALL_MSK,
1343 	 RTW_PWR_INTF_PCI_MSK,
1344 	 RTW_PWR_ADDR_MAC,
1345 	 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1346 	{0x004A,
1347 	 RTW_PWR_CUT_ALL_MSK,
1348 	 RTW_PWR_INTF_USB_MSK,
1349 	 RTW_PWR_ADDR_MAC,
1350 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1351 	{0x0067,
1352 	 RTW_PWR_CUT_ALL_MSK,
1353 	 RTW_PWR_INTF_SDIO_MSK,
1354 	 RTW_PWR_ADDR_MAC,
1355 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1356 	{0x0067,
1357 	 RTW_PWR_CUT_ALL_MSK,
1358 	 RTW_PWR_INTF_SDIO_MSK,
1359 	 RTW_PWR_ADDR_MAC,
1360 	 RTW_PWR_CMD_WRITE, BIT(4), 0},
1361 	{0x004F,
1362 	 RTW_PWR_CUT_ALL_MSK,
1363 	 RTW_PWR_INTF_SDIO_MSK,
1364 	 RTW_PWR_ADDR_MAC,
1365 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1366 	{0x0067,
1367 	 RTW_PWR_CUT_ALL_MSK,
1368 	 RTW_PWR_INTF_SDIO_MSK,
1369 	 RTW_PWR_ADDR_MAC,
1370 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1371 	{0x0046,
1372 	 RTW_PWR_CUT_ALL_MSK,
1373 	 RTW_PWR_INTF_SDIO_MSK,
1374 	 RTW_PWR_ADDR_MAC,
1375 	 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1376 	{0x0067,
1377 	 RTW_PWR_CUT_ALL_MSK,
1378 	 RTW_PWR_INTF_SDIO_MSK,
1379 	 RTW_PWR_ADDR_MAC,
1380 	 RTW_PWR_CMD_WRITE, BIT(2), 0},
1381 	{0x0046,
1382 	 RTW_PWR_CUT_ALL_MSK,
1383 	 RTW_PWR_INTF_SDIO_MSK,
1384 	 RTW_PWR_ADDR_MAC,
1385 	 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1386 	{0x0062,
1387 	 RTW_PWR_CUT_ALL_MSK,
1388 	 RTW_PWR_INTF_SDIO_MSK,
1389 	 RTW_PWR_ADDR_MAC,
1390 	 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1391 	{0x0081,
1392 	 RTW_PWR_CUT_ALL_MSK,
1393 	 RTW_PWR_INTF_ALL_MSK,
1394 	 RTW_PWR_ADDR_MAC,
1395 	 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1396 	{0x0005,
1397 	 RTW_PWR_CUT_ALL_MSK,
1398 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1399 	 RTW_PWR_ADDR_MAC,
1400 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1401 	{0x0086,
1402 	 RTW_PWR_CUT_ALL_MSK,
1403 	 RTW_PWR_INTF_SDIO_MSK,
1404 	 RTW_PWR_ADDR_SDIO,
1405 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1406 	{0x0086,
1407 	 RTW_PWR_CUT_ALL_MSK,
1408 	 RTW_PWR_INTF_SDIO_MSK,
1409 	 RTW_PWR_ADDR_SDIO,
1410 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1411 	{0x0090,
1412 	 RTW_PWR_CUT_ALL_MSK,
1413 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1414 	 RTW_PWR_ADDR_MAC,
1415 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1416 	{0x0044,
1417 	 RTW_PWR_CUT_ALL_MSK,
1418 	 RTW_PWR_INTF_SDIO_MSK,
1419 	 RTW_PWR_ADDR_SDIO,
1420 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1421 	{0x0040,
1422 	 RTW_PWR_CUT_ALL_MSK,
1423 	 RTW_PWR_INTF_SDIO_MSK,
1424 	 RTW_PWR_ADDR_SDIO,
1425 	 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1426 	{0x0041,
1427 	 RTW_PWR_CUT_ALL_MSK,
1428 	 RTW_PWR_INTF_SDIO_MSK,
1429 	 RTW_PWR_ADDR_SDIO,
1430 	 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1431 	{0x0042,
1432 	 RTW_PWR_CUT_ALL_MSK,
1433 	 RTW_PWR_INTF_SDIO_MSK,
1434 	 RTW_PWR_ADDR_SDIO,
1435 	 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1436 	{0xFFFF,
1437 	 RTW_PWR_CUT_ALL_MSK,
1438 	 RTW_PWR_INTF_ALL_MSK,
1439 	 0,
1440 	 RTW_PWR_CMD_END, 0, 0},
1441 };
1442 
1443 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = {
1444 	trans_carddis_to_cardemu_8821c,
1445 	trans_cardemu_to_act_8821c,
1446 	NULL
1447 };
1448 
1449 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = {
1450 	trans_act_to_cardemu_8821c,
1451 	trans_cardemu_to_carddis_8821c,
1452 	NULL
1453 };
1454 
1455 static const struct rtw_intf_phy_para usb2_param_8821c[] = {
1456 	{0xFFFF, 0x00,
1457 	 RTW_IP_SEL_PHY,
1458 	 RTW_INTF_PHY_CUT_ALL,
1459 	 RTW_INTF_PHY_PLATFORM_ALL},
1460 };
1461 
1462 static const struct rtw_intf_phy_para usb3_param_8821c[] = {
1463 	{0xFFFF, 0x0000,
1464 	 RTW_IP_SEL_PHY,
1465 	 RTW_INTF_PHY_CUT_ALL,
1466 	 RTW_INTF_PHY_PLATFORM_ALL},
1467 };
1468 
1469 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
1470 	{0x0009, 0x6380,
1471 	 RTW_IP_SEL_PHY,
1472 	 RTW_INTF_PHY_CUT_ALL,
1473 	 RTW_INTF_PHY_PLATFORM_ALL},
1474 	{0xFFFF, 0x0000,
1475 	 RTW_IP_SEL_PHY,
1476 	 RTW_INTF_PHY_CUT_ALL,
1477 	 RTW_INTF_PHY_PLATFORM_ALL},
1478 };
1479 
1480 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
1481 	{0xFFFF, 0x0000,
1482 	 RTW_IP_SEL_PHY,
1483 	 RTW_INTF_PHY_CUT_ALL,
1484 	 RTW_INTF_PHY_PLATFORM_ALL},
1485 };
1486 
1487 static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
1488 	.usb2_para	= usb2_param_8821c,
1489 	.usb3_para	= usb3_param_8821c,
1490 	.gen1_para	= pcie_gen1_param_8821c,
1491 	.gen2_para	= pcie_gen2_param_8821c,
1492 	.n_usb2_para	= ARRAY_SIZE(usb2_param_8821c),
1493 	.n_usb3_para	= ARRAY_SIZE(usb2_param_8821c),
1494 	.n_gen1_para	= ARRAY_SIZE(pcie_gen1_param_8821c),
1495 	.n_gen2_para	= ARRAY_SIZE(pcie_gen2_param_8821c),
1496 };
1497 
1498 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1499 	[0] = RTW_DEF_RFE(8821c, 0, 0),
1500 	[2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1501 };
1502 
1503 static struct rtw_hw_reg rtw8821c_dig[] = {
1504 	[0] = { .addr = 0xc50, .mask = 0x7f },
1505 };
1506 
1507 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1508 	.ctrl = LTECOEX_ACCESS_CTRL,
1509 	.wdata = LTECOEX_WRITE_DATA,
1510 	.rdata = LTECOEX_READ_DATA,
1511 };
1512 
1513 static struct rtw_page_table page_table_8821c[] = {
1514 	/* not sure what [0] stands for */
1515 	{16, 16, 16, 14, 1},
1516 	{16, 16, 16, 14, 1},
1517 	{16, 16, 0, 0, 1},
1518 	{16, 16, 16, 0, 1},
1519 	{16, 16, 16, 14, 1},
1520 };
1521 
1522 static struct rtw_rqpn rqpn_table_8821c[] = {
1523 	/* not sure what [0] stands for */
1524 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1525 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1526 	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1527 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1528 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1529 	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1530 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1531 	 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1532 	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1533 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1534 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1535 	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1536 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1537 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1538 	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1539 };
1540 
1541 static struct rtw_prioq_addrs prioq_addrs_8821c = {
1542 	.prio[RTW_DMA_MAPPING_EXTRA] = {
1543 		.rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
1544 	},
1545 	.prio[RTW_DMA_MAPPING_LOW] = {
1546 		.rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
1547 	},
1548 	.prio[RTW_DMA_MAPPING_NORMAL] = {
1549 		.rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
1550 	},
1551 	.prio[RTW_DMA_MAPPING_HIGH] = {
1552 		.rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
1553 	},
1554 	.wsize = true,
1555 };
1556 
1557 static struct rtw_chip_ops rtw8821c_ops = {
1558 	.phy_set_param		= rtw8821c_phy_set_param,
1559 	.read_efuse		= rtw8821c_read_efuse,
1560 	.query_rx_desc		= rtw8821c_query_rx_desc,
1561 	.set_channel		= rtw8821c_set_channel,
1562 	.mac_init		= rtw8821c_mac_init,
1563 	.read_rf		= rtw_phy_read_rf,
1564 	.write_rf		= rtw_phy_write_rf_reg_sipi,
1565 	.set_antenna		= NULL,
1566 	.set_tx_power_index	= rtw8821c_set_tx_power_index,
1567 	.cfg_ldo25		= rtw8821c_cfg_ldo25,
1568 	.false_alarm_statistics	= rtw8821c_false_alarm_statistics,
1569 	.phy_calibration	= rtw8821c_phy_calibration,
1570 	.cck_pd_set		= rtw8821c_phy_cck_pd_set,
1571 	.pwr_track		= rtw8821c_pwr_track,
1572 	.config_bfee		= rtw8821c_bf_config_bfee,
1573 	.set_gid_table		= rtw_bf_set_gid_table,
1574 	.cfg_csi_rate		= rtw_bf_cfg_csi_rate,
1575 
1576 	.coex_set_init		= rtw8821c_coex_cfg_init,
1577 	.coex_set_ant_switch	= rtw8821c_coex_cfg_ant_switch,
1578 	.coex_set_gnt_fix	= rtw8821c_coex_cfg_gnt_fix,
1579 	.coex_set_gnt_debug	= rtw8821c_coex_cfg_gnt_debug,
1580 	.coex_set_rfe_type	= rtw8821c_coex_cfg_rfe_type,
1581 	.coex_set_wl_tx_power	= rtw8821c_coex_cfg_wl_tx_power,
1582 	.coex_set_wl_rx_gain	= rtw8821c_coex_cfg_wl_rx_gain,
1583 };
1584 
1585 /* rssi in percentage % (dbm = % - 100) */
1586 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40};
1587 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101};
1588 
1589 /* Shared-Antenna Coex Table */
1590 static const struct coex_table_para table_sant_8821c[] = {
1591 	{0x55555555, 0x55555555}, /* case-0 */
1592 	{0x55555555, 0x55555555},
1593 	{0x66555555, 0x66555555},
1594 	{0xaaaaaaaa, 0xaaaaaaaa},
1595 	{0x5a5a5a5a, 0x5a5a5a5a},
1596 	{0xfafafafa, 0xfafafafa}, /* case-5 */
1597 	{0x6a5a5555, 0xaaaaaaaa},
1598 	{0x6a5a56aa, 0x6a5a56aa},
1599 	{0x6a5a5a5a, 0x6a5a5a5a},
1600 	{0x66555555, 0x5a5a5a5a},
1601 	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1602 	{0x66555555, 0xaaaaaaaa},
1603 	{0x66555555, 0x6a5a5aaa},
1604 	{0x66555555, 0x6aaa6aaa},
1605 	{0x66555555, 0x6a5a5aaa},
1606 	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1607 	{0xffff55ff, 0xfafafafa},
1608 	{0xffff55ff, 0x6afa5afa},
1609 	{0xaaffffaa, 0xfafafafa},
1610 	{0xaa5555aa, 0x5a5a5a5a},
1611 	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1612 	{0xaa5555aa, 0xaaaaaaaa},
1613 	{0xffffffff, 0x55555555},
1614 	{0xffffffff, 0x5a5a5a5a},
1615 	{0xffffffff, 0x5a5a5a5a},
1616 	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
1617 	{0x55555555, 0x5a5a5a5a},
1618 	{0x55555555, 0xaaaaaaaa},
1619 	{0x66555555, 0x6a5a6a5a},
1620 	{0x66556655, 0x66556655},
1621 	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1622 	{0xffffffff, 0x5aaa5aaa},
1623 	{0x56555555, 0x5a5a5aaa}
1624 };
1625 
1626 /* Non-Shared-Antenna Coex Table */
1627 static const struct coex_table_para table_nsant_8821c[] = {
1628 	{0xffffffff, 0xffffffff}, /* case-100 */
1629 	{0xffff55ff, 0xfafafafa},
1630 	{0x66555555, 0x66555555},
1631 	{0xaaaaaaaa, 0xaaaaaaaa},
1632 	{0x5a5a5a5a, 0x5a5a5a5a},
1633 	{0xffffffff, 0xffffffff}, /* case-105 */
1634 	{0x5afa5afa, 0x5afa5afa},
1635 	{0x55555555, 0xfafafafa},
1636 	{0x66555555, 0xfafafafa},
1637 	{0x66555555, 0x5a5a5a5a},
1638 	{0x66555555, 0x6a5a5a5a}, /* case-110 */
1639 	{0x66555555, 0xaaaaaaaa},
1640 	{0xffff55ff, 0xfafafafa},
1641 	{0xffff55ff, 0x5afa5afa},
1642 	{0xffff55ff, 0xaaaaaaaa},
1643 	{0xffff55ff, 0xffff55ff}, /* case-115 */
1644 	{0xaaffffaa, 0x5afa5afa},
1645 	{0xaaffffaa, 0xaaaaaaaa},
1646 	{0xffffffff, 0xfafafafa},
1647 	{0xffff55ff, 0xfafafafa},
1648 	{0xffffffff, 0xaaaaaaaa}, /* case-120 */
1649 	{0xffff55ff, 0x5afa5afa},
1650 	{0xffff55ff, 0x5afa5afa},
1651 	{0x55ff55ff, 0x55ff55ff}
1652 };
1653 
1654 /* Shared-Antenna TDMA */
1655 static const struct coex_tdma_para tdma_sant_8821c[] = {
1656 	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1657 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1658 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
1659 	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1660 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1661 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1662 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1663 	{ {0x61, 0x35, 0x03, 0x11, 0x10} },
1664 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1665 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1666 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1667 	{ {0x61, 0x08, 0x03, 0x11, 0x15} },
1668 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1669 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1670 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1671 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1672 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1673 	{ {0x51, 0x3a, 0x03, 0x11, 0x50} },
1674 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1675 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1676 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1677 	{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
1678 	{ {0x51, 0x08, 0x03, 0x30, 0x54} },
1679 	{ {0x55, 0x08, 0x03, 0x10, 0x54} },
1680 	{ {0x65, 0x10, 0x03, 0x11, 0x10} },
1681 	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1682 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1683 	{ {0x61, 0x08, 0x03, 0x11, 0x11} }
1684 };
1685 
1686 /* Non-Shared-Antenna TDMA */
1687 static const struct coex_tdma_para tdma_nsant_8821c[] = {
1688 	{ {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1689 	{ {0x61, 0x45, 0x03, 0x11, 0x11} },
1690 	{ {0x61, 0x25, 0x03, 0x11, 0x11} },
1691 	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1692 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1693 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1694 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1695 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1696 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1697 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1698 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1699 	{ {0x61, 0x10, 0x03, 0x11, 0x11} },
1700 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1701 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1702 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1703 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1704 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1705 	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
1706 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1707 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1708 	{ {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1709 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }
1710 };
1711 
1712 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1713 
1714 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1715 static const struct coex_rf_para rf_para_tx_8821c[] = {
1716 	{0, 0, false, 7},  /* for normal */
1717 	{0, 20, false, 7}, /* for WL-CPT */
1718 	{8, 17, true, 4},
1719 	{7, 18, true, 4},
1720 	{6, 19, true, 4},
1721 	{5, 20, true, 4}
1722 };
1723 
1724 static const struct coex_rf_para rf_para_rx_8821c[] = {
1725 	{0, 0, false, 7},  /* for normal */
1726 	{0, 20, false, 7}, /* for WL-CPT */
1727 	{3, 24, true, 5},
1728 	{2, 26, true, 5},
1729 	{1, 27, true, 5},
1730 	{0, 28, true, 5}
1731 };
1732 
1733 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c));
1734 
1735 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = {
1736 	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1737 	 11, 11, 12, 12, 12, 12, 12},
1738 	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1739 	 11, 12, 12, 12, 12, 12, 12, 12},
1740 	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1741 	 11, 12, 12, 12, 12, 12, 12},
1742 };
1743 
1744 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = {
1745 	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1746 	 12, 12, 12, 12, 12, 12, 12},
1747 	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1748 	 12, 12, 12, 12, 12, 12, 12, 12},
1749 	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1750 	 11, 12, 12, 12, 12, 12, 12, 12},
1751 };
1752 
1753 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = {
1754 	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1755 	 11, 11, 12, 12, 12, 12, 12},
1756 	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1757 	 11, 12, 12, 12, 12, 12, 12, 12},
1758 	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1759 	 11, 12, 12, 12, 12, 12, 12},
1760 };
1761 
1762 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = {
1763 	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1764 	 12, 12, 12, 12, 12, 12, 12},
1765 	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1766 	 12, 12, 12, 12, 12, 12, 12, 12},
1767 	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1768 	 11, 12, 12, 12, 12, 12, 12, 12},
1769 };
1770 
1771 static const u8 rtw8821c_pwrtrk_2gb_n[] = {
1772 	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1773 	4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1774 };
1775 
1776 static const u8 rtw8821c_pwrtrk_2gb_p[] = {
1777 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1778 	5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1779 };
1780 
1781 static const u8 rtw8821c_pwrtrk_2ga_n[] = {
1782 	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1783 	4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1784 };
1785 
1786 static const u8 rtw8821c_pwrtrk_2ga_p[] = {
1787 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1788 	5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1789 };
1790 
1791 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = {
1792 	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1793 	4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1794 };
1795 
1796 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = {
1797 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1798 	5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1799 };
1800 
1801 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = {
1802 	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1803 	4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1804 };
1805 
1806 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = {
1807 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1808 	5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1809 };
1810 
1811 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = {
1812 	.pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1813 	.pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1],
1814 	.pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2],
1815 	.pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1816 	.pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1],
1817 	.pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2],
1818 	.pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1819 	.pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1],
1820 	.pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2],
1821 	.pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1822 	.pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1],
1823 	.pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2],
1824 	.pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n,
1825 	.pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p,
1826 	.pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n,
1827 	.pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p,
1828 	.pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n,
1829 	.pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p,
1830 	.pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n,
1831 	.pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p,
1832 };
1833 
1834 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = {
1835 	{0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1836 	{0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1837 	{0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1838 	{0, 0, RTW_REG_DOMAIN_NL},
1839 	{0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1840 	{0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1841 	{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1842 	{0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1843 	{0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1844 	{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1845 	{0, 0, RTW_REG_DOMAIN_NL},
1846 	{0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1847 	{0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1848 	{0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1849 	{0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1850 	{0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1851 	{0, 0, RTW_REG_DOMAIN_NL},
1852 	{0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1853 	{0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1854 	{0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1855 	{0xc50,  MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1856 	{0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1857 };
1858 
1859 struct rtw_chip_info rtw8821c_hw_spec = {
1860 	.ops = &rtw8821c_ops,
1861 	.id = RTW_CHIP_TYPE_8821C,
1862 	.fw_name = "rtw88/rtw8821c_fw.bin",
1863 	.wlan_cpu = RTW_WCPU_11AC,
1864 	.tx_pkt_desc_sz = 48,
1865 	.tx_buf_desc_sz = 16,
1866 	.rx_pkt_desc_sz = 24,
1867 	.rx_buf_desc_sz = 8,
1868 	.phy_efuse_size = 512,
1869 	.log_efuse_size = 512,
1870 	.ptct_efuse_size = 96,
1871 	.txff_size = 65536,
1872 	.rxff_size = 16384,
1873 	.txgi_factor = 1,
1874 	.is_pwr_by_rate_dec = true,
1875 	.max_power_index = 0x3f,
1876 	.csi_buf_pg_num = 0,
1877 	.band = RTW_BAND_2G | RTW_BAND_5G,
1878 	.page_size = 128,
1879 	.dig_min = 0x1c,
1880 	.ht_supported = true,
1881 	.vht_supported = true,
1882 	.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
1883 	.sys_func_en = 0xD8,
1884 	.pwr_on_seq = card_enable_flow_8821c,
1885 	.pwr_off_seq = card_disable_flow_8821c,
1886 	.page_table = page_table_8821c,
1887 	.rqpn_table = rqpn_table_8821c,
1888 	.prioq_addrs = &prioq_addrs_8821c,
1889 	.intf_table = &phy_para_table_8821c,
1890 	.dig = rtw8821c_dig,
1891 	.rf_base_addr = {0x2800, 0x2c00},
1892 	.rf_sipi_addr = {0xc90, 0xe90},
1893 	.ltecoex_addr = &rtw8821c_ltecoex_addr,
1894 	.mac_tbl = &rtw8821c_mac_tbl,
1895 	.agc_tbl = &rtw8821c_agc_tbl,
1896 	.bb_tbl = &rtw8821c_bb_tbl,
1897 	.rf_tbl = {&rtw8821c_rf_a_tbl},
1898 	.rfe_defs = rtw8821c_rfe_defs,
1899 	.rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
1900 	.rx_ldpc = false,
1901 	.pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl,
1902 	.iqk_threshold = 8,
1903 	.bfer_su_max_num = 2,
1904 	.bfer_mu_max_num = 1,
1905 
1906 	.coex_para_ver = 0x19092746,
1907 	.bt_desired_ver = 0x46,
1908 	.scbd_support = true,
1909 	.new_scbd10_def = false,
1910 	.ble_hid_profile_support = false,
1911 	.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
1912 	.bt_rssi_type = COEX_BTRSSI_RATIO,
1913 	.ant_isolation = 15,
1914 	.rssi_tolerance = 2,
1915 	.wl_rssi_step = wl_rssi_step_8821c,
1916 	.bt_rssi_step = bt_rssi_step_8821c,
1917 	.table_sant_num = ARRAY_SIZE(table_sant_8821c),
1918 	.table_sant = table_sant_8821c,
1919 	.table_nsant_num = ARRAY_SIZE(table_nsant_8821c),
1920 	.table_nsant = table_nsant_8821c,
1921 	.tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c),
1922 	.tdma_sant = tdma_sant_8821c,
1923 	.tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c),
1924 	.tdma_nsant = tdma_nsant_8821c,
1925 	.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c),
1926 	.wl_rf_para_tx = rf_para_tx_8821c,
1927 	.wl_rf_para_rx = rf_para_rx_8821c,
1928 	.bt_afh_span_bw20 = 0x24,
1929 	.bt_afh_span_bw40 = 0x36,
1930 	.afh_5g_num = ARRAY_SIZE(afh_5g_8821c),
1931 	.afh_5g = afh_5g_8821c,
1932 
1933 	.coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c),
1934 	.coex_info_hw_regs = coex_info_hw_regs_8821c,
1935 };
1936 EXPORT_SYMBOL(rtw8821c_hw_spec);
1937 
1938 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
1939 
1940 MODULE_AUTHOR("Realtek Corporation");
1941 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
1942 MODULE_LICENSE("Dual BSD/GPL");
1943