1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 18 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 19 struct rtw8821c_efuse *map) 20 { 21 ether_addr_copy(efuse->addr, map->e.mac_addr); 22 } 23 24 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 25 { 26 struct rtw_efuse *efuse = &rtwdev->efuse; 27 struct rtw8821c_efuse *map; 28 int i; 29 30 map = (struct rtw8821c_efuse *)log_map; 31 32 efuse->rfe_option = map->rfe_option; 33 efuse->rf_board_option = map->rf_board_option; 34 efuse->crystal_cap = map->xtal_k; 35 efuse->pa_type_2g = map->pa_type; 36 efuse->pa_type_5g = map->pa_type; 37 efuse->lna_type_2g = map->lna_type_2g[0]; 38 efuse->lna_type_5g = map->lna_type_5g[0]; 39 efuse->channel_plan = map->channel_plan; 40 efuse->country_code[0] = map->country_code[0]; 41 efuse->country_code[1] = map->country_code[1]; 42 efuse->bt_setting = map->rf_bt_setting; 43 efuse->regd = map->rf_board_option & 0x7; 44 efuse->thermal_meter[0] = map->thermal_meter; 45 efuse->thermal_meter_k = map->thermal_meter; 46 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 47 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 48 49 for (i = 0; i < 4; i++) 50 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 51 52 switch (rtw_hci_type(rtwdev)) { 53 case RTW_HCI_TYPE_PCIE: 54 rtw8821ce_efuse_parsing(efuse, map); 55 break; 56 default: 57 /* unsupported now */ 58 return -ENOTSUPP; 59 } 60 61 return 0; 62 } 63 64 static const u32 rtw8821c_txscale_tbl[] = { 65 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 66 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 67 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 68 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 69 }; 70 71 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 72 { 73 u8 i = 0; 74 u32 swing, table_value; 75 76 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 77 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 78 table_value = rtw8821c_txscale_tbl[i]; 79 if (swing == table_value) 80 break; 81 } 82 83 return i; 84 } 85 86 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 87 { 88 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 89 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 90 91 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 92 dm_info->default_ofdm_index = 24; 93 else 94 dm_info->default_ofdm_index = swing_idx; 95 96 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 97 dm_info->delta_power_index[RF_PATH_A] = 0; 98 dm_info->delta_power_index_last[RF_PATH_A] = 0; 99 dm_info->pwr_trk_triggered = false; 100 dm_info->pwr_trk_init_trigger = true; 101 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 102 } 103 104 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 105 { 106 rtw_bf_phy_init(rtwdev); 107 /* Grouping bitmap parameters */ 108 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 109 } 110 111 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 112 { 113 u8 crystal_cap, val; 114 115 /* power on BB/RF domain */ 116 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 117 val |= BIT_FEN_PCIEA; 118 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 119 120 /* toggle BB reset */ 121 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 122 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 123 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 124 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 125 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 126 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 127 128 rtw_write8(rtwdev, REG_RF_CTRL, 129 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 130 usleep_range(10, 11); 131 rtw_write8(rtwdev, REG_WLRF1 + 3, 132 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 133 usleep_range(10, 11); 134 135 /* pre init before header files config */ 136 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 137 138 rtw_phy_load_tables(rtwdev); 139 140 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 141 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 142 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 143 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 144 145 /* post init after header files config */ 146 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 147 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 148 rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 149 rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 150 151 rtw_phy_init(rtwdev); 152 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 153 154 rtw8821c_pwrtrack_init(rtwdev); 155 156 rtw8821c_phy_bf_init(rtwdev); 157 } 158 159 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 160 { 161 u32 value32; 162 u16 pre_txcnt; 163 164 /* protocol configuration */ 165 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 166 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 167 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 168 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 169 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 170 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 171 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 172 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 173 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 174 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 175 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 176 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 177 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 178 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 179 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 180 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 181 182 /* EDCA configuration */ 183 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 184 rtw_write16(rtwdev, REG_TXPAUSE, 0); 185 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 186 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 187 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 188 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 189 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 190 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 191 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 192 193 /* Set beacon cotnrol - enable TSF and other related functions */ 194 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 195 196 /* Set send beacon related registers */ 197 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 198 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 199 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 200 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 201 202 /* WMAC configuration */ 203 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 204 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 205 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 206 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 207 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 208 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 209 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 210 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 211 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6)); 212 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 213 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 214 215 return 0; 216 } 217 218 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 219 { 220 u8 ldo_pwr; 221 222 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 223 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 224 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 225 } 226 227 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 228 { 229 u32 rf_reg18; 230 231 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 232 233 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 234 RF18_BW_MASK); 235 236 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 237 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 238 239 if (channel >= 100 && channel <= 140) 240 rf_reg18 |= RF18_RFSI_GE; 241 else if (channel > 140) 242 rf_reg18 |= RF18_RFSI_GT; 243 244 switch (bw) { 245 case RTW_CHANNEL_WIDTH_5: 246 case RTW_CHANNEL_WIDTH_10: 247 case RTW_CHANNEL_WIDTH_20: 248 default: 249 rf_reg18 |= RF18_BW_20M; 250 break; 251 case RTW_CHANNEL_WIDTH_40: 252 rf_reg18 |= RF18_BW_40M; 253 break; 254 case RTW_CHANNEL_WIDTH_80: 255 rf_reg18 |= RF18_BW_80M; 256 break; 257 } 258 259 if (channel <= 14) { 260 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 261 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 262 } else { 263 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 264 } 265 266 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 267 268 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 269 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 270 } 271 272 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 273 { 274 if (bw == RTW_CHANNEL_WIDTH_40) { 275 /* RX DFIR for BW40 */ 276 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 277 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 278 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 279 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 280 } else if (bw == RTW_CHANNEL_WIDTH_80) { 281 /* RX DFIR for BW80 */ 282 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 283 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 284 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 285 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 286 } else { 287 /* RX DFIR for BW20, BW10 and BW5 */ 288 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 289 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 290 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 291 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 292 } 293 } 294 295 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 296 u8 primary_ch_idx) 297 { 298 u32 val32; 299 300 if (channel <= 14) { 301 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 302 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 303 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 304 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 305 306 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 307 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 308 if (channel == 14) { 309 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 310 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 311 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 312 } else { 313 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 314 rtwdev->chip->ch_param[0]); 315 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 316 rtwdev->chip->ch_param[1] & MASKLWORD); 317 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 318 rtwdev->chip->ch_param[2]); 319 } 320 } else if (channel > 35) { 321 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 322 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 323 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 324 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 325 326 if (channel >= 36 && channel <= 64) 327 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 328 else if (channel >= 100 && channel <= 144) 329 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 330 else if (channel >= 149) 331 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 332 333 if (channel >= 36 && channel <= 48) 334 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 335 else if (channel >= 52 && channel <= 64) 336 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 337 else if (channel >= 100 && channel <= 116) 338 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 339 else if (channel >= 118 && channel <= 177) 340 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 341 } 342 343 switch (bw) { 344 case RTW_CHANNEL_WIDTH_20: 345 default: 346 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 347 val32 &= 0xffcffc00; 348 val32 |= 0x10010000; 349 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 350 351 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 352 break; 353 case RTW_CHANNEL_WIDTH_40: 354 if (primary_ch_idx == 1) 355 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 356 else 357 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 358 359 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 360 val32 &= 0xff3ff300; 361 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 362 RTW_CHANNEL_WIDTH_40; 363 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 364 365 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 366 break; 367 case RTW_CHANNEL_WIDTH_80: 368 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 369 val32 &= 0xfcffcf00; 370 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 371 RTW_CHANNEL_WIDTH_80; 372 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 373 374 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 375 break; 376 case RTW_CHANNEL_WIDTH_5: 377 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 378 val32 &= 0xefcefc00; 379 val32 |= 0x200240; 380 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 381 382 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 383 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 384 break; 385 case RTW_CHANNEL_WIDTH_10: 386 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 387 val32 &= 0xefcefc00; 388 val32 |= 0x300380; 389 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 390 391 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 392 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 393 break; 394 } 395 } 396 397 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 398 { 399 struct rtw_efuse efuse = rtwdev->efuse; 400 u8 tx_bb_swing; 401 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 402 403 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 404 efuse.tx_bb_swing_setting_5g; 405 if (tx_bb_swing > 9) 406 tx_bb_swing = 0; 407 408 return swing2setting[(tx_bb_swing / 3)]; 409 } 410 411 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 412 u8 bw, u8 primary_ch_idx) 413 { 414 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 415 rtw8821c_get_bb_swing(rtwdev, channel)); 416 rtw8821c_pwrtrack_init(rtwdev); 417 } 418 419 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 420 u8 primary_chan_idx) 421 { 422 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 423 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 424 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 425 rtw8821c_set_channel_rf(rtwdev, channel, bw); 426 rtw8821c_set_channel_rxdfir(rtwdev, bw); 427 } 428 429 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 430 struct rtw_rx_pkt_stat *pkt_stat) 431 { 432 s8 min_rx_power = -120; 433 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 434 435 pkt_stat->rx_power[RF_PATH_A] = pwdb - 100; 436 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 437 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 438 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 439 min_rx_power); 440 } 441 442 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 443 struct rtw_rx_pkt_stat *pkt_stat) 444 { 445 u8 rxsc, bw; 446 s8 min_rx_power = -120; 447 448 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 449 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 450 else 451 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 452 453 if (rxsc >= 1 && rxsc <= 8) 454 bw = RTW_CHANNEL_WIDTH_20; 455 else if (rxsc >= 9 && rxsc <= 12) 456 bw = RTW_CHANNEL_WIDTH_40; 457 else if (rxsc >= 13) 458 bw = RTW_CHANNEL_WIDTH_80; 459 else 460 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 461 462 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 463 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 464 pkt_stat->bw = bw; 465 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 466 min_rx_power); 467 } 468 469 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 470 struct rtw_rx_pkt_stat *pkt_stat) 471 { 472 u8 page; 473 474 page = *phy_status & 0xf; 475 476 switch (page) { 477 case 0: 478 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 479 break; 480 case 1: 481 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 482 break; 483 default: 484 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 485 return; 486 } 487 } 488 489 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 490 struct rtw_rx_pkt_stat *pkt_stat, 491 struct ieee80211_rx_status *rx_status) 492 { 493 struct ieee80211_hdr *hdr; 494 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 495 u8 *phy_status = NULL; 496 497 memset(pkt_stat, 0, sizeof(*pkt_stat)); 498 499 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 500 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 501 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 502 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc); 503 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 504 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 505 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 506 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 507 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 508 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 509 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 510 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 511 512 /* drv_info_sz is in unit of 8-bytes */ 513 pkt_stat->drv_info_sz *= 8; 514 515 /* c2h cmd pkt's rx/phy status is not interested */ 516 if (pkt_stat->is_c2h) 517 return; 518 519 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 520 pkt_stat->drv_info_sz); 521 if (pkt_stat->phy_status) { 522 phy_status = rx_desc + desc_sz + pkt_stat->shift; 523 query_phy_status(rtwdev, phy_status, pkt_stat); 524 } 525 526 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 527 } 528 529 static void 530 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 531 { 532 struct rtw_hal *hal = &rtwdev->hal; 533 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 534 static u32 phy_pwr_idx; 535 u8 rate, rate_idx, pwr_index, shift; 536 int j; 537 538 for (j = 0; j < rtw_rate_size[rs]; j++) { 539 rate = rtw_rate_section[rs][j]; 540 pwr_index = hal->tx_pwr_tbl[path][rate]; 541 shift = rate & 0x3; 542 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 543 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 544 rate_idx = rate & 0xfc; 545 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 546 phy_pwr_idx); 547 phy_pwr_idx = 0; 548 } 549 } 550 } 551 552 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 553 { 554 struct rtw_hal *hal = &rtwdev->hal; 555 int rs, path; 556 557 for (path = 0; path < hal->rf_path_num; path++) { 558 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 559 if (rs == RTW_RATE_SECTION_HT_2S || 560 rs == RTW_RATE_SECTION_VHT_2S) 561 continue; 562 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 563 } 564 } 565 } 566 567 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 568 { 569 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 570 u32 cck_enable; 571 u32 cck_fa_cnt; 572 u32 ofdm_fa_cnt; 573 u32 crc32_cnt; 574 u32 cca32_cnt; 575 576 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 577 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 578 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 579 580 dm_info->cck_fa_cnt = cck_fa_cnt; 581 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 582 if (cck_enable) 583 dm_info->total_fa_cnt += cck_fa_cnt; 584 dm_info->total_fa_cnt = ofdm_fa_cnt; 585 586 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 587 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 588 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 589 590 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 591 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 592 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 593 594 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 595 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 596 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 597 598 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 599 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 600 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 601 602 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 603 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 604 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 605 if (cck_enable) { 606 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 607 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 608 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 609 } 610 611 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 612 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 613 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 614 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 615 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 616 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 617 } 618 619 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 620 { 621 static int do_iqk_cnt; 622 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 623 u32 rf_reg, iqk_fail_mask; 624 int counter; 625 bool reload; 626 627 if (rtw_is_assoc(rtwdev)) 628 para.segment_iqk = 1; 629 630 rtw_fw_do_iqk(rtwdev, ¶); 631 632 for (counter = 0; counter < 300; counter++) { 633 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 634 if (rf_reg == 0xabcde) 635 break; 636 msleep(20); 637 } 638 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 639 640 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 641 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 642 rtw_dbg(rtwdev, RTW_DBG_PHY, 643 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 644 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 645 } 646 647 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 648 { 649 rtw8821c_do_iqk(rtwdev); 650 } 651 652 /* for coex */ 653 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 654 { 655 /* enable TBTT nterrupt */ 656 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 657 658 /* BT report packet sample rate */ 659 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 660 661 /* enable BT counter statistics */ 662 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 663 664 /* enable PTA (3-wire function form BT side) */ 665 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 666 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 667 668 /* enable PTA (tx/rx signal form WiFi side) */ 669 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 670 /* wl tx signal to PTA not case EDCCA */ 671 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 672 /* GNT_BT=1 while select both */ 673 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 674 675 /* beacon queue always hi-pri */ 676 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 677 BCN_PRI_EN); 678 } 679 680 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 681 u8 pos_type) 682 { 683 struct rtw_coex *coex = &rtwdev->coex; 684 struct rtw_coex_dm *coex_dm = &coex->dm; 685 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 686 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 687 bool polarity_inverse; 688 u8 regval = 0; 689 690 if (switch_status == coex_dm->cur_switch_status) 691 return; 692 693 coex_dm->cur_switch_status = switch_status; 694 695 if (coex_rfe->ant_switch_diversity && 696 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 697 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 698 699 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 700 701 switch (ctrl_type) { 702 default: 703 case COEX_SWITCH_CTRL_BY_BBSW: 704 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 705 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 706 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 707 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 708 DPDT_CTRL_PIN); 709 710 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 711 if (coex_rfe->rfe_module_type != 0x4 && 712 coex_rfe->rfe_module_type != 0x2) 713 regval = 0x3; 714 else 715 regval = (!polarity_inverse ? 0x2 : 0x1); 716 } else if (pos_type == COEX_SWITCH_TO_WLG) { 717 regval = (!polarity_inverse ? 0x2 : 0x1); 718 } else { 719 regval = (!polarity_inverse ? 0x1 : 0x2); 720 } 721 722 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 723 regval); 724 break; 725 case COEX_SWITCH_CTRL_BY_PTA: 726 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 727 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 728 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 729 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 730 PTA_CTRL_PIN); 731 732 regval = (!polarity_inverse ? 0x2 : 0x1); 733 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 734 regval); 735 break; 736 case COEX_SWITCH_CTRL_BY_ANTDIV: 737 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 738 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 739 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 740 ANTDIC_CTRL_PIN); 741 break; 742 case COEX_SWITCH_CTRL_BY_MAC: 743 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 744 745 regval = (!polarity_inverse ? 0x0 : 0x1); 746 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 747 regval); 748 break; 749 case COEX_SWITCH_CTRL_BY_FW: 750 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 751 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 752 break; 753 case COEX_SWITCH_CTRL_BY_BT: 754 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 755 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 756 break; 757 } 758 759 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 760 rtw_write32_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 761 rtw_write32_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 762 } else { 763 rtw_write32_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 764 rtw_write32_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 765 } 766 } 767 768 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 769 {} 770 771 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 772 { 773 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 774 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 775 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 776 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 777 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 778 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 779 } 780 781 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 782 { 783 struct rtw_coex *coex = &rtwdev->coex; 784 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 785 struct rtw_efuse *efuse = &rtwdev->efuse; 786 787 coex_rfe->rfe_module_type = efuse->rfe_option; 788 coex_rfe->ant_switch_polarity = 0; 789 coex_rfe->ant_switch_exist = true; 790 coex_rfe->wlg_at_btg = false; 791 792 switch (coex_rfe->rfe_module_type) { 793 case 0: 794 case 8: 795 case 1: 796 case 9: /* 1-Ant, Main, WLG */ 797 default: /* 2-Ant, DPDT, WLG */ 798 break; 799 case 2: 800 case 10: /* 1-Ant, Main, BTG */ 801 case 7: 802 case 15: /* 2-Ant, DPDT, BTG */ 803 coex_rfe->wlg_at_btg = true; 804 break; 805 case 3: 806 case 11: /* 1-Ant, Aux, WLG */ 807 coex_rfe->ant_switch_polarity = 1; 808 break; 809 case 4: 810 case 12: /* 1-Ant, Aux, BTG */ 811 coex_rfe->wlg_at_btg = true; 812 coex_rfe->ant_switch_polarity = 1; 813 break; 814 case 5: 815 case 13: /* 2-Ant, no switch, WLG */ 816 case 6: 817 case 14: /* 2-Ant, no antenna switch, WLG */ 818 coex_rfe->ant_switch_exist = false; 819 break; 820 } 821 } 822 823 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 824 { 825 struct rtw_coex *coex = &rtwdev->coex; 826 struct rtw_coex_dm *coex_dm = &coex->dm; 827 struct rtw_efuse *efuse = &rtwdev->efuse; 828 bool share_ant = efuse->share_ant; 829 830 if (share_ant) 831 return; 832 833 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 834 return; 835 836 coex_dm->cur_wl_pwr_lvl = wl_pwr; 837 } 838 839 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 840 {} 841 842 static void 843 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 844 s8 pwr_idx_offset_lower, 845 s8 *txagc_idx, u8 *swing_idx) 846 { 847 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 848 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 849 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 850 u8 swing_lower_bound = 0; 851 u8 max_pwr_idx_offset = 0xf; 852 s8 agc_index = 0; 853 u8 swing_index = dm_info->default_ofdm_index; 854 855 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 856 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 857 858 if (delta_pwr_idx >= 0) { 859 if (delta_pwr_idx <= pwr_idx_offset) { 860 agc_index = delta_pwr_idx; 861 swing_index = dm_info->default_ofdm_index; 862 } else if (delta_pwr_idx > pwr_idx_offset) { 863 agc_index = pwr_idx_offset; 864 swing_index = dm_info->default_ofdm_index + 865 delta_pwr_idx - pwr_idx_offset; 866 swing_index = min_t(u8, swing_index, swing_upper_bound); 867 } 868 } else if (delta_pwr_idx < 0) { 869 if (delta_pwr_idx >= pwr_idx_offset_lower) { 870 agc_index = delta_pwr_idx; 871 swing_index = dm_info->default_ofdm_index; 872 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 873 if (dm_info->default_ofdm_index > 874 (pwr_idx_offset_lower - delta_pwr_idx)) 875 swing_index = dm_info->default_ofdm_index + 876 delta_pwr_idx - pwr_idx_offset_lower; 877 else 878 swing_index = swing_lower_bound; 879 880 agc_index = pwr_idx_offset_lower; 881 } 882 } 883 884 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 885 rtw_warn(rtwdev, "swing index overflow\n"); 886 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 887 } 888 889 *txagc_idx = agc_index; 890 *swing_idx = swing_index; 891 } 892 893 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 894 s8 pwr_idx_offset_lower) 895 { 896 s8 txagc_idx; 897 u8 swing_idx; 898 899 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 900 &txagc_idx, &swing_idx); 901 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 902 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 903 rtw8821c_txscale_tbl[swing_idx]); 904 } 905 906 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 907 { 908 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 909 u8 pwr_idx_offset, tx_pwr_idx; 910 s8 pwr_idx_offset_lower; 911 u8 channel = rtwdev->hal.current_channel; 912 u8 band_width = rtwdev->hal.current_band_width; 913 u8 regd = rtwdev->regd.txpwr_regd; 914 u8 tx_rate = dm_info->tx_rate; 915 u8 max_pwr_idx = rtwdev->chip->max_power_index; 916 917 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 918 band_width, channel, regd); 919 920 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 921 922 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 923 pwr_idx_offset_lower = 0 - tx_pwr_idx; 924 925 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 926 } 927 928 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 929 { 930 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 931 struct rtw_swing_table swing_table; 932 u8 thermal_value, delta; 933 934 rtw_phy_config_swing_table(rtwdev, &swing_table); 935 936 if (rtwdev->efuse.thermal_meter[0] == 0xff) 937 return; 938 939 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 940 941 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 942 943 if (dm_info->pwr_trk_init_trigger) 944 dm_info->pwr_trk_init_trigger = false; 945 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 946 RF_PATH_A)) 947 goto iqk; 948 949 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 950 951 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 952 953 dm_info->delta_power_index[RF_PATH_A] = 954 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 955 RF_PATH_A, delta); 956 if (dm_info->delta_power_index[RF_PATH_A] == 957 dm_info->delta_power_index_last[RF_PATH_A]) 958 goto iqk; 959 else 960 dm_info->delta_power_index_last[RF_PATH_A] = 961 dm_info->delta_power_index[RF_PATH_A]; 962 rtw8821c_pwrtrack_set(rtwdev); 963 964 iqk: 965 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 966 rtw8821c_do_iqk(rtwdev); 967 } 968 969 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 970 { 971 struct rtw_efuse *efuse = &rtwdev->efuse; 972 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 973 974 if (efuse->power_track_type != 0) 975 return; 976 977 if (!dm_info->pwr_trk_triggered) { 978 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 979 GENMASK(17, 16), 0x03); 980 dm_info->pwr_trk_triggered = true; 981 return; 982 } 983 984 rtw8821c_phy_pwrtrack(rtwdev); 985 dm_info->pwr_trk_triggered = false; 986 } 987 988 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 989 struct rtw_vif *vif, 990 struct rtw_bfee *bfee, bool enable) 991 { 992 if (enable) 993 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 994 else 995 rtw_bf_remove_bfee_su(rtwdev, bfee); 996 } 997 998 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 999 struct rtw_vif *vif, 1000 struct rtw_bfee *bfee, bool enable) 1001 { 1002 if (enable) 1003 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1004 else 1005 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1006 } 1007 1008 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1009 struct rtw_bfee *bfee, bool enable) 1010 { 1011 if (bfee->role == RTW_BFEE_SU) 1012 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1013 else if (bfee->role == RTW_BFEE_MU) 1014 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1015 else 1016 rtw_warn(rtwdev, "wrong bfee role\n"); 1017 } 1018 1019 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1020 { 1021 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1022 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1023 u8 cck_n_rx; 1024 1025 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1026 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1027 1028 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1029 return; 1030 1031 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1032 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1033 rtw_dbg(rtwdev, RTW_DBG_PHY, 1034 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1035 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1036 dm_info->cck_pd_default + new_lvl * 2, 1037 pd[new_lvl], dm_info->cck_fa_avg); 1038 1039 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1040 1041 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1042 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1043 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1044 dm_info->cck_pd_default + new_lvl * 2); 1045 } 1046 1047 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1048 {0x0086, 1049 RTW_PWR_CUT_ALL_MSK, 1050 RTW_PWR_INTF_SDIO_MSK, 1051 RTW_PWR_ADDR_SDIO, 1052 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1053 {0x0086, 1054 RTW_PWR_CUT_ALL_MSK, 1055 RTW_PWR_INTF_SDIO_MSK, 1056 RTW_PWR_ADDR_SDIO, 1057 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1058 {0x004A, 1059 RTW_PWR_CUT_ALL_MSK, 1060 RTW_PWR_INTF_USB_MSK, 1061 RTW_PWR_ADDR_MAC, 1062 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1063 {0x0005, 1064 RTW_PWR_CUT_ALL_MSK, 1065 RTW_PWR_INTF_ALL_MSK, 1066 RTW_PWR_ADDR_MAC, 1067 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1068 {0x0300, 1069 RTW_PWR_CUT_ALL_MSK, 1070 RTW_PWR_INTF_PCI_MSK, 1071 RTW_PWR_ADDR_MAC, 1072 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1073 {0x0301, 1074 RTW_PWR_CUT_ALL_MSK, 1075 RTW_PWR_INTF_PCI_MSK, 1076 RTW_PWR_ADDR_MAC, 1077 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1078 {0xFFFF, 1079 RTW_PWR_CUT_ALL_MSK, 1080 RTW_PWR_INTF_ALL_MSK, 1081 0, 1082 RTW_PWR_CMD_END, 0, 0}, 1083 }; 1084 1085 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1086 {0x0020, 1087 RTW_PWR_CUT_ALL_MSK, 1088 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1089 RTW_PWR_ADDR_MAC, 1090 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1091 {0x0001, 1092 RTW_PWR_CUT_ALL_MSK, 1093 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1094 RTW_PWR_ADDR_MAC, 1095 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1096 {0x0000, 1097 RTW_PWR_CUT_ALL_MSK, 1098 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1099 RTW_PWR_ADDR_MAC, 1100 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1101 {0x0005, 1102 RTW_PWR_CUT_ALL_MSK, 1103 RTW_PWR_INTF_ALL_MSK, 1104 RTW_PWR_ADDR_MAC, 1105 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1106 {0x0075, 1107 RTW_PWR_CUT_ALL_MSK, 1108 RTW_PWR_INTF_PCI_MSK, 1109 RTW_PWR_ADDR_MAC, 1110 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1111 {0x0006, 1112 RTW_PWR_CUT_ALL_MSK, 1113 RTW_PWR_INTF_ALL_MSK, 1114 RTW_PWR_ADDR_MAC, 1115 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1116 {0x0075, 1117 RTW_PWR_CUT_ALL_MSK, 1118 RTW_PWR_INTF_PCI_MSK, 1119 RTW_PWR_ADDR_MAC, 1120 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1121 {0x0006, 1122 RTW_PWR_CUT_ALL_MSK, 1123 RTW_PWR_INTF_ALL_MSK, 1124 RTW_PWR_ADDR_MAC, 1125 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1126 {0x0005, 1127 RTW_PWR_CUT_ALL_MSK, 1128 RTW_PWR_INTF_ALL_MSK, 1129 RTW_PWR_ADDR_MAC, 1130 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1131 {0x0005, 1132 RTW_PWR_CUT_ALL_MSK, 1133 RTW_PWR_INTF_ALL_MSK, 1134 RTW_PWR_ADDR_MAC, 1135 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1136 {0x10C3, 1137 RTW_PWR_CUT_ALL_MSK, 1138 RTW_PWR_INTF_USB_MSK, 1139 RTW_PWR_ADDR_MAC, 1140 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1141 {0x0005, 1142 RTW_PWR_CUT_ALL_MSK, 1143 RTW_PWR_INTF_ALL_MSK, 1144 RTW_PWR_ADDR_MAC, 1145 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1146 {0x0005, 1147 RTW_PWR_CUT_ALL_MSK, 1148 RTW_PWR_INTF_ALL_MSK, 1149 RTW_PWR_ADDR_MAC, 1150 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1151 {0x0020, 1152 RTW_PWR_CUT_ALL_MSK, 1153 RTW_PWR_INTF_ALL_MSK, 1154 RTW_PWR_ADDR_MAC, 1155 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1156 {0x0074, 1157 RTW_PWR_CUT_ALL_MSK, 1158 RTW_PWR_INTF_PCI_MSK, 1159 RTW_PWR_ADDR_MAC, 1160 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1161 {0x0022, 1162 RTW_PWR_CUT_ALL_MSK, 1163 RTW_PWR_INTF_PCI_MSK, 1164 RTW_PWR_ADDR_MAC, 1165 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1166 {0x0062, 1167 RTW_PWR_CUT_ALL_MSK, 1168 RTW_PWR_INTF_PCI_MSK, 1169 RTW_PWR_ADDR_MAC, 1170 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1171 (BIT(7) | BIT(6) | BIT(5))}, 1172 {0x0061, 1173 RTW_PWR_CUT_ALL_MSK, 1174 RTW_PWR_INTF_PCI_MSK, 1175 RTW_PWR_ADDR_MAC, 1176 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1177 {0x007C, 1178 RTW_PWR_CUT_ALL_MSK, 1179 RTW_PWR_INTF_ALL_MSK, 1180 RTW_PWR_ADDR_MAC, 1181 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1182 {0xFFFF, 1183 RTW_PWR_CUT_ALL_MSK, 1184 RTW_PWR_INTF_ALL_MSK, 1185 0, 1186 RTW_PWR_CMD_END, 0, 0}, 1187 }; 1188 1189 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1190 {0x0093, 1191 RTW_PWR_CUT_ALL_MSK, 1192 RTW_PWR_INTF_ALL_MSK, 1193 RTW_PWR_ADDR_MAC, 1194 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1195 {0x001F, 1196 RTW_PWR_CUT_ALL_MSK, 1197 RTW_PWR_INTF_ALL_MSK, 1198 RTW_PWR_ADDR_MAC, 1199 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1200 {0x0049, 1201 RTW_PWR_CUT_ALL_MSK, 1202 RTW_PWR_INTF_ALL_MSK, 1203 RTW_PWR_ADDR_MAC, 1204 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1205 {0x0006, 1206 RTW_PWR_CUT_ALL_MSK, 1207 RTW_PWR_INTF_ALL_MSK, 1208 RTW_PWR_ADDR_MAC, 1209 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1210 {0x0002, 1211 RTW_PWR_CUT_ALL_MSK, 1212 RTW_PWR_INTF_ALL_MSK, 1213 RTW_PWR_ADDR_MAC, 1214 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1215 {0x10C3, 1216 RTW_PWR_CUT_ALL_MSK, 1217 RTW_PWR_INTF_USB_MSK, 1218 RTW_PWR_ADDR_MAC, 1219 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1220 {0x0005, 1221 RTW_PWR_CUT_ALL_MSK, 1222 RTW_PWR_INTF_ALL_MSK, 1223 RTW_PWR_ADDR_MAC, 1224 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1225 {0x0005, 1226 RTW_PWR_CUT_ALL_MSK, 1227 RTW_PWR_INTF_ALL_MSK, 1228 RTW_PWR_ADDR_MAC, 1229 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1230 {0x0020, 1231 RTW_PWR_CUT_ALL_MSK, 1232 RTW_PWR_INTF_ALL_MSK, 1233 RTW_PWR_ADDR_MAC, 1234 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1235 {0x0000, 1236 RTW_PWR_CUT_ALL_MSK, 1237 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1238 RTW_PWR_ADDR_MAC, 1239 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1240 {0xFFFF, 1241 RTW_PWR_CUT_ALL_MSK, 1242 RTW_PWR_INTF_ALL_MSK, 1243 0, 1244 RTW_PWR_CMD_END, 0, 0}, 1245 }; 1246 1247 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1248 {0x0007, 1249 RTW_PWR_CUT_ALL_MSK, 1250 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1251 RTW_PWR_ADDR_MAC, 1252 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1253 {0x0067, 1254 RTW_PWR_CUT_ALL_MSK, 1255 RTW_PWR_INTF_ALL_MSK, 1256 RTW_PWR_ADDR_MAC, 1257 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1258 {0x0005, 1259 RTW_PWR_CUT_ALL_MSK, 1260 RTW_PWR_INTF_PCI_MSK, 1261 RTW_PWR_ADDR_MAC, 1262 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1263 {0x004A, 1264 RTW_PWR_CUT_ALL_MSK, 1265 RTW_PWR_INTF_USB_MSK, 1266 RTW_PWR_ADDR_MAC, 1267 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1268 {0x0067, 1269 RTW_PWR_CUT_ALL_MSK, 1270 RTW_PWR_INTF_SDIO_MSK, 1271 RTW_PWR_ADDR_MAC, 1272 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1273 {0x0067, 1274 RTW_PWR_CUT_ALL_MSK, 1275 RTW_PWR_INTF_SDIO_MSK, 1276 RTW_PWR_ADDR_MAC, 1277 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1278 {0x004F, 1279 RTW_PWR_CUT_ALL_MSK, 1280 RTW_PWR_INTF_SDIO_MSK, 1281 RTW_PWR_ADDR_MAC, 1282 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1283 {0x0067, 1284 RTW_PWR_CUT_ALL_MSK, 1285 RTW_PWR_INTF_SDIO_MSK, 1286 RTW_PWR_ADDR_MAC, 1287 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1288 {0x0046, 1289 RTW_PWR_CUT_ALL_MSK, 1290 RTW_PWR_INTF_SDIO_MSK, 1291 RTW_PWR_ADDR_MAC, 1292 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1293 {0x0067, 1294 RTW_PWR_CUT_ALL_MSK, 1295 RTW_PWR_INTF_SDIO_MSK, 1296 RTW_PWR_ADDR_MAC, 1297 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1298 {0x0046, 1299 RTW_PWR_CUT_ALL_MSK, 1300 RTW_PWR_INTF_SDIO_MSK, 1301 RTW_PWR_ADDR_MAC, 1302 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1303 {0x0062, 1304 RTW_PWR_CUT_ALL_MSK, 1305 RTW_PWR_INTF_SDIO_MSK, 1306 RTW_PWR_ADDR_MAC, 1307 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1308 {0x0081, 1309 RTW_PWR_CUT_ALL_MSK, 1310 RTW_PWR_INTF_ALL_MSK, 1311 RTW_PWR_ADDR_MAC, 1312 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1313 {0x0005, 1314 RTW_PWR_CUT_ALL_MSK, 1315 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1316 RTW_PWR_ADDR_MAC, 1317 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1318 {0x0086, 1319 RTW_PWR_CUT_ALL_MSK, 1320 RTW_PWR_INTF_SDIO_MSK, 1321 RTW_PWR_ADDR_SDIO, 1322 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1323 {0x0086, 1324 RTW_PWR_CUT_ALL_MSK, 1325 RTW_PWR_INTF_SDIO_MSK, 1326 RTW_PWR_ADDR_SDIO, 1327 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1328 {0x0090, 1329 RTW_PWR_CUT_ALL_MSK, 1330 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1331 RTW_PWR_ADDR_MAC, 1332 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1333 {0x0044, 1334 RTW_PWR_CUT_ALL_MSK, 1335 RTW_PWR_INTF_SDIO_MSK, 1336 RTW_PWR_ADDR_SDIO, 1337 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1338 {0x0040, 1339 RTW_PWR_CUT_ALL_MSK, 1340 RTW_PWR_INTF_SDIO_MSK, 1341 RTW_PWR_ADDR_SDIO, 1342 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1343 {0x0041, 1344 RTW_PWR_CUT_ALL_MSK, 1345 RTW_PWR_INTF_SDIO_MSK, 1346 RTW_PWR_ADDR_SDIO, 1347 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1348 {0x0042, 1349 RTW_PWR_CUT_ALL_MSK, 1350 RTW_PWR_INTF_SDIO_MSK, 1351 RTW_PWR_ADDR_SDIO, 1352 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1353 {0xFFFF, 1354 RTW_PWR_CUT_ALL_MSK, 1355 RTW_PWR_INTF_ALL_MSK, 1356 0, 1357 RTW_PWR_CMD_END, 0, 0}, 1358 }; 1359 1360 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1361 trans_carddis_to_cardemu_8821c, 1362 trans_cardemu_to_act_8821c, 1363 NULL 1364 }; 1365 1366 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1367 trans_act_to_cardemu_8821c, 1368 trans_cardemu_to_carddis_8821c, 1369 NULL 1370 }; 1371 1372 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1373 {0xFFFF, 0x00, 1374 RTW_IP_SEL_PHY, 1375 RTW_INTF_PHY_CUT_ALL, 1376 RTW_INTF_PHY_PLATFORM_ALL}, 1377 }; 1378 1379 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1380 {0xFFFF, 0x0000, 1381 RTW_IP_SEL_PHY, 1382 RTW_INTF_PHY_CUT_ALL, 1383 RTW_INTF_PHY_PLATFORM_ALL}, 1384 }; 1385 1386 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1387 {0x0009, 0x6380, 1388 RTW_IP_SEL_PHY, 1389 RTW_INTF_PHY_CUT_ALL, 1390 RTW_INTF_PHY_PLATFORM_ALL}, 1391 {0xFFFF, 0x0000, 1392 RTW_IP_SEL_PHY, 1393 RTW_INTF_PHY_CUT_ALL, 1394 RTW_INTF_PHY_PLATFORM_ALL}, 1395 }; 1396 1397 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1398 {0xFFFF, 0x0000, 1399 RTW_IP_SEL_PHY, 1400 RTW_INTF_PHY_CUT_ALL, 1401 RTW_INTF_PHY_PLATFORM_ALL}, 1402 }; 1403 1404 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1405 .usb2_para = usb2_param_8821c, 1406 .usb3_para = usb3_param_8821c, 1407 .gen1_para = pcie_gen1_param_8821c, 1408 .gen2_para = pcie_gen2_param_8821c, 1409 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1410 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1411 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1412 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1413 }; 1414 1415 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1416 [0] = RTW_DEF_RFE(8821c, 0, 0), 1417 }; 1418 1419 static struct rtw_hw_reg rtw8821c_dig[] = { 1420 [0] = { .addr = 0xc50, .mask = 0x7f }, 1421 }; 1422 1423 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1424 .ctrl = LTECOEX_ACCESS_CTRL, 1425 .wdata = LTECOEX_WRITE_DATA, 1426 .rdata = LTECOEX_READ_DATA, 1427 }; 1428 1429 static struct rtw_page_table page_table_8821c[] = { 1430 /* not sure what [0] stands for */ 1431 {16, 16, 16, 14, 1}, 1432 {16, 16, 16, 14, 1}, 1433 {16, 16, 0, 0, 1}, 1434 {16, 16, 16, 0, 1}, 1435 {16, 16, 16, 14, 1}, 1436 }; 1437 1438 static struct rtw_rqpn rqpn_table_8821c[] = { 1439 /* not sure what [0] stands for */ 1440 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1441 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1442 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1443 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1444 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1445 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1446 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1447 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1448 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1449 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1450 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1451 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1452 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1453 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1454 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1455 }; 1456 1457 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1458 .prio[RTW_DMA_MAPPING_EXTRA] = { 1459 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1460 }, 1461 .prio[RTW_DMA_MAPPING_LOW] = { 1462 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1463 }, 1464 .prio[RTW_DMA_MAPPING_NORMAL] = { 1465 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1466 }, 1467 .prio[RTW_DMA_MAPPING_HIGH] = { 1468 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1469 }, 1470 .wsize = true, 1471 }; 1472 1473 static struct rtw_chip_ops rtw8821c_ops = { 1474 .phy_set_param = rtw8821c_phy_set_param, 1475 .read_efuse = rtw8821c_read_efuse, 1476 .query_rx_desc = rtw8821c_query_rx_desc, 1477 .set_channel = rtw8821c_set_channel, 1478 .mac_init = rtw8821c_mac_init, 1479 .read_rf = rtw_phy_read_rf, 1480 .write_rf = rtw_phy_write_rf_reg_sipi, 1481 .set_antenna = NULL, 1482 .set_tx_power_index = rtw8821c_set_tx_power_index, 1483 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1484 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1485 .phy_calibration = rtw8821c_phy_calibration, 1486 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1487 .pwr_track = rtw8821c_pwr_track, 1488 .config_bfee = rtw8821c_bf_config_bfee, 1489 .set_gid_table = rtw_bf_set_gid_table, 1490 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1491 1492 .coex_set_init = rtw8821c_coex_cfg_init, 1493 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1494 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1495 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1496 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1497 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1498 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1499 }; 1500 1501 /* rssi in percentage % (dbm = % - 100) */ 1502 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1503 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1504 1505 /* Shared-Antenna Coex Table */ 1506 static const struct coex_table_para table_sant_8821c[] = { 1507 {0x55555555, 0x55555555}, /* case-0 */ 1508 {0x55555555, 0x55555555}, 1509 {0x66555555, 0x66555555}, 1510 {0xaaaaaaaa, 0xaaaaaaaa}, 1511 {0x5a5a5a5a, 0x5a5a5a5a}, 1512 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1513 {0x6a5a5555, 0xaaaaaaaa}, 1514 {0x6a5a56aa, 0x6a5a56aa}, 1515 {0x6a5a5a5a, 0x6a5a5a5a}, 1516 {0x66555555, 0x5a5a5a5a}, 1517 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1518 {0x66555555, 0xaaaaaaaa}, 1519 {0x66555555, 0x6a5a5aaa}, 1520 {0x66555555, 0x6aaa6aaa}, 1521 {0x66555555, 0x6a5a5aaa}, 1522 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1523 {0xffff55ff, 0xfafafafa}, 1524 {0xffff55ff, 0x6afa5afa}, 1525 {0xaaffffaa, 0xfafafafa}, 1526 {0xaa5555aa, 0x5a5a5a5a}, 1527 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1528 {0xaa5555aa, 0xaaaaaaaa}, 1529 {0xffffffff, 0x55555555}, 1530 {0xffffffff, 0x5a5a5a5a}, 1531 {0xffffffff, 0x5a5a5a5a}, 1532 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1533 {0x55555555, 0x5a5a5a5a}, 1534 {0x55555555, 0xaaaaaaaa}, 1535 {0x66555555, 0x6a5a6a5a}, 1536 {0x66556655, 0x66556655}, 1537 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1538 {0xffffffff, 0x5aaa5aaa}, 1539 {0x56555555, 0x5a5a5aaa} 1540 }; 1541 1542 /* Non-Shared-Antenna Coex Table */ 1543 static const struct coex_table_para table_nsant_8821c[] = { 1544 {0xffffffff, 0xffffffff}, /* case-100 */ 1545 {0xffff55ff, 0xfafafafa}, 1546 {0x66555555, 0x66555555}, 1547 {0xaaaaaaaa, 0xaaaaaaaa}, 1548 {0x5a5a5a5a, 0x5a5a5a5a}, 1549 {0xffffffff, 0xffffffff}, /* case-105 */ 1550 {0x5afa5afa, 0x5afa5afa}, 1551 {0x55555555, 0xfafafafa}, 1552 {0x66555555, 0xfafafafa}, 1553 {0x66555555, 0x5a5a5a5a}, 1554 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1555 {0x66555555, 0xaaaaaaaa}, 1556 {0xffff55ff, 0xfafafafa}, 1557 {0xffff55ff, 0x5afa5afa}, 1558 {0xffff55ff, 0xaaaaaaaa}, 1559 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1560 {0xaaffffaa, 0x5afa5afa}, 1561 {0xaaffffaa, 0xaaaaaaaa}, 1562 {0xffffffff, 0xfafafafa}, 1563 {0xffff55ff, 0xfafafafa}, 1564 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1565 {0xffff55ff, 0x5afa5afa}, 1566 {0xffff55ff, 0x5afa5afa}, 1567 {0x55ff55ff, 0x55ff55ff} 1568 }; 1569 1570 /* Shared-Antenna TDMA */ 1571 static const struct coex_tdma_para tdma_sant_8821c[] = { 1572 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1573 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1574 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1575 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1576 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1577 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1578 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1579 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1580 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1581 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1582 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1583 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1584 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1585 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1586 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1587 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1588 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1589 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1590 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1591 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1592 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1593 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1594 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1595 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1596 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1597 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1598 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1599 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1600 }; 1601 1602 /* Non-Shared-Antenna TDMA */ 1603 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1604 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1605 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1606 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1607 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1608 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1609 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1610 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1611 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1612 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1613 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1614 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1615 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1616 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1617 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1618 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1619 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1620 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1621 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1622 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1623 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1624 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1625 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1626 }; 1627 1628 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1629 1630 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1631 static const struct coex_rf_para rf_para_tx_8821c[] = { 1632 {0, 0, false, 7}, /* for normal */ 1633 {0, 20, false, 7}, /* for WL-CPT */ 1634 {8, 17, true, 4}, 1635 {7, 18, true, 4}, 1636 {6, 19, true, 4}, 1637 {5, 20, true, 4} 1638 }; 1639 1640 static const struct coex_rf_para rf_para_rx_8821c[] = { 1641 {0, 0, false, 7}, /* for normal */ 1642 {0, 20, false, 7}, /* for WL-CPT */ 1643 {3, 24, true, 5}, 1644 {2, 26, true, 5}, 1645 {1, 27, true, 5}, 1646 {0, 28, true, 5} 1647 }; 1648 1649 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1650 1651 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1652 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1653 11, 11, 12, 12, 12, 12, 12}, 1654 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1655 11, 12, 12, 12, 12, 12, 12, 12}, 1656 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1657 11, 12, 12, 12, 12, 12, 12}, 1658 }; 1659 1660 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1661 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1662 12, 12, 12, 12, 12, 12, 12}, 1663 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1664 12, 12, 12, 12, 12, 12, 12, 12}, 1665 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1666 11, 12, 12, 12, 12, 12, 12, 12}, 1667 }; 1668 1669 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1670 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1671 11, 11, 12, 12, 12, 12, 12}, 1672 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1673 11, 12, 12, 12, 12, 12, 12, 12}, 1674 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1675 11, 12, 12, 12, 12, 12, 12}, 1676 }; 1677 1678 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1679 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1680 12, 12, 12, 12, 12, 12, 12}, 1681 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1682 12, 12, 12, 12, 12, 12, 12, 12}, 1683 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1684 11, 12, 12, 12, 12, 12, 12, 12}, 1685 }; 1686 1687 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1688 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1689 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1690 }; 1691 1692 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1693 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1694 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1695 }; 1696 1697 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1698 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1699 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1700 }; 1701 1702 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1703 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1704 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1705 }; 1706 1707 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1708 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1709 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1710 }; 1711 1712 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1713 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1714 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1715 }; 1716 1717 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1718 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1719 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1720 }; 1721 1722 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1723 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1724 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1725 }; 1726 1727 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1728 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1729 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1730 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1731 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1732 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1733 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1734 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1735 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1736 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1737 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1738 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1739 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1740 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1741 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1742 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1743 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1744 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1745 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1746 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1747 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1748 }; 1749 1750 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1751 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1752 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1753 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1754 {0, 0, RTW_REG_DOMAIN_NL}, 1755 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1756 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1757 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1758 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1759 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1760 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1761 {0, 0, RTW_REG_DOMAIN_NL}, 1762 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1763 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1764 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1765 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1766 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1767 {0, 0, RTW_REG_DOMAIN_NL}, 1768 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1769 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1770 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1771 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1772 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1773 }; 1774 1775 struct rtw_chip_info rtw8821c_hw_spec = { 1776 .ops = &rtw8821c_ops, 1777 .id = RTW_CHIP_TYPE_8821C, 1778 .fw_name = "rtw88/rtw8821c_fw.bin", 1779 .wlan_cpu = RTW_WCPU_11AC, 1780 .tx_pkt_desc_sz = 48, 1781 .tx_buf_desc_sz = 16, 1782 .rx_pkt_desc_sz = 24, 1783 .rx_buf_desc_sz = 8, 1784 .phy_efuse_size = 512, 1785 .log_efuse_size = 512, 1786 .ptct_efuse_size = 96, 1787 .txff_size = 65536, 1788 .rxff_size = 16384, 1789 .txgi_factor = 1, 1790 .is_pwr_by_rate_dec = true, 1791 .max_power_index = 0x3f, 1792 .csi_buf_pg_num = 0, 1793 .band = RTW_BAND_2G | RTW_BAND_5G, 1794 .page_size = 128, 1795 .dig_min = 0x1c, 1796 .ht_supported = true, 1797 .vht_supported = true, 1798 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1799 .sys_func_en = 0xD8, 1800 .pwr_on_seq = card_enable_flow_8821c, 1801 .pwr_off_seq = card_disable_flow_8821c, 1802 .page_table = page_table_8821c, 1803 .rqpn_table = rqpn_table_8821c, 1804 .prioq_addrs = &prioq_addrs_8821c, 1805 .intf_table = &phy_para_table_8821c, 1806 .dig = rtw8821c_dig, 1807 .rf_base_addr = {0x2800, 0x2c00}, 1808 .rf_sipi_addr = {0xc90, 0xe90}, 1809 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1810 .mac_tbl = &rtw8821c_mac_tbl, 1811 .agc_tbl = &rtw8821c_agc_tbl, 1812 .bb_tbl = &rtw8821c_bb_tbl, 1813 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1814 .rfe_defs = rtw8821c_rfe_defs, 1815 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1816 .rx_ldpc = false, 1817 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1818 .iqk_threshold = 8, 1819 .bfer_su_max_num = 2, 1820 .bfer_mu_max_num = 1, 1821 1822 .coex_para_ver = 0x19092746, 1823 .bt_desired_ver = 0x46, 1824 .scbd_support = true, 1825 .new_scbd10_def = false, 1826 .ble_hid_profile_support = false, 1827 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1828 .bt_rssi_type = COEX_BTRSSI_RATIO, 1829 .ant_isolation = 15, 1830 .rssi_tolerance = 2, 1831 .wl_rssi_step = wl_rssi_step_8821c, 1832 .bt_rssi_step = bt_rssi_step_8821c, 1833 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 1834 .table_sant = table_sant_8821c, 1835 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 1836 .table_nsant = table_nsant_8821c, 1837 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 1838 .tdma_sant = tdma_sant_8821c, 1839 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 1840 .tdma_nsant = tdma_nsant_8821c, 1841 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 1842 .wl_rf_para_tx = rf_para_tx_8821c, 1843 .wl_rf_para_rx = rf_para_rx_8821c, 1844 .bt_afh_span_bw20 = 0x24, 1845 .bt_afh_span_bw40 = 0x36, 1846 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 1847 .afh_5g = afh_5g_8821c, 1848 1849 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 1850 .coex_info_hw_regs = coex_info_hw_regs_8821c, 1851 }; 1852 EXPORT_SYMBOL(rtw8821c_hw_spec); 1853 1854 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 1855 1856 MODULE_AUTHOR("Realtek Corporation"); 1857 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 1858 MODULE_LICENSE("Dual BSD/GPL"); 1859