1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 18 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 19 struct rtw8821c_efuse *map) 20 { 21 ether_addr_copy(efuse->addr, map->e.mac_addr); 22 } 23 24 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 25 { 26 struct rtw_efuse *efuse = &rtwdev->efuse; 27 struct rtw8821c_efuse *map; 28 int i; 29 30 map = (struct rtw8821c_efuse *)log_map; 31 32 efuse->rfe_option = map->rfe_option; 33 efuse->rf_board_option = map->rf_board_option; 34 efuse->crystal_cap = map->xtal_k; 35 efuse->pa_type_2g = map->pa_type; 36 efuse->pa_type_5g = map->pa_type; 37 efuse->lna_type_2g = map->lna_type_2g[0]; 38 efuse->lna_type_5g = map->lna_type_5g[0]; 39 efuse->channel_plan = map->channel_plan; 40 efuse->country_code[0] = map->country_code[0]; 41 efuse->country_code[1] = map->country_code[1]; 42 efuse->bt_setting = map->rf_bt_setting; 43 efuse->regd = map->rf_board_option & 0x7; 44 efuse->thermal_meter[0] = map->thermal_meter; 45 efuse->thermal_meter_k = map->thermal_meter; 46 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 47 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 48 49 for (i = 0; i < 4; i++) 50 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 51 52 switch (rtw_hci_type(rtwdev)) { 53 case RTW_HCI_TYPE_PCIE: 54 rtw8821ce_efuse_parsing(efuse, map); 55 break; 56 default: 57 /* unsupported now */ 58 return -ENOTSUPP; 59 } 60 61 return 0; 62 } 63 64 static const u32 rtw8821c_txscale_tbl[] = { 65 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 66 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 67 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 68 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 69 }; 70 71 static const u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 72 { 73 u8 i = 0; 74 u32 swing, table_value; 75 76 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 77 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 78 table_value = rtw8821c_txscale_tbl[i]; 79 if (swing == table_value) 80 break; 81 } 82 83 return i; 84 } 85 86 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 87 { 88 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 89 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 90 91 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 92 dm_info->default_ofdm_index = 24; 93 else 94 dm_info->default_ofdm_index = swing_idx; 95 96 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 97 dm_info->delta_power_index[RF_PATH_A] = 0; 98 dm_info->delta_power_index_last[RF_PATH_A] = 0; 99 dm_info->pwr_trk_triggered = false; 100 dm_info->pwr_trk_init_trigger = true; 101 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 102 } 103 104 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 105 { 106 rtw_bf_phy_init(rtwdev); 107 /* Grouping bitmap parameters */ 108 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 109 } 110 111 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 112 { 113 u8 crystal_cap, val; 114 115 /* power on BB/RF domain */ 116 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 117 val |= BIT_FEN_PCIEA; 118 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 119 120 /* toggle BB reset */ 121 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 122 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 123 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 124 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 125 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 126 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 127 128 rtw_write8(rtwdev, REG_RF_CTRL, 129 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 130 usleep_range(10, 11); 131 rtw_write8(rtwdev, REG_WLRF1 + 3, 132 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 133 usleep_range(10, 11); 134 135 /* pre init before header files config */ 136 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 137 138 rtw_phy_load_tables(rtwdev); 139 140 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 141 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 142 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 143 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 144 145 /* post init after header files config */ 146 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 147 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 148 rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 149 rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 150 151 rtw_phy_init(rtwdev); 152 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 153 154 rtw8821c_pwrtrack_init(rtwdev); 155 156 rtw8821c_phy_bf_init(rtwdev); 157 } 158 159 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 160 { 161 u32 value32; 162 u16 pre_txcnt; 163 164 /* protocol configuration */ 165 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 166 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 167 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 168 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 169 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 170 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 171 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 172 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 173 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 174 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 175 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 176 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 177 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 178 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 179 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 180 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 181 182 /* EDCA configuration */ 183 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 184 rtw_write16(rtwdev, REG_TXPAUSE, 0); 185 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 186 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 187 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 188 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 189 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 190 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 191 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 192 193 /* Set beacon cotnrol - enable TSF and other related functions */ 194 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 195 196 /* Set send beacon related registers */ 197 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 198 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 199 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 200 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 201 202 /* WMAC configuration */ 203 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 204 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 205 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 206 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 207 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 208 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 209 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 210 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 211 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6)); 212 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 213 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 214 215 return 0; 216 } 217 218 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 219 { 220 u8 ldo_pwr; 221 222 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 223 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 224 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 225 } 226 227 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 228 { 229 u32 rf_reg18; 230 231 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 232 233 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 234 RF18_BW_MASK); 235 236 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 237 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 238 239 if (channel >= 100 && channel <= 140) 240 rf_reg18 |= RF18_RFSI_GE; 241 else if (channel > 140) 242 rf_reg18 |= RF18_RFSI_GT; 243 244 switch (bw) { 245 case RTW_CHANNEL_WIDTH_5: 246 case RTW_CHANNEL_WIDTH_10: 247 case RTW_CHANNEL_WIDTH_20: 248 default: 249 rf_reg18 |= RF18_BW_20M; 250 break; 251 case RTW_CHANNEL_WIDTH_40: 252 rf_reg18 |= RF18_BW_40M; 253 break; 254 case RTW_CHANNEL_WIDTH_80: 255 rf_reg18 |= RF18_BW_80M; 256 break; 257 } 258 259 if (channel <= 14) { 260 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 261 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 262 } else { 263 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 264 } 265 266 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 267 268 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 269 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 270 } 271 272 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 273 { 274 if (bw == RTW_CHANNEL_WIDTH_40) { 275 /* RX DFIR for BW40 */ 276 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 277 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 278 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 279 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 280 } else if (bw == RTW_CHANNEL_WIDTH_80) { 281 /* RX DFIR for BW80 */ 282 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 283 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 284 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 285 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 286 } else { 287 /* RX DFIR for BW20, BW10 and BW5 */ 288 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 289 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 290 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 291 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 292 } 293 } 294 295 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 296 u8 primary_ch_idx) 297 { 298 u32 val32; 299 300 if (channel <= 14) { 301 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 302 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 303 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 304 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 305 306 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 307 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 308 if (channel == 14) { 309 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 310 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 311 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 312 } else { 313 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 314 rtwdev->chip->ch_param[0]); 315 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 316 rtwdev->chip->ch_param[1] & MASKLWORD); 317 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 318 rtwdev->chip->ch_param[2]); 319 } 320 } else if (channel > 35) { 321 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 322 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 323 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 324 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 325 326 if (channel >= 36 && channel <= 64) 327 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 328 else if (channel >= 100 && channel <= 144) 329 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 330 else if (channel >= 149) 331 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 332 333 if (channel >= 36 && channel <= 48) 334 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 335 else if (channel >= 52 && channel <= 64) 336 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 337 else if (channel >= 100 && channel <= 116) 338 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 339 else if (channel >= 118 && channel <= 177) 340 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 341 } 342 343 switch (bw) { 344 case RTW_CHANNEL_WIDTH_20: 345 default: 346 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 347 val32 &= 0xffcffc00; 348 val32 |= 0x10010000; 349 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 350 351 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 352 break; 353 case RTW_CHANNEL_WIDTH_40: 354 if (primary_ch_idx == 1) 355 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 356 else 357 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 358 359 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 360 val32 &= 0xff3ff300; 361 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 362 RTW_CHANNEL_WIDTH_40; 363 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 364 365 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 366 break; 367 case RTW_CHANNEL_WIDTH_80: 368 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 369 val32 &= 0xfcffcf00; 370 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 371 RTW_CHANNEL_WIDTH_80; 372 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 373 374 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 375 break; 376 case RTW_CHANNEL_WIDTH_5: 377 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 378 val32 &= 0xefcefc00; 379 val32 |= 0x200240; 380 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 381 382 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 383 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 384 break; 385 case RTW_CHANNEL_WIDTH_10: 386 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 387 val32 &= 0xefcefc00; 388 val32 |= 0x300380; 389 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 390 391 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 392 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 393 break; 394 } 395 } 396 397 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 398 { 399 struct rtw_efuse efuse = rtwdev->efuse; 400 u8 tx_bb_swing; 401 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 402 403 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 404 efuse.tx_bb_swing_setting_5g; 405 if (tx_bb_swing > 9) 406 tx_bb_swing = 0; 407 408 return swing2setting[(tx_bb_swing / 3)]; 409 } 410 411 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 412 u8 bw, u8 primary_ch_idx) 413 { 414 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 415 rtw8821c_get_bb_swing(rtwdev, channel)); 416 rtw8821c_pwrtrack_init(rtwdev); 417 } 418 419 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 420 u8 primary_chan_idx) 421 { 422 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 423 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 424 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 425 rtw8821c_set_channel_rf(rtwdev, channel, bw); 426 rtw8821c_set_channel_rxdfir(rtwdev, bw); 427 } 428 429 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 430 struct rtw_rx_pkt_stat *pkt_stat) 431 { 432 s8 min_rx_power = -120; 433 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 434 435 pkt_stat->rx_power[RF_PATH_A] = pwdb - 100; 436 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 437 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 438 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 439 min_rx_power); 440 } 441 442 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 443 struct rtw_rx_pkt_stat *pkt_stat) 444 { 445 u8 rxsc, bw; 446 s8 min_rx_power = -120; 447 448 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 449 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 450 else 451 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 452 453 if (rxsc >= 1 && rxsc <= 8) 454 bw = RTW_CHANNEL_WIDTH_20; 455 else if (rxsc >= 9 && rxsc <= 12) 456 bw = RTW_CHANNEL_WIDTH_40; 457 else if (rxsc >= 13) 458 bw = RTW_CHANNEL_WIDTH_80; 459 else 460 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 461 462 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 463 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 464 pkt_stat->bw = bw; 465 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 466 min_rx_power); 467 } 468 469 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 470 struct rtw_rx_pkt_stat *pkt_stat) 471 { 472 u8 page; 473 474 page = *phy_status & 0xf; 475 476 switch (page) { 477 case 0: 478 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 479 break; 480 case 1: 481 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 482 break; 483 default: 484 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 485 return; 486 } 487 } 488 489 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 490 struct rtw_rx_pkt_stat *pkt_stat, 491 struct ieee80211_rx_status *rx_status) 492 { 493 struct ieee80211_hdr *hdr; 494 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 495 u8 *phy_status = NULL; 496 497 memset(pkt_stat, 0, sizeof(*pkt_stat)); 498 499 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 500 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 501 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 502 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc); 503 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 504 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 505 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 506 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 507 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 508 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 509 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 510 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 511 512 /* drv_info_sz is in unit of 8-bytes */ 513 pkt_stat->drv_info_sz *= 8; 514 515 /* c2h cmd pkt's rx/phy status is not interested */ 516 if (pkt_stat->is_c2h) 517 return; 518 519 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 520 pkt_stat->drv_info_sz); 521 if (pkt_stat->phy_status) { 522 phy_status = rx_desc + desc_sz + pkt_stat->shift; 523 query_phy_status(rtwdev, phy_status, pkt_stat); 524 } 525 526 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 527 } 528 529 static void 530 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 531 { 532 struct rtw_hal *hal = &rtwdev->hal; 533 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 534 static u32 phy_pwr_idx; 535 u8 rate, rate_idx, pwr_index, shift; 536 int j; 537 538 for (j = 0; j < rtw_rate_size[rs]; j++) { 539 rate = rtw_rate_section[rs][j]; 540 pwr_index = hal->tx_pwr_tbl[path][rate]; 541 shift = rate & 0x3; 542 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 543 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 544 rate_idx = rate & 0xfc; 545 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 546 phy_pwr_idx); 547 phy_pwr_idx = 0; 548 } 549 } 550 } 551 552 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 553 { 554 struct rtw_hal *hal = &rtwdev->hal; 555 int rs, path; 556 557 for (path = 0; path < hal->rf_path_num; path++) { 558 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 559 if (rs == RTW_RATE_SECTION_HT_2S || 560 rs == RTW_RATE_SECTION_VHT_2S) 561 continue; 562 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 563 } 564 } 565 } 566 567 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 568 { 569 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 570 u32 cck_enable; 571 u32 cck_fa_cnt; 572 u32 ofdm_fa_cnt; 573 u32 crc32_cnt; 574 u32 cca32_cnt; 575 576 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 577 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 578 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 579 580 dm_info->cck_fa_cnt = cck_fa_cnt; 581 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 582 if (cck_enable) 583 dm_info->total_fa_cnt += cck_fa_cnt; 584 dm_info->total_fa_cnt = ofdm_fa_cnt; 585 586 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 587 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 588 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 589 590 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 591 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 592 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 593 594 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 595 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 596 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 597 598 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 599 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 600 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 601 602 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 603 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 604 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 605 if (cck_enable) { 606 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 607 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 608 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 609 } 610 611 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 612 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 613 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 614 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 615 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 616 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 617 } 618 619 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 620 { 621 static int do_iqk_cnt; 622 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 623 u32 rf_reg, iqk_fail_mask; 624 int counter; 625 bool reload; 626 627 if (rtw_is_assoc(rtwdev)) 628 para.segment_iqk = 1; 629 630 rtw_fw_do_iqk(rtwdev, ¶); 631 632 for (counter = 0; counter < 300; counter++) { 633 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 634 if (rf_reg == 0xabcde) 635 break; 636 msleep(20); 637 } 638 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 639 640 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 641 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 642 rtw_dbg(rtwdev, RTW_DBG_PHY, 643 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 644 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 645 } 646 647 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 648 { 649 rtw8821c_do_iqk(rtwdev); 650 } 651 652 static void 653 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 654 s8 pwr_idx_offset_lower, 655 s8 *txagc_idx, u8 *swing_idx) 656 { 657 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 658 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 659 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 660 u8 swing_lower_bound = 0; 661 u8 max_pwr_idx_offset = 0xf; 662 s8 agc_index = 0; 663 u8 swing_index = dm_info->default_ofdm_index; 664 665 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 666 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 667 668 if (delta_pwr_idx >= 0) { 669 if (delta_pwr_idx <= pwr_idx_offset) { 670 agc_index = delta_pwr_idx; 671 swing_index = dm_info->default_ofdm_index; 672 } else if (delta_pwr_idx > pwr_idx_offset) { 673 agc_index = pwr_idx_offset; 674 swing_index = dm_info->default_ofdm_index + 675 delta_pwr_idx - pwr_idx_offset; 676 swing_index = min_t(u8, swing_index, swing_upper_bound); 677 } 678 } else if (delta_pwr_idx < 0) { 679 if (delta_pwr_idx >= pwr_idx_offset_lower) { 680 agc_index = delta_pwr_idx; 681 swing_index = dm_info->default_ofdm_index; 682 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 683 if (dm_info->default_ofdm_index > 684 (pwr_idx_offset_lower - delta_pwr_idx)) 685 swing_index = dm_info->default_ofdm_index + 686 delta_pwr_idx - pwr_idx_offset_lower; 687 else 688 swing_index = swing_lower_bound; 689 690 agc_index = pwr_idx_offset_lower; 691 } 692 } 693 694 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 695 rtw_warn(rtwdev, "swing index overflow\n"); 696 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 697 } 698 699 *txagc_idx = agc_index; 700 *swing_idx = swing_index; 701 } 702 703 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 704 s8 pwr_idx_offset_lower) 705 { 706 s8 txagc_idx; 707 u8 swing_idx; 708 709 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 710 &txagc_idx, &swing_idx); 711 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 712 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 713 rtw8821c_txscale_tbl[swing_idx]); 714 } 715 716 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 717 { 718 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 719 u8 pwr_idx_offset, tx_pwr_idx; 720 s8 pwr_idx_offset_lower; 721 u8 channel = rtwdev->hal.current_channel; 722 u8 band_width = rtwdev->hal.current_band_width; 723 u8 regd = rtwdev->regd.txpwr_regd; 724 u8 tx_rate = dm_info->tx_rate; 725 u8 max_pwr_idx = rtwdev->chip->max_power_index; 726 727 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 728 band_width, channel, regd); 729 730 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 731 732 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 733 pwr_idx_offset_lower = 0 - tx_pwr_idx; 734 735 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 736 } 737 738 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 739 { 740 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 741 struct rtw_swing_table swing_table; 742 u8 thermal_value, delta; 743 744 rtw_phy_config_swing_table(rtwdev, &swing_table); 745 746 if (rtwdev->efuse.thermal_meter[0] == 0xff) 747 return; 748 749 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 750 751 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 752 753 if (dm_info->pwr_trk_init_trigger) 754 dm_info->pwr_trk_init_trigger = false; 755 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 756 RF_PATH_A)) 757 goto iqk; 758 759 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 760 761 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 762 763 dm_info->delta_power_index[RF_PATH_A] = 764 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 765 RF_PATH_A, delta); 766 if (dm_info->delta_power_index[RF_PATH_A] == 767 dm_info->delta_power_index_last[RF_PATH_A]) 768 goto iqk; 769 else 770 dm_info->delta_power_index_last[RF_PATH_A] = 771 dm_info->delta_power_index[RF_PATH_A]; 772 rtw8821c_pwrtrack_set(rtwdev); 773 774 iqk: 775 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 776 rtw8821c_do_iqk(rtwdev); 777 } 778 779 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 780 { 781 struct rtw_efuse *efuse = &rtwdev->efuse; 782 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 783 784 if (efuse->power_track_type != 0) 785 return; 786 787 if (!dm_info->pwr_trk_triggered) { 788 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 789 GENMASK(17, 16), 0x03); 790 dm_info->pwr_trk_triggered = true; 791 return; 792 } 793 794 rtw8821c_phy_pwrtrack(rtwdev); 795 dm_info->pwr_trk_triggered = false; 796 } 797 798 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 799 struct rtw_vif *vif, 800 struct rtw_bfee *bfee, bool enable) 801 { 802 if (enable) 803 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 804 else 805 rtw_bf_remove_bfee_su(rtwdev, bfee); 806 } 807 808 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 809 struct rtw_vif *vif, 810 struct rtw_bfee *bfee, bool enable) 811 { 812 if (enable) 813 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 814 else 815 rtw_bf_remove_bfee_mu(rtwdev, bfee); 816 } 817 818 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 819 struct rtw_bfee *bfee, bool enable) 820 { 821 if (bfee->role == RTW_BFEE_SU) 822 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 823 else if (bfee->role == RTW_BFEE_MU) 824 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 825 else 826 rtw_warn(rtwdev, "wrong bfee role\n"); 827 } 828 829 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 830 { 831 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 832 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 833 834 if (dm_info->min_rssi > 60) { 835 new_lvl = 4; 836 pd[4] = 0x1d; 837 goto set_cck_pd; 838 } 839 840 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 841 return; 842 843 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 844 845 set_cck_pd: 846 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 847 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 848 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 849 dm_info->cck_pd_default + new_lvl * 2); 850 } 851 852 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 853 {0x0086, 854 RTW_PWR_CUT_ALL_MSK, 855 RTW_PWR_INTF_SDIO_MSK, 856 RTW_PWR_ADDR_SDIO, 857 RTW_PWR_CMD_WRITE, BIT(0), 0}, 858 {0x0086, 859 RTW_PWR_CUT_ALL_MSK, 860 RTW_PWR_INTF_SDIO_MSK, 861 RTW_PWR_ADDR_SDIO, 862 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 863 {0x004A, 864 RTW_PWR_CUT_ALL_MSK, 865 RTW_PWR_INTF_USB_MSK, 866 RTW_PWR_ADDR_MAC, 867 RTW_PWR_CMD_WRITE, BIT(0), 0}, 868 {0x0005, 869 RTW_PWR_CUT_ALL_MSK, 870 RTW_PWR_INTF_ALL_MSK, 871 RTW_PWR_ADDR_MAC, 872 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 873 {0x0300, 874 RTW_PWR_CUT_ALL_MSK, 875 RTW_PWR_INTF_PCI_MSK, 876 RTW_PWR_ADDR_MAC, 877 RTW_PWR_CMD_WRITE, 0xFF, 0}, 878 {0x0301, 879 RTW_PWR_CUT_ALL_MSK, 880 RTW_PWR_INTF_PCI_MSK, 881 RTW_PWR_ADDR_MAC, 882 RTW_PWR_CMD_WRITE, 0xFF, 0}, 883 {0xFFFF, 884 RTW_PWR_CUT_ALL_MSK, 885 RTW_PWR_INTF_ALL_MSK, 886 0, 887 RTW_PWR_CMD_END, 0, 0}, 888 }; 889 890 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 891 {0x0020, 892 RTW_PWR_CUT_ALL_MSK, 893 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 894 RTW_PWR_ADDR_MAC, 895 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 896 {0x0001, 897 RTW_PWR_CUT_ALL_MSK, 898 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 899 RTW_PWR_ADDR_MAC, 900 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 901 {0x0000, 902 RTW_PWR_CUT_ALL_MSK, 903 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 904 RTW_PWR_ADDR_MAC, 905 RTW_PWR_CMD_WRITE, BIT(5), 0}, 906 {0x0005, 907 RTW_PWR_CUT_ALL_MSK, 908 RTW_PWR_INTF_ALL_MSK, 909 RTW_PWR_ADDR_MAC, 910 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 911 {0x0075, 912 RTW_PWR_CUT_ALL_MSK, 913 RTW_PWR_INTF_PCI_MSK, 914 RTW_PWR_ADDR_MAC, 915 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 916 {0x0006, 917 RTW_PWR_CUT_ALL_MSK, 918 RTW_PWR_INTF_ALL_MSK, 919 RTW_PWR_ADDR_MAC, 920 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 921 {0x0075, 922 RTW_PWR_CUT_ALL_MSK, 923 RTW_PWR_INTF_PCI_MSK, 924 RTW_PWR_ADDR_MAC, 925 RTW_PWR_CMD_WRITE, BIT(0), 0}, 926 {0x0006, 927 RTW_PWR_CUT_ALL_MSK, 928 RTW_PWR_INTF_ALL_MSK, 929 RTW_PWR_ADDR_MAC, 930 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 931 {0x0005, 932 RTW_PWR_CUT_ALL_MSK, 933 RTW_PWR_INTF_ALL_MSK, 934 RTW_PWR_ADDR_MAC, 935 RTW_PWR_CMD_WRITE, BIT(7), 0}, 936 {0x0005, 937 RTW_PWR_CUT_ALL_MSK, 938 RTW_PWR_INTF_ALL_MSK, 939 RTW_PWR_ADDR_MAC, 940 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 941 {0x10C3, 942 RTW_PWR_CUT_ALL_MSK, 943 RTW_PWR_INTF_USB_MSK, 944 RTW_PWR_ADDR_MAC, 945 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 946 {0x0005, 947 RTW_PWR_CUT_ALL_MSK, 948 RTW_PWR_INTF_ALL_MSK, 949 RTW_PWR_ADDR_MAC, 950 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 951 {0x0005, 952 RTW_PWR_CUT_ALL_MSK, 953 RTW_PWR_INTF_ALL_MSK, 954 RTW_PWR_ADDR_MAC, 955 RTW_PWR_CMD_POLLING, BIT(0), 0}, 956 {0x0020, 957 RTW_PWR_CUT_ALL_MSK, 958 RTW_PWR_INTF_ALL_MSK, 959 RTW_PWR_ADDR_MAC, 960 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 961 {0x0074, 962 RTW_PWR_CUT_ALL_MSK, 963 RTW_PWR_INTF_PCI_MSK, 964 RTW_PWR_ADDR_MAC, 965 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 966 {0x0022, 967 RTW_PWR_CUT_ALL_MSK, 968 RTW_PWR_INTF_PCI_MSK, 969 RTW_PWR_ADDR_MAC, 970 RTW_PWR_CMD_WRITE, BIT(1), 0}, 971 {0x0062, 972 RTW_PWR_CUT_ALL_MSK, 973 RTW_PWR_INTF_PCI_MSK, 974 RTW_PWR_ADDR_MAC, 975 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 976 (BIT(7) | BIT(6) | BIT(5))}, 977 {0x0061, 978 RTW_PWR_CUT_ALL_MSK, 979 RTW_PWR_INTF_PCI_MSK, 980 RTW_PWR_ADDR_MAC, 981 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 982 {0x007C, 983 RTW_PWR_CUT_ALL_MSK, 984 RTW_PWR_INTF_ALL_MSK, 985 RTW_PWR_ADDR_MAC, 986 RTW_PWR_CMD_WRITE, BIT(1), 0}, 987 {0xFFFF, 988 RTW_PWR_CUT_ALL_MSK, 989 RTW_PWR_INTF_ALL_MSK, 990 0, 991 RTW_PWR_CMD_END, 0, 0}, 992 }; 993 994 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 995 {0x0093, 996 RTW_PWR_CUT_ALL_MSK, 997 RTW_PWR_INTF_ALL_MSK, 998 RTW_PWR_ADDR_MAC, 999 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1000 {0x001F, 1001 RTW_PWR_CUT_ALL_MSK, 1002 RTW_PWR_INTF_ALL_MSK, 1003 RTW_PWR_ADDR_MAC, 1004 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1005 {0x0049, 1006 RTW_PWR_CUT_ALL_MSK, 1007 RTW_PWR_INTF_ALL_MSK, 1008 RTW_PWR_ADDR_MAC, 1009 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1010 {0x0006, 1011 RTW_PWR_CUT_ALL_MSK, 1012 RTW_PWR_INTF_ALL_MSK, 1013 RTW_PWR_ADDR_MAC, 1014 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1015 {0x0002, 1016 RTW_PWR_CUT_ALL_MSK, 1017 RTW_PWR_INTF_ALL_MSK, 1018 RTW_PWR_ADDR_MAC, 1019 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1020 {0x10C3, 1021 RTW_PWR_CUT_ALL_MSK, 1022 RTW_PWR_INTF_USB_MSK, 1023 RTW_PWR_ADDR_MAC, 1024 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1025 {0x0005, 1026 RTW_PWR_CUT_ALL_MSK, 1027 RTW_PWR_INTF_ALL_MSK, 1028 RTW_PWR_ADDR_MAC, 1029 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1030 {0x0005, 1031 RTW_PWR_CUT_ALL_MSK, 1032 RTW_PWR_INTF_ALL_MSK, 1033 RTW_PWR_ADDR_MAC, 1034 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1035 {0x0020, 1036 RTW_PWR_CUT_ALL_MSK, 1037 RTW_PWR_INTF_ALL_MSK, 1038 RTW_PWR_ADDR_MAC, 1039 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1040 {0x0000, 1041 RTW_PWR_CUT_ALL_MSK, 1042 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1043 RTW_PWR_ADDR_MAC, 1044 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1045 {0xFFFF, 1046 RTW_PWR_CUT_ALL_MSK, 1047 RTW_PWR_INTF_ALL_MSK, 1048 0, 1049 RTW_PWR_CMD_END, 0, 0}, 1050 }; 1051 1052 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1053 {0x0007, 1054 RTW_PWR_CUT_ALL_MSK, 1055 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1056 RTW_PWR_ADDR_MAC, 1057 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1058 {0x0067, 1059 RTW_PWR_CUT_ALL_MSK, 1060 RTW_PWR_INTF_ALL_MSK, 1061 RTW_PWR_ADDR_MAC, 1062 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1063 {0x0005, 1064 RTW_PWR_CUT_ALL_MSK, 1065 RTW_PWR_INTF_PCI_MSK, 1066 RTW_PWR_ADDR_MAC, 1067 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1068 {0x004A, 1069 RTW_PWR_CUT_ALL_MSK, 1070 RTW_PWR_INTF_USB_MSK, 1071 RTW_PWR_ADDR_MAC, 1072 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1073 {0x0067, 1074 RTW_PWR_CUT_ALL_MSK, 1075 RTW_PWR_INTF_SDIO_MSK, 1076 RTW_PWR_ADDR_MAC, 1077 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1078 {0x0067, 1079 RTW_PWR_CUT_ALL_MSK, 1080 RTW_PWR_INTF_SDIO_MSK, 1081 RTW_PWR_ADDR_MAC, 1082 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1083 {0x004F, 1084 RTW_PWR_CUT_ALL_MSK, 1085 RTW_PWR_INTF_SDIO_MSK, 1086 RTW_PWR_ADDR_MAC, 1087 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1088 {0x0067, 1089 RTW_PWR_CUT_ALL_MSK, 1090 RTW_PWR_INTF_SDIO_MSK, 1091 RTW_PWR_ADDR_MAC, 1092 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1093 {0x0046, 1094 RTW_PWR_CUT_ALL_MSK, 1095 RTW_PWR_INTF_SDIO_MSK, 1096 RTW_PWR_ADDR_MAC, 1097 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1098 {0x0067, 1099 RTW_PWR_CUT_ALL_MSK, 1100 RTW_PWR_INTF_SDIO_MSK, 1101 RTW_PWR_ADDR_MAC, 1102 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1103 {0x0046, 1104 RTW_PWR_CUT_ALL_MSK, 1105 RTW_PWR_INTF_SDIO_MSK, 1106 RTW_PWR_ADDR_MAC, 1107 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1108 {0x0062, 1109 RTW_PWR_CUT_ALL_MSK, 1110 RTW_PWR_INTF_SDIO_MSK, 1111 RTW_PWR_ADDR_MAC, 1112 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1113 {0x0081, 1114 RTW_PWR_CUT_ALL_MSK, 1115 RTW_PWR_INTF_ALL_MSK, 1116 RTW_PWR_ADDR_MAC, 1117 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1118 {0x0005, 1119 RTW_PWR_CUT_ALL_MSK, 1120 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1121 RTW_PWR_ADDR_MAC, 1122 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1123 {0x0086, 1124 RTW_PWR_CUT_ALL_MSK, 1125 RTW_PWR_INTF_SDIO_MSK, 1126 RTW_PWR_ADDR_SDIO, 1127 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1128 {0x0086, 1129 RTW_PWR_CUT_ALL_MSK, 1130 RTW_PWR_INTF_SDIO_MSK, 1131 RTW_PWR_ADDR_SDIO, 1132 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1133 {0x0090, 1134 RTW_PWR_CUT_ALL_MSK, 1135 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1136 RTW_PWR_ADDR_MAC, 1137 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1138 {0x0044, 1139 RTW_PWR_CUT_ALL_MSK, 1140 RTW_PWR_INTF_SDIO_MSK, 1141 RTW_PWR_ADDR_SDIO, 1142 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1143 {0x0040, 1144 RTW_PWR_CUT_ALL_MSK, 1145 RTW_PWR_INTF_SDIO_MSK, 1146 RTW_PWR_ADDR_SDIO, 1147 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1148 {0x0041, 1149 RTW_PWR_CUT_ALL_MSK, 1150 RTW_PWR_INTF_SDIO_MSK, 1151 RTW_PWR_ADDR_SDIO, 1152 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1153 {0x0042, 1154 RTW_PWR_CUT_ALL_MSK, 1155 RTW_PWR_INTF_SDIO_MSK, 1156 RTW_PWR_ADDR_SDIO, 1157 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1158 {0xFFFF, 1159 RTW_PWR_CUT_ALL_MSK, 1160 RTW_PWR_INTF_ALL_MSK, 1161 0, 1162 RTW_PWR_CMD_END, 0, 0}, 1163 }; 1164 1165 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1166 trans_carddis_to_cardemu_8821c, 1167 trans_cardemu_to_act_8821c, 1168 NULL 1169 }; 1170 1171 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1172 trans_act_to_cardemu_8821c, 1173 trans_cardemu_to_carddis_8821c, 1174 NULL 1175 }; 1176 1177 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1178 {0xFFFF, 0x00, 1179 RTW_IP_SEL_PHY, 1180 RTW_INTF_PHY_CUT_ALL, 1181 RTW_INTF_PHY_PLATFORM_ALL}, 1182 }; 1183 1184 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1185 {0xFFFF, 0x0000, 1186 RTW_IP_SEL_PHY, 1187 RTW_INTF_PHY_CUT_ALL, 1188 RTW_INTF_PHY_PLATFORM_ALL}, 1189 }; 1190 1191 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1192 {0x0009, 0x6380, 1193 RTW_IP_SEL_PHY, 1194 RTW_INTF_PHY_CUT_ALL, 1195 RTW_INTF_PHY_PLATFORM_ALL}, 1196 {0xFFFF, 0x0000, 1197 RTW_IP_SEL_PHY, 1198 RTW_INTF_PHY_CUT_ALL, 1199 RTW_INTF_PHY_PLATFORM_ALL}, 1200 }; 1201 1202 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1203 {0xFFFF, 0x0000, 1204 RTW_IP_SEL_PHY, 1205 RTW_INTF_PHY_CUT_ALL, 1206 RTW_INTF_PHY_PLATFORM_ALL}, 1207 }; 1208 1209 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1210 .usb2_para = usb2_param_8821c, 1211 .usb3_para = usb3_param_8821c, 1212 .gen1_para = pcie_gen1_param_8821c, 1213 .gen2_para = pcie_gen2_param_8821c, 1214 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1215 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1216 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1217 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1218 }; 1219 1220 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1221 [0] = RTW_DEF_RFE(8821c, 0, 0), 1222 }; 1223 1224 static struct rtw_hw_reg rtw8821c_dig[] = { 1225 [0] = { .addr = 0xc50, .mask = 0x7f }, 1226 }; 1227 1228 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1229 .ctrl = LTECOEX_ACCESS_CTRL, 1230 .wdata = LTECOEX_WRITE_DATA, 1231 .rdata = LTECOEX_READ_DATA, 1232 }; 1233 1234 static struct rtw_page_table page_table_8821c[] = { 1235 /* not sure what [0] stands for */ 1236 {16, 16, 16, 14, 1}, 1237 {16, 16, 16, 14, 1}, 1238 {16, 16, 0, 0, 1}, 1239 {16, 16, 16, 0, 1}, 1240 {16, 16, 16, 14, 1}, 1241 }; 1242 1243 static struct rtw_rqpn rqpn_table_8821c[] = { 1244 /* not sure what [0] stands for */ 1245 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1246 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1247 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1248 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1249 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1250 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1251 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1252 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1253 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1254 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1255 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1256 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1257 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1258 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1259 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1260 }; 1261 1262 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1263 .prio[RTW_DMA_MAPPING_EXTRA] = { 1264 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1265 }, 1266 .prio[RTW_DMA_MAPPING_LOW] = { 1267 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1268 }, 1269 .prio[RTW_DMA_MAPPING_NORMAL] = { 1270 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1271 }, 1272 .prio[RTW_DMA_MAPPING_HIGH] = { 1273 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1274 }, 1275 .wsize = true, 1276 }; 1277 1278 static struct rtw_chip_ops rtw8821c_ops = { 1279 .phy_set_param = rtw8821c_phy_set_param, 1280 .read_efuse = rtw8821c_read_efuse, 1281 .query_rx_desc = rtw8821c_query_rx_desc, 1282 .set_channel = rtw8821c_set_channel, 1283 .mac_init = rtw8821c_mac_init, 1284 .read_rf = rtw_phy_read_rf, 1285 .write_rf = rtw_phy_write_rf_reg_sipi, 1286 .set_antenna = NULL, 1287 .set_tx_power_index = rtw8821c_set_tx_power_index, 1288 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1289 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1290 .phy_calibration = rtw8821c_phy_calibration, 1291 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1292 .pwr_track = rtw8821c_pwr_track, 1293 .config_bfee = rtw8821c_bf_config_bfee, 1294 .set_gid_table = rtw_bf_set_gid_table, 1295 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1296 }; 1297 1298 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1299 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1300 11, 11, 12, 12, 12, 12, 12}, 1301 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1302 11, 12, 12, 12, 12, 12, 12, 12}, 1303 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1304 11, 12, 12, 12, 12, 12, 12}, 1305 }; 1306 1307 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1308 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1309 12, 12, 12, 12, 12, 12, 12}, 1310 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1311 12, 12, 12, 12, 12, 12, 12, 12}, 1312 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1313 11, 12, 12, 12, 12, 12, 12, 12}, 1314 }; 1315 1316 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1317 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1318 11, 11, 12, 12, 12, 12, 12}, 1319 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1320 11, 12, 12, 12, 12, 12, 12, 12}, 1321 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1322 11, 12, 12, 12, 12, 12, 12}, 1323 }; 1324 1325 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1326 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1327 12, 12, 12, 12, 12, 12, 12}, 1328 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1329 12, 12, 12, 12, 12, 12, 12, 12}, 1330 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1331 11, 12, 12, 12, 12, 12, 12, 12}, 1332 }; 1333 1334 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1335 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1336 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1337 }; 1338 1339 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1340 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1341 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1342 }; 1343 1344 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1345 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1346 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1347 }; 1348 1349 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1350 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1351 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1352 }; 1353 1354 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1355 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1356 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1357 }; 1358 1359 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1360 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1361 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1362 }; 1363 1364 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1365 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1366 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1367 }; 1368 1369 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1370 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1371 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1372 }; 1373 1374 const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1375 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1376 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1377 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1378 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1379 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1380 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1381 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1382 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1383 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1384 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1385 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1386 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1387 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1388 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1389 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1390 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1391 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1392 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1393 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1394 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1395 }; 1396 1397 struct rtw_chip_info rtw8821c_hw_spec = { 1398 .ops = &rtw8821c_ops, 1399 .id = RTW_CHIP_TYPE_8821C, 1400 .fw_name = "rtw88/rtw8821c_fw.bin", 1401 .wlan_cpu = RTW_WCPU_11AC, 1402 .tx_pkt_desc_sz = 48, 1403 .tx_buf_desc_sz = 16, 1404 .rx_pkt_desc_sz = 24, 1405 .rx_buf_desc_sz = 8, 1406 .phy_efuse_size = 512, 1407 .log_efuse_size = 512, 1408 .ptct_efuse_size = 96, 1409 .txff_size = 65536, 1410 .rxff_size = 16384, 1411 .txgi_factor = 1, 1412 .is_pwr_by_rate_dec = true, 1413 .max_power_index = 0x3f, 1414 .csi_buf_pg_num = 0, 1415 .band = RTW_BAND_2G | RTW_BAND_5G, 1416 .page_size = 128, 1417 .dig_min = 0x1c, 1418 .ht_supported = true, 1419 .vht_supported = true, 1420 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1421 .sys_func_en = 0xD8, 1422 .pwr_on_seq = card_enable_flow_8821c, 1423 .pwr_off_seq = card_disable_flow_8821c, 1424 .page_table = page_table_8821c, 1425 .rqpn_table = rqpn_table_8821c, 1426 .prioq_addrs = &prioq_addrs_8821c, 1427 .intf_table = &phy_para_table_8821c, 1428 .dig = rtw8821c_dig, 1429 .rf_base_addr = {0x2800, 0x2c00}, 1430 .rf_sipi_addr = {0xc90, 0xe90}, 1431 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1432 .mac_tbl = &rtw8821c_mac_tbl, 1433 .agc_tbl = &rtw8821c_agc_tbl, 1434 .bb_tbl = &rtw8821c_bb_tbl, 1435 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1436 .rfe_defs = rtw8821c_rfe_defs, 1437 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1438 .rx_ldpc = false, 1439 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1440 .iqk_threshold = 8, 1441 .bfer_su_max_num = 2, 1442 .bfer_mu_max_num = 1, 1443 }; 1444 EXPORT_SYMBOL(rtw8821c_hw_spec); 1445 1446 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 1447 1448 MODULE_AUTHOR("Realtek Corporation"); 1449 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 1450 MODULE_LICENSE("Dual BSD/GPL"); 1451