1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 #include "regd.h" 18 19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; 20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, 21 -20, -24, -28, -31, -34, -37, -40, -44}; 22 23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8821c_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse, 30 struct rtw8821c_efuse *map) 31 { 32 ether_addr_copy(efuse->addr, map->u.mac_addr); 33 } 34 35 static void rtw8821cs_efuse_parsing(struct rtw_efuse *efuse, 36 struct rtw8821c_efuse *map) 37 { 38 ether_addr_copy(efuse->addr, map->s.mac_addr); 39 } 40 41 enum rtw8821ce_rf_set { 42 SWITCH_TO_BTG, 43 SWITCH_TO_WLG, 44 SWITCH_TO_WLA, 45 SWITCH_TO_BT, 46 }; 47 48 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 49 { 50 struct rtw_efuse *efuse = &rtwdev->efuse; 51 struct rtw8821c_efuse *map; 52 int i; 53 54 map = (struct rtw8821c_efuse *)log_map; 55 56 efuse->rfe_option = map->rfe_option; 57 efuse->rf_board_option = map->rf_board_option; 58 efuse->crystal_cap = map->xtal_k; 59 efuse->pa_type_2g = map->pa_type; 60 efuse->pa_type_5g = map->pa_type; 61 efuse->lna_type_2g = map->lna_type_2g[0]; 62 efuse->lna_type_5g = map->lna_type_5g[0]; 63 efuse->channel_plan = map->channel_plan; 64 efuse->country_code[0] = map->country_code[0]; 65 efuse->country_code[1] = map->country_code[1]; 66 efuse->bt_setting = map->rf_bt_setting; 67 efuse->regd = map->rf_board_option & 0x7; 68 efuse->thermal_meter[0] = map->thermal_meter; 69 efuse->thermal_meter_k = map->thermal_meter; 70 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 71 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 72 73 for (i = 0; i < 4; i++) 74 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 75 76 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) 77 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; 78 79 switch (rtw_hci_type(rtwdev)) { 80 case RTW_HCI_TYPE_PCIE: 81 rtw8821ce_efuse_parsing(efuse, map); 82 break; 83 case RTW_HCI_TYPE_USB: 84 rtw8821cu_efuse_parsing(efuse, map); 85 break; 86 case RTW_HCI_TYPE_SDIO: 87 rtw8821cs_efuse_parsing(efuse, map); 88 break; 89 default: 90 /* unsupported now */ 91 return -ENOTSUPP; 92 } 93 94 return 0; 95 } 96 97 static const u32 rtw8821c_txscale_tbl[] = { 98 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 99 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 100 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 101 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 102 }; 103 104 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 105 { 106 u8 i = 0; 107 u32 swing, table_value; 108 109 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 110 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 111 table_value = rtw8821c_txscale_tbl[i]; 112 if (swing == table_value) 113 break; 114 } 115 116 return i; 117 } 118 119 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 120 { 121 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 122 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 123 124 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 125 dm_info->default_ofdm_index = 24; 126 else 127 dm_info->default_ofdm_index = swing_idx; 128 129 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 130 dm_info->delta_power_index[RF_PATH_A] = 0; 131 dm_info->delta_power_index_last[RF_PATH_A] = 0; 132 dm_info->pwr_trk_triggered = false; 133 dm_info->pwr_trk_init_trigger = true; 134 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 135 } 136 137 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 138 { 139 rtw_bf_phy_init(rtwdev); 140 /* Grouping bitmap parameters */ 141 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 142 } 143 144 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 145 { 146 struct rtw_hal *hal = &rtwdev->hal; 147 u8 crystal_cap, val; 148 149 /* power on BB/RF domain */ 150 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 151 val |= BIT_FEN_PCIEA; 152 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 153 154 /* toggle BB reset */ 155 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 156 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 157 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 158 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 159 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 160 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 161 162 rtw_write8(rtwdev, REG_RF_CTRL, 163 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 164 usleep_range(10, 11); 165 rtw_write8(rtwdev, REG_WLRF1 + 3, 166 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 167 usleep_range(10, 11); 168 169 /* pre init before header files config */ 170 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 171 172 rtw_phy_load_tables(rtwdev); 173 174 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 175 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 176 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 177 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 178 179 /* post init after header files config */ 180 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 181 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 182 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 183 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 184 185 rtw_phy_init(rtwdev); 186 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 187 188 rtw8821c_pwrtrack_init(rtwdev); 189 190 rtw8821c_phy_bf_init(rtwdev); 191 } 192 193 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 194 { 195 u32 value32; 196 u16 pre_txcnt; 197 198 /* protocol configuration */ 199 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 200 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 201 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 202 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 203 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 204 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 205 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 206 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 207 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 208 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 209 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 210 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 211 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 212 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 213 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 214 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 215 216 /* EDCA configuration */ 217 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 218 rtw_write16(rtwdev, REG_TXPAUSE, 0); 219 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 220 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 221 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 222 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 223 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 224 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 225 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 226 227 /* Set beacon cotnrol - enable TSF and other related functions */ 228 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 229 230 /* Set send beacon related registers */ 231 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 232 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 233 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 234 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 235 236 /* WMAC configuration */ 237 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 238 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 239 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 240 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 241 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 242 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 243 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 244 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 245 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 246 BIT_DIS_CHK_VHTSIGB_CRC); 247 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 248 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 249 250 return 0; 251 } 252 253 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 254 { 255 u8 ldo_pwr; 256 257 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 258 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 259 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 260 } 261 262 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) 263 { 264 u32 reg; 265 266 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST); 267 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN); 268 269 reg = rtw_read32(rtwdev, REG_RFECTL); 270 switch (rf_set) { 271 case SWITCH_TO_BTG: 272 reg |= B_BTG_SWITCH; 273 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH | 274 B_WLA_SWITCH); 275 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); 276 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); 277 break; 278 case SWITCH_TO_WLG: 279 reg |= B_WL_SWITCH | B_WLG_SWITCH; 280 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH); 281 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); 282 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); 283 break; 284 case SWITCH_TO_WLA: 285 reg |= B_WL_SWITCH | B_WLA_SWITCH; 286 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH); 287 break; 288 case SWITCH_TO_BT: 289 default: 290 break; 291 } 292 293 rtw_write32(rtwdev, REG_RFECTL, reg); 294 } 295 296 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 297 { 298 u32 rf_reg18; 299 300 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 301 302 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 303 RF18_BW_MASK); 304 305 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 306 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 307 308 if (channel >= 100 && channel <= 140) 309 rf_reg18 |= RF18_RFSI_GE; 310 else if (channel > 140) 311 rf_reg18 |= RF18_RFSI_GT; 312 313 switch (bw) { 314 case RTW_CHANNEL_WIDTH_5: 315 case RTW_CHANNEL_WIDTH_10: 316 case RTW_CHANNEL_WIDTH_20: 317 default: 318 rf_reg18 |= RF18_BW_20M; 319 break; 320 case RTW_CHANNEL_WIDTH_40: 321 rf_reg18 |= RF18_BW_40M; 322 break; 323 case RTW_CHANNEL_WIDTH_80: 324 rf_reg18 |= RF18_BW_80M; 325 break; 326 } 327 328 if (channel <= 14) { 329 if (rtwdev->efuse.rfe_option == 0) 330 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG); 331 else if (rtwdev->efuse.rfe_option == 2 || 332 rtwdev->efuse.rfe_option == 4) 333 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG); 334 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 335 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 336 } else { 337 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA); 338 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 339 } 340 341 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 342 343 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 344 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 345 } 346 347 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 348 { 349 if (bw == RTW_CHANNEL_WIDTH_40) { 350 /* RX DFIR for BW40 */ 351 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 352 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 353 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 354 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 355 } else if (bw == RTW_CHANNEL_WIDTH_80) { 356 /* RX DFIR for BW80 */ 357 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 358 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 359 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 360 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 361 } else { 362 /* RX DFIR for BW20, BW10 and BW5 */ 363 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 364 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 365 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 366 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 367 } 368 } 369 370 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 371 u8 primary_ch_idx) 372 { 373 struct rtw_hal *hal = &rtwdev->hal; 374 u32 val32; 375 376 if (channel <= 14) { 377 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 378 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 379 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 380 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 381 382 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 383 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 384 if (channel == 14) { 385 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 386 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 387 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 388 } else { 389 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 390 hal->ch_param[0]); 391 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 392 hal->ch_param[1] & MASKLWORD); 393 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 394 hal->ch_param[2]); 395 } 396 } else if (channel > 35) { 397 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 398 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 399 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 400 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 401 402 if (channel >= 36 && channel <= 64) 403 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 404 else if (channel >= 100 && channel <= 144) 405 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 406 else if (channel >= 149) 407 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 408 409 if (channel >= 36 && channel <= 48) 410 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 411 else if (channel >= 52 && channel <= 64) 412 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 413 else if (channel >= 100 && channel <= 116) 414 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 415 else if (channel >= 118 && channel <= 177) 416 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 417 } 418 419 switch (bw) { 420 case RTW_CHANNEL_WIDTH_20: 421 default: 422 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 423 val32 &= 0xffcffc00; 424 val32 |= 0x10010000; 425 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 426 427 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 428 break; 429 case RTW_CHANNEL_WIDTH_40: 430 if (primary_ch_idx == 1) 431 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 432 else 433 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 434 435 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 436 val32 &= 0xff3ff300; 437 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 438 RTW_CHANNEL_WIDTH_40; 439 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 440 441 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 442 break; 443 case RTW_CHANNEL_WIDTH_80: 444 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 445 val32 &= 0xfcffcf00; 446 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 447 RTW_CHANNEL_WIDTH_80; 448 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 449 450 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 451 break; 452 case RTW_CHANNEL_WIDTH_5: 453 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 454 val32 &= 0xefcefc00; 455 val32 |= 0x200240; 456 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 457 458 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 459 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 460 break; 461 case RTW_CHANNEL_WIDTH_10: 462 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 463 val32 &= 0xefcefc00; 464 val32 |= 0x300380; 465 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 466 467 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 468 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 469 break; 470 } 471 } 472 473 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 474 { 475 struct rtw_efuse efuse = rtwdev->efuse; 476 u8 tx_bb_swing; 477 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 478 479 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 480 efuse.tx_bb_swing_setting_5g; 481 if (tx_bb_swing > 9) 482 tx_bb_swing = 0; 483 484 return swing2setting[(tx_bb_swing / 3)]; 485 } 486 487 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 488 u8 bw, u8 primary_ch_idx) 489 { 490 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 491 rtw8821c_get_bb_swing(rtwdev, channel)); 492 rtw8821c_pwrtrack_init(rtwdev); 493 } 494 495 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 496 u8 primary_chan_idx) 497 { 498 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 499 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 500 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 501 rtw8821c_set_channel_rf(rtwdev, channel, bw); 502 rtw8821c_set_channel_rxdfir(rtwdev, bw); 503 } 504 505 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 506 { 507 struct rtw_efuse *efuse = &rtwdev->efuse; 508 const s8 *lna_gain_table; 509 int lna_gain_table_size; 510 s8 rx_pwr_all = 0; 511 s8 lna_gain = 0; 512 513 if (efuse->rfe_option == 0) { 514 lna_gain_table = lna_gain_table_0; 515 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0); 516 } else { 517 lna_gain_table = lna_gain_table_1; 518 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1); 519 } 520 521 if (lna_idx >= lna_gain_table_size) { 522 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 523 return -120; 524 } 525 526 lna_gain = lna_gain_table[lna_idx]; 527 rx_pwr_all = lna_gain - 2 * vga_idx; 528 529 return rx_pwr_all; 530 } 531 532 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 533 struct rtw_rx_pkt_stat *pkt_stat) 534 { 535 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 536 s8 rx_power; 537 u8 lna_idx = 0; 538 u8 vga_idx = 0; 539 540 vga_idx = GET_PHY_STAT_P0_VGA(phy_status); 541 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) | 542 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status)); 543 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 544 545 pkt_stat->rx_power[RF_PATH_A] = rx_power; 546 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 547 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 548 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 549 pkt_stat->signal_power = rx_power; 550 } 551 552 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 553 struct rtw_rx_pkt_stat *pkt_stat) 554 { 555 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 556 u8 rxsc, bw; 557 s8 min_rx_power = -120; 558 559 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 560 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 561 else 562 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 563 564 if (rxsc >= 1 && rxsc <= 8) 565 bw = RTW_CHANNEL_WIDTH_20; 566 else if (rxsc >= 9 && rxsc <= 12) 567 bw = RTW_CHANNEL_WIDTH_40; 568 else if (rxsc >= 13) 569 bw = RTW_CHANNEL_WIDTH_80; 570 else 571 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 572 573 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 574 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 575 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 576 pkt_stat->bw = bw; 577 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 578 min_rx_power); 579 } 580 581 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 582 struct rtw_rx_pkt_stat *pkt_stat) 583 { 584 u8 page; 585 586 page = *phy_status & 0xf; 587 588 switch (page) { 589 case 0: 590 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 591 break; 592 case 1: 593 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 594 break; 595 default: 596 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 597 return; 598 } 599 } 600 601 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 602 struct rtw_rx_pkt_stat *pkt_stat, 603 struct ieee80211_rx_status *rx_status) 604 { 605 struct ieee80211_hdr *hdr; 606 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 607 u8 *phy_status = NULL; 608 609 memset(pkt_stat, 0, sizeof(*pkt_stat)); 610 611 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 612 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 613 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 614 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 615 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 616 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 617 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 618 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 619 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 620 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 621 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 622 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 623 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 624 625 /* drv_info_sz is in unit of 8-bytes */ 626 pkt_stat->drv_info_sz *= 8; 627 628 /* c2h cmd pkt's rx/phy status is not interested */ 629 if (pkt_stat->is_c2h) 630 return; 631 632 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 633 pkt_stat->drv_info_sz); 634 if (pkt_stat->phy_status) { 635 phy_status = rx_desc + desc_sz + pkt_stat->shift; 636 query_phy_status(rtwdev, phy_status, pkt_stat); 637 } 638 639 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 640 } 641 642 static void 643 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 644 { 645 struct rtw_hal *hal = &rtwdev->hal; 646 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 647 static u32 phy_pwr_idx; 648 u8 rate, rate_idx, pwr_index, shift; 649 int j; 650 651 for (j = 0; j < rtw_rate_size[rs]; j++) { 652 rate = rtw_rate_section[rs][j]; 653 pwr_index = hal->tx_pwr_tbl[path][rate]; 654 shift = rate & 0x3; 655 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 656 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 657 rate_idx = rate & 0xfc; 658 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 659 phy_pwr_idx); 660 phy_pwr_idx = 0; 661 } 662 } 663 } 664 665 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 666 { 667 struct rtw_hal *hal = &rtwdev->hal; 668 int rs, path; 669 670 for (path = 0; path < hal->rf_path_num; path++) { 671 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 672 if (rs == RTW_RATE_SECTION_HT_2S || 673 rs == RTW_RATE_SECTION_VHT_2S) 674 continue; 675 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 676 } 677 } 678 } 679 680 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 681 { 682 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 683 u32 cck_enable; 684 u32 cck_fa_cnt; 685 u32 ofdm_fa_cnt; 686 u32 crc32_cnt; 687 u32 cca32_cnt; 688 689 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 690 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 691 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 692 693 dm_info->cck_fa_cnt = cck_fa_cnt; 694 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 695 if (cck_enable) 696 dm_info->total_fa_cnt += cck_fa_cnt; 697 dm_info->total_fa_cnt = ofdm_fa_cnt; 698 699 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 700 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 701 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 702 703 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 704 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 705 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 706 707 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 708 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 709 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 710 711 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 712 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 713 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 714 715 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 716 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 717 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 718 if (cck_enable) { 719 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 720 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 721 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 722 } 723 724 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 725 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 726 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 727 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 728 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 729 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 730 } 731 732 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 733 { 734 static int do_iqk_cnt; 735 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 736 u32 rf_reg, iqk_fail_mask; 737 int counter; 738 bool reload; 739 740 if (rtw_is_assoc(rtwdev)) 741 para.segment_iqk = 1; 742 743 rtw_fw_do_iqk(rtwdev, ¶); 744 745 for (counter = 0; counter < 300; counter++) { 746 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 747 if (rf_reg == 0xabcde) 748 break; 749 msleep(20); 750 } 751 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 752 753 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 754 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 755 rtw_dbg(rtwdev, RTW_DBG_PHY, 756 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 757 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 758 } 759 760 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 761 { 762 rtw8821c_do_iqk(rtwdev); 763 } 764 765 /* for coex */ 766 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 767 { 768 /* enable TBTT nterrupt */ 769 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 770 771 /* BT report packet sample rate */ 772 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 773 774 /* enable BT counter statistics */ 775 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 776 777 /* enable PTA (3-wire function form BT side) */ 778 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 779 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 780 781 /* enable PTA (tx/rx signal form WiFi side) */ 782 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 783 /* wl tx signal to PTA not case EDCCA */ 784 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 785 /* GNT_BT=1 while select both */ 786 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 787 788 /* beacon queue always hi-pri */ 789 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 790 BCN_PRI_EN); 791 } 792 793 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 794 u8 pos_type) 795 { 796 struct rtw_coex *coex = &rtwdev->coex; 797 struct rtw_coex_dm *coex_dm = &coex->dm; 798 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 799 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 800 bool polarity_inverse; 801 u8 regval = 0; 802 803 if (switch_status == coex_dm->cur_switch_status) 804 return; 805 806 if (coex_rfe->wlg_at_btg) { 807 ctrl_type = COEX_SWITCH_CTRL_BY_BBSW; 808 809 if (coex_rfe->ant_switch_polarity) 810 pos_type = COEX_SWITCH_TO_WLA; 811 else 812 pos_type = COEX_SWITCH_TO_WLG_BT; 813 } 814 815 coex_dm->cur_switch_status = switch_status; 816 817 if (coex_rfe->ant_switch_diversity && 818 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 819 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 820 821 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 822 823 switch (ctrl_type) { 824 default: 825 case COEX_SWITCH_CTRL_BY_BBSW: 826 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 827 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 828 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 829 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 830 DPDT_CTRL_PIN); 831 832 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 833 if (coex_rfe->rfe_module_type != 0x4 && 834 coex_rfe->rfe_module_type != 0x2) 835 regval = 0x3; 836 else 837 regval = (!polarity_inverse ? 0x2 : 0x1); 838 } else if (pos_type == COEX_SWITCH_TO_WLG) { 839 regval = (!polarity_inverse ? 0x2 : 0x1); 840 } else { 841 regval = (!polarity_inverse ? 0x1 : 0x2); 842 } 843 844 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 845 regval); 846 break; 847 case COEX_SWITCH_CTRL_BY_PTA: 848 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 849 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 850 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 851 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 852 PTA_CTRL_PIN); 853 854 regval = (!polarity_inverse ? 0x2 : 0x1); 855 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 856 regval); 857 break; 858 case COEX_SWITCH_CTRL_BY_ANTDIV: 859 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 860 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 861 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 862 ANTDIC_CTRL_PIN); 863 break; 864 case COEX_SWITCH_CTRL_BY_MAC: 865 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 866 867 regval = (!polarity_inverse ? 0x0 : 0x1); 868 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 869 regval); 870 break; 871 case COEX_SWITCH_CTRL_BY_FW: 872 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 873 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 874 break; 875 case COEX_SWITCH_CTRL_BY_BT: 876 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 877 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 878 break; 879 } 880 881 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 882 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 883 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 884 } else { 885 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 886 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 887 } 888 } 889 890 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 891 {} 892 893 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 894 { 895 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 896 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 897 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 898 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 899 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 900 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 901 } 902 903 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 904 { 905 struct rtw_coex *coex = &rtwdev->coex; 906 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 907 struct rtw_efuse *efuse = &rtwdev->efuse; 908 909 coex_rfe->rfe_module_type = efuse->rfe_option; 910 coex_rfe->ant_switch_polarity = 0; 911 coex_rfe->ant_switch_exist = true; 912 coex_rfe->wlg_at_btg = false; 913 914 switch (coex_rfe->rfe_module_type) { 915 case 0: 916 case 8: 917 case 1: 918 case 9: /* 1-Ant, Main, WLG */ 919 default: /* 2-Ant, DPDT, WLG */ 920 break; 921 case 2: 922 case 10: /* 1-Ant, Main, BTG */ 923 case 7: 924 case 15: /* 2-Ant, DPDT, BTG */ 925 coex_rfe->wlg_at_btg = true; 926 break; 927 case 3: 928 case 11: /* 1-Ant, Aux, WLG */ 929 coex_rfe->ant_switch_polarity = 1; 930 break; 931 case 4: 932 case 12: /* 1-Ant, Aux, BTG */ 933 coex_rfe->wlg_at_btg = true; 934 coex_rfe->ant_switch_polarity = 1; 935 break; 936 case 5: 937 case 13: /* 2-Ant, no switch, WLG */ 938 case 6: 939 case 14: /* 2-Ant, no antenna switch, WLG */ 940 coex_rfe->ant_switch_exist = false; 941 break; 942 } 943 } 944 945 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 946 { 947 struct rtw_coex *coex = &rtwdev->coex; 948 struct rtw_coex_dm *coex_dm = &coex->dm; 949 struct rtw_efuse *efuse = &rtwdev->efuse; 950 bool share_ant = efuse->share_ant; 951 952 if (share_ant) 953 return; 954 955 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 956 return; 957 958 coex_dm->cur_wl_pwr_lvl = wl_pwr; 959 } 960 961 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 962 {} 963 964 static void 965 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 966 s8 pwr_idx_offset_lower, 967 s8 *txagc_idx, u8 *swing_idx) 968 { 969 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 970 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 971 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 972 u8 swing_lower_bound = 0; 973 u8 max_pwr_idx_offset = 0xf; 974 s8 agc_index = 0; 975 u8 swing_index = dm_info->default_ofdm_index; 976 977 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 978 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 979 980 if (delta_pwr_idx >= 0) { 981 if (delta_pwr_idx <= pwr_idx_offset) { 982 agc_index = delta_pwr_idx; 983 swing_index = dm_info->default_ofdm_index; 984 } else if (delta_pwr_idx > pwr_idx_offset) { 985 agc_index = pwr_idx_offset; 986 swing_index = dm_info->default_ofdm_index + 987 delta_pwr_idx - pwr_idx_offset; 988 swing_index = min_t(u8, swing_index, swing_upper_bound); 989 } 990 } else if (delta_pwr_idx < 0) { 991 if (delta_pwr_idx >= pwr_idx_offset_lower) { 992 agc_index = delta_pwr_idx; 993 swing_index = dm_info->default_ofdm_index; 994 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 995 if (dm_info->default_ofdm_index > 996 (pwr_idx_offset_lower - delta_pwr_idx)) 997 swing_index = dm_info->default_ofdm_index + 998 delta_pwr_idx - pwr_idx_offset_lower; 999 else 1000 swing_index = swing_lower_bound; 1001 1002 agc_index = pwr_idx_offset_lower; 1003 } 1004 } 1005 1006 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 1007 rtw_warn(rtwdev, "swing index overflow\n"); 1008 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 1009 } 1010 1011 *txagc_idx = agc_index; 1012 *swing_idx = swing_index; 1013 } 1014 1015 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 1016 s8 pwr_idx_offset_lower) 1017 { 1018 s8 txagc_idx; 1019 u8 swing_idx; 1020 1021 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 1022 &txagc_idx, &swing_idx); 1023 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 1024 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 1025 rtw8821c_txscale_tbl[swing_idx]); 1026 } 1027 1028 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 1029 { 1030 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1031 u8 pwr_idx_offset, tx_pwr_idx; 1032 s8 pwr_idx_offset_lower; 1033 u8 channel = rtwdev->hal.current_channel; 1034 u8 band_width = rtwdev->hal.current_band_width; 1035 u8 regd = rtw_regd_get(rtwdev); 1036 u8 tx_rate = dm_info->tx_rate; 1037 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1038 1039 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 1040 band_width, channel, regd); 1041 1042 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1043 1044 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1045 pwr_idx_offset_lower = 0 - tx_pwr_idx; 1046 1047 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 1048 } 1049 1050 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 1051 { 1052 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1053 struct rtw_swing_table swing_table; 1054 u8 thermal_value, delta; 1055 1056 rtw_phy_config_swing_table(rtwdev, &swing_table); 1057 1058 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1059 return; 1060 1061 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1062 1063 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1064 1065 if (dm_info->pwr_trk_init_trigger) 1066 dm_info->pwr_trk_init_trigger = false; 1067 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1068 RF_PATH_A)) 1069 goto iqk; 1070 1071 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1072 1073 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1074 1075 dm_info->delta_power_index[RF_PATH_A] = 1076 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 1077 RF_PATH_A, delta); 1078 if (dm_info->delta_power_index[RF_PATH_A] == 1079 dm_info->delta_power_index_last[RF_PATH_A]) 1080 goto iqk; 1081 else 1082 dm_info->delta_power_index_last[RF_PATH_A] = 1083 dm_info->delta_power_index[RF_PATH_A]; 1084 rtw8821c_pwrtrack_set(rtwdev); 1085 1086 iqk: 1087 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1088 rtw8821c_do_iqk(rtwdev); 1089 } 1090 1091 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 1092 { 1093 struct rtw_efuse *efuse = &rtwdev->efuse; 1094 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1095 1096 if (efuse->power_track_type != 0) 1097 return; 1098 1099 if (!dm_info->pwr_trk_triggered) { 1100 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1101 GENMASK(17, 16), 0x03); 1102 dm_info->pwr_trk_triggered = true; 1103 return; 1104 } 1105 1106 rtw8821c_phy_pwrtrack(rtwdev); 1107 dm_info->pwr_trk_triggered = false; 1108 } 1109 1110 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 1111 struct rtw_vif *vif, 1112 struct rtw_bfee *bfee, bool enable) 1113 { 1114 if (enable) 1115 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1116 else 1117 rtw_bf_remove_bfee_su(rtwdev, bfee); 1118 } 1119 1120 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1121 struct rtw_vif *vif, 1122 struct rtw_bfee *bfee, bool enable) 1123 { 1124 if (enable) 1125 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1126 else 1127 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1128 } 1129 1130 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1131 struct rtw_bfee *bfee, bool enable) 1132 { 1133 if (bfee->role == RTW_BFEE_SU) 1134 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1135 else if (bfee->role == RTW_BFEE_MU) 1136 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1137 else 1138 rtw_warn(rtwdev, "wrong bfee role\n"); 1139 } 1140 1141 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1142 { 1143 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1144 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1145 u8 cck_n_rx; 1146 1147 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1148 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1149 1150 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1151 return; 1152 1153 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1154 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1155 rtw_dbg(rtwdev, RTW_DBG_PHY, 1156 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1157 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1158 dm_info->cck_pd_default + new_lvl * 2, 1159 pd[new_lvl], dm_info->cck_fa_avg); 1160 1161 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1162 1163 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1164 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1165 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1166 dm_info->cck_pd_default + new_lvl * 2); 1167 } 1168 1169 static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev, 1170 struct rtw_tx_pkt_info *pkt_info, 1171 u8 *txdesc) 1172 { 1173 fill_txdesc_checksum_common(txdesc, 16); 1174 } 1175 1176 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1177 {0x0086, 1178 RTW_PWR_CUT_ALL_MSK, 1179 RTW_PWR_INTF_SDIO_MSK, 1180 RTW_PWR_ADDR_SDIO, 1181 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1182 {0x0086, 1183 RTW_PWR_CUT_ALL_MSK, 1184 RTW_PWR_INTF_SDIO_MSK, 1185 RTW_PWR_ADDR_SDIO, 1186 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1187 {0x004A, 1188 RTW_PWR_CUT_ALL_MSK, 1189 RTW_PWR_INTF_USB_MSK, 1190 RTW_PWR_ADDR_MAC, 1191 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1192 {0x0005, 1193 RTW_PWR_CUT_ALL_MSK, 1194 RTW_PWR_INTF_ALL_MSK, 1195 RTW_PWR_ADDR_MAC, 1196 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1197 {0x0300, 1198 RTW_PWR_CUT_ALL_MSK, 1199 RTW_PWR_INTF_PCI_MSK, 1200 RTW_PWR_ADDR_MAC, 1201 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1202 {0x0301, 1203 RTW_PWR_CUT_ALL_MSK, 1204 RTW_PWR_INTF_PCI_MSK, 1205 RTW_PWR_ADDR_MAC, 1206 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1207 {0xFFFF, 1208 RTW_PWR_CUT_ALL_MSK, 1209 RTW_PWR_INTF_ALL_MSK, 1210 0, 1211 RTW_PWR_CMD_END, 0, 0}, 1212 }; 1213 1214 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1215 {0x0020, 1216 RTW_PWR_CUT_ALL_MSK, 1217 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1218 RTW_PWR_ADDR_MAC, 1219 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1220 {0x0001, 1221 RTW_PWR_CUT_ALL_MSK, 1222 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1223 RTW_PWR_ADDR_MAC, 1224 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1225 {0x0000, 1226 RTW_PWR_CUT_ALL_MSK, 1227 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1228 RTW_PWR_ADDR_MAC, 1229 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1230 {0x0005, 1231 RTW_PWR_CUT_ALL_MSK, 1232 RTW_PWR_INTF_ALL_MSK, 1233 RTW_PWR_ADDR_MAC, 1234 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1235 {0x0075, 1236 RTW_PWR_CUT_ALL_MSK, 1237 RTW_PWR_INTF_PCI_MSK, 1238 RTW_PWR_ADDR_MAC, 1239 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1240 {0x0006, 1241 RTW_PWR_CUT_ALL_MSK, 1242 RTW_PWR_INTF_ALL_MSK, 1243 RTW_PWR_ADDR_MAC, 1244 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1245 {0x0075, 1246 RTW_PWR_CUT_ALL_MSK, 1247 RTW_PWR_INTF_PCI_MSK, 1248 RTW_PWR_ADDR_MAC, 1249 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1250 {0x0006, 1251 RTW_PWR_CUT_ALL_MSK, 1252 RTW_PWR_INTF_ALL_MSK, 1253 RTW_PWR_ADDR_MAC, 1254 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1255 {0x0005, 1256 RTW_PWR_CUT_ALL_MSK, 1257 RTW_PWR_INTF_ALL_MSK, 1258 RTW_PWR_ADDR_MAC, 1259 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1260 {0x0005, 1261 RTW_PWR_CUT_ALL_MSK, 1262 RTW_PWR_INTF_ALL_MSK, 1263 RTW_PWR_ADDR_MAC, 1264 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1265 {0x10C3, 1266 RTW_PWR_CUT_ALL_MSK, 1267 RTW_PWR_INTF_USB_MSK, 1268 RTW_PWR_ADDR_MAC, 1269 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1270 {0x0005, 1271 RTW_PWR_CUT_ALL_MSK, 1272 RTW_PWR_INTF_ALL_MSK, 1273 RTW_PWR_ADDR_MAC, 1274 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1275 {0x0005, 1276 RTW_PWR_CUT_ALL_MSK, 1277 RTW_PWR_INTF_ALL_MSK, 1278 RTW_PWR_ADDR_MAC, 1279 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1280 {0x0020, 1281 RTW_PWR_CUT_ALL_MSK, 1282 RTW_PWR_INTF_ALL_MSK, 1283 RTW_PWR_ADDR_MAC, 1284 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1285 {0x0074, 1286 RTW_PWR_CUT_ALL_MSK, 1287 RTW_PWR_INTF_PCI_MSK, 1288 RTW_PWR_ADDR_MAC, 1289 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1290 {0x0022, 1291 RTW_PWR_CUT_ALL_MSK, 1292 RTW_PWR_INTF_PCI_MSK, 1293 RTW_PWR_ADDR_MAC, 1294 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1295 {0x0062, 1296 RTW_PWR_CUT_ALL_MSK, 1297 RTW_PWR_INTF_PCI_MSK, 1298 RTW_PWR_ADDR_MAC, 1299 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1300 (BIT(7) | BIT(6) | BIT(5))}, 1301 {0x0061, 1302 RTW_PWR_CUT_ALL_MSK, 1303 RTW_PWR_INTF_PCI_MSK, 1304 RTW_PWR_ADDR_MAC, 1305 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1306 {0x007C, 1307 RTW_PWR_CUT_ALL_MSK, 1308 RTW_PWR_INTF_ALL_MSK, 1309 RTW_PWR_ADDR_MAC, 1310 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1311 {0xFFFF, 1312 RTW_PWR_CUT_ALL_MSK, 1313 RTW_PWR_INTF_ALL_MSK, 1314 0, 1315 RTW_PWR_CMD_END, 0, 0}, 1316 }; 1317 1318 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1319 {0x0093, 1320 RTW_PWR_CUT_ALL_MSK, 1321 RTW_PWR_INTF_ALL_MSK, 1322 RTW_PWR_ADDR_MAC, 1323 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1324 {0x001F, 1325 RTW_PWR_CUT_ALL_MSK, 1326 RTW_PWR_INTF_ALL_MSK, 1327 RTW_PWR_ADDR_MAC, 1328 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1329 {0x0049, 1330 RTW_PWR_CUT_ALL_MSK, 1331 RTW_PWR_INTF_ALL_MSK, 1332 RTW_PWR_ADDR_MAC, 1333 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1334 {0x0006, 1335 RTW_PWR_CUT_ALL_MSK, 1336 RTW_PWR_INTF_ALL_MSK, 1337 RTW_PWR_ADDR_MAC, 1338 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1339 {0x0002, 1340 RTW_PWR_CUT_ALL_MSK, 1341 RTW_PWR_INTF_ALL_MSK, 1342 RTW_PWR_ADDR_MAC, 1343 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1344 {0x10C3, 1345 RTW_PWR_CUT_ALL_MSK, 1346 RTW_PWR_INTF_USB_MSK, 1347 RTW_PWR_ADDR_MAC, 1348 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1349 {0x0005, 1350 RTW_PWR_CUT_ALL_MSK, 1351 RTW_PWR_INTF_ALL_MSK, 1352 RTW_PWR_ADDR_MAC, 1353 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1354 {0x0005, 1355 RTW_PWR_CUT_ALL_MSK, 1356 RTW_PWR_INTF_ALL_MSK, 1357 RTW_PWR_ADDR_MAC, 1358 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1359 {0x0020, 1360 RTW_PWR_CUT_ALL_MSK, 1361 RTW_PWR_INTF_ALL_MSK, 1362 RTW_PWR_ADDR_MAC, 1363 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1364 {0x0000, 1365 RTW_PWR_CUT_ALL_MSK, 1366 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1367 RTW_PWR_ADDR_MAC, 1368 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1369 {0xFFFF, 1370 RTW_PWR_CUT_ALL_MSK, 1371 RTW_PWR_INTF_ALL_MSK, 1372 0, 1373 RTW_PWR_CMD_END, 0, 0}, 1374 }; 1375 1376 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1377 {0x0007, 1378 RTW_PWR_CUT_ALL_MSK, 1379 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1380 RTW_PWR_ADDR_MAC, 1381 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1382 {0x0067, 1383 RTW_PWR_CUT_ALL_MSK, 1384 RTW_PWR_INTF_ALL_MSK, 1385 RTW_PWR_ADDR_MAC, 1386 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1387 {0x0005, 1388 RTW_PWR_CUT_ALL_MSK, 1389 RTW_PWR_INTF_PCI_MSK, 1390 RTW_PWR_ADDR_MAC, 1391 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1392 {0x004A, 1393 RTW_PWR_CUT_ALL_MSK, 1394 RTW_PWR_INTF_USB_MSK, 1395 RTW_PWR_ADDR_MAC, 1396 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1397 {0x0067, 1398 RTW_PWR_CUT_ALL_MSK, 1399 RTW_PWR_INTF_SDIO_MSK, 1400 RTW_PWR_ADDR_MAC, 1401 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1402 {0x0067, 1403 RTW_PWR_CUT_ALL_MSK, 1404 RTW_PWR_INTF_SDIO_MSK, 1405 RTW_PWR_ADDR_MAC, 1406 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1407 {0x004F, 1408 RTW_PWR_CUT_ALL_MSK, 1409 RTW_PWR_INTF_SDIO_MSK, 1410 RTW_PWR_ADDR_MAC, 1411 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1412 {0x0067, 1413 RTW_PWR_CUT_ALL_MSK, 1414 RTW_PWR_INTF_SDIO_MSK, 1415 RTW_PWR_ADDR_MAC, 1416 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1417 {0x0046, 1418 RTW_PWR_CUT_ALL_MSK, 1419 RTW_PWR_INTF_SDIO_MSK, 1420 RTW_PWR_ADDR_MAC, 1421 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1422 {0x0067, 1423 RTW_PWR_CUT_ALL_MSK, 1424 RTW_PWR_INTF_SDIO_MSK, 1425 RTW_PWR_ADDR_MAC, 1426 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1427 {0x0046, 1428 RTW_PWR_CUT_ALL_MSK, 1429 RTW_PWR_INTF_SDIO_MSK, 1430 RTW_PWR_ADDR_MAC, 1431 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1432 {0x0062, 1433 RTW_PWR_CUT_ALL_MSK, 1434 RTW_PWR_INTF_SDIO_MSK, 1435 RTW_PWR_ADDR_MAC, 1436 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1437 {0x0081, 1438 RTW_PWR_CUT_ALL_MSK, 1439 RTW_PWR_INTF_ALL_MSK, 1440 RTW_PWR_ADDR_MAC, 1441 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1442 {0x0005, 1443 RTW_PWR_CUT_ALL_MSK, 1444 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1445 RTW_PWR_ADDR_MAC, 1446 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1447 {0x0086, 1448 RTW_PWR_CUT_ALL_MSK, 1449 RTW_PWR_INTF_SDIO_MSK, 1450 RTW_PWR_ADDR_SDIO, 1451 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1452 {0x0086, 1453 RTW_PWR_CUT_ALL_MSK, 1454 RTW_PWR_INTF_SDIO_MSK, 1455 RTW_PWR_ADDR_SDIO, 1456 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1457 {0x0090, 1458 RTW_PWR_CUT_ALL_MSK, 1459 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1460 RTW_PWR_ADDR_MAC, 1461 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1462 {0x0044, 1463 RTW_PWR_CUT_ALL_MSK, 1464 RTW_PWR_INTF_SDIO_MSK, 1465 RTW_PWR_ADDR_SDIO, 1466 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1467 {0x0040, 1468 RTW_PWR_CUT_ALL_MSK, 1469 RTW_PWR_INTF_SDIO_MSK, 1470 RTW_PWR_ADDR_SDIO, 1471 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1472 {0x0041, 1473 RTW_PWR_CUT_ALL_MSK, 1474 RTW_PWR_INTF_SDIO_MSK, 1475 RTW_PWR_ADDR_SDIO, 1476 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1477 {0x0042, 1478 RTW_PWR_CUT_ALL_MSK, 1479 RTW_PWR_INTF_SDIO_MSK, 1480 RTW_PWR_ADDR_SDIO, 1481 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1482 {0xFFFF, 1483 RTW_PWR_CUT_ALL_MSK, 1484 RTW_PWR_INTF_ALL_MSK, 1485 0, 1486 RTW_PWR_CMD_END, 0, 0}, 1487 }; 1488 1489 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1490 trans_carddis_to_cardemu_8821c, 1491 trans_cardemu_to_act_8821c, 1492 NULL 1493 }; 1494 1495 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1496 trans_act_to_cardemu_8821c, 1497 trans_cardemu_to_carddis_8821c, 1498 NULL 1499 }; 1500 1501 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1502 {0xFFFF, 0x00, 1503 RTW_IP_SEL_PHY, 1504 RTW_INTF_PHY_CUT_ALL, 1505 RTW_INTF_PHY_PLATFORM_ALL}, 1506 }; 1507 1508 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1509 {0xFFFF, 0x0000, 1510 RTW_IP_SEL_PHY, 1511 RTW_INTF_PHY_CUT_ALL, 1512 RTW_INTF_PHY_PLATFORM_ALL}, 1513 }; 1514 1515 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1516 {0x0009, 0x6380, 1517 RTW_IP_SEL_PHY, 1518 RTW_INTF_PHY_CUT_ALL, 1519 RTW_INTF_PHY_PLATFORM_ALL}, 1520 {0xFFFF, 0x0000, 1521 RTW_IP_SEL_PHY, 1522 RTW_INTF_PHY_CUT_ALL, 1523 RTW_INTF_PHY_PLATFORM_ALL}, 1524 }; 1525 1526 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1527 {0xFFFF, 0x0000, 1528 RTW_IP_SEL_PHY, 1529 RTW_INTF_PHY_CUT_ALL, 1530 RTW_INTF_PHY_PLATFORM_ALL}, 1531 }; 1532 1533 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1534 .usb2_para = usb2_param_8821c, 1535 .usb3_para = usb3_param_8821c, 1536 .gen1_para = pcie_gen1_param_8821c, 1537 .gen2_para = pcie_gen2_param_8821c, 1538 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1539 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1540 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1541 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1542 }; 1543 1544 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1545 [0] = RTW_DEF_RFE(8821c, 0, 0), 1546 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1547 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1548 [6] = RTW_DEF_RFE(8821c, 0, 0), 1549 [34] = RTW_DEF_RFE(8821c, 0, 0), 1550 }; 1551 1552 static struct rtw_hw_reg rtw8821c_dig[] = { 1553 [0] = { .addr = 0xc50, .mask = 0x7f }, 1554 }; 1555 1556 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1557 .ctrl = LTECOEX_ACCESS_CTRL, 1558 .wdata = LTECOEX_WRITE_DATA, 1559 .rdata = LTECOEX_READ_DATA, 1560 }; 1561 1562 static struct rtw_page_table page_table_8821c[] = { 1563 /* not sure what [0] stands for */ 1564 {16, 16, 16, 14, 1}, 1565 {16, 16, 16, 14, 1}, 1566 {16, 16, 0, 0, 1}, 1567 {16, 16, 16, 0, 1}, 1568 {16, 16, 16, 14, 1}, 1569 }; 1570 1571 static struct rtw_rqpn rqpn_table_8821c[] = { 1572 /* not sure what [0] stands for */ 1573 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1574 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1575 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1576 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1577 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1578 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1579 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1580 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1581 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1582 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1583 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1584 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1585 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1586 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1587 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1588 }; 1589 1590 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1591 .prio[RTW_DMA_MAPPING_EXTRA] = { 1592 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1593 }, 1594 .prio[RTW_DMA_MAPPING_LOW] = { 1595 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1596 }, 1597 .prio[RTW_DMA_MAPPING_NORMAL] = { 1598 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1599 }, 1600 .prio[RTW_DMA_MAPPING_HIGH] = { 1601 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1602 }, 1603 .wsize = true, 1604 }; 1605 1606 static struct rtw_chip_ops rtw8821c_ops = { 1607 .phy_set_param = rtw8821c_phy_set_param, 1608 .read_efuse = rtw8821c_read_efuse, 1609 .query_rx_desc = rtw8821c_query_rx_desc, 1610 .set_channel = rtw8821c_set_channel, 1611 .mac_init = rtw8821c_mac_init, 1612 .read_rf = rtw_phy_read_rf, 1613 .write_rf = rtw_phy_write_rf_reg_sipi, 1614 .set_antenna = NULL, 1615 .set_tx_power_index = rtw8821c_set_tx_power_index, 1616 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1617 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1618 .phy_calibration = rtw8821c_phy_calibration, 1619 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1620 .pwr_track = rtw8821c_pwr_track, 1621 .config_bfee = rtw8821c_bf_config_bfee, 1622 .set_gid_table = rtw_bf_set_gid_table, 1623 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1624 .fill_txdesc_checksum = rtw8821c_fill_txdesc_checksum, 1625 1626 .coex_set_init = rtw8821c_coex_cfg_init, 1627 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1628 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1629 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1630 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1631 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1632 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1633 }; 1634 1635 /* rssi in percentage % (dbm = % - 100) */ 1636 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1637 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1638 1639 /* Shared-Antenna Coex Table */ 1640 static const struct coex_table_para table_sant_8821c[] = { 1641 {0x55555555, 0x55555555}, /* case-0 */ 1642 {0x55555555, 0x55555555}, 1643 {0x66555555, 0x66555555}, 1644 {0xaaaaaaaa, 0xaaaaaaaa}, 1645 {0x5a5a5a5a, 0x5a5a5a5a}, 1646 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1647 {0x6a5a5555, 0xaaaaaaaa}, 1648 {0x6a5a56aa, 0x6a5a56aa}, 1649 {0x6a5a5a5a, 0x6a5a5a5a}, 1650 {0x66555555, 0x5a5a5a5a}, 1651 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1652 {0x66555555, 0xaaaaaaaa}, 1653 {0x66555555, 0x6a5a5aaa}, 1654 {0x66555555, 0x6aaa6aaa}, 1655 {0x66555555, 0x6a5a5aaa}, 1656 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1657 {0xffff55ff, 0xfafafafa}, 1658 {0xffff55ff, 0x6afa5afa}, 1659 {0xaaffffaa, 0xfafafafa}, 1660 {0xaa5555aa, 0x5a5a5a5a}, 1661 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1662 {0xaa5555aa, 0xaaaaaaaa}, 1663 {0xffffffff, 0x55555555}, 1664 {0xffffffff, 0x5a5a5a5a}, 1665 {0xffffffff, 0x5a5a5a5a}, 1666 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1667 {0x55555555, 0x5a5a5a5a}, 1668 {0x55555555, 0xaaaaaaaa}, 1669 {0x66555555, 0x6a5a6a5a}, 1670 {0x66556655, 0x66556655}, 1671 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1672 {0xffffffff, 0x5aaa5aaa}, 1673 {0x56555555, 0x5a5a5aaa} 1674 }; 1675 1676 /* Non-Shared-Antenna Coex Table */ 1677 static const struct coex_table_para table_nsant_8821c[] = { 1678 {0xffffffff, 0xffffffff}, /* case-100 */ 1679 {0xffff55ff, 0xfafafafa}, 1680 {0x66555555, 0x66555555}, 1681 {0xaaaaaaaa, 0xaaaaaaaa}, 1682 {0x5a5a5a5a, 0x5a5a5a5a}, 1683 {0xffffffff, 0xffffffff}, /* case-105 */ 1684 {0x5afa5afa, 0x5afa5afa}, 1685 {0x55555555, 0xfafafafa}, 1686 {0x66555555, 0xfafafafa}, 1687 {0x66555555, 0x5a5a5a5a}, 1688 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1689 {0x66555555, 0xaaaaaaaa}, 1690 {0xffff55ff, 0xfafafafa}, 1691 {0xffff55ff, 0x5afa5afa}, 1692 {0xffff55ff, 0xaaaaaaaa}, 1693 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1694 {0xaaffffaa, 0x5afa5afa}, 1695 {0xaaffffaa, 0xaaaaaaaa}, 1696 {0xffffffff, 0xfafafafa}, 1697 {0xffff55ff, 0xfafafafa}, 1698 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1699 {0xffff55ff, 0x5afa5afa}, 1700 {0xffff55ff, 0x5afa5afa}, 1701 {0x55ff55ff, 0x55ff55ff} 1702 }; 1703 1704 /* Shared-Antenna TDMA */ 1705 static const struct coex_tdma_para tdma_sant_8821c[] = { 1706 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1707 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1708 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1709 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1710 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1711 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1712 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1713 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1714 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1715 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1716 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1717 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1718 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1719 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1720 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1721 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1722 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1723 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1724 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1725 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1726 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1727 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1728 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1729 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1730 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1731 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1732 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1733 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1734 }; 1735 1736 /* Non-Shared-Antenna TDMA */ 1737 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1738 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1739 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1740 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1741 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1742 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1743 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1744 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1745 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1746 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1747 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1748 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1749 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1750 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1751 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1752 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1753 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1754 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1755 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1756 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1757 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1758 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1759 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1760 }; 1761 1762 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1763 1764 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1765 static const struct coex_rf_para rf_para_tx_8821c[] = { 1766 {0, 0, false, 7}, /* for normal */ 1767 {0, 20, false, 7}, /* for WL-CPT */ 1768 {8, 17, true, 4}, 1769 {7, 18, true, 4}, 1770 {6, 19, true, 4}, 1771 {5, 20, true, 4} 1772 }; 1773 1774 static const struct coex_rf_para rf_para_rx_8821c[] = { 1775 {0, 0, false, 7}, /* for normal */ 1776 {0, 20, false, 7}, /* for WL-CPT */ 1777 {3, 24, true, 5}, 1778 {2, 26, true, 5}, 1779 {1, 27, true, 5}, 1780 {0, 28, true, 5} 1781 }; 1782 1783 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1784 1785 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1786 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1787 11, 11, 12, 12, 12, 12, 12}, 1788 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1789 11, 12, 12, 12, 12, 12, 12, 12}, 1790 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1791 11, 12, 12, 12, 12, 12, 12}, 1792 }; 1793 1794 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1795 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1796 12, 12, 12, 12, 12, 12, 12}, 1797 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1798 12, 12, 12, 12, 12, 12, 12, 12}, 1799 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1800 11, 12, 12, 12, 12, 12, 12, 12}, 1801 }; 1802 1803 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1804 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1805 11, 11, 12, 12, 12, 12, 12}, 1806 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1807 11, 12, 12, 12, 12, 12, 12, 12}, 1808 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1809 11, 12, 12, 12, 12, 12, 12}, 1810 }; 1811 1812 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1813 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1814 12, 12, 12, 12, 12, 12, 12}, 1815 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1816 12, 12, 12, 12, 12, 12, 12, 12}, 1817 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1818 11, 12, 12, 12, 12, 12, 12, 12}, 1819 }; 1820 1821 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1822 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1823 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1824 }; 1825 1826 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1827 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1828 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1829 }; 1830 1831 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1832 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1833 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1834 }; 1835 1836 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1837 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1838 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1839 }; 1840 1841 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1842 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1843 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1844 }; 1845 1846 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1847 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1848 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1849 }; 1850 1851 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1852 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1853 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1854 }; 1855 1856 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1857 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1858 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1859 }; 1860 1861 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1862 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1863 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1864 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1865 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1866 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1867 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1868 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1869 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1870 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1871 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1872 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1873 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1874 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1875 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1876 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1877 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1878 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1879 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1880 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1881 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1882 }; 1883 1884 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1885 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1886 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1887 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1888 {0, 0, RTW_REG_DOMAIN_NL}, 1889 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1890 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1891 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1892 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1893 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1894 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1895 {0, 0, RTW_REG_DOMAIN_NL}, 1896 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1897 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1898 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1899 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1900 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1901 {0, 0, RTW_REG_DOMAIN_NL}, 1902 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1903 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1904 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1905 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1906 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1907 }; 1908 1909 const struct rtw_chip_info rtw8821c_hw_spec = { 1910 .ops = &rtw8821c_ops, 1911 .id = RTW_CHIP_TYPE_8821C, 1912 .fw_name = "rtw88/rtw8821c_fw.bin", 1913 .wlan_cpu = RTW_WCPU_11AC, 1914 .tx_pkt_desc_sz = 48, 1915 .tx_buf_desc_sz = 16, 1916 .rx_pkt_desc_sz = 24, 1917 .rx_buf_desc_sz = 8, 1918 .phy_efuse_size = 512, 1919 .log_efuse_size = 512, 1920 .ptct_efuse_size = 96, 1921 .txff_size = 65536, 1922 .rxff_size = 16384, 1923 .txgi_factor = 1, 1924 .is_pwr_by_rate_dec = true, 1925 .max_power_index = 0x3f, 1926 .csi_buf_pg_num = 0, 1927 .band = RTW_BAND_2G | RTW_BAND_5G, 1928 .page_size = TX_PAGE_SIZE, 1929 .dig_min = 0x1c, 1930 .ht_supported = true, 1931 .vht_supported = true, 1932 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1933 .sys_func_en = 0xD8, 1934 .pwr_on_seq = card_enable_flow_8821c, 1935 .pwr_off_seq = card_disable_flow_8821c, 1936 .page_table = page_table_8821c, 1937 .rqpn_table = rqpn_table_8821c, 1938 .prioq_addrs = &prioq_addrs_8821c, 1939 .intf_table = &phy_para_table_8821c, 1940 .dig = rtw8821c_dig, 1941 .rf_base_addr = {0x2800, 0x2c00}, 1942 .rf_sipi_addr = {0xc90, 0xe90}, 1943 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1944 .mac_tbl = &rtw8821c_mac_tbl, 1945 .agc_tbl = &rtw8821c_agc_tbl, 1946 .bb_tbl = &rtw8821c_bb_tbl, 1947 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1948 .rfe_defs = rtw8821c_rfe_defs, 1949 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1950 .rx_ldpc = false, 1951 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1952 .iqk_threshold = 8, 1953 .bfer_su_max_num = 2, 1954 .bfer_mu_max_num = 1, 1955 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 1956 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 1957 1958 .coex_para_ver = 0x19092746, 1959 .bt_desired_ver = 0x46, 1960 .scbd_support = true, 1961 .new_scbd10_def = false, 1962 .ble_hid_profile_support = false, 1963 .wl_mimo_ps_support = false, 1964 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1965 .bt_rssi_type = COEX_BTRSSI_RATIO, 1966 .ant_isolation = 15, 1967 .rssi_tolerance = 2, 1968 .wl_rssi_step = wl_rssi_step_8821c, 1969 .bt_rssi_step = bt_rssi_step_8821c, 1970 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 1971 .table_sant = table_sant_8821c, 1972 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 1973 .table_nsant = table_nsant_8821c, 1974 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 1975 .tdma_sant = tdma_sant_8821c, 1976 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 1977 .tdma_nsant = tdma_nsant_8821c, 1978 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 1979 .wl_rf_para_tx = rf_para_tx_8821c, 1980 .wl_rf_para_rx = rf_para_rx_8821c, 1981 .bt_afh_span_bw20 = 0x24, 1982 .bt_afh_span_bw40 = 0x36, 1983 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 1984 .afh_5g = afh_5g_8821c, 1985 1986 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 1987 .coex_info_hw_regs = coex_info_hw_regs_8821c, 1988 }; 1989 EXPORT_SYMBOL(rtw8821c_hw_spec); 1990 1991 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 1992 1993 MODULE_AUTHOR("Realtek Corporation"); 1994 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 1995 MODULE_LICENSE("Dual BSD/GPL"); 1996