1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 18 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; 19 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, 20 -20, -24, -28, -31, -34, -37, -40, -44}; 21 22 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 23 struct rtw8821c_efuse *map) 24 { 25 ether_addr_copy(efuse->addr, map->e.mac_addr); 26 } 27 28 enum rtw8821ce_rf_set { 29 SWITCH_TO_BTG, 30 SWITCH_TO_WLG, 31 SWITCH_TO_WLA, 32 SWITCH_TO_BT, 33 }; 34 35 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 36 { 37 struct rtw_efuse *efuse = &rtwdev->efuse; 38 struct rtw8821c_efuse *map; 39 int i; 40 41 map = (struct rtw8821c_efuse *)log_map; 42 43 efuse->rfe_option = map->rfe_option; 44 efuse->rf_board_option = map->rf_board_option; 45 efuse->crystal_cap = map->xtal_k; 46 efuse->pa_type_2g = map->pa_type; 47 efuse->pa_type_5g = map->pa_type; 48 efuse->lna_type_2g = map->lna_type_2g[0]; 49 efuse->lna_type_5g = map->lna_type_5g[0]; 50 efuse->channel_plan = map->channel_plan; 51 efuse->country_code[0] = map->country_code[0]; 52 efuse->country_code[1] = map->country_code[1]; 53 efuse->bt_setting = map->rf_bt_setting; 54 efuse->regd = map->rf_board_option & 0x7; 55 efuse->thermal_meter[0] = map->thermal_meter; 56 efuse->thermal_meter_k = map->thermal_meter; 57 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 58 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 59 60 for (i = 0; i < 4; i++) 61 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 62 63 switch (rtw_hci_type(rtwdev)) { 64 case RTW_HCI_TYPE_PCIE: 65 rtw8821ce_efuse_parsing(efuse, map); 66 break; 67 default: 68 /* unsupported now */ 69 return -ENOTSUPP; 70 } 71 72 return 0; 73 } 74 75 static const u32 rtw8821c_txscale_tbl[] = { 76 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 77 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 78 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 79 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 80 }; 81 82 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 83 { 84 u8 i = 0; 85 u32 swing, table_value; 86 87 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 88 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 89 table_value = rtw8821c_txscale_tbl[i]; 90 if (swing == table_value) 91 break; 92 } 93 94 return i; 95 } 96 97 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 98 { 99 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 100 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 101 102 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 103 dm_info->default_ofdm_index = 24; 104 else 105 dm_info->default_ofdm_index = swing_idx; 106 107 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 108 dm_info->delta_power_index[RF_PATH_A] = 0; 109 dm_info->delta_power_index_last[RF_PATH_A] = 0; 110 dm_info->pwr_trk_triggered = false; 111 dm_info->pwr_trk_init_trigger = true; 112 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 113 } 114 115 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 116 { 117 rtw_bf_phy_init(rtwdev); 118 /* Grouping bitmap parameters */ 119 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 120 } 121 122 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 123 { 124 u8 crystal_cap, val; 125 126 /* power on BB/RF domain */ 127 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 128 val |= BIT_FEN_PCIEA; 129 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 130 131 /* toggle BB reset */ 132 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 133 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 134 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 135 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 136 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 137 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 138 139 rtw_write8(rtwdev, REG_RF_CTRL, 140 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 141 usleep_range(10, 11); 142 rtw_write8(rtwdev, REG_WLRF1 + 3, 143 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 144 usleep_range(10, 11); 145 146 /* pre init before header files config */ 147 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 148 149 rtw_phy_load_tables(rtwdev); 150 151 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 152 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 153 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 154 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 155 156 /* post init after header files config */ 157 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 158 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 159 rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 160 rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 161 162 rtw_phy_init(rtwdev); 163 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 164 165 rtw8821c_pwrtrack_init(rtwdev); 166 167 rtw8821c_phy_bf_init(rtwdev); 168 } 169 170 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 171 { 172 u32 value32; 173 u16 pre_txcnt; 174 175 /* protocol configuration */ 176 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 177 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 178 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 179 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 180 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 181 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 182 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 183 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 184 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 185 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 186 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 187 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 188 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 189 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 190 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 191 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 192 193 /* EDCA configuration */ 194 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 195 rtw_write16(rtwdev, REG_TXPAUSE, 0); 196 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 197 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 198 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 199 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 200 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 201 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 202 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 203 204 /* Set beacon cotnrol - enable TSF and other related functions */ 205 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 206 207 /* Set send beacon related registers */ 208 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 209 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 210 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 211 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 212 213 /* WMAC configuration */ 214 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 215 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 216 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 217 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 218 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 219 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 220 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 221 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 222 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6)); 223 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 224 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 225 226 return 0; 227 } 228 229 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 230 { 231 u8 ldo_pwr; 232 233 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 234 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 235 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 236 } 237 238 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) 239 { 240 u32 reg; 241 242 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST); 243 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN); 244 245 reg = rtw_read32(rtwdev, REG_RFECTL); 246 switch (rf_set) { 247 case SWITCH_TO_BTG: 248 reg |= B_BTG_SWITCH; 249 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH | 250 B_WLA_SWITCH); 251 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); 252 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); 253 break; 254 case SWITCH_TO_WLG: 255 reg |= B_WL_SWITCH | B_WLG_SWITCH; 256 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH); 257 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); 258 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); 259 break; 260 case SWITCH_TO_WLA: 261 reg |= B_WL_SWITCH | B_WLA_SWITCH; 262 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH); 263 break; 264 case SWITCH_TO_BT: 265 default: 266 break; 267 } 268 269 rtw_write32(rtwdev, REG_RFECTL, reg); 270 } 271 272 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 273 { 274 u32 rf_reg18; 275 276 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 277 278 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 279 RF18_BW_MASK); 280 281 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 282 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 283 284 if (channel >= 100 && channel <= 140) 285 rf_reg18 |= RF18_RFSI_GE; 286 else if (channel > 140) 287 rf_reg18 |= RF18_RFSI_GT; 288 289 switch (bw) { 290 case RTW_CHANNEL_WIDTH_5: 291 case RTW_CHANNEL_WIDTH_10: 292 case RTW_CHANNEL_WIDTH_20: 293 default: 294 rf_reg18 |= RF18_BW_20M; 295 break; 296 case RTW_CHANNEL_WIDTH_40: 297 rf_reg18 |= RF18_BW_40M; 298 break; 299 case RTW_CHANNEL_WIDTH_80: 300 rf_reg18 |= RF18_BW_80M; 301 break; 302 } 303 304 if (channel <= 14) { 305 if (rtwdev->efuse.rfe_option == 0) 306 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG); 307 else if (rtwdev->efuse.rfe_option == 2) 308 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG); 309 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 310 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 311 } else { 312 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA); 313 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 314 } 315 316 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 317 318 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 319 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 320 } 321 322 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 323 { 324 if (bw == RTW_CHANNEL_WIDTH_40) { 325 /* RX DFIR for BW40 */ 326 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 327 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 328 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 329 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 330 } else if (bw == RTW_CHANNEL_WIDTH_80) { 331 /* RX DFIR for BW80 */ 332 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 333 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 334 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 335 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 336 } else { 337 /* RX DFIR for BW20, BW10 and BW5 */ 338 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 339 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 340 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 341 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 342 } 343 } 344 345 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 346 u8 primary_ch_idx) 347 { 348 u32 val32; 349 350 if (channel <= 14) { 351 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 352 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 353 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 354 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 355 356 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 357 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 358 if (channel == 14) { 359 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 360 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 361 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 362 } else { 363 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 364 rtwdev->chip->ch_param[0]); 365 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 366 rtwdev->chip->ch_param[1] & MASKLWORD); 367 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 368 rtwdev->chip->ch_param[2]); 369 } 370 } else if (channel > 35) { 371 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 372 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 373 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 374 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 375 376 if (channel >= 36 && channel <= 64) 377 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 378 else if (channel >= 100 && channel <= 144) 379 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 380 else if (channel >= 149) 381 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 382 383 if (channel >= 36 && channel <= 48) 384 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 385 else if (channel >= 52 && channel <= 64) 386 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 387 else if (channel >= 100 && channel <= 116) 388 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 389 else if (channel >= 118 && channel <= 177) 390 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 391 } 392 393 switch (bw) { 394 case RTW_CHANNEL_WIDTH_20: 395 default: 396 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 397 val32 &= 0xffcffc00; 398 val32 |= 0x10010000; 399 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 400 401 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 402 break; 403 case RTW_CHANNEL_WIDTH_40: 404 if (primary_ch_idx == 1) 405 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 406 else 407 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 408 409 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 410 val32 &= 0xff3ff300; 411 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 412 RTW_CHANNEL_WIDTH_40; 413 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 414 415 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 416 break; 417 case RTW_CHANNEL_WIDTH_80: 418 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 419 val32 &= 0xfcffcf00; 420 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 421 RTW_CHANNEL_WIDTH_80; 422 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 423 424 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 425 break; 426 case RTW_CHANNEL_WIDTH_5: 427 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 428 val32 &= 0xefcefc00; 429 val32 |= 0x200240; 430 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 431 432 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 433 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 434 break; 435 case RTW_CHANNEL_WIDTH_10: 436 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 437 val32 &= 0xefcefc00; 438 val32 |= 0x300380; 439 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 440 441 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 442 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 443 break; 444 } 445 } 446 447 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 448 { 449 struct rtw_efuse efuse = rtwdev->efuse; 450 u8 tx_bb_swing; 451 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 452 453 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 454 efuse.tx_bb_swing_setting_5g; 455 if (tx_bb_swing > 9) 456 tx_bb_swing = 0; 457 458 return swing2setting[(tx_bb_swing / 3)]; 459 } 460 461 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 462 u8 bw, u8 primary_ch_idx) 463 { 464 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 465 rtw8821c_get_bb_swing(rtwdev, channel)); 466 rtw8821c_pwrtrack_init(rtwdev); 467 } 468 469 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 470 u8 primary_chan_idx) 471 { 472 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 473 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 474 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 475 rtw8821c_set_channel_rf(rtwdev, channel, bw); 476 rtw8821c_set_channel_rxdfir(rtwdev, bw); 477 } 478 479 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 480 { 481 struct rtw_efuse *efuse = &rtwdev->efuse; 482 const s8 *lna_gain_table; 483 int lna_gain_table_size; 484 s8 rx_pwr_all = 0; 485 s8 lna_gain = 0; 486 487 if (efuse->rfe_option == 0) { 488 lna_gain_table = lna_gain_table_0; 489 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0); 490 } else { 491 lna_gain_table = lna_gain_table_1; 492 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1); 493 } 494 495 if (lna_idx >= lna_gain_table_size) { 496 rtw_info(rtwdev, "incorrect lna index (%d)\n", lna_idx); 497 return -120; 498 } 499 500 lna_gain = lna_gain_table[lna_idx]; 501 rx_pwr_all = lna_gain - 2 * vga_idx; 502 503 return rx_pwr_all; 504 } 505 506 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 507 struct rtw_rx_pkt_stat *pkt_stat) 508 { 509 s8 rx_power; 510 u8 lna_idx = 0; 511 u8 vga_idx = 0; 512 513 vga_idx = GET_PHY_STAT_P0_VGA(phy_status); 514 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) | 515 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status)); 516 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 517 518 pkt_stat->rx_power[RF_PATH_A] = rx_power; 519 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 520 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 521 pkt_stat->signal_power = rx_power; 522 } 523 524 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 525 struct rtw_rx_pkt_stat *pkt_stat) 526 { 527 u8 rxsc, bw; 528 s8 min_rx_power = -120; 529 530 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 531 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 532 else 533 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 534 535 if (rxsc >= 1 && rxsc <= 8) 536 bw = RTW_CHANNEL_WIDTH_20; 537 else if (rxsc >= 9 && rxsc <= 12) 538 bw = RTW_CHANNEL_WIDTH_40; 539 else if (rxsc >= 13) 540 bw = RTW_CHANNEL_WIDTH_80; 541 else 542 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 543 544 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 545 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 546 pkt_stat->bw = bw; 547 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 548 min_rx_power); 549 } 550 551 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 552 struct rtw_rx_pkt_stat *pkt_stat) 553 { 554 u8 page; 555 556 page = *phy_status & 0xf; 557 558 switch (page) { 559 case 0: 560 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 561 break; 562 case 1: 563 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 564 break; 565 default: 566 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 567 return; 568 } 569 } 570 571 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 572 struct rtw_rx_pkt_stat *pkt_stat, 573 struct ieee80211_rx_status *rx_status) 574 { 575 struct ieee80211_hdr *hdr; 576 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 577 u8 *phy_status = NULL; 578 579 memset(pkt_stat, 0, sizeof(*pkt_stat)); 580 581 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 582 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 583 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 584 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc); 585 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 586 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 587 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 588 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 589 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 590 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 591 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 592 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 593 594 /* drv_info_sz is in unit of 8-bytes */ 595 pkt_stat->drv_info_sz *= 8; 596 597 /* c2h cmd pkt's rx/phy status is not interested */ 598 if (pkt_stat->is_c2h) 599 return; 600 601 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 602 pkt_stat->drv_info_sz); 603 if (pkt_stat->phy_status) { 604 phy_status = rx_desc + desc_sz + pkt_stat->shift; 605 query_phy_status(rtwdev, phy_status, pkt_stat); 606 } 607 608 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 609 } 610 611 static void 612 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 613 { 614 struct rtw_hal *hal = &rtwdev->hal; 615 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 616 static u32 phy_pwr_idx; 617 u8 rate, rate_idx, pwr_index, shift; 618 int j; 619 620 for (j = 0; j < rtw_rate_size[rs]; j++) { 621 rate = rtw_rate_section[rs][j]; 622 pwr_index = hal->tx_pwr_tbl[path][rate]; 623 shift = rate & 0x3; 624 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 625 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 626 rate_idx = rate & 0xfc; 627 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 628 phy_pwr_idx); 629 phy_pwr_idx = 0; 630 } 631 } 632 } 633 634 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 635 { 636 struct rtw_hal *hal = &rtwdev->hal; 637 int rs, path; 638 639 for (path = 0; path < hal->rf_path_num; path++) { 640 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 641 if (rs == RTW_RATE_SECTION_HT_2S || 642 rs == RTW_RATE_SECTION_VHT_2S) 643 continue; 644 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 645 } 646 } 647 } 648 649 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 650 { 651 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 652 u32 cck_enable; 653 u32 cck_fa_cnt; 654 u32 ofdm_fa_cnt; 655 u32 crc32_cnt; 656 u32 cca32_cnt; 657 658 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 659 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 660 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 661 662 dm_info->cck_fa_cnt = cck_fa_cnt; 663 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 664 if (cck_enable) 665 dm_info->total_fa_cnt += cck_fa_cnt; 666 dm_info->total_fa_cnt = ofdm_fa_cnt; 667 668 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 669 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 670 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 671 672 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 673 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 674 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 675 676 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 677 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 678 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 679 680 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 681 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 682 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 683 684 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 685 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 686 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 687 if (cck_enable) { 688 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 689 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 690 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 691 } 692 693 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 694 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 695 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 696 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 697 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 698 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 699 } 700 701 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 702 { 703 static int do_iqk_cnt; 704 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 705 u32 rf_reg, iqk_fail_mask; 706 int counter; 707 bool reload; 708 709 if (rtw_is_assoc(rtwdev)) 710 para.segment_iqk = 1; 711 712 rtw_fw_do_iqk(rtwdev, ¶); 713 714 for (counter = 0; counter < 300; counter++) { 715 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 716 if (rf_reg == 0xabcde) 717 break; 718 msleep(20); 719 } 720 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 721 722 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 723 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 724 rtw_dbg(rtwdev, RTW_DBG_PHY, 725 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 726 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 727 } 728 729 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 730 { 731 rtw8821c_do_iqk(rtwdev); 732 } 733 734 /* for coex */ 735 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 736 { 737 /* enable TBTT nterrupt */ 738 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 739 740 /* BT report packet sample rate */ 741 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 742 743 /* enable BT counter statistics */ 744 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 745 746 /* enable PTA (3-wire function form BT side) */ 747 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 748 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 749 750 /* enable PTA (tx/rx signal form WiFi side) */ 751 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 752 /* wl tx signal to PTA not case EDCCA */ 753 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 754 /* GNT_BT=1 while select both */ 755 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 756 757 /* beacon queue always hi-pri */ 758 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 759 BCN_PRI_EN); 760 } 761 762 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 763 u8 pos_type) 764 { 765 struct rtw_coex *coex = &rtwdev->coex; 766 struct rtw_coex_dm *coex_dm = &coex->dm; 767 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 768 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 769 bool polarity_inverse; 770 u8 regval = 0; 771 772 if (switch_status == coex_dm->cur_switch_status) 773 return; 774 775 coex_dm->cur_switch_status = switch_status; 776 777 if (coex_rfe->ant_switch_diversity && 778 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 779 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 780 781 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 782 783 switch (ctrl_type) { 784 default: 785 case COEX_SWITCH_CTRL_BY_BBSW: 786 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 787 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 788 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 789 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 790 DPDT_CTRL_PIN); 791 792 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 793 if (coex_rfe->rfe_module_type != 0x4 && 794 coex_rfe->rfe_module_type != 0x2) 795 regval = 0x3; 796 else 797 regval = (!polarity_inverse ? 0x2 : 0x1); 798 } else if (pos_type == COEX_SWITCH_TO_WLG) { 799 regval = (!polarity_inverse ? 0x2 : 0x1); 800 } else { 801 regval = (!polarity_inverse ? 0x1 : 0x2); 802 } 803 804 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 805 regval); 806 break; 807 case COEX_SWITCH_CTRL_BY_PTA: 808 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 809 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 810 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 811 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 812 PTA_CTRL_PIN); 813 814 regval = (!polarity_inverse ? 0x2 : 0x1); 815 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 816 regval); 817 break; 818 case COEX_SWITCH_CTRL_BY_ANTDIV: 819 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 820 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 821 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 822 ANTDIC_CTRL_PIN); 823 break; 824 case COEX_SWITCH_CTRL_BY_MAC: 825 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 826 827 regval = (!polarity_inverse ? 0x0 : 0x1); 828 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 829 regval); 830 break; 831 case COEX_SWITCH_CTRL_BY_FW: 832 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 833 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 834 break; 835 case COEX_SWITCH_CTRL_BY_BT: 836 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 837 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 838 break; 839 } 840 841 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 842 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 843 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 844 } else { 845 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 846 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 847 } 848 } 849 850 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 851 {} 852 853 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 854 { 855 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 856 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 857 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 858 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 859 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 860 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 861 } 862 863 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 864 { 865 struct rtw_coex *coex = &rtwdev->coex; 866 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 867 struct rtw_efuse *efuse = &rtwdev->efuse; 868 869 coex_rfe->rfe_module_type = efuse->rfe_option; 870 coex_rfe->ant_switch_polarity = 0; 871 coex_rfe->ant_switch_exist = true; 872 coex_rfe->wlg_at_btg = false; 873 874 switch (coex_rfe->rfe_module_type) { 875 case 0: 876 case 8: 877 case 1: 878 case 9: /* 1-Ant, Main, WLG */ 879 default: /* 2-Ant, DPDT, WLG */ 880 break; 881 case 2: 882 case 10: /* 1-Ant, Main, BTG */ 883 case 7: 884 case 15: /* 2-Ant, DPDT, BTG */ 885 coex_rfe->wlg_at_btg = true; 886 break; 887 case 3: 888 case 11: /* 1-Ant, Aux, WLG */ 889 coex_rfe->ant_switch_polarity = 1; 890 break; 891 case 4: 892 case 12: /* 1-Ant, Aux, BTG */ 893 coex_rfe->wlg_at_btg = true; 894 coex_rfe->ant_switch_polarity = 1; 895 break; 896 case 5: 897 case 13: /* 2-Ant, no switch, WLG */ 898 case 6: 899 case 14: /* 2-Ant, no antenna switch, WLG */ 900 coex_rfe->ant_switch_exist = false; 901 break; 902 } 903 } 904 905 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 906 { 907 struct rtw_coex *coex = &rtwdev->coex; 908 struct rtw_coex_dm *coex_dm = &coex->dm; 909 struct rtw_efuse *efuse = &rtwdev->efuse; 910 bool share_ant = efuse->share_ant; 911 912 if (share_ant) 913 return; 914 915 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 916 return; 917 918 coex_dm->cur_wl_pwr_lvl = wl_pwr; 919 } 920 921 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 922 {} 923 924 static void 925 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 926 s8 pwr_idx_offset_lower, 927 s8 *txagc_idx, u8 *swing_idx) 928 { 929 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 930 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 931 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 932 u8 swing_lower_bound = 0; 933 u8 max_pwr_idx_offset = 0xf; 934 s8 agc_index = 0; 935 u8 swing_index = dm_info->default_ofdm_index; 936 937 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 938 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 939 940 if (delta_pwr_idx >= 0) { 941 if (delta_pwr_idx <= pwr_idx_offset) { 942 agc_index = delta_pwr_idx; 943 swing_index = dm_info->default_ofdm_index; 944 } else if (delta_pwr_idx > pwr_idx_offset) { 945 agc_index = pwr_idx_offset; 946 swing_index = dm_info->default_ofdm_index + 947 delta_pwr_idx - pwr_idx_offset; 948 swing_index = min_t(u8, swing_index, swing_upper_bound); 949 } 950 } else if (delta_pwr_idx < 0) { 951 if (delta_pwr_idx >= pwr_idx_offset_lower) { 952 agc_index = delta_pwr_idx; 953 swing_index = dm_info->default_ofdm_index; 954 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 955 if (dm_info->default_ofdm_index > 956 (pwr_idx_offset_lower - delta_pwr_idx)) 957 swing_index = dm_info->default_ofdm_index + 958 delta_pwr_idx - pwr_idx_offset_lower; 959 else 960 swing_index = swing_lower_bound; 961 962 agc_index = pwr_idx_offset_lower; 963 } 964 } 965 966 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 967 rtw_warn(rtwdev, "swing index overflow\n"); 968 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 969 } 970 971 *txagc_idx = agc_index; 972 *swing_idx = swing_index; 973 } 974 975 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 976 s8 pwr_idx_offset_lower) 977 { 978 s8 txagc_idx; 979 u8 swing_idx; 980 981 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 982 &txagc_idx, &swing_idx); 983 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 984 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 985 rtw8821c_txscale_tbl[swing_idx]); 986 } 987 988 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 989 { 990 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 991 u8 pwr_idx_offset, tx_pwr_idx; 992 s8 pwr_idx_offset_lower; 993 u8 channel = rtwdev->hal.current_channel; 994 u8 band_width = rtwdev->hal.current_band_width; 995 u8 regd = rtwdev->regd.txpwr_regd; 996 u8 tx_rate = dm_info->tx_rate; 997 u8 max_pwr_idx = rtwdev->chip->max_power_index; 998 999 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 1000 band_width, channel, regd); 1001 1002 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1003 1004 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1005 pwr_idx_offset_lower = 0 - tx_pwr_idx; 1006 1007 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 1008 } 1009 1010 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 1011 { 1012 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1013 struct rtw_swing_table swing_table; 1014 u8 thermal_value, delta; 1015 1016 rtw_phy_config_swing_table(rtwdev, &swing_table); 1017 1018 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1019 return; 1020 1021 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1022 1023 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1024 1025 if (dm_info->pwr_trk_init_trigger) 1026 dm_info->pwr_trk_init_trigger = false; 1027 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1028 RF_PATH_A)) 1029 goto iqk; 1030 1031 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1032 1033 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1034 1035 dm_info->delta_power_index[RF_PATH_A] = 1036 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 1037 RF_PATH_A, delta); 1038 if (dm_info->delta_power_index[RF_PATH_A] == 1039 dm_info->delta_power_index_last[RF_PATH_A]) 1040 goto iqk; 1041 else 1042 dm_info->delta_power_index_last[RF_PATH_A] = 1043 dm_info->delta_power_index[RF_PATH_A]; 1044 rtw8821c_pwrtrack_set(rtwdev); 1045 1046 iqk: 1047 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1048 rtw8821c_do_iqk(rtwdev); 1049 } 1050 1051 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 1052 { 1053 struct rtw_efuse *efuse = &rtwdev->efuse; 1054 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1055 1056 if (efuse->power_track_type != 0) 1057 return; 1058 1059 if (!dm_info->pwr_trk_triggered) { 1060 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1061 GENMASK(17, 16), 0x03); 1062 dm_info->pwr_trk_triggered = true; 1063 return; 1064 } 1065 1066 rtw8821c_phy_pwrtrack(rtwdev); 1067 dm_info->pwr_trk_triggered = false; 1068 } 1069 1070 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 1071 struct rtw_vif *vif, 1072 struct rtw_bfee *bfee, bool enable) 1073 { 1074 if (enable) 1075 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1076 else 1077 rtw_bf_remove_bfee_su(rtwdev, bfee); 1078 } 1079 1080 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1081 struct rtw_vif *vif, 1082 struct rtw_bfee *bfee, bool enable) 1083 { 1084 if (enable) 1085 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1086 else 1087 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1088 } 1089 1090 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1091 struct rtw_bfee *bfee, bool enable) 1092 { 1093 if (bfee->role == RTW_BFEE_SU) 1094 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1095 else if (bfee->role == RTW_BFEE_MU) 1096 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1097 else 1098 rtw_warn(rtwdev, "wrong bfee role\n"); 1099 } 1100 1101 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1102 { 1103 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1104 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1105 u8 cck_n_rx; 1106 1107 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1108 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1109 1110 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1111 return; 1112 1113 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1114 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1115 rtw_dbg(rtwdev, RTW_DBG_PHY, 1116 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1117 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1118 dm_info->cck_pd_default + new_lvl * 2, 1119 pd[new_lvl], dm_info->cck_fa_avg); 1120 1121 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1122 1123 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1124 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1125 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1126 dm_info->cck_pd_default + new_lvl * 2); 1127 } 1128 1129 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1130 {0x0086, 1131 RTW_PWR_CUT_ALL_MSK, 1132 RTW_PWR_INTF_SDIO_MSK, 1133 RTW_PWR_ADDR_SDIO, 1134 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1135 {0x0086, 1136 RTW_PWR_CUT_ALL_MSK, 1137 RTW_PWR_INTF_SDIO_MSK, 1138 RTW_PWR_ADDR_SDIO, 1139 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1140 {0x004A, 1141 RTW_PWR_CUT_ALL_MSK, 1142 RTW_PWR_INTF_USB_MSK, 1143 RTW_PWR_ADDR_MAC, 1144 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1145 {0x0005, 1146 RTW_PWR_CUT_ALL_MSK, 1147 RTW_PWR_INTF_ALL_MSK, 1148 RTW_PWR_ADDR_MAC, 1149 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1150 {0x0300, 1151 RTW_PWR_CUT_ALL_MSK, 1152 RTW_PWR_INTF_PCI_MSK, 1153 RTW_PWR_ADDR_MAC, 1154 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1155 {0x0301, 1156 RTW_PWR_CUT_ALL_MSK, 1157 RTW_PWR_INTF_PCI_MSK, 1158 RTW_PWR_ADDR_MAC, 1159 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1160 {0xFFFF, 1161 RTW_PWR_CUT_ALL_MSK, 1162 RTW_PWR_INTF_ALL_MSK, 1163 0, 1164 RTW_PWR_CMD_END, 0, 0}, 1165 }; 1166 1167 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1168 {0x0020, 1169 RTW_PWR_CUT_ALL_MSK, 1170 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1171 RTW_PWR_ADDR_MAC, 1172 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1173 {0x0001, 1174 RTW_PWR_CUT_ALL_MSK, 1175 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1176 RTW_PWR_ADDR_MAC, 1177 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1178 {0x0000, 1179 RTW_PWR_CUT_ALL_MSK, 1180 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1181 RTW_PWR_ADDR_MAC, 1182 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1183 {0x0005, 1184 RTW_PWR_CUT_ALL_MSK, 1185 RTW_PWR_INTF_ALL_MSK, 1186 RTW_PWR_ADDR_MAC, 1187 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1188 {0x0075, 1189 RTW_PWR_CUT_ALL_MSK, 1190 RTW_PWR_INTF_PCI_MSK, 1191 RTW_PWR_ADDR_MAC, 1192 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1193 {0x0006, 1194 RTW_PWR_CUT_ALL_MSK, 1195 RTW_PWR_INTF_ALL_MSK, 1196 RTW_PWR_ADDR_MAC, 1197 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1198 {0x0075, 1199 RTW_PWR_CUT_ALL_MSK, 1200 RTW_PWR_INTF_PCI_MSK, 1201 RTW_PWR_ADDR_MAC, 1202 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1203 {0x0006, 1204 RTW_PWR_CUT_ALL_MSK, 1205 RTW_PWR_INTF_ALL_MSK, 1206 RTW_PWR_ADDR_MAC, 1207 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1208 {0x0005, 1209 RTW_PWR_CUT_ALL_MSK, 1210 RTW_PWR_INTF_ALL_MSK, 1211 RTW_PWR_ADDR_MAC, 1212 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1213 {0x0005, 1214 RTW_PWR_CUT_ALL_MSK, 1215 RTW_PWR_INTF_ALL_MSK, 1216 RTW_PWR_ADDR_MAC, 1217 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1218 {0x10C3, 1219 RTW_PWR_CUT_ALL_MSK, 1220 RTW_PWR_INTF_USB_MSK, 1221 RTW_PWR_ADDR_MAC, 1222 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1223 {0x0005, 1224 RTW_PWR_CUT_ALL_MSK, 1225 RTW_PWR_INTF_ALL_MSK, 1226 RTW_PWR_ADDR_MAC, 1227 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1228 {0x0005, 1229 RTW_PWR_CUT_ALL_MSK, 1230 RTW_PWR_INTF_ALL_MSK, 1231 RTW_PWR_ADDR_MAC, 1232 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1233 {0x0020, 1234 RTW_PWR_CUT_ALL_MSK, 1235 RTW_PWR_INTF_ALL_MSK, 1236 RTW_PWR_ADDR_MAC, 1237 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1238 {0x0074, 1239 RTW_PWR_CUT_ALL_MSK, 1240 RTW_PWR_INTF_PCI_MSK, 1241 RTW_PWR_ADDR_MAC, 1242 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1243 {0x0022, 1244 RTW_PWR_CUT_ALL_MSK, 1245 RTW_PWR_INTF_PCI_MSK, 1246 RTW_PWR_ADDR_MAC, 1247 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1248 {0x0062, 1249 RTW_PWR_CUT_ALL_MSK, 1250 RTW_PWR_INTF_PCI_MSK, 1251 RTW_PWR_ADDR_MAC, 1252 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1253 (BIT(7) | BIT(6) | BIT(5))}, 1254 {0x0061, 1255 RTW_PWR_CUT_ALL_MSK, 1256 RTW_PWR_INTF_PCI_MSK, 1257 RTW_PWR_ADDR_MAC, 1258 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1259 {0x007C, 1260 RTW_PWR_CUT_ALL_MSK, 1261 RTW_PWR_INTF_ALL_MSK, 1262 RTW_PWR_ADDR_MAC, 1263 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1264 {0xFFFF, 1265 RTW_PWR_CUT_ALL_MSK, 1266 RTW_PWR_INTF_ALL_MSK, 1267 0, 1268 RTW_PWR_CMD_END, 0, 0}, 1269 }; 1270 1271 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1272 {0x0093, 1273 RTW_PWR_CUT_ALL_MSK, 1274 RTW_PWR_INTF_ALL_MSK, 1275 RTW_PWR_ADDR_MAC, 1276 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1277 {0x001F, 1278 RTW_PWR_CUT_ALL_MSK, 1279 RTW_PWR_INTF_ALL_MSK, 1280 RTW_PWR_ADDR_MAC, 1281 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1282 {0x0049, 1283 RTW_PWR_CUT_ALL_MSK, 1284 RTW_PWR_INTF_ALL_MSK, 1285 RTW_PWR_ADDR_MAC, 1286 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1287 {0x0006, 1288 RTW_PWR_CUT_ALL_MSK, 1289 RTW_PWR_INTF_ALL_MSK, 1290 RTW_PWR_ADDR_MAC, 1291 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1292 {0x0002, 1293 RTW_PWR_CUT_ALL_MSK, 1294 RTW_PWR_INTF_ALL_MSK, 1295 RTW_PWR_ADDR_MAC, 1296 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1297 {0x10C3, 1298 RTW_PWR_CUT_ALL_MSK, 1299 RTW_PWR_INTF_USB_MSK, 1300 RTW_PWR_ADDR_MAC, 1301 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1302 {0x0005, 1303 RTW_PWR_CUT_ALL_MSK, 1304 RTW_PWR_INTF_ALL_MSK, 1305 RTW_PWR_ADDR_MAC, 1306 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1307 {0x0005, 1308 RTW_PWR_CUT_ALL_MSK, 1309 RTW_PWR_INTF_ALL_MSK, 1310 RTW_PWR_ADDR_MAC, 1311 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1312 {0x0020, 1313 RTW_PWR_CUT_ALL_MSK, 1314 RTW_PWR_INTF_ALL_MSK, 1315 RTW_PWR_ADDR_MAC, 1316 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1317 {0x0000, 1318 RTW_PWR_CUT_ALL_MSK, 1319 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1320 RTW_PWR_ADDR_MAC, 1321 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1322 {0xFFFF, 1323 RTW_PWR_CUT_ALL_MSK, 1324 RTW_PWR_INTF_ALL_MSK, 1325 0, 1326 RTW_PWR_CMD_END, 0, 0}, 1327 }; 1328 1329 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1330 {0x0007, 1331 RTW_PWR_CUT_ALL_MSK, 1332 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1333 RTW_PWR_ADDR_MAC, 1334 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1335 {0x0067, 1336 RTW_PWR_CUT_ALL_MSK, 1337 RTW_PWR_INTF_ALL_MSK, 1338 RTW_PWR_ADDR_MAC, 1339 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1340 {0x0005, 1341 RTW_PWR_CUT_ALL_MSK, 1342 RTW_PWR_INTF_PCI_MSK, 1343 RTW_PWR_ADDR_MAC, 1344 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1345 {0x004A, 1346 RTW_PWR_CUT_ALL_MSK, 1347 RTW_PWR_INTF_USB_MSK, 1348 RTW_PWR_ADDR_MAC, 1349 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1350 {0x0067, 1351 RTW_PWR_CUT_ALL_MSK, 1352 RTW_PWR_INTF_SDIO_MSK, 1353 RTW_PWR_ADDR_MAC, 1354 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1355 {0x0067, 1356 RTW_PWR_CUT_ALL_MSK, 1357 RTW_PWR_INTF_SDIO_MSK, 1358 RTW_PWR_ADDR_MAC, 1359 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1360 {0x004F, 1361 RTW_PWR_CUT_ALL_MSK, 1362 RTW_PWR_INTF_SDIO_MSK, 1363 RTW_PWR_ADDR_MAC, 1364 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1365 {0x0067, 1366 RTW_PWR_CUT_ALL_MSK, 1367 RTW_PWR_INTF_SDIO_MSK, 1368 RTW_PWR_ADDR_MAC, 1369 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1370 {0x0046, 1371 RTW_PWR_CUT_ALL_MSK, 1372 RTW_PWR_INTF_SDIO_MSK, 1373 RTW_PWR_ADDR_MAC, 1374 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1375 {0x0067, 1376 RTW_PWR_CUT_ALL_MSK, 1377 RTW_PWR_INTF_SDIO_MSK, 1378 RTW_PWR_ADDR_MAC, 1379 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1380 {0x0046, 1381 RTW_PWR_CUT_ALL_MSK, 1382 RTW_PWR_INTF_SDIO_MSK, 1383 RTW_PWR_ADDR_MAC, 1384 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1385 {0x0062, 1386 RTW_PWR_CUT_ALL_MSK, 1387 RTW_PWR_INTF_SDIO_MSK, 1388 RTW_PWR_ADDR_MAC, 1389 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1390 {0x0081, 1391 RTW_PWR_CUT_ALL_MSK, 1392 RTW_PWR_INTF_ALL_MSK, 1393 RTW_PWR_ADDR_MAC, 1394 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1395 {0x0005, 1396 RTW_PWR_CUT_ALL_MSK, 1397 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1398 RTW_PWR_ADDR_MAC, 1399 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1400 {0x0086, 1401 RTW_PWR_CUT_ALL_MSK, 1402 RTW_PWR_INTF_SDIO_MSK, 1403 RTW_PWR_ADDR_SDIO, 1404 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1405 {0x0086, 1406 RTW_PWR_CUT_ALL_MSK, 1407 RTW_PWR_INTF_SDIO_MSK, 1408 RTW_PWR_ADDR_SDIO, 1409 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1410 {0x0090, 1411 RTW_PWR_CUT_ALL_MSK, 1412 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1413 RTW_PWR_ADDR_MAC, 1414 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1415 {0x0044, 1416 RTW_PWR_CUT_ALL_MSK, 1417 RTW_PWR_INTF_SDIO_MSK, 1418 RTW_PWR_ADDR_SDIO, 1419 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1420 {0x0040, 1421 RTW_PWR_CUT_ALL_MSK, 1422 RTW_PWR_INTF_SDIO_MSK, 1423 RTW_PWR_ADDR_SDIO, 1424 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1425 {0x0041, 1426 RTW_PWR_CUT_ALL_MSK, 1427 RTW_PWR_INTF_SDIO_MSK, 1428 RTW_PWR_ADDR_SDIO, 1429 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1430 {0x0042, 1431 RTW_PWR_CUT_ALL_MSK, 1432 RTW_PWR_INTF_SDIO_MSK, 1433 RTW_PWR_ADDR_SDIO, 1434 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1435 {0xFFFF, 1436 RTW_PWR_CUT_ALL_MSK, 1437 RTW_PWR_INTF_ALL_MSK, 1438 0, 1439 RTW_PWR_CMD_END, 0, 0}, 1440 }; 1441 1442 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1443 trans_carddis_to_cardemu_8821c, 1444 trans_cardemu_to_act_8821c, 1445 NULL 1446 }; 1447 1448 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1449 trans_act_to_cardemu_8821c, 1450 trans_cardemu_to_carddis_8821c, 1451 NULL 1452 }; 1453 1454 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1455 {0xFFFF, 0x00, 1456 RTW_IP_SEL_PHY, 1457 RTW_INTF_PHY_CUT_ALL, 1458 RTW_INTF_PHY_PLATFORM_ALL}, 1459 }; 1460 1461 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1462 {0xFFFF, 0x0000, 1463 RTW_IP_SEL_PHY, 1464 RTW_INTF_PHY_CUT_ALL, 1465 RTW_INTF_PHY_PLATFORM_ALL}, 1466 }; 1467 1468 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1469 {0x0009, 0x6380, 1470 RTW_IP_SEL_PHY, 1471 RTW_INTF_PHY_CUT_ALL, 1472 RTW_INTF_PHY_PLATFORM_ALL}, 1473 {0xFFFF, 0x0000, 1474 RTW_IP_SEL_PHY, 1475 RTW_INTF_PHY_CUT_ALL, 1476 RTW_INTF_PHY_PLATFORM_ALL}, 1477 }; 1478 1479 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1480 {0xFFFF, 0x0000, 1481 RTW_IP_SEL_PHY, 1482 RTW_INTF_PHY_CUT_ALL, 1483 RTW_INTF_PHY_PLATFORM_ALL}, 1484 }; 1485 1486 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1487 .usb2_para = usb2_param_8821c, 1488 .usb3_para = usb3_param_8821c, 1489 .gen1_para = pcie_gen1_param_8821c, 1490 .gen2_para = pcie_gen2_param_8821c, 1491 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1492 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1493 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1494 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1495 }; 1496 1497 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1498 [0] = RTW_DEF_RFE(8821c, 0, 0), 1499 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1500 }; 1501 1502 static struct rtw_hw_reg rtw8821c_dig[] = { 1503 [0] = { .addr = 0xc50, .mask = 0x7f }, 1504 }; 1505 1506 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1507 .ctrl = LTECOEX_ACCESS_CTRL, 1508 .wdata = LTECOEX_WRITE_DATA, 1509 .rdata = LTECOEX_READ_DATA, 1510 }; 1511 1512 static struct rtw_page_table page_table_8821c[] = { 1513 /* not sure what [0] stands for */ 1514 {16, 16, 16, 14, 1}, 1515 {16, 16, 16, 14, 1}, 1516 {16, 16, 0, 0, 1}, 1517 {16, 16, 16, 0, 1}, 1518 {16, 16, 16, 14, 1}, 1519 }; 1520 1521 static struct rtw_rqpn rqpn_table_8821c[] = { 1522 /* not sure what [0] stands for */ 1523 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1524 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1525 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1526 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1527 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1528 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1529 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1530 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1531 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1532 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1533 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1534 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1535 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1536 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1537 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1538 }; 1539 1540 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1541 .prio[RTW_DMA_MAPPING_EXTRA] = { 1542 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1543 }, 1544 .prio[RTW_DMA_MAPPING_LOW] = { 1545 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1546 }, 1547 .prio[RTW_DMA_MAPPING_NORMAL] = { 1548 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1549 }, 1550 .prio[RTW_DMA_MAPPING_HIGH] = { 1551 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1552 }, 1553 .wsize = true, 1554 }; 1555 1556 static struct rtw_chip_ops rtw8821c_ops = { 1557 .phy_set_param = rtw8821c_phy_set_param, 1558 .read_efuse = rtw8821c_read_efuse, 1559 .query_rx_desc = rtw8821c_query_rx_desc, 1560 .set_channel = rtw8821c_set_channel, 1561 .mac_init = rtw8821c_mac_init, 1562 .read_rf = rtw_phy_read_rf, 1563 .write_rf = rtw_phy_write_rf_reg_sipi, 1564 .set_antenna = NULL, 1565 .set_tx_power_index = rtw8821c_set_tx_power_index, 1566 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1567 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1568 .phy_calibration = rtw8821c_phy_calibration, 1569 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1570 .pwr_track = rtw8821c_pwr_track, 1571 .config_bfee = rtw8821c_bf_config_bfee, 1572 .set_gid_table = rtw_bf_set_gid_table, 1573 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1574 1575 .coex_set_init = rtw8821c_coex_cfg_init, 1576 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1577 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1578 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1579 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1580 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1581 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1582 }; 1583 1584 /* rssi in percentage % (dbm = % - 100) */ 1585 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1586 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1587 1588 /* Shared-Antenna Coex Table */ 1589 static const struct coex_table_para table_sant_8821c[] = { 1590 {0x55555555, 0x55555555}, /* case-0 */ 1591 {0x55555555, 0x55555555}, 1592 {0x66555555, 0x66555555}, 1593 {0xaaaaaaaa, 0xaaaaaaaa}, 1594 {0x5a5a5a5a, 0x5a5a5a5a}, 1595 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1596 {0x6a5a5555, 0xaaaaaaaa}, 1597 {0x6a5a56aa, 0x6a5a56aa}, 1598 {0x6a5a5a5a, 0x6a5a5a5a}, 1599 {0x66555555, 0x5a5a5a5a}, 1600 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1601 {0x66555555, 0xaaaaaaaa}, 1602 {0x66555555, 0x6a5a5aaa}, 1603 {0x66555555, 0x6aaa6aaa}, 1604 {0x66555555, 0x6a5a5aaa}, 1605 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1606 {0xffff55ff, 0xfafafafa}, 1607 {0xffff55ff, 0x6afa5afa}, 1608 {0xaaffffaa, 0xfafafafa}, 1609 {0xaa5555aa, 0x5a5a5a5a}, 1610 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1611 {0xaa5555aa, 0xaaaaaaaa}, 1612 {0xffffffff, 0x55555555}, 1613 {0xffffffff, 0x5a5a5a5a}, 1614 {0xffffffff, 0x5a5a5a5a}, 1615 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1616 {0x55555555, 0x5a5a5a5a}, 1617 {0x55555555, 0xaaaaaaaa}, 1618 {0x66555555, 0x6a5a6a5a}, 1619 {0x66556655, 0x66556655}, 1620 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1621 {0xffffffff, 0x5aaa5aaa}, 1622 {0x56555555, 0x5a5a5aaa} 1623 }; 1624 1625 /* Non-Shared-Antenna Coex Table */ 1626 static const struct coex_table_para table_nsant_8821c[] = { 1627 {0xffffffff, 0xffffffff}, /* case-100 */ 1628 {0xffff55ff, 0xfafafafa}, 1629 {0x66555555, 0x66555555}, 1630 {0xaaaaaaaa, 0xaaaaaaaa}, 1631 {0x5a5a5a5a, 0x5a5a5a5a}, 1632 {0xffffffff, 0xffffffff}, /* case-105 */ 1633 {0x5afa5afa, 0x5afa5afa}, 1634 {0x55555555, 0xfafafafa}, 1635 {0x66555555, 0xfafafafa}, 1636 {0x66555555, 0x5a5a5a5a}, 1637 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1638 {0x66555555, 0xaaaaaaaa}, 1639 {0xffff55ff, 0xfafafafa}, 1640 {0xffff55ff, 0x5afa5afa}, 1641 {0xffff55ff, 0xaaaaaaaa}, 1642 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1643 {0xaaffffaa, 0x5afa5afa}, 1644 {0xaaffffaa, 0xaaaaaaaa}, 1645 {0xffffffff, 0xfafafafa}, 1646 {0xffff55ff, 0xfafafafa}, 1647 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1648 {0xffff55ff, 0x5afa5afa}, 1649 {0xffff55ff, 0x5afa5afa}, 1650 {0x55ff55ff, 0x55ff55ff} 1651 }; 1652 1653 /* Shared-Antenna TDMA */ 1654 static const struct coex_tdma_para tdma_sant_8821c[] = { 1655 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1656 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1657 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1658 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1659 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1660 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1661 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1662 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1663 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1664 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1665 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1666 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1667 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1668 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1669 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1670 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1671 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1672 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1673 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1674 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1675 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1676 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1677 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1678 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1679 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1680 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1681 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1682 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1683 }; 1684 1685 /* Non-Shared-Antenna TDMA */ 1686 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1687 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1688 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1689 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1690 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1691 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1692 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1693 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1694 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1695 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1696 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1697 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1698 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1699 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1700 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1701 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1702 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1703 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1704 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1705 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1706 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1707 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1708 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1709 }; 1710 1711 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1712 1713 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1714 static const struct coex_rf_para rf_para_tx_8821c[] = { 1715 {0, 0, false, 7}, /* for normal */ 1716 {0, 20, false, 7}, /* for WL-CPT */ 1717 {8, 17, true, 4}, 1718 {7, 18, true, 4}, 1719 {6, 19, true, 4}, 1720 {5, 20, true, 4} 1721 }; 1722 1723 static const struct coex_rf_para rf_para_rx_8821c[] = { 1724 {0, 0, false, 7}, /* for normal */ 1725 {0, 20, false, 7}, /* for WL-CPT */ 1726 {3, 24, true, 5}, 1727 {2, 26, true, 5}, 1728 {1, 27, true, 5}, 1729 {0, 28, true, 5} 1730 }; 1731 1732 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1733 1734 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1735 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1736 11, 11, 12, 12, 12, 12, 12}, 1737 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1738 11, 12, 12, 12, 12, 12, 12, 12}, 1739 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1740 11, 12, 12, 12, 12, 12, 12}, 1741 }; 1742 1743 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1744 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1745 12, 12, 12, 12, 12, 12, 12}, 1746 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1747 12, 12, 12, 12, 12, 12, 12, 12}, 1748 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1749 11, 12, 12, 12, 12, 12, 12, 12}, 1750 }; 1751 1752 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1753 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1754 11, 11, 12, 12, 12, 12, 12}, 1755 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1756 11, 12, 12, 12, 12, 12, 12, 12}, 1757 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1758 11, 12, 12, 12, 12, 12, 12}, 1759 }; 1760 1761 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1762 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1763 12, 12, 12, 12, 12, 12, 12}, 1764 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1765 12, 12, 12, 12, 12, 12, 12, 12}, 1766 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1767 11, 12, 12, 12, 12, 12, 12, 12}, 1768 }; 1769 1770 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1771 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1772 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1773 }; 1774 1775 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1776 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1777 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1778 }; 1779 1780 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1781 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1782 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1783 }; 1784 1785 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1786 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1787 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1788 }; 1789 1790 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1791 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1792 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1793 }; 1794 1795 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1796 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1797 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1798 }; 1799 1800 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1801 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1802 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1803 }; 1804 1805 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1806 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1807 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1808 }; 1809 1810 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1811 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1812 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1813 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1814 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1815 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1816 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1817 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1818 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1819 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1820 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1821 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1822 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1823 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1824 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1825 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1826 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1827 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1828 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1829 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1830 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1831 }; 1832 1833 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1834 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1835 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1836 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1837 {0, 0, RTW_REG_DOMAIN_NL}, 1838 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1839 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1840 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1841 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1842 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1843 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1844 {0, 0, RTW_REG_DOMAIN_NL}, 1845 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1846 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1847 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1848 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1849 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1850 {0, 0, RTW_REG_DOMAIN_NL}, 1851 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1852 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1853 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1854 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1855 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1856 }; 1857 1858 struct rtw_chip_info rtw8821c_hw_spec = { 1859 .ops = &rtw8821c_ops, 1860 .id = RTW_CHIP_TYPE_8821C, 1861 .fw_name = "rtw88/rtw8821c_fw.bin", 1862 .wlan_cpu = RTW_WCPU_11AC, 1863 .tx_pkt_desc_sz = 48, 1864 .tx_buf_desc_sz = 16, 1865 .rx_pkt_desc_sz = 24, 1866 .rx_buf_desc_sz = 8, 1867 .phy_efuse_size = 512, 1868 .log_efuse_size = 512, 1869 .ptct_efuse_size = 96, 1870 .txff_size = 65536, 1871 .rxff_size = 16384, 1872 .txgi_factor = 1, 1873 .is_pwr_by_rate_dec = true, 1874 .max_power_index = 0x3f, 1875 .csi_buf_pg_num = 0, 1876 .band = RTW_BAND_2G | RTW_BAND_5G, 1877 .page_size = 128, 1878 .dig_min = 0x1c, 1879 .ht_supported = true, 1880 .vht_supported = true, 1881 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1882 .sys_func_en = 0xD8, 1883 .pwr_on_seq = card_enable_flow_8821c, 1884 .pwr_off_seq = card_disable_flow_8821c, 1885 .page_table = page_table_8821c, 1886 .rqpn_table = rqpn_table_8821c, 1887 .prioq_addrs = &prioq_addrs_8821c, 1888 .intf_table = &phy_para_table_8821c, 1889 .dig = rtw8821c_dig, 1890 .rf_base_addr = {0x2800, 0x2c00}, 1891 .rf_sipi_addr = {0xc90, 0xe90}, 1892 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1893 .mac_tbl = &rtw8821c_mac_tbl, 1894 .agc_tbl = &rtw8821c_agc_tbl, 1895 .bb_tbl = &rtw8821c_bb_tbl, 1896 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1897 .rfe_defs = rtw8821c_rfe_defs, 1898 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1899 .rx_ldpc = false, 1900 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1901 .iqk_threshold = 8, 1902 .bfer_su_max_num = 2, 1903 .bfer_mu_max_num = 1, 1904 1905 .coex_para_ver = 0x19092746, 1906 .bt_desired_ver = 0x46, 1907 .scbd_support = true, 1908 .new_scbd10_def = false, 1909 .ble_hid_profile_support = false, 1910 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1911 .bt_rssi_type = COEX_BTRSSI_RATIO, 1912 .ant_isolation = 15, 1913 .rssi_tolerance = 2, 1914 .wl_rssi_step = wl_rssi_step_8821c, 1915 .bt_rssi_step = bt_rssi_step_8821c, 1916 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 1917 .table_sant = table_sant_8821c, 1918 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 1919 .table_nsant = table_nsant_8821c, 1920 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 1921 .tdma_sant = tdma_sant_8821c, 1922 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 1923 .tdma_nsant = tdma_nsant_8821c, 1924 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 1925 .wl_rf_para_tx = rf_para_tx_8821c, 1926 .wl_rf_para_rx = rf_para_rx_8821c, 1927 .bt_afh_span_bw20 = 0x24, 1928 .bt_afh_span_bw40 = 0x36, 1929 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 1930 .afh_5g = afh_5g_8821c, 1931 1932 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 1933 .coex_info_hw_regs = coex_info_hw_regs_8821c, 1934 }; 1935 EXPORT_SYMBOL(rtw8821c_hw_spec); 1936 1937 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 1938 1939 MODULE_AUTHOR("Realtek Corporation"); 1940 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 1941 MODULE_LICENSE("Dual BSD/GPL"); 1942