1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 #include "regd.h" 18 19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; 20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, 21 -20, -24, -28, -31, -34, -37, -40, -44}; 22 23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8821c_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 enum rtw8821ce_rf_set { 30 SWITCH_TO_BTG, 31 SWITCH_TO_WLG, 32 SWITCH_TO_WLA, 33 SWITCH_TO_BT, 34 }; 35 36 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 37 { 38 struct rtw_efuse *efuse = &rtwdev->efuse; 39 struct rtw8821c_efuse *map; 40 int i; 41 42 map = (struct rtw8821c_efuse *)log_map; 43 44 efuse->rfe_option = map->rfe_option; 45 efuse->rf_board_option = map->rf_board_option; 46 efuse->crystal_cap = map->xtal_k; 47 efuse->pa_type_2g = map->pa_type; 48 efuse->pa_type_5g = map->pa_type; 49 efuse->lna_type_2g = map->lna_type_2g[0]; 50 efuse->lna_type_5g = map->lna_type_5g[0]; 51 efuse->channel_plan = map->channel_plan; 52 efuse->country_code[0] = map->country_code[0]; 53 efuse->country_code[1] = map->country_code[1]; 54 efuse->bt_setting = map->rf_bt_setting; 55 efuse->regd = map->rf_board_option & 0x7; 56 efuse->thermal_meter[0] = map->thermal_meter; 57 efuse->thermal_meter_k = map->thermal_meter; 58 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 59 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 60 61 for (i = 0; i < 4; i++) 62 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 63 64 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) 65 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; 66 67 switch (rtw_hci_type(rtwdev)) { 68 case RTW_HCI_TYPE_PCIE: 69 rtw8821ce_efuse_parsing(efuse, map); 70 break; 71 default: 72 /* unsupported now */ 73 return -ENOTSUPP; 74 } 75 76 return 0; 77 } 78 79 static const u32 rtw8821c_txscale_tbl[] = { 80 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 81 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 82 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 83 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 84 }; 85 86 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 87 { 88 u8 i = 0; 89 u32 swing, table_value; 90 91 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 92 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 93 table_value = rtw8821c_txscale_tbl[i]; 94 if (swing == table_value) 95 break; 96 } 97 98 return i; 99 } 100 101 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 102 { 103 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 104 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 105 106 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 107 dm_info->default_ofdm_index = 24; 108 else 109 dm_info->default_ofdm_index = swing_idx; 110 111 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 112 dm_info->delta_power_index[RF_PATH_A] = 0; 113 dm_info->delta_power_index_last[RF_PATH_A] = 0; 114 dm_info->pwr_trk_triggered = false; 115 dm_info->pwr_trk_init_trigger = true; 116 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 117 } 118 119 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 120 { 121 rtw_bf_phy_init(rtwdev); 122 /* Grouping bitmap parameters */ 123 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 124 } 125 126 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 127 { 128 u8 crystal_cap, val; 129 130 /* power on BB/RF domain */ 131 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 132 val |= BIT_FEN_PCIEA; 133 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 134 135 /* toggle BB reset */ 136 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 137 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 138 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 139 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 140 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 141 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 142 143 rtw_write8(rtwdev, REG_RF_CTRL, 144 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 145 usleep_range(10, 11); 146 rtw_write8(rtwdev, REG_WLRF1 + 3, 147 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 148 usleep_range(10, 11); 149 150 /* pre init before header files config */ 151 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 152 153 rtw_phy_load_tables(rtwdev); 154 155 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 156 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 157 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 158 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 159 160 /* post init after header files config */ 161 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 162 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 163 rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 164 rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 165 166 rtw_phy_init(rtwdev); 167 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 168 169 rtw8821c_pwrtrack_init(rtwdev); 170 171 rtw8821c_phy_bf_init(rtwdev); 172 } 173 174 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 175 { 176 u32 value32; 177 u16 pre_txcnt; 178 179 /* protocol configuration */ 180 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 181 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 182 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 183 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 184 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 185 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 186 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 187 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 188 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 189 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 190 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 191 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 192 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 193 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 194 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 195 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 196 197 /* EDCA configuration */ 198 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 199 rtw_write16(rtwdev, REG_TXPAUSE, 0); 200 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 201 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 202 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 203 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 204 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 205 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 206 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 207 208 /* Set beacon cotnrol - enable TSF and other related functions */ 209 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 210 211 /* Set send beacon related registers */ 212 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 213 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 214 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 215 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 216 217 /* WMAC configuration */ 218 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 219 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 220 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 221 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 222 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 223 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 224 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 225 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 226 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6)); 227 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 228 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 229 230 return 0; 231 } 232 233 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 234 { 235 u8 ldo_pwr; 236 237 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 238 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 239 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 240 } 241 242 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) 243 { 244 u32 reg; 245 246 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST); 247 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN); 248 249 reg = rtw_read32(rtwdev, REG_RFECTL); 250 switch (rf_set) { 251 case SWITCH_TO_BTG: 252 reg |= B_BTG_SWITCH; 253 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH | 254 B_WLA_SWITCH); 255 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); 256 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); 257 break; 258 case SWITCH_TO_WLG: 259 reg |= B_WL_SWITCH | B_WLG_SWITCH; 260 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH); 261 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); 262 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); 263 break; 264 case SWITCH_TO_WLA: 265 reg |= B_WL_SWITCH | B_WLA_SWITCH; 266 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH); 267 break; 268 case SWITCH_TO_BT: 269 default: 270 break; 271 } 272 273 rtw_write32(rtwdev, REG_RFECTL, reg); 274 } 275 276 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 277 { 278 u32 rf_reg18; 279 280 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 281 282 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 283 RF18_BW_MASK); 284 285 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 286 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 287 288 if (channel >= 100 && channel <= 140) 289 rf_reg18 |= RF18_RFSI_GE; 290 else if (channel > 140) 291 rf_reg18 |= RF18_RFSI_GT; 292 293 switch (bw) { 294 case RTW_CHANNEL_WIDTH_5: 295 case RTW_CHANNEL_WIDTH_10: 296 case RTW_CHANNEL_WIDTH_20: 297 default: 298 rf_reg18 |= RF18_BW_20M; 299 break; 300 case RTW_CHANNEL_WIDTH_40: 301 rf_reg18 |= RF18_BW_40M; 302 break; 303 case RTW_CHANNEL_WIDTH_80: 304 rf_reg18 |= RF18_BW_80M; 305 break; 306 } 307 308 if (channel <= 14) { 309 if (rtwdev->efuse.rfe_option == 0) 310 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG); 311 else if (rtwdev->efuse.rfe_option == 2 || 312 rtwdev->efuse.rfe_option == 4) 313 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG); 314 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 315 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 316 } else { 317 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA); 318 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 319 } 320 321 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 322 323 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 324 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 325 } 326 327 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 328 { 329 if (bw == RTW_CHANNEL_WIDTH_40) { 330 /* RX DFIR for BW40 */ 331 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 332 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 333 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 334 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 335 } else if (bw == RTW_CHANNEL_WIDTH_80) { 336 /* RX DFIR for BW80 */ 337 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 338 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 339 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 340 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 341 } else { 342 /* RX DFIR for BW20, BW10 and BW5 */ 343 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 344 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 345 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 346 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 347 } 348 } 349 350 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 351 u8 primary_ch_idx) 352 { 353 u32 val32; 354 355 if (channel <= 14) { 356 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 357 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 358 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 359 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 360 361 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 362 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 363 if (channel == 14) { 364 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 365 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 366 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 367 } else { 368 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 369 rtwdev->chip->ch_param[0]); 370 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 371 rtwdev->chip->ch_param[1] & MASKLWORD); 372 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 373 rtwdev->chip->ch_param[2]); 374 } 375 } else if (channel > 35) { 376 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 377 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 378 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 379 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 380 381 if (channel >= 36 && channel <= 64) 382 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 383 else if (channel >= 100 && channel <= 144) 384 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 385 else if (channel >= 149) 386 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 387 388 if (channel >= 36 && channel <= 48) 389 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 390 else if (channel >= 52 && channel <= 64) 391 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 392 else if (channel >= 100 && channel <= 116) 393 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 394 else if (channel >= 118 && channel <= 177) 395 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 396 } 397 398 switch (bw) { 399 case RTW_CHANNEL_WIDTH_20: 400 default: 401 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 402 val32 &= 0xffcffc00; 403 val32 |= 0x10010000; 404 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 405 406 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 407 break; 408 case RTW_CHANNEL_WIDTH_40: 409 if (primary_ch_idx == 1) 410 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 411 else 412 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 413 414 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 415 val32 &= 0xff3ff300; 416 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 417 RTW_CHANNEL_WIDTH_40; 418 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 419 420 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 421 break; 422 case RTW_CHANNEL_WIDTH_80: 423 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 424 val32 &= 0xfcffcf00; 425 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 426 RTW_CHANNEL_WIDTH_80; 427 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 428 429 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 430 break; 431 case RTW_CHANNEL_WIDTH_5: 432 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 433 val32 &= 0xefcefc00; 434 val32 |= 0x200240; 435 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 436 437 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 438 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 439 break; 440 case RTW_CHANNEL_WIDTH_10: 441 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 442 val32 &= 0xefcefc00; 443 val32 |= 0x300380; 444 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 445 446 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 447 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 448 break; 449 } 450 } 451 452 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 453 { 454 struct rtw_efuse efuse = rtwdev->efuse; 455 u8 tx_bb_swing; 456 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 457 458 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 459 efuse.tx_bb_swing_setting_5g; 460 if (tx_bb_swing > 9) 461 tx_bb_swing = 0; 462 463 return swing2setting[(tx_bb_swing / 3)]; 464 } 465 466 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 467 u8 bw, u8 primary_ch_idx) 468 { 469 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 470 rtw8821c_get_bb_swing(rtwdev, channel)); 471 rtw8821c_pwrtrack_init(rtwdev); 472 } 473 474 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 475 u8 primary_chan_idx) 476 { 477 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 478 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 479 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 480 rtw8821c_set_channel_rf(rtwdev, channel, bw); 481 rtw8821c_set_channel_rxdfir(rtwdev, bw); 482 } 483 484 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 485 { 486 struct rtw_efuse *efuse = &rtwdev->efuse; 487 const s8 *lna_gain_table; 488 int lna_gain_table_size; 489 s8 rx_pwr_all = 0; 490 s8 lna_gain = 0; 491 492 if (efuse->rfe_option == 0) { 493 lna_gain_table = lna_gain_table_0; 494 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0); 495 } else { 496 lna_gain_table = lna_gain_table_1; 497 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1); 498 } 499 500 if (lna_idx >= lna_gain_table_size) { 501 rtw_info(rtwdev, "incorrect lna index (%d)\n", lna_idx); 502 return -120; 503 } 504 505 lna_gain = lna_gain_table[lna_idx]; 506 rx_pwr_all = lna_gain - 2 * vga_idx; 507 508 return rx_pwr_all; 509 } 510 511 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 512 struct rtw_rx_pkt_stat *pkt_stat) 513 { 514 s8 rx_power; 515 u8 lna_idx = 0; 516 u8 vga_idx = 0; 517 518 vga_idx = GET_PHY_STAT_P0_VGA(phy_status); 519 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) | 520 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status)); 521 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 522 523 pkt_stat->rx_power[RF_PATH_A] = rx_power; 524 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 525 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 526 pkt_stat->signal_power = rx_power; 527 } 528 529 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 530 struct rtw_rx_pkt_stat *pkt_stat) 531 { 532 u8 rxsc, bw; 533 s8 min_rx_power = -120; 534 535 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 536 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 537 else 538 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 539 540 if (rxsc >= 1 && rxsc <= 8) 541 bw = RTW_CHANNEL_WIDTH_20; 542 else if (rxsc >= 9 && rxsc <= 12) 543 bw = RTW_CHANNEL_WIDTH_40; 544 else if (rxsc >= 13) 545 bw = RTW_CHANNEL_WIDTH_80; 546 else 547 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 548 549 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 550 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 551 pkt_stat->bw = bw; 552 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 553 min_rx_power); 554 } 555 556 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 557 struct rtw_rx_pkt_stat *pkt_stat) 558 { 559 u8 page; 560 561 page = *phy_status & 0xf; 562 563 switch (page) { 564 case 0: 565 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 566 break; 567 case 1: 568 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 569 break; 570 default: 571 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 572 return; 573 } 574 } 575 576 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 577 struct rtw_rx_pkt_stat *pkt_stat, 578 struct ieee80211_rx_status *rx_status) 579 { 580 struct ieee80211_hdr *hdr; 581 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 582 u8 *phy_status = NULL; 583 584 memset(pkt_stat, 0, sizeof(*pkt_stat)); 585 586 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 587 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 588 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 589 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 590 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 591 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 592 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 593 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 594 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 595 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 596 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 597 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 598 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 599 600 /* drv_info_sz is in unit of 8-bytes */ 601 pkt_stat->drv_info_sz *= 8; 602 603 /* c2h cmd pkt's rx/phy status is not interested */ 604 if (pkt_stat->is_c2h) 605 return; 606 607 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 608 pkt_stat->drv_info_sz); 609 if (pkt_stat->phy_status) { 610 phy_status = rx_desc + desc_sz + pkt_stat->shift; 611 query_phy_status(rtwdev, phy_status, pkt_stat); 612 } 613 614 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 615 } 616 617 static void 618 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 619 { 620 struct rtw_hal *hal = &rtwdev->hal; 621 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 622 static u32 phy_pwr_idx; 623 u8 rate, rate_idx, pwr_index, shift; 624 int j; 625 626 for (j = 0; j < rtw_rate_size[rs]; j++) { 627 rate = rtw_rate_section[rs][j]; 628 pwr_index = hal->tx_pwr_tbl[path][rate]; 629 shift = rate & 0x3; 630 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 631 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 632 rate_idx = rate & 0xfc; 633 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 634 phy_pwr_idx); 635 phy_pwr_idx = 0; 636 } 637 } 638 } 639 640 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 641 { 642 struct rtw_hal *hal = &rtwdev->hal; 643 int rs, path; 644 645 for (path = 0; path < hal->rf_path_num; path++) { 646 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 647 if (rs == RTW_RATE_SECTION_HT_2S || 648 rs == RTW_RATE_SECTION_VHT_2S) 649 continue; 650 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 651 } 652 } 653 } 654 655 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 656 { 657 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 658 u32 cck_enable; 659 u32 cck_fa_cnt; 660 u32 ofdm_fa_cnt; 661 u32 crc32_cnt; 662 u32 cca32_cnt; 663 664 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 665 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 666 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 667 668 dm_info->cck_fa_cnt = cck_fa_cnt; 669 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 670 if (cck_enable) 671 dm_info->total_fa_cnt += cck_fa_cnt; 672 dm_info->total_fa_cnt = ofdm_fa_cnt; 673 674 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 675 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 676 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 677 678 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 679 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 680 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 681 682 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 683 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 684 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 685 686 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 687 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 688 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 689 690 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 691 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 692 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 693 if (cck_enable) { 694 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 695 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 696 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 697 } 698 699 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 700 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 701 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 702 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 703 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 704 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 705 } 706 707 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 708 { 709 static int do_iqk_cnt; 710 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 711 u32 rf_reg, iqk_fail_mask; 712 int counter; 713 bool reload; 714 715 if (rtw_is_assoc(rtwdev)) 716 para.segment_iqk = 1; 717 718 rtw_fw_do_iqk(rtwdev, ¶); 719 720 for (counter = 0; counter < 300; counter++) { 721 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 722 if (rf_reg == 0xabcde) 723 break; 724 msleep(20); 725 } 726 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 727 728 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 729 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 730 rtw_dbg(rtwdev, RTW_DBG_PHY, 731 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 732 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 733 } 734 735 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 736 { 737 rtw8821c_do_iqk(rtwdev); 738 } 739 740 /* for coex */ 741 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 742 { 743 /* enable TBTT nterrupt */ 744 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 745 746 /* BT report packet sample rate */ 747 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 748 749 /* enable BT counter statistics */ 750 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 751 752 /* enable PTA (3-wire function form BT side) */ 753 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 754 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 755 756 /* enable PTA (tx/rx signal form WiFi side) */ 757 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 758 /* wl tx signal to PTA not case EDCCA */ 759 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 760 /* GNT_BT=1 while select both */ 761 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 762 763 /* beacon queue always hi-pri */ 764 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 765 BCN_PRI_EN); 766 } 767 768 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 769 u8 pos_type) 770 { 771 struct rtw_coex *coex = &rtwdev->coex; 772 struct rtw_coex_dm *coex_dm = &coex->dm; 773 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 774 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 775 bool polarity_inverse; 776 u8 regval = 0; 777 778 if (switch_status == coex_dm->cur_switch_status) 779 return; 780 781 if (coex_rfe->wlg_at_btg) { 782 ctrl_type = COEX_SWITCH_CTRL_BY_BBSW; 783 784 if (coex_rfe->ant_switch_polarity) 785 pos_type = COEX_SWITCH_TO_WLA; 786 else 787 pos_type = COEX_SWITCH_TO_WLG_BT; 788 } 789 790 coex_dm->cur_switch_status = switch_status; 791 792 if (coex_rfe->ant_switch_diversity && 793 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 794 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 795 796 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 797 798 switch (ctrl_type) { 799 default: 800 case COEX_SWITCH_CTRL_BY_BBSW: 801 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 802 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 803 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 804 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 805 DPDT_CTRL_PIN); 806 807 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 808 if (coex_rfe->rfe_module_type != 0x4 && 809 coex_rfe->rfe_module_type != 0x2) 810 regval = 0x3; 811 else 812 regval = (!polarity_inverse ? 0x2 : 0x1); 813 } else if (pos_type == COEX_SWITCH_TO_WLG) { 814 regval = (!polarity_inverse ? 0x2 : 0x1); 815 } else { 816 regval = (!polarity_inverse ? 0x1 : 0x2); 817 } 818 819 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 820 regval); 821 break; 822 case COEX_SWITCH_CTRL_BY_PTA: 823 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 824 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 825 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 826 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 827 PTA_CTRL_PIN); 828 829 regval = (!polarity_inverse ? 0x2 : 0x1); 830 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 831 regval); 832 break; 833 case COEX_SWITCH_CTRL_BY_ANTDIV: 834 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 835 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 836 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 837 ANTDIC_CTRL_PIN); 838 break; 839 case COEX_SWITCH_CTRL_BY_MAC: 840 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 841 842 regval = (!polarity_inverse ? 0x0 : 0x1); 843 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 844 regval); 845 break; 846 case COEX_SWITCH_CTRL_BY_FW: 847 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 848 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 849 break; 850 case COEX_SWITCH_CTRL_BY_BT: 851 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 852 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 853 break; 854 } 855 856 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 857 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 858 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 859 } else { 860 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 861 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 862 } 863 } 864 865 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 866 {} 867 868 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 869 { 870 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 871 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 872 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 873 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 874 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 875 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 876 } 877 878 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 879 { 880 struct rtw_coex *coex = &rtwdev->coex; 881 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 882 struct rtw_efuse *efuse = &rtwdev->efuse; 883 884 coex_rfe->rfe_module_type = efuse->rfe_option; 885 coex_rfe->ant_switch_polarity = 0; 886 coex_rfe->ant_switch_exist = true; 887 coex_rfe->wlg_at_btg = false; 888 889 switch (coex_rfe->rfe_module_type) { 890 case 0: 891 case 8: 892 case 1: 893 case 9: /* 1-Ant, Main, WLG */ 894 default: /* 2-Ant, DPDT, WLG */ 895 break; 896 case 2: 897 case 10: /* 1-Ant, Main, BTG */ 898 case 7: 899 case 15: /* 2-Ant, DPDT, BTG */ 900 coex_rfe->wlg_at_btg = true; 901 break; 902 case 3: 903 case 11: /* 1-Ant, Aux, WLG */ 904 coex_rfe->ant_switch_polarity = 1; 905 break; 906 case 4: 907 case 12: /* 1-Ant, Aux, BTG */ 908 coex_rfe->wlg_at_btg = true; 909 coex_rfe->ant_switch_polarity = 1; 910 break; 911 case 5: 912 case 13: /* 2-Ant, no switch, WLG */ 913 case 6: 914 case 14: /* 2-Ant, no antenna switch, WLG */ 915 coex_rfe->ant_switch_exist = false; 916 break; 917 } 918 } 919 920 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 921 { 922 struct rtw_coex *coex = &rtwdev->coex; 923 struct rtw_coex_dm *coex_dm = &coex->dm; 924 struct rtw_efuse *efuse = &rtwdev->efuse; 925 bool share_ant = efuse->share_ant; 926 927 if (share_ant) 928 return; 929 930 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 931 return; 932 933 coex_dm->cur_wl_pwr_lvl = wl_pwr; 934 } 935 936 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 937 {} 938 939 static void 940 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 941 s8 pwr_idx_offset_lower, 942 s8 *txagc_idx, u8 *swing_idx) 943 { 944 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 945 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 946 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 947 u8 swing_lower_bound = 0; 948 u8 max_pwr_idx_offset = 0xf; 949 s8 agc_index = 0; 950 u8 swing_index = dm_info->default_ofdm_index; 951 952 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 953 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 954 955 if (delta_pwr_idx >= 0) { 956 if (delta_pwr_idx <= pwr_idx_offset) { 957 agc_index = delta_pwr_idx; 958 swing_index = dm_info->default_ofdm_index; 959 } else if (delta_pwr_idx > pwr_idx_offset) { 960 agc_index = pwr_idx_offset; 961 swing_index = dm_info->default_ofdm_index + 962 delta_pwr_idx - pwr_idx_offset; 963 swing_index = min_t(u8, swing_index, swing_upper_bound); 964 } 965 } else if (delta_pwr_idx < 0) { 966 if (delta_pwr_idx >= pwr_idx_offset_lower) { 967 agc_index = delta_pwr_idx; 968 swing_index = dm_info->default_ofdm_index; 969 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 970 if (dm_info->default_ofdm_index > 971 (pwr_idx_offset_lower - delta_pwr_idx)) 972 swing_index = dm_info->default_ofdm_index + 973 delta_pwr_idx - pwr_idx_offset_lower; 974 else 975 swing_index = swing_lower_bound; 976 977 agc_index = pwr_idx_offset_lower; 978 } 979 } 980 981 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 982 rtw_warn(rtwdev, "swing index overflow\n"); 983 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 984 } 985 986 *txagc_idx = agc_index; 987 *swing_idx = swing_index; 988 } 989 990 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 991 s8 pwr_idx_offset_lower) 992 { 993 s8 txagc_idx; 994 u8 swing_idx; 995 996 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 997 &txagc_idx, &swing_idx); 998 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 999 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 1000 rtw8821c_txscale_tbl[swing_idx]); 1001 } 1002 1003 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 1004 { 1005 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1006 u8 pwr_idx_offset, tx_pwr_idx; 1007 s8 pwr_idx_offset_lower; 1008 u8 channel = rtwdev->hal.current_channel; 1009 u8 band_width = rtwdev->hal.current_band_width; 1010 u8 regd = rtw_regd_get(rtwdev); 1011 u8 tx_rate = dm_info->tx_rate; 1012 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1013 1014 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 1015 band_width, channel, regd); 1016 1017 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1018 1019 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1020 pwr_idx_offset_lower = 0 - tx_pwr_idx; 1021 1022 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 1023 } 1024 1025 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 1026 { 1027 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1028 struct rtw_swing_table swing_table; 1029 u8 thermal_value, delta; 1030 1031 rtw_phy_config_swing_table(rtwdev, &swing_table); 1032 1033 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1034 return; 1035 1036 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1037 1038 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1039 1040 if (dm_info->pwr_trk_init_trigger) 1041 dm_info->pwr_trk_init_trigger = false; 1042 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1043 RF_PATH_A)) 1044 goto iqk; 1045 1046 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1047 1048 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1049 1050 dm_info->delta_power_index[RF_PATH_A] = 1051 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 1052 RF_PATH_A, delta); 1053 if (dm_info->delta_power_index[RF_PATH_A] == 1054 dm_info->delta_power_index_last[RF_PATH_A]) 1055 goto iqk; 1056 else 1057 dm_info->delta_power_index_last[RF_PATH_A] = 1058 dm_info->delta_power_index[RF_PATH_A]; 1059 rtw8821c_pwrtrack_set(rtwdev); 1060 1061 iqk: 1062 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1063 rtw8821c_do_iqk(rtwdev); 1064 } 1065 1066 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 1067 { 1068 struct rtw_efuse *efuse = &rtwdev->efuse; 1069 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1070 1071 if (efuse->power_track_type != 0) 1072 return; 1073 1074 if (!dm_info->pwr_trk_triggered) { 1075 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1076 GENMASK(17, 16), 0x03); 1077 dm_info->pwr_trk_triggered = true; 1078 return; 1079 } 1080 1081 rtw8821c_phy_pwrtrack(rtwdev); 1082 dm_info->pwr_trk_triggered = false; 1083 } 1084 1085 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 1086 struct rtw_vif *vif, 1087 struct rtw_bfee *bfee, bool enable) 1088 { 1089 if (enable) 1090 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1091 else 1092 rtw_bf_remove_bfee_su(rtwdev, bfee); 1093 } 1094 1095 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1096 struct rtw_vif *vif, 1097 struct rtw_bfee *bfee, bool enable) 1098 { 1099 if (enable) 1100 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1101 else 1102 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1103 } 1104 1105 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1106 struct rtw_bfee *bfee, bool enable) 1107 { 1108 if (bfee->role == RTW_BFEE_SU) 1109 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1110 else if (bfee->role == RTW_BFEE_MU) 1111 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1112 else 1113 rtw_warn(rtwdev, "wrong bfee role\n"); 1114 } 1115 1116 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1117 { 1118 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1119 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1120 u8 cck_n_rx; 1121 1122 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1123 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1124 1125 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1126 return; 1127 1128 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1129 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1130 rtw_dbg(rtwdev, RTW_DBG_PHY, 1131 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1132 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1133 dm_info->cck_pd_default + new_lvl * 2, 1134 pd[new_lvl], dm_info->cck_fa_avg); 1135 1136 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1137 1138 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1139 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1140 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1141 dm_info->cck_pd_default + new_lvl * 2); 1142 } 1143 1144 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1145 {0x0086, 1146 RTW_PWR_CUT_ALL_MSK, 1147 RTW_PWR_INTF_SDIO_MSK, 1148 RTW_PWR_ADDR_SDIO, 1149 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1150 {0x0086, 1151 RTW_PWR_CUT_ALL_MSK, 1152 RTW_PWR_INTF_SDIO_MSK, 1153 RTW_PWR_ADDR_SDIO, 1154 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1155 {0x004A, 1156 RTW_PWR_CUT_ALL_MSK, 1157 RTW_PWR_INTF_USB_MSK, 1158 RTW_PWR_ADDR_MAC, 1159 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1160 {0x0005, 1161 RTW_PWR_CUT_ALL_MSK, 1162 RTW_PWR_INTF_ALL_MSK, 1163 RTW_PWR_ADDR_MAC, 1164 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1165 {0x0300, 1166 RTW_PWR_CUT_ALL_MSK, 1167 RTW_PWR_INTF_PCI_MSK, 1168 RTW_PWR_ADDR_MAC, 1169 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1170 {0x0301, 1171 RTW_PWR_CUT_ALL_MSK, 1172 RTW_PWR_INTF_PCI_MSK, 1173 RTW_PWR_ADDR_MAC, 1174 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1175 {0xFFFF, 1176 RTW_PWR_CUT_ALL_MSK, 1177 RTW_PWR_INTF_ALL_MSK, 1178 0, 1179 RTW_PWR_CMD_END, 0, 0}, 1180 }; 1181 1182 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1183 {0x0020, 1184 RTW_PWR_CUT_ALL_MSK, 1185 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1186 RTW_PWR_ADDR_MAC, 1187 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1188 {0x0001, 1189 RTW_PWR_CUT_ALL_MSK, 1190 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1191 RTW_PWR_ADDR_MAC, 1192 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1193 {0x0000, 1194 RTW_PWR_CUT_ALL_MSK, 1195 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1196 RTW_PWR_ADDR_MAC, 1197 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1198 {0x0005, 1199 RTW_PWR_CUT_ALL_MSK, 1200 RTW_PWR_INTF_ALL_MSK, 1201 RTW_PWR_ADDR_MAC, 1202 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1203 {0x0075, 1204 RTW_PWR_CUT_ALL_MSK, 1205 RTW_PWR_INTF_PCI_MSK, 1206 RTW_PWR_ADDR_MAC, 1207 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1208 {0x0006, 1209 RTW_PWR_CUT_ALL_MSK, 1210 RTW_PWR_INTF_ALL_MSK, 1211 RTW_PWR_ADDR_MAC, 1212 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1213 {0x0075, 1214 RTW_PWR_CUT_ALL_MSK, 1215 RTW_PWR_INTF_PCI_MSK, 1216 RTW_PWR_ADDR_MAC, 1217 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1218 {0x0006, 1219 RTW_PWR_CUT_ALL_MSK, 1220 RTW_PWR_INTF_ALL_MSK, 1221 RTW_PWR_ADDR_MAC, 1222 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1223 {0x0005, 1224 RTW_PWR_CUT_ALL_MSK, 1225 RTW_PWR_INTF_ALL_MSK, 1226 RTW_PWR_ADDR_MAC, 1227 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1228 {0x0005, 1229 RTW_PWR_CUT_ALL_MSK, 1230 RTW_PWR_INTF_ALL_MSK, 1231 RTW_PWR_ADDR_MAC, 1232 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1233 {0x10C3, 1234 RTW_PWR_CUT_ALL_MSK, 1235 RTW_PWR_INTF_USB_MSK, 1236 RTW_PWR_ADDR_MAC, 1237 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1238 {0x0005, 1239 RTW_PWR_CUT_ALL_MSK, 1240 RTW_PWR_INTF_ALL_MSK, 1241 RTW_PWR_ADDR_MAC, 1242 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1243 {0x0005, 1244 RTW_PWR_CUT_ALL_MSK, 1245 RTW_PWR_INTF_ALL_MSK, 1246 RTW_PWR_ADDR_MAC, 1247 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1248 {0x0020, 1249 RTW_PWR_CUT_ALL_MSK, 1250 RTW_PWR_INTF_ALL_MSK, 1251 RTW_PWR_ADDR_MAC, 1252 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1253 {0x0074, 1254 RTW_PWR_CUT_ALL_MSK, 1255 RTW_PWR_INTF_PCI_MSK, 1256 RTW_PWR_ADDR_MAC, 1257 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1258 {0x0022, 1259 RTW_PWR_CUT_ALL_MSK, 1260 RTW_PWR_INTF_PCI_MSK, 1261 RTW_PWR_ADDR_MAC, 1262 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1263 {0x0062, 1264 RTW_PWR_CUT_ALL_MSK, 1265 RTW_PWR_INTF_PCI_MSK, 1266 RTW_PWR_ADDR_MAC, 1267 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1268 (BIT(7) | BIT(6) | BIT(5))}, 1269 {0x0061, 1270 RTW_PWR_CUT_ALL_MSK, 1271 RTW_PWR_INTF_PCI_MSK, 1272 RTW_PWR_ADDR_MAC, 1273 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1274 {0x007C, 1275 RTW_PWR_CUT_ALL_MSK, 1276 RTW_PWR_INTF_ALL_MSK, 1277 RTW_PWR_ADDR_MAC, 1278 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1279 {0xFFFF, 1280 RTW_PWR_CUT_ALL_MSK, 1281 RTW_PWR_INTF_ALL_MSK, 1282 0, 1283 RTW_PWR_CMD_END, 0, 0}, 1284 }; 1285 1286 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1287 {0x0093, 1288 RTW_PWR_CUT_ALL_MSK, 1289 RTW_PWR_INTF_ALL_MSK, 1290 RTW_PWR_ADDR_MAC, 1291 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1292 {0x001F, 1293 RTW_PWR_CUT_ALL_MSK, 1294 RTW_PWR_INTF_ALL_MSK, 1295 RTW_PWR_ADDR_MAC, 1296 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1297 {0x0049, 1298 RTW_PWR_CUT_ALL_MSK, 1299 RTW_PWR_INTF_ALL_MSK, 1300 RTW_PWR_ADDR_MAC, 1301 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1302 {0x0006, 1303 RTW_PWR_CUT_ALL_MSK, 1304 RTW_PWR_INTF_ALL_MSK, 1305 RTW_PWR_ADDR_MAC, 1306 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1307 {0x0002, 1308 RTW_PWR_CUT_ALL_MSK, 1309 RTW_PWR_INTF_ALL_MSK, 1310 RTW_PWR_ADDR_MAC, 1311 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1312 {0x10C3, 1313 RTW_PWR_CUT_ALL_MSK, 1314 RTW_PWR_INTF_USB_MSK, 1315 RTW_PWR_ADDR_MAC, 1316 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1317 {0x0005, 1318 RTW_PWR_CUT_ALL_MSK, 1319 RTW_PWR_INTF_ALL_MSK, 1320 RTW_PWR_ADDR_MAC, 1321 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1322 {0x0005, 1323 RTW_PWR_CUT_ALL_MSK, 1324 RTW_PWR_INTF_ALL_MSK, 1325 RTW_PWR_ADDR_MAC, 1326 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1327 {0x0020, 1328 RTW_PWR_CUT_ALL_MSK, 1329 RTW_PWR_INTF_ALL_MSK, 1330 RTW_PWR_ADDR_MAC, 1331 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1332 {0x0000, 1333 RTW_PWR_CUT_ALL_MSK, 1334 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1335 RTW_PWR_ADDR_MAC, 1336 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1337 {0xFFFF, 1338 RTW_PWR_CUT_ALL_MSK, 1339 RTW_PWR_INTF_ALL_MSK, 1340 0, 1341 RTW_PWR_CMD_END, 0, 0}, 1342 }; 1343 1344 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1345 {0x0007, 1346 RTW_PWR_CUT_ALL_MSK, 1347 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1348 RTW_PWR_ADDR_MAC, 1349 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1350 {0x0067, 1351 RTW_PWR_CUT_ALL_MSK, 1352 RTW_PWR_INTF_ALL_MSK, 1353 RTW_PWR_ADDR_MAC, 1354 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1355 {0x0005, 1356 RTW_PWR_CUT_ALL_MSK, 1357 RTW_PWR_INTF_PCI_MSK, 1358 RTW_PWR_ADDR_MAC, 1359 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1360 {0x004A, 1361 RTW_PWR_CUT_ALL_MSK, 1362 RTW_PWR_INTF_USB_MSK, 1363 RTW_PWR_ADDR_MAC, 1364 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1365 {0x0067, 1366 RTW_PWR_CUT_ALL_MSK, 1367 RTW_PWR_INTF_SDIO_MSK, 1368 RTW_PWR_ADDR_MAC, 1369 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1370 {0x0067, 1371 RTW_PWR_CUT_ALL_MSK, 1372 RTW_PWR_INTF_SDIO_MSK, 1373 RTW_PWR_ADDR_MAC, 1374 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1375 {0x004F, 1376 RTW_PWR_CUT_ALL_MSK, 1377 RTW_PWR_INTF_SDIO_MSK, 1378 RTW_PWR_ADDR_MAC, 1379 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1380 {0x0067, 1381 RTW_PWR_CUT_ALL_MSK, 1382 RTW_PWR_INTF_SDIO_MSK, 1383 RTW_PWR_ADDR_MAC, 1384 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1385 {0x0046, 1386 RTW_PWR_CUT_ALL_MSK, 1387 RTW_PWR_INTF_SDIO_MSK, 1388 RTW_PWR_ADDR_MAC, 1389 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1390 {0x0067, 1391 RTW_PWR_CUT_ALL_MSK, 1392 RTW_PWR_INTF_SDIO_MSK, 1393 RTW_PWR_ADDR_MAC, 1394 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1395 {0x0046, 1396 RTW_PWR_CUT_ALL_MSK, 1397 RTW_PWR_INTF_SDIO_MSK, 1398 RTW_PWR_ADDR_MAC, 1399 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1400 {0x0062, 1401 RTW_PWR_CUT_ALL_MSK, 1402 RTW_PWR_INTF_SDIO_MSK, 1403 RTW_PWR_ADDR_MAC, 1404 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1405 {0x0081, 1406 RTW_PWR_CUT_ALL_MSK, 1407 RTW_PWR_INTF_ALL_MSK, 1408 RTW_PWR_ADDR_MAC, 1409 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1410 {0x0005, 1411 RTW_PWR_CUT_ALL_MSK, 1412 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1413 RTW_PWR_ADDR_MAC, 1414 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1415 {0x0086, 1416 RTW_PWR_CUT_ALL_MSK, 1417 RTW_PWR_INTF_SDIO_MSK, 1418 RTW_PWR_ADDR_SDIO, 1419 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1420 {0x0086, 1421 RTW_PWR_CUT_ALL_MSK, 1422 RTW_PWR_INTF_SDIO_MSK, 1423 RTW_PWR_ADDR_SDIO, 1424 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1425 {0x0090, 1426 RTW_PWR_CUT_ALL_MSK, 1427 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1428 RTW_PWR_ADDR_MAC, 1429 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1430 {0x0044, 1431 RTW_PWR_CUT_ALL_MSK, 1432 RTW_PWR_INTF_SDIO_MSK, 1433 RTW_PWR_ADDR_SDIO, 1434 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1435 {0x0040, 1436 RTW_PWR_CUT_ALL_MSK, 1437 RTW_PWR_INTF_SDIO_MSK, 1438 RTW_PWR_ADDR_SDIO, 1439 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1440 {0x0041, 1441 RTW_PWR_CUT_ALL_MSK, 1442 RTW_PWR_INTF_SDIO_MSK, 1443 RTW_PWR_ADDR_SDIO, 1444 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1445 {0x0042, 1446 RTW_PWR_CUT_ALL_MSK, 1447 RTW_PWR_INTF_SDIO_MSK, 1448 RTW_PWR_ADDR_SDIO, 1449 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1450 {0xFFFF, 1451 RTW_PWR_CUT_ALL_MSK, 1452 RTW_PWR_INTF_ALL_MSK, 1453 0, 1454 RTW_PWR_CMD_END, 0, 0}, 1455 }; 1456 1457 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1458 trans_carddis_to_cardemu_8821c, 1459 trans_cardemu_to_act_8821c, 1460 NULL 1461 }; 1462 1463 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1464 trans_act_to_cardemu_8821c, 1465 trans_cardemu_to_carddis_8821c, 1466 NULL 1467 }; 1468 1469 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1470 {0xFFFF, 0x00, 1471 RTW_IP_SEL_PHY, 1472 RTW_INTF_PHY_CUT_ALL, 1473 RTW_INTF_PHY_PLATFORM_ALL}, 1474 }; 1475 1476 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1477 {0xFFFF, 0x0000, 1478 RTW_IP_SEL_PHY, 1479 RTW_INTF_PHY_CUT_ALL, 1480 RTW_INTF_PHY_PLATFORM_ALL}, 1481 }; 1482 1483 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1484 {0x0009, 0x6380, 1485 RTW_IP_SEL_PHY, 1486 RTW_INTF_PHY_CUT_ALL, 1487 RTW_INTF_PHY_PLATFORM_ALL}, 1488 {0xFFFF, 0x0000, 1489 RTW_IP_SEL_PHY, 1490 RTW_INTF_PHY_CUT_ALL, 1491 RTW_INTF_PHY_PLATFORM_ALL}, 1492 }; 1493 1494 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1495 {0xFFFF, 0x0000, 1496 RTW_IP_SEL_PHY, 1497 RTW_INTF_PHY_CUT_ALL, 1498 RTW_INTF_PHY_PLATFORM_ALL}, 1499 }; 1500 1501 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1502 .usb2_para = usb2_param_8821c, 1503 .usb3_para = usb3_param_8821c, 1504 .gen1_para = pcie_gen1_param_8821c, 1505 .gen2_para = pcie_gen2_param_8821c, 1506 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1507 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1508 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1509 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1510 }; 1511 1512 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1513 [0] = RTW_DEF_RFE(8821c, 0, 0), 1514 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1515 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1516 }; 1517 1518 static struct rtw_hw_reg rtw8821c_dig[] = { 1519 [0] = { .addr = 0xc50, .mask = 0x7f }, 1520 }; 1521 1522 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1523 .ctrl = LTECOEX_ACCESS_CTRL, 1524 .wdata = LTECOEX_WRITE_DATA, 1525 .rdata = LTECOEX_READ_DATA, 1526 }; 1527 1528 static struct rtw_page_table page_table_8821c[] = { 1529 /* not sure what [0] stands for */ 1530 {16, 16, 16, 14, 1}, 1531 {16, 16, 16, 14, 1}, 1532 {16, 16, 0, 0, 1}, 1533 {16, 16, 16, 0, 1}, 1534 {16, 16, 16, 14, 1}, 1535 }; 1536 1537 static struct rtw_rqpn rqpn_table_8821c[] = { 1538 /* not sure what [0] stands for */ 1539 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1540 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1541 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1542 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1543 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1544 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1545 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1546 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1547 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1548 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1549 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1550 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1551 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1552 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1553 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1554 }; 1555 1556 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1557 .prio[RTW_DMA_MAPPING_EXTRA] = { 1558 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1559 }, 1560 .prio[RTW_DMA_MAPPING_LOW] = { 1561 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1562 }, 1563 .prio[RTW_DMA_MAPPING_NORMAL] = { 1564 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1565 }, 1566 .prio[RTW_DMA_MAPPING_HIGH] = { 1567 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1568 }, 1569 .wsize = true, 1570 }; 1571 1572 static struct rtw_chip_ops rtw8821c_ops = { 1573 .phy_set_param = rtw8821c_phy_set_param, 1574 .read_efuse = rtw8821c_read_efuse, 1575 .query_rx_desc = rtw8821c_query_rx_desc, 1576 .set_channel = rtw8821c_set_channel, 1577 .mac_init = rtw8821c_mac_init, 1578 .read_rf = rtw_phy_read_rf, 1579 .write_rf = rtw_phy_write_rf_reg_sipi, 1580 .set_antenna = NULL, 1581 .set_tx_power_index = rtw8821c_set_tx_power_index, 1582 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1583 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1584 .phy_calibration = rtw8821c_phy_calibration, 1585 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1586 .pwr_track = rtw8821c_pwr_track, 1587 .config_bfee = rtw8821c_bf_config_bfee, 1588 .set_gid_table = rtw_bf_set_gid_table, 1589 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1590 1591 .coex_set_init = rtw8821c_coex_cfg_init, 1592 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1593 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1594 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1595 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1596 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1597 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1598 }; 1599 1600 /* rssi in percentage % (dbm = % - 100) */ 1601 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1602 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1603 1604 /* Shared-Antenna Coex Table */ 1605 static const struct coex_table_para table_sant_8821c[] = { 1606 {0x55555555, 0x55555555}, /* case-0 */ 1607 {0x55555555, 0x55555555}, 1608 {0x66555555, 0x66555555}, 1609 {0xaaaaaaaa, 0xaaaaaaaa}, 1610 {0x5a5a5a5a, 0x5a5a5a5a}, 1611 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1612 {0x6a5a5555, 0xaaaaaaaa}, 1613 {0x6a5a56aa, 0x6a5a56aa}, 1614 {0x6a5a5a5a, 0x6a5a5a5a}, 1615 {0x66555555, 0x5a5a5a5a}, 1616 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1617 {0x66555555, 0xaaaaaaaa}, 1618 {0x66555555, 0x6a5a5aaa}, 1619 {0x66555555, 0x6aaa6aaa}, 1620 {0x66555555, 0x6a5a5aaa}, 1621 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1622 {0xffff55ff, 0xfafafafa}, 1623 {0xffff55ff, 0x6afa5afa}, 1624 {0xaaffffaa, 0xfafafafa}, 1625 {0xaa5555aa, 0x5a5a5a5a}, 1626 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1627 {0xaa5555aa, 0xaaaaaaaa}, 1628 {0xffffffff, 0x55555555}, 1629 {0xffffffff, 0x5a5a5a5a}, 1630 {0xffffffff, 0x5a5a5a5a}, 1631 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1632 {0x55555555, 0x5a5a5a5a}, 1633 {0x55555555, 0xaaaaaaaa}, 1634 {0x66555555, 0x6a5a6a5a}, 1635 {0x66556655, 0x66556655}, 1636 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1637 {0xffffffff, 0x5aaa5aaa}, 1638 {0x56555555, 0x5a5a5aaa} 1639 }; 1640 1641 /* Non-Shared-Antenna Coex Table */ 1642 static const struct coex_table_para table_nsant_8821c[] = { 1643 {0xffffffff, 0xffffffff}, /* case-100 */ 1644 {0xffff55ff, 0xfafafafa}, 1645 {0x66555555, 0x66555555}, 1646 {0xaaaaaaaa, 0xaaaaaaaa}, 1647 {0x5a5a5a5a, 0x5a5a5a5a}, 1648 {0xffffffff, 0xffffffff}, /* case-105 */ 1649 {0x5afa5afa, 0x5afa5afa}, 1650 {0x55555555, 0xfafafafa}, 1651 {0x66555555, 0xfafafafa}, 1652 {0x66555555, 0x5a5a5a5a}, 1653 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1654 {0x66555555, 0xaaaaaaaa}, 1655 {0xffff55ff, 0xfafafafa}, 1656 {0xffff55ff, 0x5afa5afa}, 1657 {0xffff55ff, 0xaaaaaaaa}, 1658 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1659 {0xaaffffaa, 0x5afa5afa}, 1660 {0xaaffffaa, 0xaaaaaaaa}, 1661 {0xffffffff, 0xfafafafa}, 1662 {0xffff55ff, 0xfafafafa}, 1663 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1664 {0xffff55ff, 0x5afa5afa}, 1665 {0xffff55ff, 0x5afa5afa}, 1666 {0x55ff55ff, 0x55ff55ff} 1667 }; 1668 1669 /* Shared-Antenna TDMA */ 1670 static const struct coex_tdma_para tdma_sant_8821c[] = { 1671 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1672 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1673 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1674 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1675 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1676 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1677 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1678 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1679 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1680 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1681 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1682 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1683 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1684 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1685 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1686 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1687 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1688 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1689 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1690 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1691 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1692 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1693 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1694 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1695 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1696 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1697 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1698 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1699 }; 1700 1701 /* Non-Shared-Antenna TDMA */ 1702 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1703 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1704 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1705 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1706 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1707 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1708 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1709 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1710 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1711 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1712 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1713 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1714 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1715 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1716 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1717 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1718 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1719 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1720 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1721 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1722 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1723 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1724 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1725 }; 1726 1727 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1728 1729 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1730 static const struct coex_rf_para rf_para_tx_8821c[] = { 1731 {0, 0, false, 7}, /* for normal */ 1732 {0, 20, false, 7}, /* for WL-CPT */ 1733 {8, 17, true, 4}, 1734 {7, 18, true, 4}, 1735 {6, 19, true, 4}, 1736 {5, 20, true, 4} 1737 }; 1738 1739 static const struct coex_rf_para rf_para_rx_8821c[] = { 1740 {0, 0, false, 7}, /* for normal */ 1741 {0, 20, false, 7}, /* for WL-CPT */ 1742 {3, 24, true, 5}, 1743 {2, 26, true, 5}, 1744 {1, 27, true, 5}, 1745 {0, 28, true, 5} 1746 }; 1747 1748 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1749 1750 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1751 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1752 11, 11, 12, 12, 12, 12, 12}, 1753 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1754 11, 12, 12, 12, 12, 12, 12, 12}, 1755 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1756 11, 12, 12, 12, 12, 12, 12}, 1757 }; 1758 1759 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1760 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1761 12, 12, 12, 12, 12, 12, 12}, 1762 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1763 12, 12, 12, 12, 12, 12, 12, 12}, 1764 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1765 11, 12, 12, 12, 12, 12, 12, 12}, 1766 }; 1767 1768 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1769 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1770 11, 11, 12, 12, 12, 12, 12}, 1771 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1772 11, 12, 12, 12, 12, 12, 12, 12}, 1773 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1774 11, 12, 12, 12, 12, 12, 12}, 1775 }; 1776 1777 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1778 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1779 12, 12, 12, 12, 12, 12, 12}, 1780 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1781 12, 12, 12, 12, 12, 12, 12, 12}, 1782 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1783 11, 12, 12, 12, 12, 12, 12, 12}, 1784 }; 1785 1786 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1787 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1788 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1789 }; 1790 1791 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1792 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1793 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1794 }; 1795 1796 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1797 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1798 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1799 }; 1800 1801 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1802 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1803 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1804 }; 1805 1806 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1807 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1808 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1809 }; 1810 1811 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1812 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1813 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1814 }; 1815 1816 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1817 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1818 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1819 }; 1820 1821 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1822 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1823 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1824 }; 1825 1826 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1827 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1828 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1829 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1830 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1831 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1832 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1833 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1834 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1835 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1836 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1837 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1838 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1839 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1840 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1841 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1842 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1843 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1844 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1845 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1846 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1847 }; 1848 1849 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1850 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1851 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1852 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1853 {0, 0, RTW_REG_DOMAIN_NL}, 1854 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1855 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1856 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1857 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1858 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1859 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1860 {0, 0, RTW_REG_DOMAIN_NL}, 1861 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1862 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1863 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1864 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1865 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1866 {0, 0, RTW_REG_DOMAIN_NL}, 1867 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1868 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1869 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1870 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1871 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1872 }; 1873 1874 struct rtw_chip_info rtw8821c_hw_spec = { 1875 .ops = &rtw8821c_ops, 1876 .id = RTW_CHIP_TYPE_8821C, 1877 .fw_name = "rtw88/rtw8821c_fw.bin", 1878 .wlan_cpu = RTW_WCPU_11AC, 1879 .tx_pkt_desc_sz = 48, 1880 .tx_buf_desc_sz = 16, 1881 .rx_pkt_desc_sz = 24, 1882 .rx_buf_desc_sz = 8, 1883 .phy_efuse_size = 512, 1884 .log_efuse_size = 512, 1885 .ptct_efuse_size = 96, 1886 .txff_size = 65536, 1887 .rxff_size = 16384, 1888 .txgi_factor = 1, 1889 .is_pwr_by_rate_dec = true, 1890 .max_power_index = 0x3f, 1891 .csi_buf_pg_num = 0, 1892 .band = RTW_BAND_2G | RTW_BAND_5G, 1893 .page_size = 128, 1894 .dig_min = 0x1c, 1895 .ht_supported = true, 1896 .vht_supported = true, 1897 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1898 .sys_func_en = 0xD8, 1899 .pwr_on_seq = card_enable_flow_8821c, 1900 .pwr_off_seq = card_disable_flow_8821c, 1901 .page_table = page_table_8821c, 1902 .rqpn_table = rqpn_table_8821c, 1903 .prioq_addrs = &prioq_addrs_8821c, 1904 .intf_table = &phy_para_table_8821c, 1905 .dig = rtw8821c_dig, 1906 .rf_base_addr = {0x2800, 0x2c00}, 1907 .rf_sipi_addr = {0xc90, 0xe90}, 1908 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1909 .mac_tbl = &rtw8821c_mac_tbl, 1910 .agc_tbl = &rtw8821c_agc_tbl, 1911 .bb_tbl = &rtw8821c_bb_tbl, 1912 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1913 .rfe_defs = rtw8821c_rfe_defs, 1914 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1915 .rx_ldpc = false, 1916 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1917 .iqk_threshold = 8, 1918 .bfer_su_max_num = 2, 1919 .bfer_mu_max_num = 1, 1920 1921 .coex_para_ver = 0x19092746, 1922 .bt_desired_ver = 0x46, 1923 .scbd_support = true, 1924 .new_scbd10_def = false, 1925 .ble_hid_profile_support = false, 1926 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1927 .bt_rssi_type = COEX_BTRSSI_RATIO, 1928 .ant_isolation = 15, 1929 .rssi_tolerance = 2, 1930 .wl_rssi_step = wl_rssi_step_8821c, 1931 .bt_rssi_step = bt_rssi_step_8821c, 1932 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 1933 .table_sant = table_sant_8821c, 1934 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 1935 .table_nsant = table_nsant_8821c, 1936 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 1937 .tdma_sant = tdma_sant_8821c, 1938 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 1939 .tdma_nsant = tdma_nsant_8821c, 1940 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 1941 .wl_rf_para_tx = rf_para_tx_8821c, 1942 .wl_rf_para_rx = rf_para_rx_8821c, 1943 .bt_afh_span_bw20 = 0x24, 1944 .bt_afh_span_bw40 = 0x36, 1945 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 1946 .afh_5g = afh_5g_8821c, 1947 1948 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 1949 .coex_info_hw_regs = coex_info_hw_regs_8821c, 1950 }; 1951 EXPORT_SYMBOL(rtw8821c_hw_spec); 1952 1953 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 1954 1955 MODULE_AUTHOR("Realtek Corporation"); 1956 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 1957 MODULE_LICENSE("Dual BSD/GPL"); 1958