1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #include "main.h"
6 #include "coex.h"
7 #include "fw.h"
8 #include "tx.h"
9 #include "rx.h"
10 #include "phy.h"
11 #include "rtw8821c.h"
12 #include "rtw8821c_table.h"
13 #include "mac.h"
14 #include "reg.h"
15 #include "debug.h"
16 #include "bf.h"
17 #include "regd.h"
18 
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 					-20, -24, -28, -31, -34, -37, -40, -44};
22 
23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
24 				    struct rtw8821c_efuse *map)
25 {
26 	ether_addr_copy(efuse->addr, map->e.mac_addr);
27 }
28 
29 enum rtw8821ce_rf_set {
30 	SWITCH_TO_BTG,
31 	SWITCH_TO_WLG,
32 	SWITCH_TO_WLA,
33 	SWITCH_TO_BT,
34 };
35 
36 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
37 {
38 	struct rtw_efuse *efuse = &rtwdev->efuse;
39 	struct rtw8821c_efuse *map;
40 	int i;
41 
42 	map = (struct rtw8821c_efuse *)log_map;
43 
44 	efuse->rfe_option = map->rfe_option;
45 	efuse->rf_board_option = map->rf_board_option;
46 	efuse->crystal_cap = map->xtal_k;
47 	efuse->pa_type_2g = map->pa_type;
48 	efuse->pa_type_5g = map->pa_type;
49 	efuse->lna_type_2g = map->lna_type_2g[0];
50 	efuse->lna_type_5g = map->lna_type_5g[0];
51 	efuse->channel_plan = map->channel_plan;
52 	efuse->country_code[0] = map->country_code[0];
53 	efuse->country_code[1] = map->country_code[1];
54 	efuse->bt_setting = map->rf_bt_setting;
55 	efuse->regd = map->rf_board_option & 0x7;
56 	efuse->thermal_meter[0] = map->thermal_meter;
57 	efuse->thermal_meter_k = map->thermal_meter;
58 	efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
59 	efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
60 
61 	for (i = 0; i < 4; i++)
62 		efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
63 
64 	if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
65 		efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
66 
67 	switch (rtw_hci_type(rtwdev)) {
68 	case RTW_HCI_TYPE_PCIE:
69 		rtw8821ce_efuse_parsing(efuse, map);
70 		break;
71 	default:
72 		/* unsupported now */
73 		return -ENOTSUPP;
74 	}
75 
76 	return 0;
77 }
78 
79 static const u32 rtw8821c_txscale_tbl[] = {
80 	0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
81 	0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
82 	0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
83 	0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
84 };
85 
86 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
87 {
88 	u8 i = 0;
89 	u32 swing, table_value;
90 
91 	swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
92 	for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
93 		table_value = rtw8821c_txscale_tbl[i];
94 		if (swing == table_value)
95 			break;
96 	}
97 
98 	return i;
99 }
100 
101 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
102 {
103 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
104 	u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
105 
106 	if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
107 		dm_info->default_ofdm_index = 24;
108 	else
109 		dm_info->default_ofdm_index = swing_idx;
110 
111 	ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
112 	dm_info->delta_power_index[RF_PATH_A] = 0;
113 	dm_info->delta_power_index_last[RF_PATH_A] = 0;
114 	dm_info->pwr_trk_triggered = false;
115 	dm_info->pwr_trk_init_trigger = true;
116 	dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
117 }
118 
119 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
120 {
121 	rtw_bf_phy_init(rtwdev);
122 	/* Grouping bitmap parameters */
123 	rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
124 }
125 
126 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
127 {
128 	u8 crystal_cap, val;
129 
130 	/* power on BB/RF domain */
131 	val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
132 	val |= BIT_FEN_PCIEA;
133 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
134 
135 	/* toggle BB reset */
136 	val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
137 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
138 	val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
139 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
140 	val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
141 	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
142 
143 	rtw_write8(rtwdev, REG_RF_CTRL,
144 		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
145 	usleep_range(10, 11);
146 	rtw_write8(rtwdev, REG_WLRF1 + 3,
147 		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
148 	usleep_range(10, 11);
149 
150 	/* pre init before header files config */
151 	rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
152 
153 	rtw_phy_load_tables(rtwdev);
154 
155 	crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
156 	rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
157 	rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
158 	rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
159 
160 	/* post init after header files config */
161 	rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
162 	rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
163 	rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
164 	rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
165 
166 	rtw_phy_init(rtwdev);
167 	rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
168 
169 	rtw8821c_pwrtrack_init(rtwdev);
170 
171 	rtw8821c_phy_bf_init(rtwdev);
172 }
173 
174 static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
175 {
176 	u32 value32;
177 	u16 pre_txcnt;
178 
179 	/* protocol configuration */
180 	rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
181 	rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
182 	pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
183 	rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
184 	rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
185 	value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
186 		  (WLAN_MAX_AGG_PKT_LIMIT << 16) |
187 		  (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
188 	rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
189 	rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
190 		    WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
191 	rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
192 	rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
193 	rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
194 	rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
195 	rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
196 
197 	/* EDCA configuration */
198 	rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
199 	rtw_write16(rtwdev, REG_TXPAUSE, 0);
200 	rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
201 	rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
202 	rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
203 	rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
204 	rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
205 	rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
206 	rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
207 
208 	/* Set beacon cotnrol - enable TSF and other related functions */
209 	rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
210 
211 	/* Set send beacon related registers */
212 	rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
213 	rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
214 	rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
215 	rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
216 
217 	/* WMAC configuration */
218 	rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
219 	rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
220 	rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
221 	rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
222 	rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
223 	rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
224 	rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
225 	rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
226 	rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
227 		       BIT_DIS_CHK_VHTSIGB_CRC);
228 	rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
229 	rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
230 
231 	return 0;
232 }
233 
234 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
235 {
236 	u8 ldo_pwr;
237 
238 	ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
239 	ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
240 	rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
241 }
242 
243 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
244 {
245 	u32 reg;
246 
247 	rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
248 	rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
249 
250 	reg = rtw_read32(rtwdev, REG_RFECTL);
251 	switch (rf_set) {
252 	case SWITCH_TO_BTG:
253 		reg |= B_BTG_SWITCH;
254 		reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH |
255 			 B_WLA_SWITCH);
256 		rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
257 		rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
258 		break;
259 	case SWITCH_TO_WLG:
260 		reg |= B_WL_SWITCH | B_WLG_SWITCH;
261 		reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH);
262 		rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
263 		rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
264 		break;
265 	case SWITCH_TO_WLA:
266 		reg |= B_WL_SWITCH | B_WLA_SWITCH;
267 		reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH);
268 		break;
269 	case SWITCH_TO_BT:
270 	default:
271 		break;
272 	}
273 
274 	rtw_write32(rtwdev, REG_RFECTL, reg);
275 }
276 
277 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
278 {
279 	u32 rf_reg18;
280 
281 	rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
282 
283 	rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
284 		      RF18_BW_MASK);
285 
286 	rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
287 	rf_reg18 |= (channel & RF18_CHANNEL_MASK);
288 
289 	if (channel >= 100 && channel <= 140)
290 		rf_reg18 |= RF18_RFSI_GE;
291 	else if (channel > 140)
292 		rf_reg18 |= RF18_RFSI_GT;
293 
294 	switch (bw) {
295 	case RTW_CHANNEL_WIDTH_5:
296 	case RTW_CHANNEL_WIDTH_10:
297 	case RTW_CHANNEL_WIDTH_20:
298 	default:
299 		rf_reg18 |= RF18_BW_20M;
300 		break;
301 	case RTW_CHANNEL_WIDTH_40:
302 		rf_reg18 |= RF18_BW_40M;
303 		break;
304 	case RTW_CHANNEL_WIDTH_80:
305 		rf_reg18 |= RF18_BW_80M;
306 		break;
307 	}
308 
309 	if (channel <= 14) {
310 		if (rtwdev->efuse.rfe_option == 0)
311 			rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
312 		else if (rtwdev->efuse.rfe_option == 2 ||
313 			 rtwdev->efuse.rfe_option == 4)
314 			rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
315 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
316 		rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
317 	} else {
318 		rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
319 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
320 	}
321 
322 	rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
323 
324 	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
325 	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
326 }
327 
328 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
329 {
330 	if (bw == RTW_CHANNEL_WIDTH_40) {
331 		/* RX DFIR for BW40 */
332 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
333 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
334 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
335 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
336 	} else if (bw == RTW_CHANNEL_WIDTH_80) {
337 		/* RX DFIR for BW80 */
338 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
339 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
340 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
341 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
342 	} else {
343 		/* RX DFIR for BW20, BW10 and BW5 */
344 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
345 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
346 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
347 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
348 	}
349 }
350 
351 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
352 				    u8 primary_ch_idx)
353 {
354 	u32 val32;
355 
356 	if (channel <= 14) {
357 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
358 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
359 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
360 		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
361 
362 		rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
363 		rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
364 		if (channel == 14) {
365 			rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
366 			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
367 			rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
368 		} else {
369 			rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
370 					 rtwdev->chip->ch_param[0]);
371 			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
372 					 rtwdev->chip->ch_param[1] & MASKLWORD);
373 			rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
374 					 rtwdev->chip->ch_param[2]);
375 		}
376 	} else if (channel > 35) {
377 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
378 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
379 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
380 		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
381 
382 		if (channel >= 36 && channel <= 64)
383 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
384 		else if (channel >= 100 && channel <= 144)
385 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
386 		else if (channel >= 149)
387 			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
388 
389 		if (channel >= 36 && channel <= 48)
390 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
391 		else if (channel >= 52 && channel <= 64)
392 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
393 		else if (channel >= 100 && channel <= 116)
394 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
395 		else if (channel >= 118 && channel <= 177)
396 			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
397 	}
398 
399 	switch (bw) {
400 	case RTW_CHANNEL_WIDTH_20:
401 	default:
402 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
403 		val32 &= 0xffcffc00;
404 		val32 |= 0x10010000;
405 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
406 
407 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
408 		break;
409 	case RTW_CHANNEL_WIDTH_40:
410 		if (primary_ch_idx == 1)
411 			rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
412 		else
413 			rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
414 
415 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
416 		val32 &= 0xff3ff300;
417 		val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
418 			 RTW_CHANNEL_WIDTH_40;
419 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
420 
421 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
422 		break;
423 	case RTW_CHANNEL_WIDTH_80:
424 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
425 		val32 &= 0xfcffcf00;
426 		val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
427 			 RTW_CHANNEL_WIDTH_80;
428 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
429 
430 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
431 		break;
432 	case RTW_CHANNEL_WIDTH_5:
433 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
434 		val32 &= 0xefcefc00;
435 		val32 |= 0x200240;
436 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
437 
438 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
439 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
440 		break;
441 	case RTW_CHANNEL_WIDTH_10:
442 		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
443 		val32 &= 0xefcefc00;
444 		val32 |= 0x300380;
445 		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
446 
447 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
448 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
449 		break;
450 	}
451 }
452 
453 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
454 {
455 	struct rtw_efuse efuse = rtwdev->efuse;
456 	u8 tx_bb_swing;
457 	u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
458 
459 	tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
460 				      efuse.tx_bb_swing_setting_5g;
461 	if (tx_bb_swing > 9)
462 		tx_bb_swing = 0;
463 
464 	return swing2setting[(tx_bb_swing / 3)];
465 }
466 
467 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
468 					  u8 bw, u8 primary_ch_idx)
469 {
470 	rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
471 			 rtw8821c_get_bb_swing(rtwdev, channel));
472 	rtw8821c_pwrtrack_init(rtwdev);
473 }
474 
475 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
476 				 u8 primary_chan_idx)
477 {
478 	rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
479 	rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
480 	rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
481 	rtw8821c_set_channel_rf(rtwdev, channel, bw);
482 	rtw8821c_set_channel_rxdfir(rtwdev, bw);
483 }
484 
485 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
486 {
487 	struct rtw_efuse *efuse = &rtwdev->efuse;
488 	const s8 *lna_gain_table;
489 	int lna_gain_table_size;
490 	s8 rx_pwr_all = 0;
491 	s8 lna_gain = 0;
492 
493 	if (efuse->rfe_option == 0) {
494 		lna_gain_table = lna_gain_table_0;
495 		lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0);
496 	} else {
497 		lna_gain_table = lna_gain_table_1;
498 		lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1);
499 	}
500 
501 	if (lna_idx >= lna_gain_table_size) {
502 		rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
503 		return -120;
504 	}
505 
506 	lna_gain = lna_gain_table[lna_idx];
507 	rx_pwr_all = lna_gain - 2 * vga_idx;
508 
509 	return rx_pwr_all;
510 }
511 
512 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
513 				   struct rtw_rx_pkt_stat *pkt_stat)
514 {
515 	s8 rx_power;
516 	u8 lna_idx = 0;
517 	u8 vga_idx = 0;
518 
519 	vga_idx = GET_PHY_STAT_P0_VGA(phy_status);
520 	lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) |
521 		  FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status));
522 	rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
523 
524 	pkt_stat->rx_power[RF_PATH_A] = rx_power;
525 	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
526 	pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
527 	pkt_stat->signal_power = rx_power;
528 }
529 
530 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
531 				   struct rtw_rx_pkt_stat *pkt_stat)
532 {
533 	u8 rxsc, bw;
534 	s8 min_rx_power = -120;
535 
536 	if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
537 		rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
538 	else
539 		rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
540 
541 	if (rxsc >= 1 && rxsc <= 8)
542 		bw = RTW_CHANNEL_WIDTH_20;
543 	else if (rxsc >= 9 && rxsc <= 12)
544 		bw = RTW_CHANNEL_WIDTH_40;
545 	else if (rxsc >= 13)
546 		bw = RTW_CHANNEL_WIDTH_80;
547 	else
548 		bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
549 
550 	pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
551 	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
552 	pkt_stat->bw = bw;
553 	pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
554 				     min_rx_power);
555 }
556 
557 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
558 			     struct rtw_rx_pkt_stat *pkt_stat)
559 {
560 	u8 page;
561 
562 	page = *phy_status & 0xf;
563 
564 	switch (page) {
565 	case 0:
566 		query_phy_status_page0(rtwdev, phy_status, pkt_stat);
567 		break;
568 	case 1:
569 		query_phy_status_page1(rtwdev, phy_status, pkt_stat);
570 		break;
571 	default:
572 		rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
573 		return;
574 	}
575 }
576 
577 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
578 				   struct rtw_rx_pkt_stat *pkt_stat,
579 				   struct ieee80211_rx_status *rx_status)
580 {
581 	struct ieee80211_hdr *hdr;
582 	u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
583 	u8 *phy_status = NULL;
584 
585 	memset(pkt_stat, 0, sizeof(*pkt_stat));
586 
587 	pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
588 	pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
589 	pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
590 	pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
591 			      GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
592 	pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
593 	pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
594 	pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
595 	pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
596 	pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
597 	pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
598 	pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
599 	pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
600 
601 	/* drv_info_sz is in unit of 8-bytes */
602 	pkt_stat->drv_info_sz *= 8;
603 
604 	/* c2h cmd pkt's rx/phy status is not interested */
605 	if (pkt_stat->is_c2h)
606 		return;
607 
608 	hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
609 				       pkt_stat->drv_info_sz);
610 	if (pkt_stat->phy_status) {
611 		phy_status = rx_desc + desc_sz + pkt_stat->shift;
612 		query_phy_status(rtwdev, phy_status, pkt_stat);
613 	}
614 
615 	rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
616 }
617 
618 static void
619 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
620 {
621 	struct rtw_hal *hal = &rtwdev->hal;
622 	static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
623 	static u32 phy_pwr_idx;
624 	u8 rate, rate_idx, pwr_index, shift;
625 	int j;
626 
627 	for (j = 0; j < rtw_rate_size[rs]; j++) {
628 		rate = rtw_rate_section[rs][j];
629 		pwr_index = hal->tx_pwr_tbl[path][rate];
630 		shift = rate & 0x3;
631 		phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
632 		if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
633 			rate_idx = rate & 0xfc;
634 			rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
635 				    phy_pwr_idx);
636 			phy_pwr_idx = 0;
637 		}
638 	}
639 }
640 
641 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
642 {
643 	struct rtw_hal *hal = &rtwdev->hal;
644 	int rs, path;
645 
646 	for (path = 0; path < hal->rf_path_num; path++) {
647 		for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
648 			if (rs == RTW_RATE_SECTION_HT_2S ||
649 			    rs == RTW_RATE_SECTION_VHT_2S)
650 				continue;
651 			rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs);
652 		}
653 	}
654 }
655 
656 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
657 {
658 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
659 	u32 cck_enable;
660 	u32 cck_fa_cnt;
661 	u32 ofdm_fa_cnt;
662 	u32 crc32_cnt;
663 	u32 cca32_cnt;
664 
665 	cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
666 	cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
667 	ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
668 
669 	dm_info->cck_fa_cnt = cck_fa_cnt;
670 	dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
671 	if (cck_enable)
672 		dm_info->total_fa_cnt += cck_fa_cnt;
673 	dm_info->total_fa_cnt = ofdm_fa_cnt;
674 
675 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
676 	dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
677 	dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
678 
679 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
680 	dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
681 	dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
682 
683 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
684 	dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
685 	dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
686 
687 	crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
688 	dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
689 	dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
690 
691 	cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
692 	dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
693 	dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
694 	if (cck_enable) {
695 		cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
696 		dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
697 		dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
698 	}
699 
700 	rtw_write32_set(rtwdev, REG_FAS, BIT(17));
701 	rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
702 	rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
703 	rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
704 	rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
705 	rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
706 }
707 
708 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
709 {
710 	static int do_iqk_cnt;
711 	struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
712 	u32 rf_reg, iqk_fail_mask;
713 	int counter;
714 	bool reload;
715 
716 	if (rtw_is_assoc(rtwdev))
717 		para.segment_iqk = 1;
718 
719 	rtw_fw_do_iqk(rtwdev, &para);
720 
721 	for (counter = 0; counter < 300; counter++) {
722 		rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
723 		if (rf_reg == 0xabcde)
724 			break;
725 		msleep(20);
726 	}
727 	rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
728 
729 	reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
730 	iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
731 	rtw_dbg(rtwdev, RTW_DBG_PHY,
732 		"iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
733 		counter, reload, ++do_iqk_cnt, iqk_fail_mask);
734 }
735 
736 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
737 {
738 	rtw8821c_do_iqk(rtwdev);
739 }
740 
741 /* for coex */
742 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
743 {
744 	/* enable TBTT nterrupt */
745 	rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
746 
747 	/* BT report packet sample rate */
748 	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
749 
750 	/* enable BT counter statistics */
751 	rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
752 
753 	/* enable PTA (3-wire function form BT side) */
754 	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
755 	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
756 
757 	/* enable PTA (tx/rx signal form WiFi side) */
758 	rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
759 	/* wl tx signal to PTA not case EDCCA */
760 	rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
761 	/* GNT_BT=1 while select both */
762 	rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
763 
764 	/* beacon queue always hi-pri  */
765 	rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
766 			BCN_PRI_EN);
767 }
768 
769 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
770 					 u8 pos_type)
771 {
772 	struct rtw_coex *coex = &rtwdev->coex;
773 	struct rtw_coex_dm *coex_dm = &coex->dm;
774 	struct rtw_coex_rfe *coex_rfe = &coex->rfe;
775 	u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type;
776 	bool polarity_inverse;
777 	u8 regval = 0;
778 
779 	if (switch_status == coex_dm->cur_switch_status)
780 		return;
781 
782 	if (coex_rfe->wlg_at_btg) {
783 		ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
784 
785 		if (coex_rfe->ant_switch_polarity)
786 			pos_type = COEX_SWITCH_TO_WLA;
787 		else
788 			pos_type = COEX_SWITCH_TO_WLG_BT;
789 	}
790 
791 	coex_dm->cur_switch_status = switch_status;
792 
793 	if (coex_rfe->ant_switch_diversity &&
794 	    ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
795 		ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
796 
797 	polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
798 
799 	switch (ctrl_type) {
800 	default:
801 	case COEX_SWITCH_CTRL_BY_BBSW:
802 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
803 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
804 		/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
805 		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
806 				DPDT_CTRL_PIN);
807 
808 		if (pos_type == COEX_SWITCH_TO_WLG_BT) {
809 			if (coex_rfe->rfe_module_type != 0x4 &&
810 			    coex_rfe->rfe_module_type != 0x2)
811 				regval = 0x3;
812 			else
813 				regval = (!polarity_inverse ? 0x2 : 0x1);
814 		} else if (pos_type == COEX_SWITCH_TO_WLG) {
815 			regval = (!polarity_inverse ? 0x2 : 0x1);
816 		} else {
817 			regval = (!polarity_inverse ? 0x1 : 0x2);
818 		}
819 
820 		rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
821 				 regval);
822 		break;
823 	case COEX_SWITCH_CTRL_BY_PTA:
824 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
825 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
826 		/* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
827 		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
828 				PTA_CTRL_PIN);
829 
830 		regval = (!polarity_inverse ? 0x2 : 0x1);
831 		rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
832 				 regval);
833 		break;
834 	case COEX_SWITCH_CTRL_BY_ANTDIV:
835 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
836 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
837 		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
838 				ANTDIC_CTRL_PIN);
839 		break;
840 	case COEX_SWITCH_CTRL_BY_MAC:
841 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
842 
843 		regval = (!polarity_inverse ? 0x0 : 0x1);
844 		rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
845 				regval);
846 		break;
847 	case COEX_SWITCH_CTRL_BY_FW:
848 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
849 		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
850 		break;
851 	case COEX_SWITCH_CTRL_BY_BT:
852 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
853 		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
854 		break;
855 	}
856 
857 	if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
858 		rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
859 		rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
860 	} else {
861 		rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
862 		rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
863 	}
864 }
865 
866 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
867 {}
868 
869 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
870 {
871 	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
872 	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
873 	rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
874 	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
875 	rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
876 	rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
877 }
878 
879 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
880 {
881 	struct rtw_coex *coex = &rtwdev->coex;
882 	struct rtw_coex_rfe *coex_rfe = &coex->rfe;
883 	struct rtw_efuse *efuse = &rtwdev->efuse;
884 
885 	coex_rfe->rfe_module_type = efuse->rfe_option;
886 	coex_rfe->ant_switch_polarity = 0;
887 	coex_rfe->ant_switch_exist = true;
888 	coex_rfe->wlg_at_btg = false;
889 
890 	switch (coex_rfe->rfe_module_type) {
891 	case 0:
892 	case 8:
893 	case 1:
894 	case 9:  /* 1-Ant, Main, WLG */
895 	default: /* 2-Ant, DPDT, WLG */
896 		break;
897 	case 2:
898 	case 10: /* 1-Ant, Main, BTG */
899 	case 7:
900 	case 15: /* 2-Ant, DPDT, BTG */
901 		coex_rfe->wlg_at_btg = true;
902 		break;
903 	case 3:
904 	case 11: /* 1-Ant, Aux, WLG */
905 		coex_rfe->ant_switch_polarity = 1;
906 		break;
907 	case 4:
908 	case 12: /* 1-Ant, Aux, BTG */
909 		coex_rfe->wlg_at_btg = true;
910 		coex_rfe->ant_switch_polarity = 1;
911 		break;
912 	case 5:
913 	case 13: /* 2-Ant, no switch, WLG */
914 	case 6:
915 	case 14: /* 2-Ant, no antenna switch, WLG */
916 		coex_rfe->ant_switch_exist = false;
917 		break;
918 	}
919 }
920 
921 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
922 {
923 	struct rtw_coex *coex = &rtwdev->coex;
924 	struct rtw_coex_dm *coex_dm = &coex->dm;
925 	struct rtw_efuse *efuse = &rtwdev->efuse;
926 	bool share_ant = efuse->share_ant;
927 
928 	if (share_ant)
929 		return;
930 
931 	if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
932 		return;
933 
934 	coex_dm->cur_wl_pwr_lvl = wl_pwr;
935 }
936 
937 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
938 {}
939 
940 static void
941 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
942 			    s8 pwr_idx_offset_lower,
943 			    s8 *txagc_idx, u8 *swing_idx)
944 {
945 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
946 	s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
947 	u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
948 	u8 swing_lower_bound = 0;
949 	u8 max_pwr_idx_offset = 0xf;
950 	s8 agc_index = 0;
951 	u8 swing_index = dm_info->default_ofdm_index;
952 
953 	pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset);
954 	pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
955 
956 	if (delta_pwr_idx >= 0) {
957 		if (delta_pwr_idx <= pwr_idx_offset) {
958 			agc_index = delta_pwr_idx;
959 			swing_index = dm_info->default_ofdm_index;
960 		} else if (delta_pwr_idx > pwr_idx_offset) {
961 			agc_index = pwr_idx_offset;
962 			swing_index = dm_info->default_ofdm_index +
963 					delta_pwr_idx - pwr_idx_offset;
964 			swing_index = min_t(u8, swing_index, swing_upper_bound);
965 		}
966 	} else if (delta_pwr_idx < 0) {
967 		if (delta_pwr_idx >= pwr_idx_offset_lower) {
968 			agc_index = delta_pwr_idx;
969 			swing_index = dm_info->default_ofdm_index;
970 		} else if (delta_pwr_idx < pwr_idx_offset_lower) {
971 			if (dm_info->default_ofdm_index >
972 				(pwr_idx_offset_lower - delta_pwr_idx))
973 				swing_index = dm_info->default_ofdm_index +
974 					delta_pwr_idx - pwr_idx_offset_lower;
975 			else
976 				swing_index = swing_lower_bound;
977 
978 			agc_index = pwr_idx_offset_lower;
979 		}
980 	}
981 
982 	if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) {
983 		rtw_warn(rtwdev, "swing index overflow\n");
984 		swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
985 	}
986 
987 	*txagc_idx = agc_index;
988 	*swing_idx = swing_index;
989 }
990 
991 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
992 				      s8 pwr_idx_offset_lower)
993 {
994 	s8 txagc_idx;
995 	u8 swing_idx;
996 
997 	rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
998 				    &txagc_idx, &swing_idx);
999 	rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
1000 	rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
1001 			 rtw8821c_txscale_tbl[swing_idx]);
1002 }
1003 
1004 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
1005 {
1006 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1007 	u8 pwr_idx_offset, tx_pwr_idx;
1008 	s8 pwr_idx_offset_lower;
1009 	u8 channel = rtwdev->hal.current_channel;
1010 	u8 band_width = rtwdev->hal.current_band_width;
1011 	u8 regd = rtw_regd_get(rtwdev);
1012 	u8 tx_rate = dm_info->tx_rate;
1013 	u8 max_pwr_idx = rtwdev->chip->max_power_index;
1014 
1015 	tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
1016 						band_width, channel, regd);
1017 
1018 	tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1019 
1020 	pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1021 	pwr_idx_offset_lower = 0 - tx_pwr_idx;
1022 
1023 	rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
1024 }
1025 
1026 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
1027 {
1028 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1029 	struct rtw_swing_table swing_table;
1030 	u8 thermal_value, delta;
1031 
1032 	rtw_phy_config_swing_table(rtwdev, &swing_table);
1033 
1034 	if (rtwdev->efuse.thermal_meter[0] == 0xff)
1035 		return;
1036 
1037 	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1038 
1039 	rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1040 
1041 	if (dm_info->pwr_trk_init_trigger)
1042 		dm_info->pwr_trk_init_trigger = false;
1043 	else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1044 						   RF_PATH_A))
1045 		goto iqk;
1046 
1047 	delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1048 
1049 	delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1050 
1051 	dm_info->delta_power_index[RF_PATH_A] =
1052 		rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
1053 					    RF_PATH_A, delta);
1054 	if (dm_info->delta_power_index[RF_PATH_A] ==
1055 			dm_info->delta_power_index_last[RF_PATH_A])
1056 		goto iqk;
1057 	else
1058 		dm_info->delta_power_index_last[RF_PATH_A] =
1059 			dm_info->delta_power_index[RF_PATH_A];
1060 	rtw8821c_pwrtrack_set(rtwdev);
1061 
1062 iqk:
1063 	if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1064 		rtw8821c_do_iqk(rtwdev);
1065 }
1066 
1067 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
1068 {
1069 	struct rtw_efuse *efuse = &rtwdev->efuse;
1070 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1071 
1072 	if (efuse->power_track_type != 0)
1073 		return;
1074 
1075 	if (!dm_info->pwr_trk_triggered) {
1076 		rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1077 			     GENMASK(17, 16), 0x03);
1078 		dm_info->pwr_trk_triggered = true;
1079 		return;
1080 	}
1081 
1082 	rtw8821c_phy_pwrtrack(rtwdev);
1083 	dm_info->pwr_trk_triggered = false;
1084 }
1085 
1086 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev,
1087 				       struct rtw_vif *vif,
1088 				       struct rtw_bfee *bfee, bool enable)
1089 {
1090 	if (enable)
1091 		rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1092 	else
1093 		rtw_bf_remove_bfee_su(rtwdev, bfee);
1094 }
1095 
1096 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1097 				       struct rtw_vif *vif,
1098 				       struct rtw_bfee *bfee, bool enable)
1099 {
1100 	if (enable)
1101 		rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1102 	else
1103 		rtw_bf_remove_bfee_mu(rtwdev, bfee);
1104 }
1105 
1106 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1107 				    struct rtw_bfee *bfee, bool enable)
1108 {
1109 	if (bfee->role == RTW_BFEE_SU)
1110 		rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1111 	else if (bfee->role == RTW_BFEE_MU)
1112 		rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1113 	else
1114 		rtw_warn(rtwdev, "wrong bfee role\n");
1115 }
1116 
1117 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1118 {
1119 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1120 	u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1121 	u8 cck_n_rx;
1122 
1123 	rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1124 		dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1125 
1126 	if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1127 		return;
1128 
1129 	cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1130 		    rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1131 	rtw_dbg(rtwdev, RTW_DBG_PHY,
1132 		"is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1133 		rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1134 		dm_info->cck_pd_default + new_lvl * 2,
1135 		pd[new_lvl], dm_info->cck_fa_avg);
1136 
1137 	dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1138 
1139 	dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1140 	rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1141 	rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1142 			 dm_info->cck_pd_default + new_lvl * 2);
1143 }
1144 
1145 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1146 	{0x0086,
1147 	 RTW_PWR_CUT_ALL_MSK,
1148 	 RTW_PWR_INTF_SDIO_MSK,
1149 	 RTW_PWR_ADDR_SDIO,
1150 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1151 	{0x0086,
1152 	 RTW_PWR_CUT_ALL_MSK,
1153 	 RTW_PWR_INTF_SDIO_MSK,
1154 	 RTW_PWR_ADDR_SDIO,
1155 	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1156 	{0x004A,
1157 	 RTW_PWR_CUT_ALL_MSK,
1158 	 RTW_PWR_INTF_USB_MSK,
1159 	 RTW_PWR_ADDR_MAC,
1160 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1161 	{0x0005,
1162 	 RTW_PWR_CUT_ALL_MSK,
1163 	 RTW_PWR_INTF_ALL_MSK,
1164 	 RTW_PWR_ADDR_MAC,
1165 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1166 	{0x0300,
1167 	 RTW_PWR_CUT_ALL_MSK,
1168 	 RTW_PWR_INTF_PCI_MSK,
1169 	 RTW_PWR_ADDR_MAC,
1170 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1171 	{0x0301,
1172 	 RTW_PWR_CUT_ALL_MSK,
1173 	 RTW_PWR_INTF_PCI_MSK,
1174 	 RTW_PWR_ADDR_MAC,
1175 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1176 	{0xFFFF,
1177 	 RTW_PWR_CUT_ALL_MSK,
1178 	 RTW_PWR_INTF_ALL_MSK,
1179 	 0,
1180 	 RTW_PWR_CMD_END, 0, 0},
1181 };
1182 
1183 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
1184 	{0x0020,
1185 	 RTW_PWR_CUT_ALL_MSK,
1186 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1187 	 RTW_PWR_ADDR_MAC,
1188 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1189 	{0x0001,
1190 	 RTW_PWR_CUT_ALL_MSK,
1191 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1192 	 RTW_PWR_ADDR_MAC,
1193 	 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1194 	{0x0000,
1195 	 RTW_PWR_CUT_ALL_MSK,
1196 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1197 	 RTW_PWR_ADDR_MAC,
1198 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1199 	{0x0005,
1200 	 RTW_PWR_CUT_ALL_MSK,
1201 	 RTW_PWR_INTF_ALL_MSK,
1202 	 RTW_PWR_ADDR_MAC,
1203 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1204 	{0x0075,
1205 	 RTW_PWR_CUT_ALL_MSK,
1206 	 RTW_PWR_INTF_PCI_MSK,
1207 	 RTW_PWR_ADDR_MAC,
1208 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1209 	{0x0006,
1210 	 RTW_PWR_CUT_ALL_MSK,
1211 	 RTW_PWR_INTF_ALL_MSK,
1212 	 RTW_PWR_ADDR_MAC,
1213 	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1214 	{0x0075,
1215 	 RTW_PWR_CUT_ALL_MSK,
1216 	 RTW_PWR_INTF_PCI_MSK,
1217 	 RTW_PWR_ADDR_MAC,
1218 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1219 	{0x0006,
1220 	 RTW_PWR_CUT_ALL_MSK,
1221 	 RTW_PWR_INTF_ALL_MSK,
1222 	 RTW_PWR_ADDR_MAC,
1223 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1224 	{0x0005,
1225 	 RTW_PWR_CUT_ALL_MSK,
1226 	 RTW_PWR_INTF_ALL_MSK,
1227 	 RTW_PWR_ADDR_MAC,
1228 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
1229 	{0x0005,
1230 	 RTW_PWR_CUT_ALL_MSK,
1231 	 RTW_PWR_INTF_ALL_MSK,
1232 	 RTW_PWR_ADDR_MAC,
1233 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1234 	{0x10C3,
1235 	 RTW_PWR_CUT_ALL_MSK,
1236 	 RTW_PWR_INTF_USB_MSK,
1237 	 RTW_PWR_ADDR_MAC,
1238 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1239 	{0x0005,
1240 	 RTW_PWR_CUT_ALL_MSK,
1241 	 RTW_PWR_INTF_ALL_MSK,
1242 	 RTW_PWR_ADDR_MAC,
1243 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1244 	{0x0005,
1245 	 RTW_PWR_CUT_ALL_MSK,
1246 	 RTW_PWR_INTF_ALL_MSK,
1247 	 RTW_PWR_ADDR_MAC,
1248 	 RTW_PWR_CMD_POLLING, BIT(0), 0},
1249 	{0x0020,
1250 	 RTW_PWR_CUT_ALL_MSK,
1251 	 RTW_PWR_INTF_ALL_MSK,
1252 	 RTW_PWR_ADDR_MAC,
1253 	 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1254 	{0x0074,
1255 	 RTW_PWR_CUT_ALL_MSK,
1256 	 RTW_PWR_INTF_PCI_MSK,
1257 	 RTW_PWR_ADDR_MAC,
1258 	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1259 	{0x0022,
1260 	 RTW_PWR_CUT_ALL_MSK,
1261 	 RTW_PWR_INTF_PCI_MSK,
1262 	 RTW_PWR_ADDR_MAC,
1263 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1264 	{0x0062,
1265 	 RTW_PWR_CUT_ALL_MSK,
1266 	 RTW_PWR_INTF_PCI_MSK,
1267 	 RTW_PWR_ADDR_MAC,
1268 	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1269 	 (BIT(7) | BIT(6) | BIT(5))},
1270 	{0x0061,
1271 	 RTW_PWR_CUT_ALL_MSK,
1272 	 RTW_PWR_INTF_PCI_MSK,
1273 	 RTW_PWR_ADDR_MAC,
1274 	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1275 	{0x007C,
1276 	 RTW_PWR_CUT_ALL_MSK,
1277 	 RTW_PWR_INTF_ALL_MSK,
1278 	 RTW_PWR_ADDR_MAC,
1279 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1280 	{0xFFFF,
1281 	 RTW_PWR_CUT_ALL_MSK,
1282 	 RTW_PWR_INTF_ALL_MSK,
1283 	 0,
1284 	 RTW_PWR_CMD_END, 0, 0},
1285 };
1286 
1287 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
1288 	{0x0093,
1289 	 RTW_PWR_CUT_ALL_MSK,
1290 	 RTW_PWR_INTF_ALL_MSK,
1291 	 RTW_PWR_ADDR_MAC,
1292 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1293 	{0x001F,
1294 	 RTW_PWR_CUT_ALL_MSK,
1295 	 RTW_PWR_INTF_ALL_MSK,
1296 	 RTW_PWR_ADDR_MAC,
1297 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1298 	{0x0049,
1299 	 RTW_PWR_CUT_ALL_MSK,
1300 	 RTW_PWR_INTF_ALL_MSK,
1301 	 RTW_PWR_ADDR_MAC,
1302 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1303 	{0x0006,
1304 	 RTW_PWR_CUT_ALL_MSK,
1305 	 RTW_PWR_INTF_ALL_MSK,
1306 	 RTW_PWR_ADDR_MAC,
1307 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1308 	{0x0002,
1309 	 RTW_PWR_CUT_ALL_MSK,
1310 	 RTW_PWR_INTF_ALL_MSK,
1311 	 RTW_PWR_ADDR_MAC,
1312 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1313 	{0x10C3,
1314 	 RTW_PWR_CUT_ALL_MSK,
1315 	 RTW_PWR_INTF_USB_MSK,
1316 	 RTW_PWR_ADDR_MAC,
1317 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1318 	{0x0005,
1319 	 RTW_PWR_CUT_ALL_MSK,
1320 	 RTW_PWR_INTF_ALL_MSK,
1321 	 RTW_PWR_ADDR_MAC,
1322 	 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1323 	{0x0005,
1324 	 RTW_PWR_CUT_ALL_MSK,
1325 	 RTW_PWR_INTF_ALL_MSK,
1326 	 RTW_PWR_ADDR_MAC,
1327 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1328 	{0x0020,
1329 	 RTW_PWR_CUT_ALL_MSK,
1330 	 RTW_PWR_INTF_ALL_MSK,
1331 	 RTW_PWR_ADDR_MAC,
1332 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1333 	{0x0000,
1334 	 RTW_PWR_CUT_ALL_MSK,
1335 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1336 	 RTW_PWR_ADDR_MAC,
1337 	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1338 	{0xFFFF,
1339 	 RTW_PWR_CUT_ALL_MSK,
1340 	 RTW_PWR_INTF_ALL_MSK,
1341 	 0,
1342 	 RTW_PWR_CMD_END, 0, 0},
1343 };
1344 
1345 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
1346 	{0x0007,
1347 	 RTW_PWR_CUT_ALL_MSK,
1348 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1349 	 RTW_PWR_ADDR_MAC,
1350 	 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1351 	{0x0067,
1352 	 RTW_PWR_CUT_ALL_MSK,
1353 	 RTW_PWR_INTF_ALL_MSK,
1354 	 RTW_PWR_ADDR_MAC,
1355 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1356 	{0x0005,
1357 	 RTW_PWR_CUT_ALL_MSK,
1358 	 RTW_PWR_INTF_PCI_MSK,
1359 	 RTW_PWR_ADDR_MAC,
1360 	 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1361 	{0x004A,
1362 	 RTW_PWR_CUT_ALL_MSK,
1363 	 RTW_PWR_INTF_USB_MSK,
1364 	 RTW_PWR_ADDR_MAC,
1365 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1366 	{0x0067,
1367 	 RTW_PWR_CUT_ALL_MSK,
1368 	 RTW_PWR_INTF_SDIO_MSK,
1369 	 RTW_PWR_ADDR_MAC,
1370 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1371 	{0x0067,
1372 	 RTW_PWR_CUT_ALL_MSK,
1373 	 RTW_PWR_INTF_SDIO_MSK,
1374 	 RTW_PWR_ADDR_MAC,
1375 	 RTW_PWR_CMD_WRITE, BIT(4), 0},
1376 	{0x004F,
1377 	 RTW_PWR_CUT_ALL_MSK,
1378 	 RTW_PWR_INTF_SDIO_MSK,
1379 	 RTW_PWR_ADDR_MAC,
1380 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1381 	{0x0067,
1382 	 RTW_PWR_CUT_ALL_MSK,
1383 	 RTW_PWR_INTF_SDIO_MSK,
1384 	 RTW_PWR_ADDR_MAC,
1385 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1386 	{0x0046,
1387 	 RTW_PWR_CUT_ALL_MSK,
1388 	 RTW_PWR_INTF_SDIO_MSK,
1389 	 RTW_PWR_ADDR_MAC,
1390 	 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1391 	{0x0067,
1392 	 RTW_PWR_CUT_ALL_MSK,
1393 	 RTW_PWR_INTF_SDIO_MSK,
1394 	 RTW_PWR_ADDR_MAC,
1395 	 RTW_PWR_CMD_WRITE, BIT(2), 0},
1396 	{0x0046,
1397 	 RTW_PWR_CUT_ALL_MSK,
1398 	 RTW_PWR_INTF_SDIO_MSK,
1399 	 RTW_PWR_ADDR_MAC,
1400 	 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1401 	{0x0062,
1402 	 RTW_PWR_CUT_ALL_MSK,
1403 	 RTW_PWR_INTF_SDIO_MSK,
1404 	 RTW_PWR_ADDR_MAC,
1405 	 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1406 	{0x0081,
1407 	 RTW_PWR_CUT_ALL_MSK,
1408 	 RTW_PWR_INTF_ALL_MSK,
1409 	 RTW_PWR_ADDR_MAC,
1410 	 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1411 	{0x0005,
1412 	 RTW_PWR_CUT_ALL_MSK,
1413 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1414 	 RTW_PWR_ADDR_MAC,
1415 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1416 	{0x0086,
1417 	 RTW_PWR_CUT_ALL_MSK,
1418 	 RTW_PWR_INTF_SDIO_MSK,
1419 	 RTW_PWR_ADDR_SDIO,
1420 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1421 	{0x0086,
1422 	 RTW_PWR_CUT_ALL_MSK,
1423 	 RTW_PWR_INTF_SDIO_MSK,
1424 	 RTW_PWR_ADDR_SDIO,
1425 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1426 	{0x0090,
1427 	 RTW_PWR_CUT_ALL_MSK,
1428 	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1429 	 RTW_PWR_ADDR_MAC,
1430 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1431 	{0x0044,
1432 	 RTW_PWR_CUT_ALL_MSK,
1433 	 RTW_PWR_INTF_SDIO_MSK,
1434 	 RTW_PWR_ADDR_SDIO,
1435 	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1436 	{0x0040,
1437 	 RTW_PWR_CUT_ALL_MSK,
1438 	 RTW_PWR_INTF_SDIO_MSK,
1439 	 RTW_PWR_ADDR_SDIO,
1440 	 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1441 	{0x0041,
1442 	 RTW_PWR_CUT_ALL_MSK,
1443 	 RTW_PWR_INTF_SDIO_MSK,
1444 	 RTW_PWR_ADDR_SDIO,
1445 	 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1446 	{0x0042,
1447 	 RTW_PWR_CUT_ALL_MSK,
1448 	 RTW_PWR_INTF_SDIO_MSK,
1449 	 RTW_PWR_ADDR_SDIO,
1450 	 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1451 	{0xFFFF,
1452 	 RTW_PWR_CUT_ALL_MSK,
1453 	 RTW_PWR_INTF_ALL_MSK,
1454 	 0,
1455 	 RTW_PWR_CMD_END, 0, 0},
1456 };
1457 
1458 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = {
1459 	trans_carddis_to_cardemu_8821c,
1460 	trans_cardemu_to_act_8821c,
1461 	NULL
1462 };
1463 
1464 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = {
1465 	trans_act_to_cardemu_8821c,
1466 	trans_cardemu_to_carddis_8821c,
1467 	NULL
1468 };
1469 
1470 static const struct rtw_intf_phy_para usb2_param_8821c[] = {
1471 	{0xFFFF, 0x00,
1472 	 RTW_IP_SEL_PHY,
1473 	 RTW_INTF_PHY_CUT_ALL,
1474 	 RTW_INTF_PHY_PLATFORM_ALL},
1475 };
1476 
1477 static const struct rtw_intf_phy_para usb3_param_8821c[] = {
1478 	{0xFFFF, 0x0000,
1479 	 RTW_IP_SEL_PHY,
1480 	 RTW_INTF_PHY_CUT_ALL,
1481 	 RTW_INTF_PHY_PLATFORM_ALL},
1482 };
1483 
1484 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
1485 	{0x0009, 0x6380,
1486 	 RTW_IP_SEL_PHY,
1487 	 RTW_INTF_PHY_CUT_ALL,
1488 	 RTW_INTF_PHY_PLATFORM_ALL},
1489 	{0xFFFF, 0x0000,
1490 	 RTW_IP_SEL_PHY,
1491 	 RTW_INTF_PHY_CUT_ALL,
1492 	 RTW_INTF_PHY_PLATFORM_ALL},
1493 };
1494 
1495 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
1496 	{0xFFFF, 0x0000,
1497 	 RTW_IP_SEL_PHY,
1498 	 RTW_INTF_PHY_CUT_ALL,
1499 	 RTW_INTF_PHY_PLATFORM_ALL},
1500 };
1501 
1502 static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
1503 	.usb2_para	= usb2_param_8821c,
1504 	.usb3_para	= usb3_param_8821c,
1505 	.gen1_para	= pcie_gen1_param_8821c,
1506 	.gen2_para	= pcie_gen2_param_8821c,
1507 	.n_usb2_para	= ARRAY_SIZE(usb2_param_8821c),
1508 	.n_usb3_para	= ARRAY_SIZE(usb2_param_8821c),
1509 	.n_gen1_para	= ARRAY_SIZE(pcie_gen1_param_8821c),
1510 	.n_gen2_para	= ARRAY_SIZE(pcie_gen2_param_8821c),
1511 };
1512 
1513 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1514 	[0] = RTW_DEF_RFE(8821c, 0, 0),
1515 	[2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1516 	[4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1517 	[6] = RTW_DEF_RFE(8821c, 0, 0),
1518 };
1519 
1520 static struct rtw_hw_reg rtw8821c_dig[] = {
1521 	[0] = { .addr = 0xc50, .mask = 0x7f },
1522 };
1523 
1524 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1525 	.ctrl = LTECOEX_ACCESS_CTRL,
1526 	.wdata = LTECOEX_WRITE_DATA,
1527 	.rdata = LTECOEX_READ_DATA,
1528 };
1529 
1530 static struct rtw_page_table page_table_8821c[] = {
1531 	/* not sure what [0] stands for */
1532 	{16, 16, 16, 14, 1},
1533 	{16, 16, 16, 14, 1},
1534 	{16, 16, 0, 0, 1},
1535 	{16, 16, 16, 0, 1},
1536 	{16, 16, 16, 14, 1},
1537 };
1538 
1539 static struct rtw_rqpn rqpn_table_8821c[] = {
1540 	/* not sure what [0] stands for */
1541 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1542 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1543 	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1544 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1545 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1546 	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1547 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1548 	 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1549 	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1550 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1551 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1552 	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1553 	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1554 	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1555 	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1556 };
1557 
1558 static struct rtw_prioq_addrs prioq_addrs_8821c = {
1559 	.prio[RTW_DMA_MAPPING_EXTRA] = {
1560 		.rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
1561 	},
1562 	.prio[RTW_DMA_MAPPING_LOW] = {
1563 		.rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
1564 	},
1565 	.prio[RTW_DMA_MAPPING_NORMAL] = {
1566 		.rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
1567 	},
1568 	.prio[RTW_DMA_MAPPING_HIGH] = {
1569 		.rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
1570 	},
1571 	.wsize = true,
1572 };
1573 
1574 static struct rtw_chip_ops rtw8821c_ops = {
1575 	.phy_set_param		= rtw8821c_phy_set_param,
1576 	.read_efuse		= rtw8821c_read_efuse,
1577 	.query_rx_desc		= rtw8821c_query_rx_desc,
1578 	.set_channel		= rtw8821c_set_channel,
1579 	.mac_init		= rtw8821c_mac_init,
1580 	.read_rf		= rtw_phy_read_rf,
1581 	.write_rf		= rtw_phy_write_rf_reg_sipi,
1582 	.set_antenna		= NULL,
1583 	.set_tx_power_index	= rtw8821c_set_tx_power_index,
1584 	.cfg_ldo25		= rtw8821c_cfg_ldo25,
1585 	.false_alarm_statistics	= rtw8821c_false_alarm_statistics,
1586 	.phy_calibration	= rtw8821c_phy_calibration,
1587 	.cck_pd_set		= rtw8821c_phy_cck_pd_set,
1588 	.pwr_track		= rtw8821c_pwr_track,
1589 	.config_bfee		= rtw8821c_bf_config_bfee,
1590 	.set_gid_table		= rtw_bf_set_gid_table,
1591 	.cfg_csi_rate		= rtw_bf_cfg_csi_rate,
1592 
1593 	.coex_set_init		= rtw8821c_coex_cfg_init,
1594 	.coex_set_ant_switch	= rtw8821c_coex_cfg_ant_switch,
1595 	.coex_set_gnt_fix	= rtw8821c_coex_cfg_gnt_fix,
1596 	.coex_set_gnt_debug	= rtw8821c_coex_cfg_gnt_debug,
1597 	.coex_set_rfe_type	= rtw8821c_coex_cfg_rfe_type,
1598 	.coex_set_wl_tx_power	= rtw8821c_coex_cfg_wl_tx_power,
1599 	.coex_set_wl_rx_gain	= rtw8821c_coex_cfg_wl_rx_gain,
1600 };
1601 
1602 /* rssi in percentage % (dbm = % - 100) */
1603 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40};
1604 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101};
1605 
1606 /* Shared-Antenna Coex Table */
1607 static const struct coex_table_para table_sant_8821c[] = {
1608 	{0x55555555, 0x55555555}, /* case-0 */
1609 	{0x55555555, 0x55555555},
1610 	{0x66555555, 0x66555555},
1611 	{0xaaaaaaaa, 0xaaaaaaaa},
1612 	{0x5a5a5a5a, 0x5a5a5a5a},
1613 	{0xfafafafa, 0xfafafafa}, /* case-5 */
1614 	{0x6a5a5555, 0xaaaaaaaa},
1615 	{0x6a5a56aa, 0x6a5a56aa},
1616 	{0x6a5a5a5a, 0x6a5a5a5a},
1617 	{0x66555555, 0x5a5a5a5a},
1618 	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1619 	{0x66555555, 0xaaaaaaaa},
1620 	{0x66555555, 0x6a5a5aaa},
1621 	{0x66555555, 0x6aaa6aaa},
1622 	{0x66555555, 0x6a5a5aaa},
1623 	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1624 	{0xffff55ff, 0xfafafafa},
1625 	{0xffff55ff, 0x6afa5afa},
1626 	{0xaaffffaa, 0xfafafafa},
1627 	{0xaa5555aa, 0x5a5a5a5a},
1628 	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1629 	{0xaa5555aa, 0xaaaaaaaa},
1630 	{0xffffffff, 0x55555555},
1631 	{0xffffffff, 0x5a5a5a5a},
1632 	{0xffffffff, 0x5a5a5a5a},
1633 	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
1634 	{0x55555555, 0x5a5a5a5a},
1635 	{0x55555555, 0xaaaaaaaa},
1636 	{0x66555555, 0x6a5a6a5a},
1637 	{0x66556655, 0x66556655},
1638 	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1639 	{0xffffffff, 0x5aaa5aaa},
1640 	{0x56555555, 0x5a5a5aaa}
1641 };
1642 
1643 /* Non-Shared-Antenna Coex Table */
1644 static const struct coex_table_para table_nsant_8821c[] = {
1645 	{0xffffffff, 0xffffffff}, /* case-100 */
1646 	{0xffff55ff, 0xfafafafa},
1647 	{0x66555555, 0x66555555},
1648 	{0xaaaaaaaa, 0xaaaaaaaa},
1649 	{0x5a5a5a5a, 0x5a5a5a5a},
1650 	{0xffffffff, 0xffffffff}, /* case-105 */
1651 	{0x5afa5afa, 0x5afa5afa},
1652 	{0x55555555, 0xfafafafa},
1653 	{0x66555555, 0xfafafafa},
1654 	{0x66555555, 0x5a5a5a5a},
1655 	{0x66555555, 0x6a5a5a5a}, /* case-110 */
1656 	{0x66555555, 0xaaaaaaaa},
1657 	{0xffff55ff, 0xfafafafa},
1658 	{0xffff55ff, 0x5afa5afa},
1659 	{0xffff55ff, 0xaaaaaaaa},
1660 	{0xffff55ff, 0xffff55ff}, /* case-115 */
1661 	{0xaaffffaa, 0x5afa5afa},
1662 	{0xaaffffaa, 0xaaaaaaaa},
1663 	{0xffffffff, 0xfafafafa},
1664 	{0xffff55ff, 0xfafafafa},
1665 	{0xffffffff, 0xaaaaaaaa}, /* case-120 */
1666 	{0xffff55ff, 0x5afa5afa},
1667 	{0xffff55ff, 0x5afa5afa},
1668 	{0x55ff55ff, 0x55ff55ff}
1669 };
1670 
1671 /* Shared-Antenna TDMA */
1672 static const struct coex_tdma_para tdma_sant_8821c[] = {
1673 	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1674 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1675 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
1676 	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1677 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1678 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1679 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1680 	{ {0x61, 0x35, 0x03, 0x11, 0x10} },
1681 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1682 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1683 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1684 	{ {0x61, 0x08, 0x03, 0x11, 0x15} },
1685 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1686 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1687 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1688 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1689 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1690 	{ {0x51, 0x3a, 0x03, 0x11, 0x50} },
1691 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1692 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1693 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1694 	{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
1695 	{ {0x51, 0x08, 0x03, 0x30, 0x54} },
1696 	{ {0x55, 0x08, 0x03, 0x10, 0x54} },
1697 	{ {0x65, 0x10, 0x03, 0x11, 0x10} },
1698 	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1699 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1700 	{ {0x61, 0x08, 0x03, 0x11, 0x11} }
1701 };
1702 
1703 /* Non-Shared-Antenna TDMA */
1704 static const struct coex_tdma_para tdma_nsant_8821c[] = {
1705 	{ {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1706 	{ {0x61, 0x45, 0x03, 0x11, 0x11} },
1707 	{ {0x61, 0x25, 0x03, 0x11, 0x11} },
1708 	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1709 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1710 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1711 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1712 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1713 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1714 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1715 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1716 	{ {0x61, 0x10, 0x03, 0x11, 0x11} },
1717 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1718 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1719 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1720 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1721 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1722 	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
1723 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1724 	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1725 	{ {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1726 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }
1727 };
1728 
1729 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1730 
1731 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1732 static const struct coex_rf_para rf_para_tx_8821c[] = {
1733 	{0, 0, false, 7},  /* for normal */
1734 	{0, 20, false, 7}, /* for WL-CPT */
1735 	{8, 17, true, 4},
1736 	{7, 18, true, 4},
1737 	{6, 19, true, 4},
1738 	{5, 20, true, 4}
1739 };
1740 
1741 static const struct coex_rf_para rf_para_rx_8821c[] = {
1742 	{0, 0, false, 7},  /* for normal */
1743 	{0, 20, false, 7}, /* for WL-CPT */
1744 	{3, 24, true, 5},
1745 	{2, 26, true, 5},
1746 	{1, 27, true, 5},
1747 	{0, 28, true, 5}
1748 };
1749 
1750 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c));
1751 
1752 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = {
1753 	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1754 	 11, 11, 12, 12, 12, 12, 12},
1755 	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1756 	 11, 12, 12, 12, 12, 12, 12, 12},
1757 	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1758 	 11, 12, 12, 12, 12, 12, 12},
1759 };
1760 
1761 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = {
1762 	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1763 	 12, 12, 12, 12, 12, 12, 12},
1764 	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1765 	 12, 12, 12, 12, 12, 12, 12, 12},
1766 	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1767 	 11, 12, 12, 12, 12, 12, 12, 12},
1768 };
1769 
1770 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = {
1771 	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1772 	 11, 11, 12, 12, 12, 12, 12},
1773 	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1774 	 11, 12, 12, 12, 12, 12, 12, 12},
1775 	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1776 	 11, 12, 12, 12, 12, 12, 12},
1777 };
1778 
1779 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = {
1780 	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1781 	 12, 12, 12, 12, 12, 12, 12},
1782 	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1783 	 12, 12, 12, 12, 12, 12, 12, 12},
1784 	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1785 	 11, 12, 12, 12, 12, 12, 12, 12},
1786 };
1787 
1788 static const u8 rtw8821c_pwrtrk_2gb_n[] = {
1789 	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1790 	4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1791 };
1792 
1793 static const u8 rtw8821c_pwrtrk_2gb_p[] = {
1794 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1795 	5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1796 };
1797 
1798 static const u8 rtw8821c_pwrtrk_2ga_n[] = {
1799 	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1800 	4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1801 };
1802 
1803 static const u8 rtw8821c_pwrtrk_2ga_p[] = {
1804 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1805 	5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1806 };
1807 
1808 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = {
1809 	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1810 	4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1811 };
1812 
1813 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = {
1814 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1815 	5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1816 };
1817 
1818 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = {
1819 	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1820 	4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1821 };
1822 
1823 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = {
1824 	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1825 	5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1826 };
1827 
1828 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = {
1829 	.pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1830 	.pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1],
1831 	.pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2],
1832 	.pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1833 	.pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1],
1834 	.pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2],
1835 	.pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1836 	.pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1],
1837 	.pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2],
1838 	.pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1839 	.pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1],
1840 	.pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2],
1841 	.pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n,
1842 	.pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p,
1843 	.pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n,
1844 	.pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p,
1845 	.pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n,
1846 	.pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p,
1847 	.pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n,
1848 	.pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p,
1849 };
1850 
1851 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = {
1852 	{0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1853 	{0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1854 	{0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1855 	{0, 0, RTW_REG_DOMAIN_NL},
1856 	{0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1857 	{0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1858 	{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1859 	{0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1860 	{0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1861 	{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1862 	{0, 0, RTW_REG_DOMAIN_NL},
1863 	{0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1864 	{0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1865 	{0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1866 	{0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1867 	{0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1868 	{0, 0, RTW_REG_DOMAIN_NL},
1869 	{0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1870 	{0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1871 	{0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1872 	{0xc50,  MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1873 	{0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1874 };
1875 
1876 struct rtw_chip_info rtw8821c_hw_spec = {
1877 	.ops = &rtw8821c_ops,
1878 	.id = RTW_CHIP_TYPE_8821C,
1879 	.fw_name = "rtw88/rtw8821c_fw.bin",
1880 	.wlan_cpu = RTW_WCPU_11AC,
1881 	.tx_pkt_desc_sz = 48,
1882 	.tx_buf_desc_sz = 16,
1883 	.rx_pkt_desc_sz = 24,
1884 	.rx_buf_desc_sz = 8,
1885 	.phy_efuse_size = 512,
1886 	.log_efuse_size = 512,
1887 	.ptct_efuse_size = 96,
1888 	.txff_size = 65536,
1889 	.rxff_size = 16384,
1890 	.txgi_factor = 1,
1891 	.is_pwr_by_rate_dec = true,
1892 	.max_power_index = 0x3f,
1893 	.csi_buf_pg_num = 0,
1894 	.band = RTW_BAND_2G | RTW_BAND_5G,
1895 	.page_size = 128,
1896 	.dig_min = 0x1c,
1897 	.ht_supported = true,
1898 	.vht_supported = true,
1899 	.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
1900 	.sys_func_en = 0xD8,
1901 	.pwr_on_seq = card_enable_flow_8821c,
1902 	.pwr_off_seq = card_disable_flow_8821c,
1903 	.page_table = page_table_8821c,
1904 	.rqpn_table = rqpn_table_8821c,
1905 	.prioq_addrs = &prioq_addrs_8821c,
1906 	.intf_table = &phy_para_table_8821c,
1907 	.dig = rtw8821c_dig,
1908 	.rf_base_addr = {0x2800, 0x2c00},
1909 	.rf_sipi_addr = {0xc90, 0xe90},
1910 	.ltecoex_addr = &rtw8821c_ltecoex_addr,
1911 	.mac_tbl = &rtw8821c_mac_tbl,
1912 	.agc_tbl = &rtw8821c_agc_tbl,
1913 	.bb_tbl = &rtw8821c_bb_tbl,
1914 	.rf_tbl = {&rtw8821c_rf_a_tbl},
1915 	.rfe_defs = rtw8821c_rfe_defs,
1916 	.rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
1917 	.rx_ldpc = false,
1918 	.pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl,
1919 	.iqk_threshold = 8,
1920 	.bfer_su_max_num = 2,
1921 	.bfer_mu_max_num = 1,
1922 
1923 	.coex_para_ver = 0x19092746,
1924 	.bt_desired_ver = 0x46,
1925 	.scbd_support = true,
1926 	.new_scbd10_def = false,
1927 	.ble_hid_profile_support = false,
1928 	.wl_mimo_ps_support = false,
1929 	.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
1930 	.bt_rssi_type = COEX_BTRSSI_RATIO,
1931 	.ant_isolation = 15,
1932 	.rssi_tolerance = 2,
1933 	.wl_rssi_step = wl_rssi_step_8821c,
1934 	.bt_rssi_step = bt_rssi_step_8821c,
1935 	.table_sant_num = ARRAY_SIZE(table_sant_8821c),
1936 	.table_sant = table_sant_8821c,
1937 	.table_nsant_num = ARRAY_SIZE(table_nsant_8821c),
1938 	.table_nsant = table_nsant_8821c,
1939 	.tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c),
1940 	.tdma_sant = tdma_sant_8821c,
1941 	.tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c),
1942 	.tdma_nsant = tdma_nsant_8821c,
1943 	.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c),
1944 	.wl_rf_para_tx = rf_para_tx_8821c,
1945 	.wl_rf_para_rx = rf_para_rx_8821c,
1946 	.bt_afh_span_bw20 = 0x24,
1947 	.bt_afh_span_bw40 = 0x36,
1948 	.afh_5g_num = ARRAY_SIZE(afh_5g_8821c),
1949 	.afh_5g = afh_5g_8821c,
1950 
1951 	.coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c),
1952 	.coex_info_hw_regs = coex_info_hw_regs_8821c,
1953 };
1954 EXPORT_SYMBOL(rtw8821c_hw_spec);
1955 
1956 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
1957 
1958 MODULE_AUTHOR("Realtek Corporation");
1959 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
1960 MODULE_LICENSE("Dual BSD/GPL");
1961