1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW8723D_H__ 6 #define __RTW8723D_H__ 7 8 enum rtw8723d_path { 9 PATH_S1, 10 PATH_S0, 11 PATH_NR, 12 }; 13 14 enum rtw8723d_iqk_round { 15 IQK_ROUND_0, 16 IQK_ROUND_1, 17 IQK_ROUND_2, 18 IQK_ROUND_HYBRID, 19 IQK_ROUND_SIZE, 20 IQK_ROUND_INVALID = 0xff, 21 }; 22 23 enum rtw8723d_iqk_result { 24 IQK_S1_TX_X, 25 IQK_S1_TX_Y, 26 IQK_S1_RX_X, 27 IQK_S1_RX_Y, 28 IQK_S0_TX_X, 29 IQK_S0_TX_Y, 30 IQK_S0_RX_X, 31 IQK_S0_RX_Y, 32 IQK_NR, 33 IQK_SX_NR = IQK_NR / PATH_NR, 34 }; 35 36 struct rtw8723de_efuse { 37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */ 38 u8 vender_id[2]; 39 u8 device_id[2]; 40 u8 sub_vender_id[2]; 41 u8 sub_device_id[2]; 42 }; 43 44 struct rtw8723d_efuse { 45 __le16 rtl_id; 46 u8 rsvd[2]; 47 u8 afe; 48 u8 rsvd1[11]; 49 50 /* power index for four RF paths */ 51 struct rtw_txpwr_idx txpwr_idx_table[4]; 52 53 u8 channel_plan; /* 0xb8 */ 54 u8 xtal_k; 55 u8 thermal_meter; 56 u8 iqk_lck; 57 u8 pa_type; /* 0xbc */ 58 u8 lna_type_2g[2]; /* 0xbd */ 59 u8 lna_type_5g[2]; 60 u8 rf_board_option; 61 u8 rf_feature_option; 62 u8 rf_bt_setting; 63 u8 eeprom_version; 64 u8 eeprom_customer_id; 65 u8 tx_bb_swing_setting_2g; 66 u8 res_c7; 67 u8 tx_pwr_calibrate_rate; 68 u8 rf_antenna_option; /* 0xc9 */ 69 u8 rfe_option; 70 u8 country_code[2]; 71 u8 res[3]; 72 struct rtw8723de_efuse e; 73 }; 74 75 /* phy status page0 */ 76 #define GET_PHY_STAT_P0_PWDB(phy_stat) \ 77 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 78 79 /* phy status page1 */ 80 #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \ 81 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 82 #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \ 83 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16)) 84 #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \ 85 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28)) 86 #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \ 87 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8)) 88 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \ 89 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12)) 90 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \ 91 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) 92 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \ 93 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0)) 94 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ 95 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) 96 97 static inline s32 iqkxy_to_s32(s32 val) 98 { 99 /* val is Q10.8 */ 100 return sign_extend32(val, 9); 101 } 102 103 static inline s32 iqk_mult(s32 x, s32 y, s32 *ext) 104 { 105 /* x, y and return value are Q10.8 */ 106 s32 t; 107 108 t = x * y; 109 if (ext) 110 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ 111 112 return (t >> 8); /* Q.16 --> Q.8 */ 113 } 114 115 #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing) 116 #define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing) 117 #define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing) 118 #define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing) 119 #define RTW_DEF_OFDM_SWING_INDEX 28 120 #define RTW_DEF_CCK_SWING_INDEX 28 121 122 #define MAX_TOLERANCE 5 123 #define IQK_TX_X_ERR 0x142 124 #define IQK_TX_Y_ERR 0x42 125 #define IQK_RX_X_UPPER 0x11a 126 #define IQK_RX_X_LOWER 0xe6 127 #define IQK_RX_Y_LMT 0x1a 128 #define IQK_TX_OK BIT(0) 129 #define IQK_RX_OK BIT(1) 130 #define PATH_IQK_RETRY 2 131 132 #define SPUR_THRES 0x16 133 #define CCK_DFIR_NR 3 134 #define DIS_3WIRE 0xccf000c0 135 #define EN_3WIRE 0xccc000c0 136 #define START_PSD 0x400000 137 #define FREQ_CH13 0xfccd 138 #define FREQ_CH14 0xff9a 139 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) 140 #define RFCFGCH_BW_MASK (BIT(11) | BIT(10)) 141 #define RFCFGCH_BW_20M (BIT(11) | BIT(10)) 142 #define RFCFGCH_BW_40M BIT(10) 143 #define BIT_MASK_RFMOD BIT(0) 144 #define BIT_LCK BIT(15) 145 146 #define REG_GPIO_INTM 0x0048 147 #define REG_BTG_SEL 0x0067 148 #define BIT_MASK_BTG_WL BIT(7) 149 #define REG_LTECOEX_PATH_CONTROL 0x0070 150 #define REG_LTECOEX_CTRL 0x07c0 151 #define REG_LTECOEX_WRITE_DATA 0x07c4 152 #define REG_LTECOEX_READ_DATA 0x07c8 153 #define REG_PSDFN 0x0808 154 #define REG_BB_PWR_SAV1_11N 0x0874 155 #define REG_ANA_PARAM1 0x0880 156 #define REG_ANALOG_P4 0x088c 157 #define REG_PSDRPT 0x08b4 158 #define REG_FPGA1_RFMOD 0x0900 159 #define REG_BB_SEL_BTG 0x0948 160 #define REG_BBRX_DFIR 0x0954 161 #define BIT_MASK_RXBB_DFIR GENMASK(27, 24) 162 #define BIT_RXBB_DFIR_EN BIT(19) 163 #define REG_CCK0_SYS 0x0a00 164 #define BIT_CCK_SIDE_BAND BIT(4) 165 #define REG_CCK_ANT_SEL_11N 0x0a04 166 #define REG_CCK_FA_RST_11N 0x0a2c 167 #define BIT_MASK_CCK_CNT_KEEP BIT(12) 168 #define BIT_MASK_CCK_CNT_EN BIT(13) 169 #define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN) 170 #define BIT_MASK_CCK_FA_KEEP BIT(14) 171 #define BIT_MASK_CCK_FA_EN BIT(15) 172 #define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN) 173 #define REG_CCK_FA_LSB_11N 0x0a5c 174 #define REG_CCK_FA_MSB_11N 0x0a58 175 #define REG_CCK_CCA_CNT_11N 0x0a60 176 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0) 177 #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8) 178 #define REG_OFDM_FA_HOLDC_11N 0x0c00 179 #define BIT_MASK_OFDM_FA_KEEP BIT(31) 180 #define REG_BB_RX_PATH_11N 0x0c04 181 #define REG_TRMUX_11N 0x0c08 182 #define REG_OFDM_FA_RSTC_11N 0x0c0c 183 #define BIT_MASK_OFDM_FA_RST BIT(31) 184 #define REG_A_RXIQI 0x0c14 185 #define BIT_MASK_RXIQ_S1_X 0x000003FF 186 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00 187 #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F) 188 #define REG_OFDM0_RXDSP 0x0c40 189 #define BIT_MASK_RXDSP GENMASK(28, 24) 190 #define BIT_EN_RXDSP BIT(9) 191 #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c 192 #define BIT_MASK_OFDM0_EXT_A BIT(31) 193 #define BIT_MASK_OFDM0_EXT_C BIT(29) 194 #define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28)) 195 #define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28)) 196 #define REG_OFDM0_XAAGC1 0x0c50 197 #define REG_OFDM0_XBAGC1 0x0c58 198 #define REG_AGCRSSI 0x0c78 199 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80 200 #define BIT_MASK_TXIQ_ELM_A 0x03ff 201 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \ 202 ((a) & 0x03ff)) 203 #define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16) 204 #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F) 205 #define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22) 206 #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94 207 #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6) 208 #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0 209 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000 210 #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF) 211 #define REG_TXIQ_AB_S0 0x0cd0 212 #define BIT_MASK_TXIQ_A_S0 0x000007FE 213 #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0) 214 #define BIT_MASK_TXIQ_B_S0 0x0007E000 215 #define REG_TXIQ_CD_S0 0x0cd4 216 #define BIT_MASK_TXIQ_C_S0 0x000007FE 217 #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0) 218 #define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13) 219 #define BIT_MASK_TXIQ_D_EXT_S0 BIT(12) 220 #define REG_RXIQ_AB_S0 0x0cd8 221 #define BIT_MASK_RXIQ_X_S0 0x000003FF 222 #define BIT_MASK_RXIQ_Y_S0 0x003FF000 223 #define REG_OFDM_FA_TYPE1_11N 0x0cf0 224 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0) 225 #define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16) 226 #define REG_OFDM_FA_RSTD_11N 0x0d00 227 #define BIT_MASK_OFDM_FA_RST1 BIT(27) 228 #define BIT_MASK_OFDM_FA_KEEP1 BIT(31) 229 #define REG_CTX 0x0d03 230 #define BIT_MASK_CTX_TYPE GENMASK(6, 4) 231 #define REG_OFDM1_CFOTRK 0x0d2c 232 #define BIT_EN_CFOTRK BIT(28) 233 #define REG_OFDM1_CSI1 0x0d40 234 #define REG_OFDM1_CSI2 0x0d44 235 #define REG_OFDM1_CSI3 0x0d48 236 #define REG_OFDM1_CSI4 0x0d4c 237 #define REG_OFDM_FA_TYPE2_11N 0x0da0 238 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0) 239 #define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16) 240 #define REG_OFDM_FA_TYPE3_11N 0x0da4 241 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0) 242 #define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16) 243 #define REG_OFDM_FA_TYPE4_11N 0x0da8 244 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0) 245 #define REG_FPGA0_IQK_11N 0x0e28 246 #define BIT_MASK_IQK_MOD 0xffffff00 247 #define EN_IQK 0x808000 248 #define RST_IQK 0x000000 249 #define REG_TXIQK_TONE_A_11N 0x0e30 250 #define REG_RXIQK_TONE_A_11N 0x0e34 251 #define REG_TXIQK_PI_A_11N 0x0e38 252 #define REG_RXIQK_PI_A_11N 0x0e3c 253 #define REG_TXIQK_11N 0x0e40 254 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y)) 255 #define REG_RXIQK_11N 0x0e44 256 #define REG_IQK_AGC_PTS_11N 0x0e48 257 #define REG_IQK_AGC_RSP_11N 0x0e4c 258 #define REG_TX_IQK_TONE_B 0x0e50 259 #define REG_RX_IQK_TONE_B 0x0e54 260 #define REG_IQK_RES_TX 0x0e94 261 #define BIT_MASK_RES_TX GENMASK(25, 16) 262 #define REG_IQK_RES_TY 0x0e9c 263 #define BIT_MASK_RES_TY GENMASK(25, 16) 264 #define REG_IQK_RES_RX 0x0ea4 265 #define BIT_MASK_RES_RX GENMASK(25, 16) 266 #define REG_IQK_RES_RY 0x0eac 267 #define BIT_IQK_TX_FAIL BIT(28) 268 #define BIT_IQK_RX_FAIL BIT(27) 269 #define BIT_IQK_DONE BIT(26) 270 #define BIT_MASK_RES_RY GENMASK(25, 16) 271 #define REG_PAGE_F_RST_11N 0x0f14 272 #define BIT_MASK_F_RST_ALL BIT(16) 273 #define REG_IGI_C_11N 0x0f84 274 #define REG_IGI_D_11N 0x0f88 275 #define REG_HT_CRC32_CNT_11N 0x0f90 276 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0) 277 #define BIT_MASK_HT_CRC_ERR GENMASK(31, 16) 278 #define REG_OFDM_CRC32_CNT_11N 0x0f94 279 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0) 280 #define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16) 281 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8 282 283 #endif 284