1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8723d.h" 13 #include "rtw8723d_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 18 static const struct rtw_hw_reg rtw8723d_txagc[] = { 19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, 20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, 21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, 22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, 23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, 24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, 25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, 26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, 27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, 28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, 29 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, 30 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, 31 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, 32 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, 33 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, 34 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, 35 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, 36 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, 37 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, 38 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, 39 }; 40 41 #define WLAN_TXQ_RPT_EN 0x1F 42 #define WLAN_SLOT_TIME 0x09 43 #define WLAN_RL_VAL 0x3030 44 #define WLAN_BAR_VAL 0x0201ffff 45 #define BIT_MASK_TBTT_HOLD 0x00000fff 46 #define BIT_SHIFT_TBTT_HOLD 8 47 #define BIT_MASK_TBTT_SETUP 0x000000ff 48 #define BIT_SHIFT_TBTT_SETUP 0 49 #define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \ 50 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP)) 51 #define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\ 52 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD)) 53 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80) 54 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64) 55 #define WLAN_PIFS_VAL 0 56 #define WLAN_AGG_BRK_TIME 0x16 57 #define WLAN_NAV_PROT_LEN 0x0040 58 #define WLAN_SPEC_SIFS 0x100a 59 #define WLAN_RX_PKT_LIMIT 0x17 60 #define WLAN_MAX_AGG_NR 0x0A 61 #define WLAN_AMPDU_MAX_TIME 0x1C 62 #define WLAN_ANT_SEL 0x82 63 #define WLAN_LTR_IDLE_LAT 0x90039003 64 #define WLAN_LTR_ACT_LAT 0x883c883c 65 #define WLAN_LTR_CTRL1 0xCB004010 66 #define WLAN_LTR_CTRL2 0x01233425 67 68 static void rtw8723d_lck(struct rtw_dev *rtwdev) 69 { 70 u32 lc_cal; 71 u8 val_ctx, rf_val; 72 int ret; 73 74 val_ctx = rtw_read8(rtwdev, REG_CTX); 75 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 76 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); 77 else 78 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); 79 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 80 81 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); 82 83 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, 84 10000, 1000000, false, 85 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); 86 if (ret) 87 rtw_warn(rtwdev, "failed to poll LCK status bit\n"); 88 89 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); 90 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 91 rtw_write8(rtwdev, REG_CTX, val_ctx); 92 else 93 rtw_write8(rtwdev, REG_TXPAUSE, 0x00); 94 } 95 96 static const u32 rtw8723d_ofdm_swing_table[] = { 97 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c, 98 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056, 99 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079, 100 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab, 101 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2, 102 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155, 103 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2, 104 0x7f8001fe, 105 }; 106 107 static const u32 rtw8723d_cck_swing_table[] = { 108 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 109 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 110 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 111 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 112 0x7FF, 113 }; 114 115 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_ofdm_swing_table) 116 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_cck_swing_table) 117 118 static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev) 119 { 120 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 121 u8 path; 122 123 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX; 124 125 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 126 ewma_thermal_init(&dm_info->avg_thermal[path]); 127 dm_info->delta_power_index[path] = 0; 128 } 129 dm_info->pwr_trk_triggered = false; 130 dm_info->pwr_trk_init_trigger = true; 131 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 132 dm_info->txagc_remnant_cck = 0; 133 dm_info->txagc_remnant_ofdm = 0; 134 } 135 136 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) 137 { 138 u8 xtal_cap; 139 u32 val32; 140 141 /* power on BB/RF domain */ 142 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 143 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 144 rtw_write8_set(rtwdev, REG_RF_CTRL, 145 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 146 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 147 148 rtw_phy_load_tables(rtwdev); 149 150 /* post init after header files config */ 151 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 152 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT); 153 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 154 155 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 156 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 157 xtal_cap | (xtal_cap << 6)); 158 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 159 if ((rtwdev->efuse.afe >> 4) == 14) { 160 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4); 161 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL); 162 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1); 163 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0); 164 } 165 166 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 167 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 168 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 169 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 170 rtw_write8(rtwdev, REG_ATIMWND, 0x2); 171 rtw_write8(rtwdev, REG_BCN_CTRL, 172 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 173 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT); 174 val32 &= ~BIT_MASK_TBTT_MASK; 175 val32 |= WLAN_TBTT_TIME_STOP_BCN; 176 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32); 177 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 178 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME); 179 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN); 180 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 181 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); 182 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); 183 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 184 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 185 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 186 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 187 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL); 188 189 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT); 190 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT); 191 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1); 192 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2); 193 194 rtw_phy_init(rtwdev); 195 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 196 197 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); 198 199 rtw8723d_lck(rtwdev); 200 201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 202 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 203 204 rtw8723d_pwrtrack_init(rtwdev); 205 } 206 207 static void rtw8723de_efuse_parsing(struct rtw_efuse *efuse, 208 struct rtw8723d_efuse *map) 209 { 210 ether_addr_copy(efuse->addr, map->e.mac_addr); 211 } 212 213 static void rtw8723du_efuse_parsing(struct rtw_efuse *efuse, 214 struct rtw8723d_efuse *map) 215 { 216 ether_addr_copy(efuse->addr, map->u.mac_addr); 217 } 218 219 static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 220 { 221 struct rtw_efuse *efuse = &rtwdev->efuse; 222 struct rtw8723d_efuse *map; 223 int i; 224 225 map = (struct rtw8723d_efuse *)log_map; 226 227 efuse->rfe_option = 0; 228 efuse->rf_board_option = map->rf_board_option; 229 efuse->crystal_cap = map->xtal_k; 230 efuse->pa_type_2g = map->pa_type; 231 efuse->lna_type_2g = map->lna_type_2g[0]; 232 efuse->channel_plan = map->channel_plan; 233 efuse->country_code[0] = map->country_code[0]; 234 efuse->country_code[1] = map->country_code[1]; 235 efuse->bt_setting = map->rf_bt_setting; 236 efuse->regd = map->rf_board_option & 0x7; 237 efuse->thermal_meter[0] = map->thermal_meter; 238 efuse->thermal_meter_k = map->thermal_meter; 239 efuse->afe = map->afe; 240 241 for (i = 0; i < 4; i++) 242 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 243 244 switch (rtw_hci_type(rtwdev)) { 245 case RTW_HCI_TYPE_PCIE: 246 rtw8723de_efuse_parsing(efuse, map); 247 break; 248 case RTW_HCI_TYPE_USB: 249 rtw8723du_efuse_parsing(efuse, map); 250 break; 251 default: 252 /* unsupported now */ 253 return -ENOTSUPP; 254 } 255 256 return 0; 257 } 258 259 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 260 struct rtw_rx_pkt_stat *pkt_stat) 261 { 262 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 263 s8 min_rx_power = -120; 264 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 265 266 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97; 267 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 268 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 269 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 270 min_rx_power); 271 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 272 } 273 274 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 275 struct rtw_rx_pkt_stat *pkt_stat) 276 { 277 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 278 u8 rxsc, bw; 279 s8 min_rx_power = -120; 280 s8 rx_evm; 281 282 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 283 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 284 else 285 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 286 287 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0) 288 bw = RTW_CHANNEL_WIDTH_20; 289 else if ((rxsc == 1) || (rxsc == 2)) 290 bw = RTW_CHANNEL_WIDTH_20; 291 else 292 bw = RTW_CHANNEL_WIDTH_40; 293 294 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 295 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 296 pkt_stat->bw = bw; 297 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 298 min_rx_power); 299 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 300 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 301 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 302 303 dm_info->curr_rx_rate = pkt_stat->rate; 304 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 305 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 306 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 307 308 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64); 309 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 310 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm; 311 } 312 313 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 314 struct rtw_rx_pkt_stat *pkt_stat) 315 { 316 u8 page; 317 318 page = *phy_status & 0xf; 319 320 switch (page) { 321 case 0: 322 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 323 break; 324 case 1: 325 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 326 break; 327 default: 328 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 329 return; 330 } 331 } 332 333 static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 334 struct rtw_rx_pkt_stat *pkt_stat, 335 struct ieee80211_rx_status *rx_status) 336 { 337 struct ieee80211_hdr *hdr; 338 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 339 u8 *phy_status = NULL; 340 341 memset(pkt_stat, 0, sizeof(*pkt_stat)); 342 343 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 344 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 345 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 346 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 347 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 348 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 349 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 350 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 351 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 352 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 353 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 354 pkt_stat->ppdu_cnt = 0; 355 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 356 357 /* drv_info_sz is in unit of 8-bytes */ 358 pkt_stat->drv_info_sz *= 8; 359 360 /* c2h cmd pkt's rx/phy status is not interested */ 361 if (pkt_stat->is_c2h) 362 return; 363 364 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 365 pkt_stat->drv_info_sz); 366 if (pkt_stat->phy_status) { 367 phy_status = rx_desc + desc_sz + pkt_stat->shift; 368 query_phy_status(rtwdev, phy_status, pkt_stat); 369 } 370 371 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 372 } 373 374 static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev, 375 u8 channel, u32 thres) 376 { 377 u32 freq; 378 bool ret = false; 379 380 if (channel == 13) 381 freq = FREQ_CH13; 382 else if (channel == 14) 383 freq = FREQ_CH14; 384 else 385 return false; 386 387 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 388 rtw_write32(rtwdev, REG_PSDFN, freq); 389 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 390 391 msleep(30); 392 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 393 ret = true; 394 395 rtw_write32(rtwdev, REG_PSDFN, freq); 396 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 397 398 return ret; 399 } 400 401 static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 402 { 403 if (!notch) { 404 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 405 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 406 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 407 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 408 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 409 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 410 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 411 return; 412 } 413 414 switch (channel) { 415 case 13: 416 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 417 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 418 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000); 419 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 420 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 421 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 422 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 423 break; 424 case 14: 425 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 426 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 427 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 428 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 429 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 430 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000); 431 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 432 break; 433 default: 434 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 435 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 436 break; 437 } 438 } 439 440 static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel) 441 { 442 bool notch; 443 444 if (channel < 13) { 445 rtw8723d_cfg_notch(rtwdev, channel, false); 446 return; 447 } 448 449 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES); 450 rtw8723d_cfg_notch(rtwdev, channel, notch); 451 } 452 453 static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 454 { 455 u32 rf_cfgch_a, rf_cfgch_b; 456 457 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 458 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 459 460 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 461 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 462 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 463 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 464 465 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 466 switch (bw) { 467 case RTW_CHANNEL_WIDTH_20: 468 rf_cfgch_a |= RFCFGCH_BW_20M; 469 break; 470 case RTW_CHANNEL_WIDTH_40: 471 rf_cfgch_a |= RFCFGCH_BW_40M; 472 break; 473 default: 474 break; 475 } 476 477 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 478 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 479 480 rtw8723d_spur_cal(rtwdev, channel); 481 } 482 483 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = { 484 [0] = { 485 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C }, 486 { .len = 4, .reg = 0xA28, .val = 0x00008810 }, 487 { .len = 4, .reg = 0xAAC, .val = 0x01235667 }, 488 }, 489 [1] = { 490 { .len = 4, .reg = 0xA24, .val = 0x0000B81C }, 491 { .len = 4, .reg = 0xA28, .val = 0x00000000 }, 492 { .len = 4, .reg = 0xAAC, .val = 0x00003667 }, 493 }, 494 }; 495 496 static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 497 u8 primary_ch_idx) 498 { 499 const struct rtw_backup_info *cck_dfir; 500 int i; 501 502 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 503 504 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++) 505 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 506 507 switch (bw) { 508 case RTW_CHANNEL_WIDTH_20: 509 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 510 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 511 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1); 512 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); 513 break; 514 case RTW_CHANNEL_WIDTH_40: 515 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 516 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 517 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); 518 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 519 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 520 break; 521 default: 522 break; 523 } 524 } 525 526 static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 527 u8 primary_chan_idx) 528 { 529 rtw8723d_set_channel_rf(rtwdev, channel, bw); 530 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 531 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 532 } 533 534 #define BIT_CFENDFORM BIT(9) 535 #define BIT_WMAC_TCR_ERR0 BIT(12) 536 #define BIT_WMAC_TCR_ERR1 BIT(13) 537 #define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ 538 BIT_WMAC_TCR_ERR1) 539 #define WLAN_RX_FILTER0 0xFFFF 540 #define WLAN_RX_FILTER1 0x400 541 #define WLAN_RX_FILTER2 0xFFFF 542 #define WLAN_RCR_CFG 0x700060CE 543 544 static int rtw8723d_mac_init(struct rtw_dev *rtwdev) 545 { 546 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 547 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); 548 549 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 550 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); 551 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 552 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 553 554 rtw_write32(rtwdev, REG_INT_MIG, 0); 555 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); 556 557 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 558 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); 559 560 return 0; 561 } 562 563 static void rtw8723d_shutdown(struct rtw_dev *rtwdev) 564 { 565 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); 566 } 567 568 static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 569 { 570 u8 ldo_pwr; 571 572 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 573 if (enable) { 574 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; 575 ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; 576 } else { 577 ldo_pwr &= ~BIT_LDO25_EN; 578 } 579 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 580 } 581 582 static void 583 rtw8723d_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 584 { 585 struct rtw_hal *hal = &rtwdev->hal; 586 const struct rtw_hw_reg *txagc; 587 u8 rate, pwr_index; 588 int j; 589 590 for (j = 0; j < rtw_rate_size[rs]; j++) { 591 rate = rtw_rate_section[rs][j]; 592 pwr_index = hal->tx_pwr_tbl[path][rate]; 593 594 if (rate >= ARRAY_SIZE(rtw8723d_txagc)) { 595 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); 596 continue; 597 } 598 txagc = &rtw8723d_txagc[rate]; 599 if (!txagc->addr) { 600 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); 601 continue; 602 } 603 604 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); 605 } 606 } 607 608 static void rtw8723d_set_tx_power_index(struct rtw_dev *rtwdev) 609 { 610 struct rtw_hal *hal = &rtwdev->hal; 611 int rs, path; 612 613 for (path = 0; path < hal->rf_path_num; path++) { 614 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) 615 rtw8723d_set_tx_power_index_by_rate(rtwdev, path, rs); 616 } 617 } 618 619 static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on) 620 { 621 if (on) { 622 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 623 624 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 625 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); 626 } else { 627 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 628 } 629 } 630 631 static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev) 632 { 633 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 634 u32 cck_fa_cnt; 635 u32 ofdm_fa_cnt; 636 u32 crc32_cnt; 637 u32 val32; 638 639 /* hold counter */ 640 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); 641 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); 642 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); 643 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); 644 645 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); 646 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; 647 648 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); 649 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); 650 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); 651 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); 652 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); 653 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); 654 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); 655 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); 656 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); 657 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); 658 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); 659 660 dm_info->cck_fa_cnt = cck_fa_cnt; 661 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 662 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; 663 664 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); 665 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); 666 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); 667 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); 668 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); 669 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); 670 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); 671 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); 672 dm_info->vht_err_cnt = 0; 673 dm_info->vht_ok_cnt = 0; 674 675 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); 676 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | 677 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); 678 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; 679 680 /* reset counter */ 681 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); 682 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); 683 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); 684 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); 685 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); 686 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); 687 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); 688 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); 689 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); 690 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); 691 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); 692 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); 693 } 694 695 static const u32 iqk_adda_regs[] = { 696 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 697 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec 698 }; 699 700 static const u32 iqk_mac8_regs[] = {0x522, 0x550, 0x551}; 701 static const u32 iqk_mac32_regs[] = {0x40}; 702 703 static const u32 iqk_bb_regs[] = { 704 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04 705 }; 706 707 #define IQK_ADDA_REG_NUM ARRAY_SIZE(iqk_adda_regs) 708 #define IQK_MAC8_REG_NUM ARRAY_SIZE(iqk_mac8_regs) 709 #define IQK_MAC32_REG_NUM ARRAY_SIZE(iqk_mac32_regs) 710 #define IQK_BB_REG_NUM ARRAY_SIZE(iqk_bb_regs) 711 712 struct iqk_backup_regs { 713 u32 adda[IQK_ADDA_REG_NUM]; 714 u8 mac8[IQK_MAC8_REG_NUM]; 715 u32 mac32[IQK_MAC32_REG_NUM]; 716 u32 bb[IQK_BB_REG_NUM]; 717 718 u32 lte_path; 719 u32 lte_gnt; 720 721 u32 bb_sel_btg; 722 u8 btg_sel; 723 724 u8 igia; 725 u8 igib; 726 }; 727 728 static void rtw8723d_iqk_backup_regs(struct rtw_dev *rtwdev, 729 struct iqk_backup_regs *backup) 730 { 731 int i; 732 733 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 734 backup->adda[i] = rtw_read32(rtwdev, iqk_adda_regs[i]); 735 736 for (i = 0; i < IQK_MAC8_REG_NUM; i++) 737 backup->mac8[i] = rtw_read8(rtwdev, iqk_mac8_regs[i]); 738 for (i = 0; i < IQK_MAC32_REG_NUM; i++) 739 backup->mac32[i] = rtw_read32(rtwdev, iqk_mac32_regs[i]); 740 741 for (i = 0; i < IQK_BB_REG_NUM; i++) 742 backup->bb[i] = rtw_read32(rtwdev, iqk_bb_regs[i]); 743 744 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); 745 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); 746 747 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); 748 } 749 750 static void rtw8723d_iqk_restore_regs(struct rtw_dev *rtwdev, 751 const struct iqk_backup_regs *backup) 752 { 753 int i; 754 755 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 756 rtw_write32(rtwdev, iqk_adda_regs[i], backup->adda[i]); 757 758 for (i = 0; i < IQK_MAC8_REG_NUM; i++) 759 rtw_write8(rtwdev, iqk_mac8_regs[i], backup->mac8[i]); 760 for (i = 0; i < IQK_MAC32_REG_NUM; i++) 761 rtw_write32(rtwdev, iqk_mac32_regs[i], backup->mac32[i]); 762 763 for (i = 0; i < IQK_BB_REG_NUM; i++) 764 rtw_write32(rtwdev, iqk_bb_regs[i], backup->bb[i]); 765 766 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 767 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); 768 769 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); 770 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); 771 772 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); 773 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); 774 } 775 776 static void rtw8723d_iqk_backup_path_ctrl(struct rtw_dev *rtwdev, 777 struct iqk_backup_regs *backup) 778 { 779 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL); 780 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", 781 backup->btg_sel); 782 } 783 784 static void rtw8723d_iqk_config_path_ctrl(struct rtw_dev *rtwdev) 785 { 786 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); 787 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", 788 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 789 } 790 791 static void rtw8723d_iqk_restore_path_ctrl(struct rtw_dev *rtwdev, 792 const struct iqk_backup_regs *backup) 793 { 794 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel); 795 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", 796 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 797 } 798 799 static void rtw8723d_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev, 800 struct iqk_backup_regs *backup) 801 { 802 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL); 803 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); 804 mdelay(1); 805 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA); 806 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", 807 backup->lte_gnt); 808 } 809 810 static void rtw8723d_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev) 811 { 812 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00); 813 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); 814 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1); 815 } 816 817 static void rtw8723d_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev, 818 const struct iqk_backup_regs *bak) 819 { 820 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt); 821 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); 822 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path); 823 } 824 825 struct rtw_8723d_iqk_cfg { 826 const char *name; 827 u32 val_bb_sel_btg; 828 u32 reg_lutwe; 829 u32 val_txiqk_pi; 830 u32 reg_padlut; 831 u32 reg_gaintx; 832 u32 reg_bspad; 833 u32 val_wlint; 834 u32 val_wlsel; 835 u32 val_iqkpts; 836 }; 837 838 static const struct rtw_8723d_iqk_cfg iqk_tx_cfg[PATH_NR] = { 839 [PATH_S1] = { 840 .name = "S1", 841 .val_bb_sel_btg = 0x99000000, 842 .reg_lutwe = RF_LUTWE, 843 .val_txiqk_pi = 0x8214019f, 844 .reg_padlut = RF_LUTDBG, 845 .reg_gaintx = RF_GAINTX, 846 .reg_bspad = RF_BSPAD, 847 .val_wlint = 0xe0d, 848 .val_wlsel = 0x60d, 849 .val_iqkpts = 0xfa000000, 850 }, 851 [PATH_S0] = { 852 .name = "S0", 853 .val_bb_sel_btg = 0x99000280, 854 .reg_lutwe = RF_LUTWE2, 855 .val_txiqk_pi = 0x8214018a, 856 .reg_padlut = RF_TXADBG, 857 .reg_gaintx = RF_TRXIQ, 858 .reg_bspad = RF_TXATANK, 859 .val_wlint = 0xe6d, 860 .val_wlsel = 0x66d, 861 .val_iqkpts = 0xf9000000, 862 }, 863 }; 864 865 static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev, 866 const struct rtw_8723d_iqk_cfg *iqk_cfg) 867 { 868 s32 tx_x, tx_y; 869 u32 tx_fail; 870 871 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 872 rtw_read32(rtwdev, REG_IQK_RES_RY)); 873 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 874 rtw_read32(rtwdev, REG_IQK_RES_TX), 875 rtw_read32(rtwdev, REG_IQK_RES_TY)); 876 rtw_dbg(rtwdev, RTW_DBG_RFK, 877 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", 878 rtw_read32(rtwdev, 0xe90), 879 rtw_read32(rtwdev, 0xe98)); 880 881 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 882 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 883 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 884 885 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 886 return IQK_TX_OK; 887 888 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n", 889 iqk_cfg->name); 890 891 return 0; 892 } 893 894 static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev, 895 const struct rtw_8723d_iqk_cfg *iqk_cfg) 896 { 897 s32 rx_x, rx_y; 898 u32 rx_fail; 899 900 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 901 rtw_read32(rtwdev, REG_IQK_RES_RX), 902 rtw_read32(rtwdev, REG_IQK_RES_RY)); 903 904 rtw_dbg(rtwdev, RTW_DBG_RFK, 905 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", 906 rtw_read32(rtwdev, 0xea0), 907 rtw_read32(rtwdev, 0xea8)); 908 909 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 910 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 911 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 912 rx_y = abs(iqkxy_to_s32(rx_y)); 913 914 if (!rx_fail && rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 915 rx_y < IQK_RX_Y_LMT) 916 return IQK_RX_OK; 917 918 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n", 919 iqk_cfg->name); 920 921 return 0; 922 } 923 924 static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, 925 const struct rtw_8723d_iqk_cfg *iqk_cfg) 926 { 927 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000); 928 929 /* enter IQK mode */ 930 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 931 rtw8723d_iqk_config_lte_path_gnt(rtwdev); 932 933 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054); 934 mdelay(1); 935 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n", 936 iqk_cfg->name, tx ? "TX" : "RX", 937 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA)); 938 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n", 939 iqk_cfg->name, tx ? "TX" : "RX", 940 rtw_read32(rtwdev, REG_BB_SEL_BTG)); 941 942 /* One shot, LOK & IQK */ 943 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts); 944 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 945 946 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1)) 947 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name, 948 tx ? "TX" : "RX"); 949 } 950 951 static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev, 952 const struct rtw_8723d_iqk_cfg *iqk_cfg, 953 const struct iqk_backup_regs *backup) 954 { 955 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, backup); 956 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 957 958 /* leave IQK mode */ 959 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 960 mdelay(1); 961 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0); 962 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0); 963 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0); 964 } 965 966 static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev, 967 const struct rtw_8723d_iqk_cfg *iqk_cfg, 968 const struct iqk_backup_regs *backup) 969 { 970 u8 status; 971 972 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name); 973 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n", 974 iqk_cfg->name, 975 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 976 977 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 978 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 979 mdelay(1); 980 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 981 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004); 982 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d); 983 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0); 984 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 985 986 /* IQK setting */ 987 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c); 988 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 989 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi); 990 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200); 991 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 992 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 993 994 /* LOK setting */ 995 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 996 997 /* PA, PAD setting */ 998 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 999 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 1000 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3); 1001 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf); 1002 1003 /* LOK setting for 8723D */ 1004 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1); 1005 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1); 1006 1007 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 1008 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 1009 1010 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n", 1011 iqk_cfg->name, 1012 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1013 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n", 1014 iqk_cfg->name, 1015 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1016 1017 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg); 1018 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 1019 1020 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 1021 1022 return status; 1023 } 1024 1025 static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev, 1026 const struct rtw_8723d_iqk_cfg *iqk_cfg, 1027 const struct iqk_backup_regs *backup) 1028 { 1029 u32 tx_x, tx_y; 1030 u8 status; 1031 1032 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n", 1033 iqk_cfg->name); 1034 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n", 1035 iqk_cfg->name, 1036 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1037 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 1038 1039 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1040 1041 /* IQK setting */ 1042 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1043 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1044 1045 /* path IQK setting */ 1046 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1047 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1048 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1049 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1050 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000); 1051 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000); 1052 1053 /* LOK setting */ 1054 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 1055 1056 /* RXIQK mode */ 1057 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 1058 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006); 1059 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 1060 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb); 1061 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 1062 1063 /* PA/PAD=0 */ 1064 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 1065 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 1066 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 1067 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 1068 1069 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n", 1070 iqk_cfg->name, 1071 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1072 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n", 1073 iqk_cfg->name, 1074 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1075 1076 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 1077 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 1078 1079 if (!status) 1080 goto restore; 1081 1082 /* second round */ 1083 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1084 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1085 1086 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 1087 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 1088 rtw_read32(rtwdev, REG_TXIQK_11N), 1089 BIT_SET_TXIQK_11N(tx_x, tx_y)); 1090 1091 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n", 1092 iqk_cfg->name); 1093 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n", 1094 iqk_cfg->name, 1095 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1096 1097 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1098 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 1099 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 1100 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1101 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1102 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000); 1103 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400); 1104 1105 /* LOK setting */ 1106 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 1107 1108 /* RXIQK mode */ 1109 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1110 mdelay(1); 1111 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1); 1112 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007); 1113 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 1114 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb); 1115 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 1116 1117 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n", 1118 iqk_cfg->name, 1119 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1120 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n", 1121 iqk_cfg->name, 1122 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1123 1124 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 1125 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg); 1126 1127 restore: 1128 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 1129 1130 return status; 1131 } 1132 1133 static 1134 void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1135 { 1136 s32 oldval_1; 1137 s32 x, y; 1138 s32 tx1_a, tx1_a_ext; 1139 s32 tx1_c, tx1_c_ext; 1140 1141 if (result[IQK_S1_TX_X] == 0) 1142 return; 1143 1144 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1145 BIT_MASK_TXIQ_ELM_D); 1146 1147 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 1148 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 1149 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1150 BIT_MASK_TXIQ_ELM_A, tx1_a); 1151 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1152 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 1153 1154 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 1155 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 1156 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1157 BIT_SET_TXIQ_ELM_C1(tx1_c)); 1158 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1159 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 1160 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1161 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 1162 1163 rtw_dbg(rtwdev, RTW_DBG_RFK, 1164 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 1165 x, tx1_a, oldval_1); 1166 rtw_dbg(rtwdev, RTW_DBG_RFK, 1167 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 1168 1169 if (result[IQK_S1_RX_X] == 0) 1170 return; 1171 1172 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X, 1173 result[IQK_S1_RX_X]); 1174 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1, 1175 BIT_SET_RXIQ_S1_Y1(result[IQK_S1_RX_Y])); 1176 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 1177 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 1178 } 1179 1180 static 1181 void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1182 { 1183 s32 oldval_0; 1184 s32 x, y; 1185 s32 tx0_a, tx0_a_ext; 1186 s32 tx0_c, tx0_c_ext; 1187 1188 if (result[IQK_S0_TX_X] == 0) 1189 return; 1190 1191 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0); 1192 1193 x = iqkxy_to_s32(result[IQK_S0_TX_X]); 1194 tx0_a = iqk_mult(x, oldval_0, &tx0_a_ext); 1195 1196 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a); 1197 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext); 1198 1199 y = iqkxy_to_s32(result[IQK_S0_TX_Y]); 1200 tx0_c = iqk_mult(y, oldval_0, &tx0_c_ext); 1201 1202 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c); 1203 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext); 1204 1205 if (result[IQK_S0_RX_X] == 0) 1206 return; 1207 1208 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0, 1209 result[IQK_S0_RX_X]); 1210 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0, 1211 result[IQK_S0_RX_Y]); 1212 } 1213 1214 static void rtw8723d_iqk_path_adda_on(struct rtw_dev *rtwdev) 1215 { 1216 int i; 1217 1218 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1219 rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016); 1220 } 1221 1222 static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev) 1223 { 1224 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); 1225 } 1226 1227 static 1228 void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path) 1229 { 1230 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n", 1231 path == RF_PATH_A ? "S1" : "S0"); 1232 1233 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1234 mdelay(1); 1235 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000); 1236 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1237 } 1238 1239 static 1240 bool rtw8723d_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR], 1241 u8 c1, u8 c2) 1242 { 1243 u32 i, j, diff; 1244 u32 bitmap = 0; 1245 u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID}; 1246 bool ret = true; 1247 1248 s32 tmp1, tmp2; 1249 1250 for (i = 0; i < IQK_NR; i++) { 1251 tmp1 = iqkxy_to_s32(result[c1][i]); 1252 tmp2 = iqkxy_to_s32(result[c2][i]); 1253 1254 diff = abs(tmp1 - tmp2); 1255 1256 if (diff <= MAX_TOLERANCE) 1257 continue; 1258 1259 if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) { 1260 if (result[c1][i] + result[c1][i + 1] == 0) 1261 candidate[i / IQK_SX_NR] = c2; 1262 else if (result[c2][i] + result[c2][i + 1] == 0) 1263 candidate[i / IQK_SX_NR] = c1; 1264 else 1265 bitmap |= BIT(i); 1266 } else { 1267 bitmap |= BIT(i); 1268 } 1269 } 1270 1271 if (bitmap != 0) 1272 goto check_sim; 1273 1274 for (i = 0; i < PATH_NR; i++) { 1275 if (candidate[i] == IQK_ROUND_INVALID) 1276 continue; 1277 1278 for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++) 1279 result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j]; 1280 ret = false; 1281 } 1282 1283 return ret; 1284 1285 check_sim: 1286 for (i = 0; i < IQK_NR; i++) { 1287 j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */ 1288 if (bitmap & GENMASK(j + 1, j)) 1289 continue; 1290 1291 result[IQK_ROUND_HYBRID][i] = result[c1][i]; 1292 } 1293 1294 return false; 1295 } 1296 1297 static 1298 void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723d_path path) 1299 { 1300 if (path == PATH_S0) { 1301 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A); 1302 rtw8723d_iqk_path_adda_on(rtwdev); 1303 } 1304 1305 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1306 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1307 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1308 1309 if (path == PATH_S1) { 1310 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B); 1311 rtw8723d_iqk_path_adda_on(rtwdev); 1312 } 1313 } 1314 1315 static 1316 void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 1317 const struct iqk_backup_regs *backup) 1318 { 1319 u32 i; 1320 u8 s1_ok, s0_ok; 1321 1322 rtw_dbg(rtwdev, RTW_DBG_RFK, 1323 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 1324 1325 rtw8723d_iqk_path_adda_on(rtwdev); 1326 rtw8723d_iqk_config_mac(rtwdev); 1327 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 1328 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611); 1329 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 1330 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200); 1331 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1); 1332 1333 for (i = 0; i < PATH_IQK_RETRY; i++) { 1334 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 1335 if (s1_ok == IQK_TX_OK) { 1336 rtw_dbg(rtwdev, RTW_DBG_RFK, 1337 "[IQK] path S1 Tx IQK Success!!\n"); 1338 result[t][IQK_S1_TX_X] = 1339 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1340 result[t][IQK_S1_TX_Y] = 1341 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1342 break; 1343 } 1344 1345 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n"); 1346 result[t][IQK_S1_TX_X] = 0x100; 1347 result[t][IQK_S1_TX_Y] = 0x0; 1348 } 1349 1350 for (i = 0; i < PATH_IQK_RETRY; i++) { 1351 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 1352 if (s1_ok == (IQK_TX_OK | IQK_RX_OK)) { 1353 rtw_dbg(rtwdev, RTW_DBG_RFK, 1354 "[IQK] path S1 Rx IQK Success!!\n"); 1355 result[t][IQK_S1_RX_X] = 1356 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1357 result[t][IQK_S1_RX_Y] = 1358 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1359 break; 1360 } 1361 1362 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n"); 1363 result[t][IQK_S1_RX_X] = 0x100; 1364 result[t][IQK_S1_RX_Y] = 0x0; 1365 } 1366 1367 if (s1_ok == 0x0) 1368 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n"); 1369 1370 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0); 1371 1372 for (i = 0; i < PATH_IQK_RETRY; i++) { 1373 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 1374 if (s0_ok == IQK_TX_OK) { 1375 rtw_dbg(rtwdev, RTW_DBG_RFK, 1376 "[IQK] path S0 Tx IQK Success!!\n"); 1377 result[t][IQK_S0_TX_X] = 1378 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1379 result[t][IQK_S0_TX_Y] = 1380 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1381 break; 1382 } 1383 1384 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n"); 1385 result[t][IQK_S0_TX_X] = 0x100; 1386 result[t][IQK_S0_TX_Y] = 0x0; 1387 } 1388 1389 for (i = 0; i < PATH_IQK_RETRY; i++) { 1390 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 1391 if (s0_ok == (IQK_TX_OK | IQK_RX_OK)) { 1392 rtw_dbg(rtwdev, RTW_DBG_RFK, 1393 "[IQK] path S0 Rx IQK Success!!\n"); 1394 1395 result[t][IQK_S0_RX_X] = 1396 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1397 result[t][IQK_S0_RX_Y] = 1398 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1399 break; 1400 } 1401 1402 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n"); 1403 result[t][IQK_S0_RX_X] = 0x100; 1404 result[t][IQK_S0_RX_Y] = 0x0; 1405 } 1406 1407 if (s0_ok == 0x0) 1408 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n"); 1409 1410 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1411 mdelay(1); 1412 1413 rtw_dbg(rtwdev, RTW_DBG_RFK, 1414 "[IQK] back to BB mode, load original value!\n"); 1415 } 1416 1417 static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev) 1418 { 1419 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1420 s32 result[IQK_ROUND_SIZE][IQK_NR]; 1421 struct iqk_backup_regs backup; 1422 u8 i, j; 1423 u8 final_candidate = IQK_ROUND_INVALID; 1424 bool good; 1425 1426 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n"); 1427 1428 memset(result, 0, sizeof(result)); 1429 1430 rtw8723d_iqk_backup_path_ctrl(rtwdev, &backup); 1431 rtw8723d_iqk_backup_lte_path_gnt(rtwdev, &backup); 1432 rtw8723d_iqk_backup_regs(rtwdev, &backup); 1433 1434 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 1435 rtw8723d_iqk_config_path_ctrl(rtwdev); 1436 rtw8723d_iqk_config_lte_path_gnt(rtwdev); 1437 1438 rtw8723d_iqk_one_round(rtwdev, result, i, &backup); 1439 1440 if (i > IQK_ROUND_0) 1441 rtw8723d_iqk_restore_regs(rtwdev, &backup); 1442 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, &backup); 1443 rtw8723d_iqk_restore_path_ctrl(rtwdev, &backup); 1444 1445 for (j = IQK_ROUND_0; j < i; j++) { 1446 good = rtw8723d_iqk_similarity_cmp(rtwdev, result, j, i); 1447 1448 if (good) { 1449 final_candidate = j; 1450 rtw_dbg(rtwdev, RTW_DBG_RFK, 1451 "[IQK] cmp %d:%d final_candidate is %x\n", 1452 j, i, final_candidate); 1453 goto iqk_done; 1454 } 1455 } 1456 } 1457 1458 if (final_candidate == IQK_ROUND_INVALID) { 1459 s32 reg_tmp = 0; 1460 1461 for (i = 0; i < IQK_NR; i++) 1462 reg_tmp += result[IQK_ROUND_HYBRID][i]; 1463 1464 if (reg_tmp != 0) { 1465 final_candidate = IQK_ROUND_HYBRID; 1466 } else { 1467 WARN(1, "IQK is failed\n"); 1468 goto out; 1469 } 1470 } 1471 1472 iqk_done: 1473 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]); 1474 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]); 1475 1476 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 1477 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 1478 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 1479 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 1480 dm_info->iqk.done = true; 1481 1482 out: 1483 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 1484 1485 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 1486 final_candidate); 1487 1488 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 1489 rtw_dbg(rtwdev, RTW_DBG_RFK, 1490 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 1491 i, 1492 result[i][0], result[i][1], result[i][2], result[i][3], 1493 result[i][4], result[i][5], result[i][6], result[i][7], 1494 final_candidate == i ? "(final candidate)" : ""); 1495 1496 rtw_dbg(rtwdev, RTW_DBG_RFK, 1497 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1498 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1499 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1500 rtw_read32(rtwdev, REG_A_RXIQI), 1501 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1502 rtw_dbg(rtwdev, RTW_DBG_RFK, 1503 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1504 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1505 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1506 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1507 1508 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n"); 1509 } 1510 1511 static void rtw8723d_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1512 { 1513 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1514 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1515 u8 cck_n_rx; 1516 1517 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1518 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1519 1520 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1521 return; 1522 1523 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1524 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1525 rtw_dbg(rtwdev, RTW_DBG_PHY, 1526 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1527 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1528 dm_info->cck_pd_default + new_lvl * 2, 1529 pd[new_lvl], dm_info->cck_fa_avg); 1530 1531 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1532 1533 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1534 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1535 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1536 dm_info->cck_pd_default + new_lvl * 2); 1537 } 1538 1539 /* for coex */ 1540 static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev) 1541 { 1542 /* enable TBTT nterrupt */ 1543 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1544 1545 /* BT report packet sample rate */ 1546 /* 0x790[5:0]=0x5 */ 1547 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 1548 1549 /* enable BT counter statistics */ 1550 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1551 1552 /* enable PTA (3-wire function form BT side) */ 1553 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1554 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 1555 1556 /* enable PTA (tx/rx signal form WiFi side) */ 1557 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1558 } 1559 1560 static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1561 { 1562 } 1563 1564 static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1565 { 1566 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0); 1567 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); 1568 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0); 1569 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0); 1570 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); 1571 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); 1572 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0); 1573 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0); 1574 } 1575 1576 static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1577 { 1578 struct rtw_efuse *efuse = &rtwdev->efuse; 1579 struct rtw_coex *coex = &rtwdev->coex; 1580 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1581 bool aux = efuse->bt_setting & BIT(6); 1582 1583 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1584 coex_rfe->ant_switch_polarity = 0; 1585 coex_rfe->ant_switch_exist = false; 1586 coex_rfe->ant_switch_with_bt = false; 1587 coex_rfe->ant_switch_diversity = false; 1588 coex_rfe->wlg_at_btg = true; 1589 1590 /* decide antenna at main or aux */ 1591 if (efuse->share_ant) { 1592 if (aux) 1593 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80); 1594 else 1595 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200); 1596 } else { 1597 if (aux) 1598 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280); 1599 else 1600 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0); 1601 } 1602 1603 /* disable LTE coex in wifi side */ 1604 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1605 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1606 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1607 } 1608 1609 static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1610 { 1611 struct rtw_coex *coex = &rtwdev->coex; 1612 struct rtw_coex_dm *coex_dm = &coex->dm; 1613 static const u8 wl_tx_power[] = {0xb2, 0x90}; 1614 u8 pwr; 1615 1616 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1617 return; 1618 1619 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1620 1621 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1622 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1623 1624 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1625 1626 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr); 1627 } 1628 1629 static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1630 { 1631 struct rtw_coex *coex = &rtwdev->coex; 1632 struct rtw_coex_dm *coex_dm = &coex->dm; 1633 /* WL Rx Low gain on */ 1634 static const u32 wl_rx_low_gain_on[] = { 1635 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101, 1636 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101, 1637 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101, 1638 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001, 1639 0xcd260001, 0xcc270001, 0x8f280001 1640 }; 1641 /* WL Rx Low gain off */ 1642 static const u32 wl_rx_low_gain_off[] = { 1643 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101, 1644 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101, 1645 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101, 1646 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101, 1647 0x44260101, 0x43270101, 0x42280101 1648 }; 1649 u8 i; 1650 1651 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1652 return; 1653 1654 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1655 1656 if (coex_dm->cur_wl_rx_low_gain_en) { 1657 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1658 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]); 1659 } else { 1660 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1661 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]); 1662 } 1663 } 1664 1665 static u8 rtw8723d_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) 1666 { 1667 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1668 u8 tx_rate = dm_info->tx_rate; 1669 u8 limit_ofdm = 30; 1670 1671 switch (tx_rate) { 1672 case DESC_RATE1M...DESC_RATE5_5M: 1673 case DESC_RATE11M: 1674 break; 1675 case DESC_RATE6M...DESC_RATE48M: 1676 limit_ofdm = 36; 1677 break; 1678 case DESC_RATE54M: 1679 limit_ofdm = 34; 1680 break; 1681 case DESC_RATEMCS0...DESC_RATEMCS2: 1682 limit_ofdm = 38; 1683 break; 1684 case DESC_RATEMCS3...DESC_RATEMCS4: 1685 limit_ofdm = 36; 1686 break; 1687 case DESC_RATEMCS5...DESC_RATEMCS7: 1688 limit_ofdm = 34; 1689 break; 1690 default: 1691 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); 1692 break; 1693 } 1694 1695 return limit_ofdm; 1696 } 1697 1698 static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1699 u32 ofdm_swing, u8 rf_path) 1700 { 1701 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1702 s32 ele_A, ele_D, ele_C; 1703 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1704 s32 iqk_result_x; 1705 s32 iqk_result_y; 1706 s32 value32; 1707 1708 switch (rf_path) { 1709 default: 1710 case RF_PATH_A: 1711 iqk_result_x = dm_info->iqk.result.s1_x; 1712 iqk_result_y = dm_info->iqk.result.s1_y; 1713 break; 1714 case RF_PATH_B: 1715 iqk_result_x = dm_info->iqk.result.s0_x; 1716 iqk_result_y = dm_info->iqk.result.s0_y; 1717 break; 1718 } 1719 1720 /* new element D */ 1721 ele_D = OFDM_SWING_D(ofdm_swing); 1722 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1723 /* new element A */ 1724 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1725 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1726 /* new element C */ 1727 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1728 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1729 1730 switch (rf_path) { 1731 case RF_PATH_A: 1732 default: 1733 /* write new elements A, C, D, and element B is always 0 */ 1734 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1735 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1736 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1737 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1738 value32); 1739 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1740 value32 &= ~BIT_MASK_OFDM0_EXTS; 1741 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1742 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1743 break; 1744 1745 case RF_PATH_B: 1746 /* write new elements A, C, D, and element B is always 0 */ 1747 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D); 1748 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C); 1749 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A); 1750 1751 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 1752 ele_D_ext); 1753 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 1754 ele_A_ext); 1755 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 1756 ele_C_ext); 1757 break; 1758 } 1759 } 1760 1761 static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1762 u8 rf_path) 1763 { 1764 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1765 s32 value32; 1766 u32 ofdm_swing; 1767 1768 if (ofdm_index >= RTW_OFDM_SWING_TABLE_SIZE) 1769 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1; 1770 else if (ofdm_index < 0) 1771 ofdm_index = 0; 1772 1773 ofdm_swing = rtw8723d_ofdm_swing_table[ofdm_index]; 1774 1775 if (dm_info->iqk.done) { 1776 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1777 return; 1778 } 1779 1780 switch (rf_path) { 1781 case RF_PATH_A: 1782 default: 1783 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1784 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1785 0x00); 1786 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1787 value32 &= ~BIT_MASK_OFDM0_EXTS; 1788 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1789 break; 1790 1791 case RF_PATH_B: 1792 /* image S1:c80 to S0:Cd0 and Cd4 */ 1793 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, 1794 OFDM_SWING_A(ofdm_swing)); 1795 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0, 1796 OFDM_SWING_B(ofdm_swing)); 1797 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, 1798 OFDM_SWING_C(ofdm_swing)); 1799 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, 1800 OFDM_SWING_D(ofdm_swing)); 1801 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0); 1802 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0); 1803 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0); 1804 break; 1805 } 1806 } 1807 1808 static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1809 s8 txagc_idx) 1810 { 1811 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1812 1813 dm_info->txagc_remnant_ofdm = txagc_idx; 1814 1815 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1816 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B); 1817 } 1818 1819 static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1820 s8 txagc_idx) 1821 { 1822 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1823 1824 dm_info->txagc_remnant_cck = txagc_idx; 1825 1826 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, 1827 rtw8723d_cck_swing_table[swing_idx]); 1828 } 1829 1830 static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1831 { 1832 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1833 struct rtw_hal *hal = &rtwdev->hal; 1834 u8 limit_ofdm; 1835 u8 limit_cck = 40; 1836 s8 final_ofdm_swing_index; 1837 s8 final_cck_swing_index; 1838 1839 limit_ofdm = rtw8723d_pwrtrack_get_limit_ofdm(rtwdev); 1840 1841 final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX + 1842 dm_info->delta_power_index[path]; 1843 final_cck_swing_index = RTW_DEF_CCK_SWING_INDEX + 1844 dm_info->delta_power_index[path]; 1845 1846 if (final_ofdm_swing_index > limit_ofdm) 1847 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1848 final_ofdm_swing_index - limit_ofdm); 1849 else if (final_ofdm_swing_index < 0) 1850 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1851 final_ofdm_swing_index); 1852 else 1853 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1854 1855 if (final_cck_swing_index > limit_cck) 1856 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1857 final_cck_swing_index - limit_cck); 1858 else if (final_cck_swing_index < 0) 1859 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0, 1860 final_cck_swing_index); 1861 else 1862 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1863 1864 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1865 } 1866 1867 static void rtw8723d_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, 1868 u8 delta) 1869 { 1870 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1871 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; 1872 const s8 *pwrtrk_xtal; 1873 s8 xtal_cap; 1874 1875 if (dm_info->thermal_avg[therm_path] > 1876 rtwdev->efuse.thermal_meter[therm_path]) 1877 pwrtrk_xtal = tbl->pwrtrk_xtal_p; 1878 else 1879 pwrtrk_xtal = tbl->pwrtrk_xtal_n; 1880 1881 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 1882 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); 1883 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 1884 xtal_cap | (xtal_cap << 6)); 1885 } 1886 1887 static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) 1888 { 1889 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1890 struct rtw_swing_table swing_table; 1891 u8 thermal_value, delta, path; 1892 bool do_iqk = false; 1893 1894 rtw_phy_config_swing_table(rtwdev, &swing_table); 1895 1896 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1897 return; 1898 1899 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1900 1901 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1902 1903 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1904 1905 if (do_iqk) 1906 rtw8723d_lck(rtwdev); 1907 1908 if (dm_info->pwr_trk_init_trigger) 1909 dm_info->pwr_trk_init_trigger = false; 1910 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1911 RF_PATH_A)) 1912 goto iqk; 1913 1914 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1915 1916 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1917 1918 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1919 s8 delta_cur, delta_last; 1920 1921 delta_last = dm_info->delta_power_index[path]; 1922 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1923 path, RF_PATH_A, delta); 1924 if (delta_last == delta_cur) 1925 continue; 1926 1927 dm_info->delta_power_index[path] = delta_cur; 1928 rtw8723d_pwrtrack_set(rtwdev, path); 1929 } 1930 1931 rtw8723d_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1932 1933 iqk: 1934 if (do_iqk) 1935 rtw8723d_phy_calibration(rtwdev); 1936 } 1937 1938 static void rtw8723d_pwr_track(struct rtw_dev *rtwdev) 1939 { 1940 struct rtw_efuse *efuse = &rtwdev->efuse; 1941 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1942 1943 if (efuse->power_track_type != 0) 1944 return; 1945 1946 if (!dm_info->pwr_trk_triggered) { 1947 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1948 GENMASK(17, 16), 0x03); 1949 dm_info->pwr_trk_triggered = true; 1950 return; 1951 } 1952 1953 rtw8723d_phy_pwrtrack(rtwdev); 1954 dm_info->pwr_trk_triggered = false; 1955 } 1956 1957 static void rtw8723d_fill_txdesc_checksum(struct rtw_dev *rtwdev, 1958 struct rtw_tx_pkt_info *pkt_info, 1959 u8 *txdesc) 1960 { 1961 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ 1962 __le16 chksum = 0; 1963 __le16 *data = (__le16 *)(txdesc); 1964 1965 SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000); 1966 1967 while (words--) 1968 chksum ^= *data++; 1969 1970 chksum = ~chksum; 1971 1972 SET_TX_DESC_TXDESC_CHECKSUM(txdesc, __le16_to_cpu(chksum)); 1973 } 1974 1975 static struct rtw_chip_ops rtw8723d_ops = { 1976 .phy_set_param = rtw8723d_phy_set_param, 1977 .read_efuse = rtw8723d_read_efuse, 1978 .query_rx_desc = rtw8723d_query_rx_desc, 1979 .set_channel = rtw8723d_set_channel, 1980 .mac_init = rtw8723d_mac_init, 1981 .shutdown = rtw8723d_shutdown, 1982 .read_rf = rtw_phy_read_rf_sipi, 1983 .write_rf = rtw_phy_write_rf_reg_sipi, 1984 .set_tx_power_index = rtw8723d_set_tx_power_index, 1985 .set_antenna = NULL, 1986 .cfg_ldo25 = rtw8723d_cfg_ldo25, 1987 .efuse_grant = rtw8723d_efuse_grant, 1988 .false_alarm_statistics = rtw8723d_false_alarm_statistics, 1989 .phy_calibration = rtw8723d_phy_calibration, 1990 .cck_pd_set = rtw8723d_phy_cck_pd_set, 1991 .pwr_track = rtw8723d_pwr_track, 1992 .config_bfee = NULL, 1993 .set_gid_table = NULL, 1994 .cfg_csi_rate = NULL, 1995 .fill_txdesc_checksum = rtw8723d_fill_txdesc_checksum, 1996 1997 .coex_set_init = rtw8723d_coex_cfg_init, 1998 .coex_set_ant_switch = NULL, 1999 .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix, 2000 .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug, 2001 .coex_set_rfe_type = rtw8723d_coex_cfg_rfe_type, 2002 .coex_set_wl_tx_power = rtw8723d_coex_cfg_wl_tx_power, 2003 .coex_set_wl_rx_gain = rtw8723d_coex_cfg_wl_rx_gain, 2004 }; 2005 2006 /* Shared-Antenna Coex Table */ 2007 static const struct coex_table_para table_sant_8723d[] = { 2008 {0xffffffff, 0xffffffff}, /* case-0 */ 2009 {0x55555555, 0x55555555}, 2010 {0x66555555, 0x66555555}, 2011 {0xaaaaaaaa, 0xaaaaaaaa}, 2012 {0x5a5a5a5a, 0x5a5a5a5a}, 2013 {0xfafafafa, 0xfafafafa}, /* case-5 */ 2014 {0x6a5a5555, 0xaaaaaaaa}, 2015 {0x6a5a56aa, 0x6a5a56aa}, 2016 {0x6a5a5a5a, 0x6a5a5a5a}, 2017 {0x66555555, 0x5a5a5a5a}, 2018 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 2019 {0x66555555, 0x6a5a5aaa}, 2020 {0x66555555, 0x5a5a5aaa}, 2021 {0x66555555, 0x6aaa5aaa}, 2022 {0x66555555, 0xaaaa5aaa}, 2023 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 2024 {0xffff55ff, 0xfafafafa}, 2025 {0xffff55ff, 0x6afa5afa}, 2026 {0xaaffffaa, 0xfafafafa}, 2027 {0xaa5555aa, 0x5a5a5a5a}, 2028 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 2029 {0xaa5555aa, 0xaaaaaaaa}, 2030 {0xffffffff, 0x5a5a5a5a}, 2031 {0xffffffff, 0x5a5a5a5a}, 2032 {0xffffffff, 0x55555555}, 2033 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 2034 {0x55555555, 0x5a5a5a5a}, 2035 {0x55555555, 0xaaaaaaaa}, 2036 {0x55555555, 0x6a5a6a5a}, 2037 {0x66556655, 0x66556655}, 2038 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 2039 {0xffffffff, 0x5aaa5aaa}, 2040 {0x56555555, 0x5a5a5aaa}, 2041 }; 2042 2043 /* Non-Shared-Antenna Coex Table */ 2044 static const struct coex_table_para table_nsant_8723d[] = { 2045 {0xffffffff, 0xffffffff}, /* case-100 */ 2046 {0x55555555, 0x55555555}, 2047 {0x66555555, 0x66555555}, 2048 {0xaaaaaaaa, 0xaaaaaaaa}, 2049 {0x5a5a5a5a, 0x5a5a5a5a}, 2050 {0xfafafafa, 0xfafafafa}, /* case-105 */ 2051 {0x5afa5afa, 0x5afa5afa}, 2052 {0x55555555, 0xfafafafa}, 2053 {0x66555555, 0xfafafafa}, 2054 {0x66555555, 0x5a5a5a5a}, 2055 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 2056 {0x66555555, 0xaaaaaaaa}, 2057 {0xffff55ff, 0xfafafafa}, 2058 {0xffff55ff, 0x5afa5afa}, 2059 {0xffff55ff, 0xaaaaaaaa}, 2060 {0xffff55ff, 0xffff55ff}, /* case-115 */ 2061 {0xaaffffaa, 0x5afa5afa}, 2062 {0xaaffffaa, 0xaaaaaaaa}, 2063 {0xffffffff, 0xfafafafa}, 2064 {0xffffffff, 0x5afa5afa}, 2065 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 2066 {0x55ff55ff, 0x5afa5afa}, 2067 {0x55ff55ff, 0xaaaaaaaa}, 2068 {0x55ff55ff, 0x55ff55ff} 2069 }; 2070 2071 /* Shared-Antenna TDMA */ 2072 static const struct coex_tdma_para tdma_sant_8723d[] = { 2073 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2074 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 2075 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2076 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2077 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2078 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2079 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2080 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2081 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2082 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2083 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2084 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2085 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2086 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2087 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2088 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 2089 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2090 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2091 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2092 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2093 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 2094 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2095 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2096 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2097 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 2098 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 2099 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 2100 { {0x61, 0x08, 0x03, 0x11, 0x11} } 2101 }; 2102 2103 /* Non-Shared-Antenna TDMA */ 2104 static const struct coex_tdma_para tdma_nsant_8723d[] = { 2105 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */ 2106 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */ 2107 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2108 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2109 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2110 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2111 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2112 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2113 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2114 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2115 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2116 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2117 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2118 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2119 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2120 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2121 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2122 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2123 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2124 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2125 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 2126 { {0x51, 0x08, 0x03, 0x10, 0x50} } 2127 }; 2128 2129 /* rssi in percentage % (dbm = % - 100) */ 2130 static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30}; 2131 static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30}; 2132 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} }; 2133 2134 static const struct rtw_hw_reg btg_reg_8723d = { 2135 .addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL, 2136 }; 2137 2138 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2139 static const struct coex_rf_para rf_para_tx_8723d[] = { 2140 {0, 0, false, 7}, /* for normal */ 2141 {0, 10, false, 7}, /* for WL-CPT */ 2142 {1, 0, true, 4}, 2143 {1, 2, true, 4}, 2144 {1, 10, true, 4}, 2145 {1, 15, true, 4} 2146 }; 2147 2148 static const struct coex_rf_para rf_para_rx_8723d[] = { 2149 {0, 0, false, 7}, /* for normal */ 2150 {0, 10, false, 7}, /* for WL-CPT */ 2151 {1, 0, true, 5}, 2152 {1, 2, true, 5}, 2153 {1, 10, true, 5}, 2154 {1, 15, true, 5} 2155 }; 2156 2157 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = { 2158 {0x0005, 2159 RTW_PWR_CUT_ALL_MSK, 2160 RTW_PWR_INTF_ALL_MSK, 2161 RTW_PWR_ADDR_MAC, 2162 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, 2163 {0x0086, 2164 RTW_PWR_CUT_ALL_MSK, 2165 RTW_PWR_INTF_SDIO_MSK, 2166 RTW_PWR_ADDR_SDIO, 2167 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2168 {0x0086, 2169 RTW_PWR_CUT_ALL_MSK, 2170 RTW_PWR_INTF_SDIO_MSK, 2171 RTW_PWR_ADDR_SDIO, 2172 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2173 {0x004A, 2174 RTW_PWR_CUT_ALL_MSK, 2175 RTW_PWR_INTF_USB_MSK, 2176 RTW_PWR_ADDR_MAC, 2177 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2178 {0x0005, 2179 RTW_PWR_CUT_ALL_MSK, 2180 RTW_PWR_INTF_ALL_MSK, 2181 RTW_PWR_ADDR_MAC, 2182 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, 2183 {0x0023, 2184 RTW_PWR_CUT_ALL_MSK, 2185 RTW_PWR_INTF_SDIO_MSK, 2186 RTW_PWR_ADDR_MAC, 2187 RTW_PWR_CMD_WRITE, BIT(4), 0}, 2188 {0x0301, 2189 RTW_PWR_CUT_ALL_MSK, 2190 RTW_PWR_INTF_PCI_MSK, 2191 RTW_PWR_ADDR_MAC, 2192 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2193 {0xFFFF, 2194 RTW_PWR_CUT_ALL_MSK, 2195 RTW_PWR_INTF_ALL_MSK, 2196 0, 2197 RTW_PWR_CMD_END, 0, 0}, 2198 }; 2199 2200 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = { 2201 {0x0020, 2202 RTW_PWR_CUT_ALL_MSK, 2203 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2204 RTW_PWR_ADDR_MAC, 2205 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2206 {0x0001, 2207 RTW_PWR_CUT_ALL_MSK, 2208 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2209 RTW_PWR_ADDR_MAC, 2210 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 2211 {0x0000, 2212 RTW_PWR_CUT_ALL_MSK, 2213 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2214 RTW_PWR_ADDR_MAC, 2215 RTW_PWR_CMD_WRITE, BIT(5), 0}, 2216 {0x0005, 2217 RTW_PWR_CUT_ALL_MSK, 2218 RTW_PWR_INTF_ALL_MSK, 2219 RTW_PWR_ADDR_MAC, 2220 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 2221 {0x0075, 2222 RTW_PWR_CUT_ALL_MSK, 2223 RTW_PWR_INTF_PCI_MSK, 2224 RTW_PWR_ADDR_MAC, 2225 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2226 {0x0006, 2227 RTW_PWR_CUT_ALL_MSK, 2228 RTW_PWR_INTF_ALL_MSK, 2229 RTW_PWR_ADDR_MAC, 2230 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2231 {0x0075, 2232 RTW_PWR_CUT_ALL_MSK, 2233 RTW_PWR_INTF_PCI_MSK, 2234 RTW_PWR_ADDR_MAC, 2235 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2236 {0x0006, 2237 RTW_PWR_CUT_ALL_MSK, 2238 RTW_PWR_INTF_ALL_MSK, 2239 RTW_PWR_ADDR_MAC, 2240 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2241 {0x0005, 2242 RTW_PWR_CUT_ALL_MSK, 2243 RTW_PWR_INTF_ALL_MSK, 2244 RTW_PWR_ADDR_MAC, 2245 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, 2246 {0x0005, 2247 RTW_PWR_CUT_ALL_MSK, 2248 RTW_PWR_INTF_ALL_MSK, 2249 RTW_PWR_ADDR_MAC, 2250 RTW_PWR_CMD_WRITE, BIT(7), 0}, 2251 {0x0005, 2252 RTW_PWR_CUT_ALL_MSK, 2253 RTW_PWR_INTF_ALL_MSK, 2254 RTW_PWR_ADDR_MAC, 2255 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 2256 {0x0005, 2257 RTW_PWR_CUT_ALL_MSK, 2258 RTW_PWR_INTF_ALL_MSK, 2259 RTW_PWR_ADDR_MAC, 2260 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2261 {0x0005, 2262 RTW_PWR_CUT_ALL_MSK, 2263 RTW_PWR_INTF_ALL_MSK, 2264 RTW_PWR_ADDR_MAC, 2265 RTW_PWR_CMD_POLLING, BIT(0), 0}, 2266 {0x0010, 2267 RTW_PWR_CUT_ALL_MSK, 2268 RTW_PWR_INTF_ALL_MSK, 2269 RTW_PWR_ADDR_MAC, 2270 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 2271 {0x0049, 2272 RTW_PWR_CUT_ALL_MSK, 2273 RTW_PWR_INTF_ALL_MSK, 2274 RTW_PWR_ADDR_MAC, 2275 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2276 {0x0063, 2277 RTW_PWR_CUT_ALL_MSK, 2278 RTW_PWR_INTF_ALL_MSK, 2279 RTW_PWR_ADDR_MAC, 2280 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2281 {0x0062, 2282 RTW_PWR_CUT_ALL_MSK, 2283 RTW_PWR_INTF_ALL_MSK, 2284 RTW_PWR_ADDR_MAC, 2285 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2286 {0x0058, 2287 RTW_PWR_CUT_ALL_MSK, 2288 RTW_PWR_INTF_ALL_MSK, 2289 RTW_PWR_ADDR_MAC, 2290 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2291 {0x005A, 2292 RTW_PWR_CUT_ALL_MSK, 2293 RTW_PWR_INTF_ALL_MSK, 2294 RTW_PWR_ADDR_MAC, 2295 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2296 {0x0068, 2297 RTW_PWR_CUT_TEST_MSK, 2298 RTW_PWR_INTF_ALL_MSK, 2299 RTW_PWR_ADDR_MAC, 2300 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 2301 {0x0069, 2302 RTW_PWR_CUT_ALL_MSK, 2303 RTW_PWR_INTF_ALL_MSK, 2304 RTW_PWR_ADDR_MAC, 2305 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 2306 {0x001f, 2307 RTW_PWR_CUT_ALL_MSK, 2308 RTW_PWR_INTF_ALL_MSK, 2309 RTW_PWR_ADDR_MAC, 2310 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2311 {0x0077, 2312 RTW_PWR_CUT_ALL_MSK, 2313 RTW_PWR_INTF_ALL_MSK, 2314 RTW_PWR_ADDR_MAC, 2315 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2316 {0x001f, 2317 RTW_PWR_CUT_ALL_MSK, 2318 RTW_PWR_INTF_ALL_MSK, 2319 RTW_PWR_ADDR_MAC, 2320 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 2321 {0x0077, 2322 RTW_PWR_CUT_ALL_MSK, 2323 RTW_PWR_INTF_ALL_MSK, 2324 RTW_PWR_ADDR_MAC, 2325 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 2326 {0xFFFF, 2327 RTW_PWR_CUT_ALL_MSK, 2328 RTW_PWR_INTF_ALL_MSK, 2329 0, 2330 RTW_PWR_CMD_END, 0, 0}, 2331 }; 2332 2333 static const struct rtw_pwr_seq_cmd *card_enable_flow_8723d[] = { 2334 trans_carddis_to_cardemu_8723d, 2335 trans_cardemu_to_act_8723d, 2336 NULL 2337 }; 2338 2339 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = { 2340 {0x0301, 2341 RTW_PWR_CUT_ALL_MSK, 2342 RTW_PWR_INTF_PCI_MSK, 2343 RTW_PWR_ADDR_MAC, 2344 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 2345 {0x0522, 2346 RTW_PWR_CUT_ALL_MSK, 2347 RTW_PWR_INTF_ALL_MSK, 2348 RTW_PWR_ADDR_MAC, 2349 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 2350 {0x05F8, 2351 RTW_PWR_CUT_ALL_MSK, 2352 RTW_PWR_INTF_ALL_MSK, 2353 RTW_PWR_ADDR_MAC, 2354 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2355 {0x05F9, 2356 RTW_PWR_CUT_ALL_MSK, 2357 RTW_PWR_INTF_ALL_MSK, 2358 RTW_PWR_ADDR_MAC, 2359 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2360 {0x05FA, 2361 RTW_PWR_CUT_ALL_MSK, 2362 RTW_PWR_INTF_ALL_MSK, 2363 RTW_PWR_ADDR_MAC, 2364 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2365 {0x05FB, 2366 RTW_PWR_CUT_ALL_MSK, 2367 RTW_PWR_INTF_ALL_MSK, 2368 RTW_PWR_ADDR_MAC, 2369 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2370 {0x0002, 2371 RTW_PWR_CUT_ALL_MSK, 2372 RTW_PWR_INTF_ALL_MSK, 2373 RTW_PWR_ADDR_MAC, 2374 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2375 {0x0002, 2376 RTW_PWR_CUT_ALL_MSK, 2377 RTW_PWR_INTF_ALL_MSK, 2378 RTW_PWR_ADDR_MAC, 2379 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 2380 {0x0002, 2381 RTW_PWR_CUT_ALL_MSK, 2382 RTW_PWR_INTF_ALL_MSK, 2383 RTW_PWR_ADDR_MAC, 2384 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2385 {0x0100, 2386 RTW_PWR_CUT_ALL_MSK, 2387 RTW_PWR_INTF_ALL_MSK, 2388 RTW_PWR_ADDR_MAC, 2389 RTW_PWR_CMD_WRITE, 0xFF, 0x03}, 2390 {0x0101, 2391 RTW_PWR_CUT_ALL_MSK, 2392 RTW_PWR_INTF_ALL_MSK, 2393 RTW_PWR_ADDR_MAC, 2394 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2395 {0x0093, 2396 RTW_PWR_CUT_ALL_MSK, 2397 RTW_PWR_INTF_SDIO_MSK, 2398 RTW_PWR_ADDR_MAC, 2399 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2400 {0x0553, 2401 RTW_PWR_CUT_ALL_MSK, 2402 RTW_PWR_INTF_ALL_MSK, 2403 RTW_PWR_ADDR_MAC, 2404 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2405 {0xFFFF, 2406 RTW_PWR_CUT_ALL_MSK, 2407 RTW_PWR_INTF_ALL_MSK, 2408 0, 2409 RTW_PWR_CMD_END, 0, 0}, 2410 }; 2411 2412 static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = { 2413 {0x0003, 2414 RTW_PWR_CUT_ALL_MSK, 2415 RTW_PWR_INTF_ALL_MSK, 2416 RTW_PWR_ADDR_MAC, 2417 RTW_PWR_CMD_WRITE, BIT(2), 0}, 2418 {0x0080, 2419 RTW_PWR_CUT_ALL_MSK, 2420 RTW_PWR_INTF_ALL_MSK, 2421 RTW_PWR_ADDR_MAC, 2422 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2423 {0xFFFF, 2424 RTW_PWR_CUT_ALL_MSK, 2425 RTW_PWR_INTF_ALL_MSK, 2426 0, 2427 RTW_PWR_CMD_END, 0, 0}, 2428 }; 2429 2430 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = { 2431 {0x0002, 2432 RTW_PWR_CUT_ALL_MSK, 2433 RTW_PWR_INTF_ALL_MSK, 2434 RTW_PWR_ADDR_MAC, 2435 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2436 {0x0049, 2437 RTW_PWR_CUT_ALL_MSK, 2438 RTW_PWR_INTF_ALL_MSK, 2439 RTW_PWR_ADDR_MAC, 2440 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2441 {0x0006, 2442 RTW_PWR_CUT_ALL_MSK, 2443 RTW_PWR_INTF_ALL_MSK, 2444 RTW_PWR_ADDR_MAC, 2445 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2446 {0x0005, 2447 RTW_PWR_CUT_ALL_MSK, 2448 RTW_PWR_INTF_ALL_MSK, 2449 RTW_PWR_ADDR_MAC, 2450 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2451 {0x0005, 2452 RTW_PWR_CUT_ALL_MSK, 2453 RTW_PWR_INTF_ALL_MSK, 2454 RTW_PWR_ADDR_MAC, 2455 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2456 {0x0010, 2457 RTW_PWR_CUT_ALL_MSK, 2458 RTW_PWR_INTF_ALL_MSK, 2459 RTW_PWR_ADDR_MAC, 2460 RTW_PWR_CMD_WRITE, BIT(6), 0}, 2461 {0x0000, 2462 RTW_PWR_CUT_ALL_MSK, 2463 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2464 RTW_PWR_ADDR_MAC, 2465 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2466 {0x0020, 2467 RTW_PWR_CUT_ALL_MSK, 2468 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2469 RTW_PWR_ADDR_MAC, 2470 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2471 {0xFFFF, 2472 RTW_PWR_CUT_ALL_MSK, 2473 RTW_PWR_INTF_ALL_MSK, 2474 0, 2475 RTW_PWR_CMD_END, 0, 0}, 2476 }; 2477 2478 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = { 2479 {0x0007, 2480 RTW_PWR_CUT_ALL_MSK, 2481 RTW_PWR_INTF_SDIO_MSK, 2482 RTW_PWR_ADDR_MAC, 2483 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 2484 {0x0005, 2485 RTW_PWR_CUT_ALL_MSK, 2486 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2487 RTW_PWR_ADDR_MAC, 2488 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 2489 {0x0005, 2490 RTW_PWR_CUT_ALL_MSK, 2491 RTW_PWR_INTF_PCI_MSK, 2492 RTW_PWR_ADDR_MAC, 2493 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2494 {0x0005, 2495 RTW_PWR_CUT_ALL_MSK, 2496 RTW_PWR_INTF_PCI_MSK, 2497 RTW_PWR_ADDR_MAC, 2498 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, 2499 {0x004A, 2500 RTW_PWR_CUT_ALL_MSK, 2501 RTW_PWR_INTF_USB_MSK, 2502 RTW_PWR_ADDR_MAC, 2503 RTW_PWR_CMD_WRITE, BIT(0), 1}, 2504 {0x0023, 2505 RTW_PWR_CUT_ALL_MSK, 2506 RTW_PWR_INTF_SDIO_MSK, 2507 RTW_PWR_ADDR_MAC, 2508 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 2509 {0x0086, 2510 RTW_PWR_CUT_ALL_MSK, 2511 RTW_PWR_INTF_SDIO_MSK, 2512 RTW_PWR_ADDR_SDIO, 2513 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2514 {0x0086, 2515 RTW_PWR_CUT_ALL_MSK, 2516 RTW_PWR_INTF_SDIO_MSK, 2517 RTW_PWR_ADDR_SDIO, 2518 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2519 {0xFFFF, 2520 RTW_PWR_CUT_ALL_MSK, 2521 RTW_PWR_INTF_ALL_MSK, 2522 0, 2523 RTW_PWR_CMD_END, 0, 0}, 2524 }; 2525 2526 static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = { 2527 {0x001D, 2528 RTW_PWR_CUT_ALL_MSK, 2529 RTW_PWR_INTF_ALL_MSK, 2530 RTW_PWR_ADDR_MAC, 2531 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2532 {0x001D, 2533 RTW_PWR_CUT_ALL_MSK, 2534 RTW_PWR_INTF_ALL_MSK, 2535 RTW_PWR_ADDR_MAC, 2536 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2537 {0x001C, 2538 RTW_PWR_CUT_ALL_MSK, 2539 RTW_PWR_INTF_ALL_MSK, 2540 RTW_PWR_ADDR_MAC, 2541 RTW_PWR_CMD_WRITE, 0xFF, 0x0E}, 2542 {0xFFFF, 2543 RTW_PWR_CUT_ALL_MSK, 2544 RTW_PWR_INTF_ALL_MSK, 2545 0, 2546 RTW_PWR_CMD_END, 0, 0}, 2547 }; 2548 2549 static const struct rtw_pwr_seq_cmd *card_disable_flow_8723d[] = { 2550 trans_act_to_lps_8723d, 2551 trans_act_to_pre_carddis_8723d, 2552 trans_act_to_cardemu_8723d, 2553 trans_cardemu_to_carddis_8723d, 2554 trans_act_to_post_carddis_8723d, 2555 NULL 2556 }; 2557 2558 static const struct rtw_page_table page_table_8723d[] = { 2559 {12, 2, 2, 0, 1}, 2560 {12, 2, 2, 0, 1}, 2561 {12, 2, 2, 0, 1}, 2562 {12, 2, 2, 0, 1}, 2563 {12, 2, 2, 0, 1}, 2564 }; 2565 2566 static const struct rtw_rqpn rqpn_table_8723d[] = { 2567 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2568 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2569 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2570 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2571 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2572 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2573 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2574 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2575 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2576 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2577 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2578 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2579 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2580 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2581 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2582 }; 2583 2584 static const struct rtw_prioq_addrs prioq_addrs_8723d = { 2585 .prio[RTW_DMA_MAPPING_EXTRA] = { 2586 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, 2587 }, 2588 .prio[RTW_DMA_MAPPING_LOW] = { 2589 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, 2590 }, 2591 .prio[RTW_DMA_MAPPING_NORMAL] = { 2592 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, 2593 }, 2594 .prio[RTW_DMA_MAPPING_HIGH] = { 2595 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, 2596 }, 2597 .wsize = false, 2598 }; 2599 2600 static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = { 2601 {0x0008, 0x4a22, 2602 RTW_IP_SEL_PHY, 2603 RTW_INTF_PHY_CUT_ALL, 2604 RTW_INTF_PHY_PLATFORM_ALL}, 2605 {0x0009, 0x1000, 2606 RTW_IP_SEL_PHY, 2607 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B), 2608 RTW_INTF_PHY_PLATFORM_ALL}, 2609 {0xFFFF, 0x0000, 2610 RTW_IP_SEL_PHY, 2611 RTW_INTF_PHY_CUT_ALL, 2612 RTW_INTF_PHY_PLATFORM_ALL}, 2613 }; 2614 2615 static const struct rtw_intf_phy_para_table phy_para_table_8723d = { 2616 .gen1_para = pcie_gen1_param_8723d, 2617 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d), 2618 }; 2619 2620 static const struct rtw_hw_reg rtw8723d_dig[] = { 2621 [0] = { .addr = 0xc50, .mask = 0x7f }, 2622 [1] = { .addr = 0xc50, .mask = 0x7f }, 2623 }; 2624 2625 static const struct rtw_hw_reg rtw8723d_dig_cck[] = { 2626 [0] = { .addr = 0xa0c, .mask = 0x3f00 }, 2627 }; 2628 2629 static const struct rtw_rf_sipi_addr rtw8723d_rf_sipi_addr[] = { 2630 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, 2631 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, 2632 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, 2633 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, 2634 }; 2635 2636 static const struct rtw_ltecoex_addr rtw8723d_ltecoex_addr = { 2637 .ctrl = REG_LTECOEX_CTRL, 2638 .wdata = REG_LTECOEX_WRITE_DATA, 2639 .rdata = REG_LTECOEX_READ_DATA, 2640 }; 2641 2642 static const struct rtw_rfe_def rtw8723d_rfe_defs[] = { 2643 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl, 2644 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,}, 2645 }; 2646 2647 static const u8 rtw8723d_pwrtrk_2gb_n[] = { 2648 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2649 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2650 }; 2651 2652 static const u8 rtw8723d_pwrtrk_2gb_p[] = { 2653 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2654 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2655 }; 2656 2657 static const u8 rtw8723d_pwrtrk_2ga_n[] = { 2658 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2659 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2660 }; 2661 2662 static const u8 rtw8723d_pwrtrk_2ga_p[] = { 2663 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2664 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2665 }; 2666 2667 static const u8 rtw8723d_pwrtrk_2g_cck_b_n[] = { 2668 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2669 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2670 }; 2671 2672 static const u8 rtw8723d_pwrtrk_2g_cck_b_p[] = { 2673 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2674 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2675 }; 2676 2677 static const u8 rtw8723d_pwrtrk_2g_cck_a_n[] = { 2678 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2679 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2680 }; 2681 2682 static const u8 rtw8723d_pwrtrk_2g_cck_a_p[] = { 2683 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2684 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2685 }; 2686 2687 static const s8 rtw8723d_pwrtrk_xtal_n[] = { 2688 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2689 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 2690 }; 2691 2692 static const s8 rtw8723d_pwrtrk_xtal_p[] = { 2693 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2694 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16 2695 }; 2696 2697 static const struct rtw_pwr_track_tbl rtw8723d_rtw_pwr_track_tbl = { 2698 .pwrtrk_2gb_n = rtw8723d_pwrtrk_2gb_n, 2699 .pwrtrk_2gb_p = rtw8723d_pwrtrk_2gb_p, 2700 .pwrtrk_2ga_n = rtw8723d_pwrtrk_2ga_n, 2701 .pwrtrk_2ga_p = rtw8723d_pwrtrk_2ga_p, 2702 .pwrtrk_2g_cckb_n = rtw8723d_pwrtrk_2g_cck_b_n, 2703 .pwrtrk_2g_cckb_p = rtw8723d_pwrtrk_2g_cck_b_p, 2704 .pwrtrk_2g_ccka_n = rtw8723d_pwrtrk_2g_cck_a_n, 2705 .pwrtrk_2g_ccka_p = rtw8723d_pwrtrk_2g_cck_a_p, 2706 .pwrtrk_xtal_p = rtw8723d_pwrtrk_xtal_p, 2707 .pwrtrk_xtal_n = rtw8723d_pwrtrk_xtal_n, 2708 }; 2709 2710 static const struct rtw_reg_domain coex_info_hw_regs_8723d[] = { 2711 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2712 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8}, 2713 {0, 0, RTW_REG_DOMAIN_NL}, 2714 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8}, 2715 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8}, 2716 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8}, 2717 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8}, 2718 {0, 0, RTW_REG_DOMAIN_NL}, 2719 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2720 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2721 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2722 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2723 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2724 {0, 0, RTW_REG_DOMAIN_NL}, 2725 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2726 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2727 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2728 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2729 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2730 }; 2731 2732 const struct rtw_chip_info rtw8723d_hw_spec = { 2733 .ops = &rtw8723d_ops, 2734 .id = RTW_CHIP_TYPE_8723D, 2735 .fw_name = "rtw88/rtw8723d_fw.bin", 2736 .wlan_cpu = RTW_WCPU_11N, 2737 .tx_pkt_desc_sz = 40, 2738 .tx_buf_desc_sz = 16, 2739 .rx_pkt_desc_sz = 24, 2740 .rx_buf_desc_sz = 8, 2741 .phy_efuse_size = 512, 2742 .log_efuse_size = 512, 2743 .ptct_efuse_size = 96 + 1, 2744 .txff_size = 32768, 2745 .rxff_size = 16384, 2746 .rsvd_drv_pg_num = 8, 2747 .txgi_factor = 1, 2748 .is_pwr_by_rate_dec = true, 2749 .max_power_index = 0x3f, 2750 .csi_buf_pg_num = 0, 2751 .band = RTW_BAND_2G, 2752 .page_size = TX_PAGE_SIZE, 2753 .dig_min = 0x20, 2754 .ht_supported = true, 2755 .vht_supported = false, 2756 .lps_deep_mode_supported = 0, 2757 .sys_func_en = 0xFD, 2758 .pwr_on_seq = card_enable_flow_8723d, 2759 .pwr_off_seq = card_disable_flow_8723d, 2760 .page_table = page_table_8723d, 2761 .rqpn_table = rqpn_table_8723d, 2762 .prioq_addrs = &prioq_addrs_8723d, 2763 .intf_table = &phy_para_table_8723d, 2764 .dig = rtw8723d_dig, 2765 .dig_cck = rtw8723d_dig_cck, 2766 .rf_sipi_addr = {0x840, 0x844}, 2767 .rf_sipi_read_addr = rtw8723d_rf_sipi_addr, 2768 .fix_rf_phy_num = 2, 2769 .ltecoex_addr = &rtw8723d_ltecoex_addr, 2770 .mac_tbl = &rtw8723d_mac_tbl, 2771 .agc_tbl = &rtw8723d_agc_tbl, 2772 .bb_tbl = &rtw8723d_bb_tbl, 2773 .rf_tbl = {&rtw8723d_rf_a_tbl}, 2774 .rfe_defs = rtw8723d_rfe_defs, 2775 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs), 2776 .rx_ldpc = false, 2777 .pwr_track_tbl = &rtw8723d_rtw_pwr_track_tbl, 2778 .iqk_threshold = 8, 2779 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 2780 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2781 2782 .coex_para_ver = 0x2007022f, 2783 .bt_desired_ver = 0x2f, 2784 .scbd_support = true, 2785 .new_scbd10_def = true, 2786 .ble_hid_profile_support = false, 2787 .wl_mimo_ps_support = false, 2788 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2789 .bt_rssi_type = COEX_BTRSSI_RATIO, 2790 .ant_isolation = 15, 2791 .rssi_tolerance = 2, 2792 .wl_rssi_step = wl_rssi_step_8723d, 2793 .bt_rssi_step = bt_rssi_step_8723d, 2794 .table_sant_num = ARRAY_SIZE(table_sant_8723d), 2795 .table_sant = table_sant_8723d, 2796 .table_nsant_num = ARRAY_SIZE(table_nsant_8723d), 2797 .table_nsant = table_nsant_8723d, 2798 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8723d), 2799 .tdma_sant = tdma_sant_8723d, 2800 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8723d), 2801 .tdma_nsant = tdma_nsant_8723d, 2802 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8723d), 2803 .wl_rf_para_tx = rf_para_tx_8723d, 2804 .wl_rf_para_rx = rf_para_rx_8723d, 2805 .bt_afh_span_bw20 = 0x20, 2806 .bt_afh_span_bw40 = 0x30, 2807 .afh_5g_num = ARRAY_SIZE(afh_5g_8723d), 2808 .afh_5g = afh_5g_8723d, 2809 .btg_reg = &btg_reg_8723d, 2810 2811 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d), 2812 .coex_info_hw_regs = coex_info_hw_regs_8723d, 2813 }; 2814 EXPORT_SYMBOL(rtw8723d_hw_spec); 2815 2816 MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin"); 2817 2818 MODULE_AUTHOR("Realtek Corporation"); 2819 MODULE_DESCRIPTION("Realtek 802.11n wireless 8723d driver"); 2820 MODULE_LICENSE("Dual BSD/GPL"); 2821