1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_REG_DEF_H__ 6 #define __RTW_REG_DEF_H__ 7 8 #define REG_SYS_FUNC_EN 0x0002 9 #define BIT_FEN_EN_25_1 BIT(13) 10 #define BIT_FEN_ELDR BIT(12) 11 #define BIT_FEN_CPUEN BIT(2) 12 #define BIT_FEN_BB_GLB_RST BIT(1) 13 #define BIT_FEN_BB_RSTB BIT(0) 14 #define BIT_R_DIS_PRST BIT(6) 15 #define BIT_WLOCK_1C_B6 BIT(5) 16 #define REG_SYS_PW_CTRL 0x0004 17 #define BIT_PFM_WOWL BIT(3) 18 #define REG_SYS_CLK_CTRL 0x0008 19 #define BIT_CPU_CLK_EN BIT(14) 20 21 #define REG_SYS_CLKR 0x0008 22 #define BIT_ANA8M BIT(1) 23 #define BIT_WAKEPAD_EN BIT(3) 24 #define BIT_LOADER_CLK_EN BIT(5) 25 26 #define REG_RSV_CTRL 0x001C 27 #define DISABLE_PI 0x3 28 #define ENABLE_PI 0x2 29 #define BITS_RFC_DIRECT (BIT(31) | BIT(30)) 30 #define BIT_WLMCU_IOIF BIT(0) 31 #define REG_RF_CTRL 0x001F 32 #define BIT_RF_SDM_RSTB BIT(2) 33 #define BIT_RF_RSTB BIT(1) 34 #define BIT_RF_EN BIT(0) 35 36 #define REG_AFE_CTRL1 0x0024 37 #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21)) 38 #define REG_EFUSE_CTRL 0x0030 39 #define BIT_EF_FLAG BIT(31) 40 #define BIT_SHIFT_EF_ADDR 8 41 #define BIT_MASK_EF_ADDR 0x3ff 42 #define BIT_MASK_EF_DATA 0xff 43 #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) 44 #define BITS_PLL 0xf0 45 46 #define REG_AFE_XTAL_CTRL 0x24 47 #define REG_AFE_PLL_CTRL 0x28 48 #define REG_AFE_CTRL3 0x2c 49 #define BIT_MASK_XTAL 0x00FFF000 50 #define BIT_XTAL_GMP_BIT4 BIT(28) 51 52 #define REG_LDO_EFUSE_CTRL 0x0034 53 #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9)) 54 55 #define BIT_LDO25_VOLTAGE_V25 0x03 56 #define BIT_MASK_LDO25_VOLTAGE GENMASK(6, 4) 57 #define BIT_SHIFT_LDO25_VOLTAGE 4 58 #define BIT_LDO25_EN BIT(7) 59 60 #define REG_GPIO_MUXCFG 0x0040 61 #define BIT_FSPI_EN BIT(19) 62 #define BIT_EN_SIC BIT(12) 63 64 #define BIT_PO_BT_PTA_PINS BIT(9) 65 #define BIT_BT_PTA_EN BIT(5) 66 #define BIT_WLRFE_4_5_EN BIT(2) 67 68 #define REG_LED_CFG 0x004C 69 #define BIT_LNAON_SEL_EN BIT(26) 70 #define BIT_PAPE_SEL_EN BIT(25) 71 #define BIT_DPDT_WL_SEL BIT(24) 72 #define BIT_DPDT_SEL_EN BIT(23) 73 #define REG_LEDCFG2 0x004E 74 #define REG_PAD_CTRL1 0x0064 75 #define BIT_BT_BTG_SEL BIT(31) 76 #define BIT_PAPE_WLBT_SEL BIT(29) 77 #define BIT_LNAON_WLBT_SEL BIT(28) 78 #define BIT_BTGP_JTAG_EN BIT(24) 79 #define BIT_BTGP_SPI_EN BIT(20) 80 #define BIT_LED1DIS BIT(15) 81 #define BIT_SW_DPDT_SEL_DATA BIT(0) 82 #define REG_WL_BT_PWR_CTRL 0x0068 83 #define BIT_BT_FUNC_EN BIT(18) 84 #define BIT_BT_DIG_CLK_EN BIT(8) 85 #define REG_SYS_SDIO_CTRL 0x0070 86 #define BIT_DBG_GNT_WL_BT BIT(27) 87 #define BIT_LTE_MUX_CTRL_PATH BIT(26) 88 #define REG_HCI_OPT_CTRL 0x0074 89 #define BIT_USB_SUS_DIS BIT(8) 90 91 #define REG_AFE_CTRL_4 0x0078 92 #define BIT_CK320M_AFE_EN BIT(4) 93 #define BIT_EN_SYN BIT(15) 94 95 #define REG_LDO_SWR_CTRL 0x007C 96 #define LDO_SEL 0xC3 97 #define SPS_SEL 0x83 98 #define BIT_XTA1 BIT(29) 99 #define BIT_XTA0 BIT(28) 100 101 #define REG_MCUFW_CTRL 0x0080 102 #define BIT_ANA_PORT_EN BIT(22) 103 #define BIT_MAC_PORT_EN BIT(21) 104 #define BIT_BOOT_FSPI_EN BIT(20) 105 #define BIT_ROM_DLEN BIT(19) 106 #define BIT_ROM_PGE GENMASK(18, 16) /* legacy only */ 107 #define BIT_SHIFT_ROM_PGE 16 108 #define BIT_FW_INIT_RDY BIT(15) 109 #define BIT_FW_DW_RDY BIT(14) 110 #define BIT_RPWM_TOGGLE BIT(7) 111 #define BIT_RAM_DL_SEL BIT(7) /* legacy only */ 112 #define BIT_DMEM_CHKSUM_OK BIT(6) 113 #define BIT_WINTINI_RDY BIT(6) /* legacy only */ 114 #define BIT_DMEM_DW_OK BIT(5) 115 #define BIT_IMEM_CHKSUM_OK BIT(4) 116 #define BIT_IMEM_DW_OK BIT(3) 117 #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2) 118 #define BIT_FWDL_CHK_RPT BIT(2) /* legacy only */ 119 #define BIT_MCUFWDL_RDY BIT(1) /* legacy only */ 120 #define BIT_MCUFWDL_EN BIT(0) 121 #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6)) 122 #define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \ 123 BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \ 124 BIT_CHECK_SUM_OK) 125 #define FW_READY_LEGACY (BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT | \ 126 BIT_WINTINI_RDY | BIT_RAM_DL_SEL) 127 #define FW_READY_MASK 0xffff 128 129 #define REG_MCU_TST_CFG 0x84 130 #define VAL_FW_TRIGGER 0x1 131 132 #define REG_EFUSE_ACCESS 0x00CF 133 #define EFUSE_ACCESS_ON 0x69 134 #define EFUSE_ACCESS_OFF 0x00 135 136 #define REG_WLRF1 0x00EC 137 #define REG_WIFI_BT_INFO 0x00AA 138 #define BIT_BT_INT_EN BIT(15) 139 #define REG_SYS_CFG1 0x00F0 140 #define BIT_RTL_ID BIT(23) 141 #define BIT_LDO BIT(24) 142 #define BIT_RF_TYPE_ID BIT(27) 143 #define BIT_SHIFT_VENDOR_ID 16 144 #define BIT_MASK_VENDOR_ID 0xf 145 #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) 146 #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) 147 #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) 148 #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) 149 #define BIT_SHIFT_CHIP_VER 12 150 #define BIT_MASK_CHIP_VER 0xf 151 #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) 152 #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) 153 #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) 154 #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) 155 #define REG_SYS_STATUS1 0x00F4 156 #define REG_SYS_STATUS2 0x00F8 157 #define REG_SYS_CFG2 0x00FC 158 #define REG_WLRF1 0x00EC 159 #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26)) 160 #define REG_CR 0x0100 161 #define BIT_32K_CAL_TMR_EN BIT(10) 162 #define BIT_MAC_SEC_EN BIT(9) 163 #define BIT_ENSWBCN BIT(8) 164 #define BIT_MACRXEN BIT(7) 165 #define BIT_MACTXEN BIT(6) 166 #define BIT_SCHEDULE_EN BIT(5) 167 #define BIT_PROTOCOL_EN BIT(4) 168 #define BIT_RXDMA_EN BIT(3) 169 #define BIT_TXDMA_EN BIT(2) 170 #define BIT_HCI_RXDMA_EN BIT(1) 171 #define BIT_HCI_TXDMA_EN BIT(0) 172 #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ 173 BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ 174 BIT_MACTXEN | BIT_MACRXEN) 175 #define BIT_SHIFT_TXDMA_VOQ_MAP 4 176 #define BIT_MASK_TXDMA_VOQ_MAP 0x3 177 #define BIT_TXDMA_VOQ_MAP(x) \ 178 (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 179 #define BIT_SHIFT_TXDMA_VIQ_MAP 6 180 #define BIT_MASK_TXDMA_VIQ_MAP 0x3 181 #define BIT_TXDMA_VIQ_MAP(x) \ 182 (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 183 #define REG_TXDMA_PQ_MAP 0x010C 184 #define BIT_SHIFT_TXDMA_BEQ_MAP 8 185 #define BIT_MASK_TXDMA_BEQ_MAP 0x3 186 #define BIT_TXDMA_BEQ_MAP(x) \ 187 (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 188 #define BIT_SHIFT_TXDMA_BKQ_MAP 10 189 #define BIT_MASK_TXDMA_BKQ_MAP 0x3 190 #define BIT_TXDMA_BKQ_MAP(x) \ 191 (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) 192 #define BIT_SHIFT_TXDMA_MGQ_MAP 12 193 #define BIT_MASK_TXDMA_MGQ_MAP 0x3 194 #define BIT_TXDMA_MGQ_MAP(x) \ 195 (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) 196 #define BIT_SHIFT_TXDMA_HIQ_MAP 14 197 #define BIT_MASK_TXDMA_HIQ_MAP 0x3 198 #define BIT_TXDMA_HIQ_MAP(x) \ 199 (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) 200 #define BIT_SHIFT_TXSC_40M 4 201 #define BIT_MASK_TXSC_40M 0xf 202 #define BIT_TXSC_40M(x) \ 203 (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) 204 #define BIT_SHIFT_TXSC_20M 0 205 #define BIT_MASK_TXSC_20M 0xf 206 #define BIT_TXSC_20M(x) \ 207 (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) 208 #define BIT_SHIFT_MAC_CLK_SEL 20 209 #define MAC_CLK_HW_DEF_80M 0 210 #define MAC_CLK_HW_DEF_40M 1 211 #define MAC_CLK_HW_DEF_20M 2 212 #define MAC_CLK_SPEED 80 213 214 #define REG_CR 0x0100 215 #define REG_TRXFF_BNDY 0x0114 216 #define REG_RXFF_BNDY 0x011C 217 #define REG_FE1IMR 0x0120 218 #define BIT_FS_RXDONE BIT(16) 219 #define REG_PKTBUF_DBG_CTRL 0x0140 220 #define REG_C2HEVT 0x01A0 221 #define REG_MCUTST_1 0x01C0 222 #define REG_MCUTST_II 0x01C4 223 #define REG_WOWLAN_WAKE_REASON 0x01C7 224 #define REG_HMETFR 0x01CC 225 #define REG_HMEBOX0 0x01D0 226 #define REG_HMEBOX1 0x01D4 227 #define REG_HMEBOX2 0x01D8 228 #define REG_HMEBOX3 0x01DC 229 #define REG_HMEBOX0_EX 0x01F0 230 #define REG_HMEBOX1_EX 0x01F4 231 #define REG_HMEBOX2_EX 0x01F8 232 #define REG_HMEBOX3_EX 0x01FC 233 234 #define REG_RQPN 0x0200 235 #define BIT_MASK_HPQ 0xff 236 #define BIT_SHIFT_HPQ 0 237 #define BIT_RQPN_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) 238 #define BIT_MASK_LPQ 0xff 239 #define BIT_SHIFT_LPQ 8 240 #define BIT_RQPN_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) 241 #define BIT_MASK_PUBQ 0xff 242 #define BIT_SHIFT_PUBQ 16 243 #define BIT_RQPN_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) 244 #define BIT_RQPN_HLP(h, l, p) (BIT_LD_RQPN | BIT_RQPN_HPQ(h) | \ 245 BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p)) 246 247 #define REG_FIFOPAGE_CTRL_2 0x0204 248 #define BIT_BCN_VALID_V1 BIT(15) 249 #define BIT_MASK_BCN_HEAD_1_V1 0xfff 250 #define REG_AUTO_LLT_V1 0x0208 251 #define BIT_AUTO_INIT_LLT_V1 BIT(0) 252 #define REG_DWBCN0_CTRL 0x0208 253 #define BIT_BCN_VALID BIT(16) 254 #define REG_TXDMA_OFFSET_CHK 0x020C 255 #define BIT_DROP_DATA_EN BIT(9) 256 #define REG_TXDMA_STATUS 0x0210 257 #define BTI_PAGE_OVF BIT(2) 258 259 #define REG_RQPN_NPQ 0x0214 260 #define BIT_MASK_NPQ 0xff 261 #define BIT_SHIFT_NPQ 0 262 #define BIT_MASK_EPQ 0xff 263 #define BIT_SHIFT_EPQ 16 264 #define BIT_RQPN_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) 265 #define BIT_RQPN_EPQ(x) (((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ) 266 #define BIT_RQPN_NE(n, e) (BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e)) 267 268 #define REG_AUTO_LLT 0x0224 269 #define BIT_AUTO_INIT_LLT BIT(16) 270 #define REG_RQPN_CTRL_1 0x0228 271 #define REG_RQPN_CTRL_2 0x022C 272 #define BIT_LD_RQPN BIT(31) 273 #define REG_FIFOPAGE_INFO_1 0x0230 274 #define REG_FIFOPAGE_INFO_2 0x0234 275 #define REG_FIFOPAGE_INFO_3 0x0238 276 #define REG_FIFOPAGE_INFO_4 0x023C 277 #define REG_FIFOPAGE_INFO_5 0x0240 278 #define REG_H2C_HEAD 0x0244 279 #define REG_H2C_TAIL 0x0248 280 #define REG_H2C_READ_ADDR 0x024C 281 #define REG_H2C_INFO 0x0254 282 #define REG_RXPKT_NUM 0x0284 283 #define BIT_RXDMA_REQ BIT(19) 284 #define BIT_RW_RELEASE BIT(18) 285 #define BIT_RXDMA_IDLE BIT(17) 286 #define REG_RXPKTNUM 0x02B0 287 288 #define REG_INT_MIG 0x0304 289 #define REG_HCI_MIX_CFG 0x03FC 290 #define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26) 291 292 #define REG_BCNQ_INFO 0x0418 293 #define BIT_MGQ_CPU_EMPTY BIT(24) 294 #define REG_FWHW_TXQ_CTRL 0x0420 295 #define BIT_EN_BCNQ_DL BIT(22) 296 #define BIT_EN_WR_FREE_TAIL BIT(20) 297 #define REG_HWSEQ_CTRL 0x0423 298 299 #define REG_BCNQ_BDNY_V1 0x0424 300 #define REG_BCNQ_BDNY 0x0424 301 #define REG_MGQ_BDNY 0x0425 302 #define REG_LIFETIME_EN 0x0426 303 #define BIT_BA_PARSER_EN BIT(5) 304 #define REG_SPEC_SIFS 0x0428 305 #define REG_RETRY_LIMIT 0x042a 306 #define REG_DARFRC 0x0430 307 #define REG_DARFRCH 0x0434 308 #define REG_RARFRCH 0x043C 309 #define REG_RRSR 0x0440 310 #define BITS_RRSR_RSC GENMASK(22, 21) 311 #define REG_ARFR0 0x0444 312 #define REG_ARFRH0 0x0448 313 #define REG_ARFR1_V1 0x044C 314 #define REG_ARFRH1_V1 0x0450 315 #define REG_CCK_CHECK 0x0454 316 #define BIT_CHECK_CCK_EN BIT(7) 317 #define REG_AMPDU_MAX_TIME_V1 0x0455 318 #define REG_BCNQ1_BDNY_V1 0x0456 319 #define REG_AMPDU_MAX_TIME 0x0456 320 #define REG_WMAC_LBK_BF_HD 0x045D 321 #define REG_TX_HANG_CTRL 0x045E 322 #define BIT_EN_GNT_BT_AWAKE BIT(3) 323 #define BIT_EN_EOF_V1 BIT(2) 324 #define REG_DATA_SC 0x0483 325 #define REG_ARFR4 0x049C 326 #define BIT_WL_RFK BIT(0) 327 #define REG_ARFRH4 0x04A0 328 #define REG_ARFR5 0x04A4 329 #define REG_ARFRH5 0x04A8 330 #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC 331 #define BIT_PRE_TX_CMD BIT(6) 332 #define REG_QUEUE_CTRL 0x04C6 333 #define BIT_PTA_WL_TX_EN BIT(4) 334 #define BIT_PTA_EDCCA_EN BIT(5) 335 #define REG_SINGLE_AMPDU_CTRL 0x04C7 336 #define BIT_EN_SINGLE_APMDU BIT(7) 337 #define REG_PROT_MODE_CTRL 0x04C8 338 #define REG_MAX_AGGR_NUM 0x04CA 339 #define REG_BAR_MODE_CTRL 0x04CC 340 #define REG_PRECNT_CTRL 0x04E5 341 #define BIT_BTCCA_CTRL (BIT(0) | BIT(1)) 342 #define BIT_EN_PRECNT BIT(11) 343 #define REG_DUMMY_PAGE4_V1 0x04FC 344 345 #define REG_EDCA_VO_PARAM 0x0500 346 #define REG_EDCA_VI_PARAM 0x0504 347 #define REG_EDCA_BE_PARAM 0x0508 348 #define REG_EDCA_BK_PARAM 0x050C 349 #define BIT_MASK_TXOP_LMT GENMASK(26, 16) 350 #define BIT_MASK_CWMAX GENMASK(15, 12) 351 #define BIT_MASK_CWMIN GENMASK(11, 8) 352 #define BIT_MASK_AIFS GENMASK(7, 0) 353 #define REG_PIFS 0x0512 354 #define REG_SIFS 0x0514 355 #define BIT_SHIFT_SIFS_OFDM_CTX 8 356 #define BIT_SHIFT_SIFS_CCK_TRX 16 357 #define BIT_SHIFT_SIFS_OFDM_TRX 24 358 #define REG_AGGR_BREAK_TIME 0x051A 359 #define REG_SLOT 0x051B 360 #define REG_TX_PTCL_CTRL 0x0520 361 #define BIT_SIFS_BK_EN BIT(12) 362 #define REG_TXPAUSE 0x0522 363 #define REG_RD_CTRL 0x0524 364 #define BIT_DIS_TXOP_CFE BIT(10) 365 #define BIT_DIS_LSIG_CFE BIT(9) 366 #define BIT_DIS_STBC_CFE BIT(8) 367 #define REG_TBTT_PROHIBIT 0x0540 368 #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 369 #define REG_RD_NAV_NXT 0x0544 370 #define REG_NAV_PROT_LEN 0x0546 371 #define REG_BCN_CTRL 0x0550 372 #define BIT_DIS_TSF_UDT BIT(4) 373 #define BIT_EN_BCN_FUNCTION BIT(3) 374 #define BIT_EN_TXBCN_RPT BIT(2) 375 #define REG_BCN_CTRL_CLINT0 0x0551 376 #define REG_DRVERLYINT 0x0558 377 #define REG_BCNDMATIM 0x0559 378 #define REG_ATIMWND 0x055A 379 #define REG_USTIME_TSF 0x055C 380 #define REG_BCN_MAX_ERR 0x055D 381 #define REG_RXTSF_OFFSET_CCK 0x055E 382 #define REG_MISC_CTRL 0x0577 383 #define BIT_EN_FREE_CNT BIT(3) 384 #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1)) 385 #define REG_HIQ_NO_LMT_EN 0x5A7 386 #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) 387 #define REG_TIMER0_SRC_SEL 0x05B4 388 #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6)) 389 390 #define REG_TCR 0x0604 391 #define BIT_PWRMGT_HWDATA_EN BIT(7) 392 #define REG_RCR 0x0608 393 #define BIT_APP_FCS BIT(31) 394 #define BIT_APP_MIC BIT(30) 395 #define BIT_APP_ICV BIT(29) 396 #define BIT_APP_PHYSTS BIT(28) 397 #define BIT_APP_BASSN BIT(27) 398 #define BIT_VHT_DACK BIT(26) 399 #define BIT_TCPOFLD_EN BIT(25) 400 #define BIT_ENMBID BIT(24) 401 #define BIT_LSIGEN BIT(23) 402 #define BIT_MFBEN BIT(22) 403 #define BIT_DISCHKPPDLLEN BIT(21) 404 #define BIT_PKTCTL_DLEN BIT(20) 405 #define BIT_TIM_PARSER_EN BIT(18) 406 #define BIT_BC_MD_EN BIT(17) 407 #define BIT_UC_MD_EN BIT(16) 408 #define BIT_RXSK_PERPKT BIT(15) 409 #define BIT_HTC_LOC_CTRL BIT(14) 410 #define BIT_RPFM_CAM_ENABLE BIT(12) 411 #define BIT_TA_BCN BIT(11) 412 #define BIT_RCR_ADF BIT(11) 413 #define BIT_DISDECMYPKT BIT(10) 414 #define BIT_AICV BIT(9) 415 #define BIT_ACRC32 BIT(8) 416 #define BIT_CBSSID_BCN BIT(7) 417 #define BIT_CBSSID_DATA BIT(6) 418 #define BIT_APWRMGT BIT(5) 419 #define BIT_ADD3 BIT(4) 420 #define BIT_AB BIT(3) 421 #define BIT_AM BIT(2) 422 #define BIT_APM BIT(1) 423 #define BIT_AAP BIT(0) 424 #define REG_RX_PKT_LIMIT 0x060C 425 #define REG_RX_DRVINFO_SZ 0x060F 426 #define BIT_APP_PHYSTS BIT(28) 427 #define REG_MAR 0x0620 428 #define REG_USTIME_EDCA 0x0638 429 #define REG_ACKTO_CCK 0x0639 430 #define REG_MAC_SPEC_SIFS 0x063A 431 #define REG_RESP_SIFS_CCK 0x063C 432 #define REG_RESP_SIFS_OFDM 0x063E 433 #define REG_ACKTO 0x0640 434 #define REG_EIFS 0x0642 435 #define REG_NAV_CTRL 0x0650 436 #define REG_WMAC_TRXPTCL_CTL 0x0668 437 #define BIT_RFMOD (BIT(7) | BIT(8)) 438 #define BIT_RFMOD_80M BIT(8) 439 #define BIT_RFMOD_40M BIT(7) 440 #define REG_WMAC_TRXPTCL_CTL_H 0x066C 441 #define REG_WKFMCAM_CMD 0x0698 442 #define BIT_WKFCAM_POLLING_V1 BIT(31) 443 #define BIT_WKFCAM_CLR_V1 BIT(30) 444 #define BIT_WKFCAM_WE BIT(16) 445 #define BIT_SHIFT_WKFCAM_ADDR_V2 8 446 #define BIT_MASK_WKFCAM_ADDR_V2 0xff 447 #define BIT_WKFCAM_ADDR_V2(x) \ 448 (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) 449 #define REG_WKFMCAM_RWD 0x069C 450 #define BIT_WKFMCAM_VALID BIT(31) 451 #define BIT_WKFMCAM_BC BIT(26) 452 #define BIT_WKFMCAM_MC BIT(25) 453 #define BIT_WKFMCAM_UC BIT(24) 454 455 #define REG_RXFLTMAP0 0x06A0 456 #define REG_RXFLTMAP1 0x06A2 457 #define REG_RXFLTMAP2 0x06A4 458 #define REG_RXFLTMAP4 0x068A 459 #define REG_BT_COEX_TABLE0 0x06C0 460 #define REG_BT_COEX_TABLE1 0x06C4 461 #define REG_BT_COEX_BRK_TABLE 0x06C8 462 #define REG_BT_COEX_TABLE_H 0x06CC 463 #define REG_BT_COEX_TABLE_H1 0x06CD 464 #define REG_BT_COEX_TABLE_H2 0x06CE 465 #define REG_BT_COEX_TABLE_H3 0x06CF 466 #define REG_BBPSF_CTRL 0x06DC 467 468 #define REG_BT_COEX_V2 0x0762 469 #define BIT_GNT_BT_POLARITY BIT(12) 470 #define BIT_LTE_COEX_EN BIT(7) 471 #define REG_BT_COEX_ENH_INTR_CTRL 0x76E 472 #define BIT_R_GRANTALL_WLMASK BIT(3) 473 #define BIT_STATIS_BT_EN BIT(2) 474 #define REG_BT_ACT_STATISTICS 0x0770 475 #define REG_BT_ACT_STATISTICS_1 0x0774 476 #define REG_BT_STAT_CTRL 0x0778 477 #define REG_BT_TDMA_TIME 0x0790 478 #define BIT_MASK_SAMPLE_RATE GENMASK(5, 0) 479 #define REG_LTR_IDLE_LATENCY 0x0798 480 #define REG_LTR_ACTIVE_LATENCY 0x079C 481 #define REG_LTR_CTRL_BASIC 0x07A4 482 #define REG_WMAC_OPTION_FUNCTION 0x07D0 483 #define REG_WMAC_OPTION_FUNCTION_1 0x07D4 484 485 #define REG_FPGA0_RFMOD 0x0800 486 #define BIT_CCKEN BIT(24) 487 #define BIT_OFDMEN BIT(25) 488 #define REG_RX_GAIN_EN 0x081c 489 490 #define REG_RFE_CTRL_E 0x0974 491 #define REG_2ND_CCA_CTRL 0x0976 492 493 #define REG_CCK0_FAREPORT 0xa2c 494 #define BIT_CCK0_2RX BIT(18) 495 #define BIT_CCK0_MRC BIT(22) 496 497 #define REG_DIS_DPD 0x0a70 498 #define DIS_DPD_MASK GENMASK(9, 0) 499 #define DIS_DPD_RATE6M BIT(0) 500 #define DIS_DPD_RATE9M BIT(1) 501 #define DIS_DPD_RATEMCS0 BIT(2) 502 #define DIS_DPD_RATEMCS1 BIT(3) 503 #define DIS_DPD_RATEMCS8 BIT(4) 504 #define DIS_DPD_RATEMCS9 BIT(5) 505 #define DIS_DPD_RATEVHT1SS_MCS0 BIT(6) 506 #define DIS_DPD_RATEVHT1SS_MCS1 BIT(7) 507 #define DIS_DPD_RATEVHT2SS_MCS0 BIT(8) 508 #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9) 509 #define DIS_DPD_RATEALL GENMASK(9, 0) 510 511 #define REG_RFE_CTRL8 0x0cb4 512 #define BIT_MASK_RFE_SEL89 GENMASK(7, 0) 513 #define REG_RFE_INV8 0x0cbd 514 #define BIT_MASK_RFE_INV89 GENMASK(1, 0) 515 #define REG_RFE_INV16 0x0cbe 516 #define BIT_RFE_BUF_EN BIT(3) 517 518 #define REG_ANAPAR_XTAL_0 0x1040 519 #define REG_CPU_DMEM_CON 0x1080 520 #define BIT_WL_PLATFORM_RST BIT(16) 521 #define BIT_WL_SECURITY_CLK BIT(15) 522 #define BIT_DDMA_EN BIT(8) 523 524 #define REG_H2C_PKT_READADDR 0x10D0 525 #define REG_H2C_PKT_WRITEADDR 0x10D4 526 #define REG_FW_DBG7 0x10FC 527 #define FW_KEY_MASK 0xffffff00 528 529 #define REG_CR_EXT 0x1100 530 531 #define REG_DDMA_CH0SA 0x1200 532 #define REG_DDMA_CH0DA 0x1204 533 #define REG_DDMA_CH0CTRL 0x1208 534 #define BIT_DDMACH0_OWN BIT(31) 535 #define BIT_DDMACH0_CHKSUM_EN BIT(29) 536 #define BIT_DDMACH0_CHKSUM_STS BIT(27) 537 #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) 538 #define BIT_DDMACH0_CHKSUM_CONT BIT(24) 539 #define BIT_MASK_DDMACH0_DLEN 0x3ffff 540 541 #define REG_H2CQ_CSR 0x1330 542 #define BIT_H2CQ_FULL BIT(31) 543 #define REG_FAST_EDCA_VOVI_SETTING 0x1448 544 #define REG_FAST_EDCA_BEBK_SETTING 0x144C 545 546 #define REG_RXPSF_CTRL 0x1610 547 #define BIT_RXGCK_FIFOTHR_EN BIT(28) 548 549 #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 550 #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 551 #define BIT_RXGCK_VHT_FIFOTHR(x) \ 552 (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 553 #define BITS_RXGCK_VHT_FIFOTHR \ 554 (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 555 556 #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 557 #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 558 #define BIT_RXGCK_HT_FIFOTHR(x) \ 559 (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) 560 #define BITS_RXGCK_HT_FIFOTHR \ 561 (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) 562 563 #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 564 #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 565 #define BIT_RXGCK_OFDM_FIFOTHR(x) \ 566 (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 567 #define BITS_RXGCK_OFDM_FIFOTHR \ 568 (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 569 570 #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 571 #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 572 #define BIT_RXGCK_CCK_FIFOTHR(x) \ 573 (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 574 #define BITS_RXGCK_CCK_FIFOTHR \ 575 (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 576 577 #define BIT_RXGCK_OFDMCCA_EN BIT(16) 578 579 #define BIT_SHIFT_RXPSF_PKTLENTHR 13 580 #define BIT_MASK_RXPSF_PKTLENTHR 0x7 581 #define BIT_RXPSF_PKTLENTHR(x) \ 582 (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) 583 #define BITS_RXPSF_PKTLENTHR \ 584 (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) 585 #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) 586 #define BIT_SET_RXPSF_PKTLENTHR(x, v) \ 587 (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) 588 589 #define BIT_RXPSF_CTRLEN BIT(12) 590 #define BIT_RXPSF_VHTCHKEN BIT(11) 591 #define BIT_RXPSF_HTCHKEN BIT(10) 592 #define BIT_RXPSF_OFDMCHKEN BIT(9) 593 #define BIT_RXPSF_CCKCHKEN BIT(8) 594 #define BIT_RXPSF_OFDMRST BIT(7) 595 #define BIT_RXPSF_CCKRST BIT(6) 596 #define BIT_RXPSF_MHCHKEN BIT(5) 597 #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) 598 #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) 599 600 #define BIT_SHIFT_RXPSF_ERRTHR 0 601 #define BIT_MASK_RXPSF_ERRTHR 0x7 602 #define BIT_RXPSF_ERRTHR(x) \ 603 (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) 604 #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) 605 #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) 606 #define BIT_GET_RXPSF_ERRTHR(x) \ 607 (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) 608 #define BIT_SET_RXPSF_ERRTHR(x, v) \ 609 (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) 610 611 #define REG_RXPSF_TYPE_CTRL 0x1614 612 #define REG_GENERAL_OPTION 0x1664 613 #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) 614 615 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 616 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 617 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 618 #define LTECOEX_READY BIT(29) 619 #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 620 #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 621 #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 622 623 #define REG_IGN_GNT_BT1 0x1860 624 625 #define REG_RFESEL_CTRL 0x1990 626 627 #define REG_NOMASK_TXBT 0x1ca7 628 #define REG_ANAPAR 0x1c30 629 #define BIT_ANAPAR_BTPS BIT(22) 630 #define REG_RSTB_SEL 0x1c38 631 #define BIT_DAC_OFF_ENABLE BIT(4) 632 #define BIT_PI_IGNORE_GNT_BT BIT(3) 633 #define BIT_NOMASK_TXBT_ENABLE BIT(3) 634 635 #define REG_HRCV_MSG 0x1cf 636 637 #define REG_IGN_GNTBT4 0x4160 638 639 #define RF_MODE 0x00 640 #define RF_MODOPT 0x01 641 #define RF_WLINT 0x01 642 #define RF_WLSEL 0x02 643 #define RF_DTXLOK 0x08 644 #define RF_CFGCH 0x18 645 #define RF_RCK 0x1d 646 #define RF_LUTWA 0x33 647 #define RF_LUTWD1 0x3e 648 #define RF_LUTWD0 0x3f 649 #define RF_T_METER 0x42 650 #define RF_BSPAD 0x54 651 #define RF_GAINTX 0x56 652 #define RF_TXATANK 0x64 653 #define RF_TRXIQ 0x66 654 #define RF_RXIQGEN 0x8d 655 #define RF_XTALX2 0xb8 656 #define RF_MALSEL 0xbe 657 #define RF_RCKD 0xde 658 #define RF_TXADBG 0xde 659 #define RF_LUTDBG 0xdf 660 #define RF_LUTWE2 0xee 661 #define RF_LUTWE 0xef 662 663 #define LTE_COEX_CTRL 0x38 664 #define LTE_WL_TRX_CTRL 0xa0 665 #define LTE_BT_TRX_CTRL 0xa4 666 667 #endif 668