1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTW_REG_DEF_H__
6 #define __RTW_REG_DEF_H__
7 
8 #define REG_SYS_FUNC_EN		0x0002
9 #define BIT_FEN_EN_25_1		BIT(13)
10 #define BIT_FEN_ELDR		BIT(12)
11 #define BIT_FEN_CPUEN		BIT(2)
12 #define BIT_FEN_BB_GLB_RST	BIT(1)
13 #define BIT_FEN_BB_RSTB		BIT(0)
14 #define BIT_R_DIS_PRST		BIT(6)
15 #define BIT_WLOCK_1C_B6		BIT(5)
16 #define REG_SYS_PW_CTRL		0x0004
17 #define BIT_PFM_WOWL		BIT(3)
18 #define REG_SYS_CLK_CTRL	0x0008
19 #define BIT_CPU_CLK_EN		BIT(14)
20 
21 #define REG_SYS_CLKR		0x0008
22 #define BIT_ANA8M		BIT(1)
23 #define BIT_WAKEPAD_EN		BIT(3)
24 #define BIT_LOADER_CLK_EN	BIT(5)
25 
26 #define REG_RSV_CTRL		0x001C
27 #define DISABLE_PI		0x3
28 #define ENABLE_PI		0x2
29 #define BITS_RFC_DIRECT		(BIT(31) | BIT(30))
30 #define BIT_WLMCU_IOIF		BIT(0)
31 #define REG_RF_CTRL		0x001F
32 #define BIT_RF_SDM_RSTB		BIT(2)
33 #define BIT_RF_RSTB		BIT(1)
34 #define BIT_RF_EN		BIT(0)
35 
36 #define REG_AFE_CTRL1		0x0024
37 #define BIT_MAC_CLK_SEL		(BIT(20) | BIT(21))
38 #define REG_EFUSE_CTRL		0x0030
39 #define BIT_EF_FLAG		BIT(31)
40 #define BIT_SHIFT_EF_ADDR	8
41 #define BIT_MASK_EF_ADDR	0x3ff
42 #define BIT_MASK_EF_DATA	0xff
43 #define BITS_EF_ADDR		(BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
44 #define BITS_PLL		0xf0
45 
46 #define REG_AFE_XTAL_CTRL	0x24
47 #define REG_AFE_PLL_CTRL	0x28
48 #define REG_AFE_CTRL3		0x2c
49 #define BIT_MASK_XTAL		0x00FFF000
50 #define BIT_XTAL_GMP_BIT4	BIT(28)
51 
52 #define REG_LDO_EFUSE_CTRL	0x0034
53 #define BIT_MASK_EFUSE_BANK_SEL	(BIT(8) | BIT(9))
54 
55 #define BIT_LDO25_VOLTAGE_V25	0x03
56 #define BIT_MASK_LDO25_VOLTAGE	GENMASK(6, 4)
57 #define BIT_SHIFT_LDO25_VOLTAGE	4
58 #define BIT_LDO25_EN		BIT(7)
59 
60 #define REG_GPIO_MUXCFG		0x0040
61 #define BIT_FSPI_EN		BIT(19)
62 #define BIT_EN_SIC		BIT(12)
63 
64 #define BIT_PO_BT_PTA_PINS	BIT(9)
65 #define BIT_BT_PTA_EN		BIT(5)
66 #define BIT_WLRFE_4_5_EN	BIT(2)
67 
68 #define REG_LED_CFG		0x004C
69 #define BIT_LNAON_SEL_EN	BIT(26)
70 #define BIT_PAPE_SEL_EN		BIT(25)
71 #define BIT_DPDT_WL_SEL		BIT(24)
72 #define BIT_DPDT_SEL_EN		BIT(23)
73 #define REG_LEDCFG2		0x004E
74 #define REG_PAD_CTRL1		0x0064
75 #define BIT_BT_BTG_SEL		BIT(31)
76 #define BIT_PAPE_WLBT_SEL	BIT(29)
77 #define BIT_LNAON_WLBT_SEL	BIT(28)
78 #define BIT_BTGP_JTAG_EN	BIT(24)
79 #define BIT_BTGP_SPI_EN		BIT(20)
80 #define BIT_LED1DIS		BIT(15)
81 #define BIT_SW_DPDT_SEL_DATA	BIT(0)
82 #define REG_WL_BT_PWR_CTRL	0x0068
83 #define BIT_BT_FUNC_EN		BIT(18)
84 #define BIT_BT_DIG_CLK_EN	BIT(8)
85 #define REG_SYS_SDIO_CTRL	0x0070
86 #define BIT_DBG_GNT_WL_BT	BIT(27)
87 #define BIT_LTE_MUX_CTRL_PATH	BIT(26)
88 #define REG_HCI_OPT_CTRL	0x0074
89 #define BIT_USB_SUS_DIS		BIT(8)
90 
91 #define REG_AFE_CTRL_4		0x0078
92 #define BIT_CK320M_AFE_EN	BIT(4)
93 #define BIT_EN_SYN		BIT(15)
94 
95 #define REG_LDO_SWR_CTRL	0x007C
96 #define LDO_SEL			0xC3
97 #define SPS_SEL			0x83
98 #define BIT_XTA1		BIT(29)
99 #define BIT_XTA0		BIT(28)
100 
101 #define REG_MCUFW_CTRL		0x0080
102 #define BIT_ANA_PORT_EN		BIT(22)
103 #define BIT_MAC_PORT_EN		BIT(21)
104 #define BIT_BOOT_FSPI_EN	BIT(20)
105 #define BIT_ROM_DLEN		BIT(19)
106 #define BIT_ROM_PGE		GENMASK(18, 16)	/* legacy only */
107 #define BIT_SHIFT_ROM_PGE	16
108 #define BIT_FW_INIT_RDY		BIT(15)
109 #define BIT_FW_DW_RDY		BIT(14)
110 #define BIT_RPWM_TOGGLE		BIT(7)
111 #define BIT_RAM_DL_SEL		BIT(7)	/* legacy only */
112 #define BIT_DMEM_CHKSUM_OK	BIT(6)
113 #define BIT_WINTINI_RDY		BIT(6)	/* legacy only */
114 #define BIT_DMEM_DW_OK		BIT(5)
115 #define BIT_IMEM_CHKSUM_OK	BIT(4)
116 #define BIT_IMEM_DW_OK		BIT(3)
117 #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2)
118 #define BIT_FWDL_CHK_RPT	BIT(2)	/* legacy only */
119 #define BIT_MCUFWDL_RDY		BIT(1)	/* legacy only */
120 #define BIT_MCUFWDL_EN		BIT(0)
121 #define BIT_CHECK_SUM_OK	(BIT(4) | BIT(6))
122 #define FW_READY		(BIT_FW_INIT_RDY | BIT_FW_DW_RDY |             \
123 				 BIT_IMEM_DW_OK | BIT_DMEM_DW_OK |             \
124 				 BIT_CHECK_SUM_OK)
125 #define FW_READY_LEGACY		(BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT |	       \
126 				 BIT_WINTINI_RDY | BIT_RAM_DL_SEL)
127 #define FW_READY_MASK		0xffff
128 
129 #define REG_MCU_TST_CFG		0x84
130 #define VAL_FW_TRIGGER		0x1
131 
132 #define REG_PMC_DBG_CTRL1	0xa8
133 #define BITS_PMC_BT_IQK_STS	GENMASK(22, 21)
134 
135 #define REG_EFUSE_ACCESS	0x00CF
136 #define EFUSE_ACCESS_ON		0x69
137 #define EFUSE_ACCESS_OFF	0x00
138 
139 #define REG_WLRF1		0x00EC
140 #define REG_WIFI_BT_INFO	0x00AA
141 #define BIT_BT_INT_EN		BIT(15)
142 #define REG_SYS_CFG1		0x00F0
143 #define	BIT_RTL_ID		BIT(23)
144 #define BIT_LDO			BIT(24)
145 #define BIT_RF_TYPE_ID		BIT(27)
146 #define BIT_SHIFT_VENDOR_ID	16
147 #define BIT_MASK_VENDOR_ID	0xf
148 #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
149 #define BITS_VENDOR_ID		(BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
150 #define BIT_CLEAR_VENDOR_ID(x)	((x) & (~BITS_VENDOR_ID))
151 #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
152 #define BIT_SHIFT_CHIP_VER	12
153 #define BIT_MASK_CHIP_VER	0xf
154 #define BIT_CHIP_VER(x)	 (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
155 #define BITS_CHIP_VER		(BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
156 #define BIT_CLEAR_CHIP_VER(x)	((x) & (~BITS_CHIP_VER))
157 #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
158 #define REG_SYS_STATUS1		0x00F4
159 #define REG_SYS_STATUS2		0x00F8
160 #define REG_SYS_CFG2		0x00FC
161 #define REG_WLRF1		0x00EC
162 #define BIT_WLRF1_BBRF_EN	(BIT(24) | BIT(25) | BIT(26))
163 #define REG_CR			0x0100
164 #define BIT_32K_CAL_TMR_EN	BIT(10)
165 #define BIT_MAC_SEC_EN		BIT(9)
166 #define BIT_ENSWBCN		BIT(8)
167 #define BIT_MACRXEN		BIT(7)
168 #define BIT_MACTXEN		BIT(6)
169 #define BIT_SCHEDULE_EN		BIT(5)
170 #define BIT_PROTOCOL_EN		BIT(4)
171 #define BIT_RXDMA_EN		BIT(3)
172 #define BIT_TXDMA_EN		BIT(2)
173 #define BIT_HCI_RXDMA_EN	BIT(1)
174 #define BIT_HCI_TXDMA_EN	BIT(0)
175 #define MAC_TRX_ENABLE	(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
176 			BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
177 			BIT_MACTXEN | BIT_MACRXEN)
178 #define BIT_SHIFT_TXDMA_VOQ_MAP	4
179 #define BIT_MASK_TXDMA_VOQ_MAP	0x3
180 #define BIT_TXDMA_VOQ_MAP(x)                                                   \
181 	(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
182 #define BIT_SHIFT_TXDMA_VIQ_MAP	6
183 #define BIT_MASK_TXDMA_VIQ_MAP	0x3
184 #define BIT_TXDMA_VIQ_MAP(x)                                                   \
185 	(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
186 #define REG_TXDMA_PQ_MAP	0x010C
187 #define BIT_SHIFT_TXDMA_BEQ_MAP	8
188 #define BIT_MASK_TXDMA_BEQ_MAP	0x3
189 #define BIT_TXDMA_BEQ_MAP(x)                                                   \
190 	(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
191 #define BIT_SHIFT_TXDMA_BKQ_MAP	10
192 #define BIT_MASK_TXDMA_BKQ_MAP	0x3
193 #define BIT_TXDMA_BKQ_MAP(x)                                                   \
194 	(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
195 #define BIT_SHIFT_TXDMA_MGQ_MAP	12
196 #define BIT_MASK_TXDMA_MGQ_MAP	0x3
197 #define BIT_TXDMA_MGQ_MAP(x)                                                   \
198 	(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
199 #define BIT_SHIFT_TXDMA_HIQ_MAP	14
200 #define BIT_MASK_TXDMA_HIQ_MAP	0x3
201 #define BIT_TXDMA_HIQ_MAP(x)                                                   \
202 	(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
203 #define BIT_SHIFT_TXSC_40M	4
204 #define BIT_MASK_TXSC_40M	0xf
205 #define BIT_TXSC_40M(x)							       \
206 	(((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
207 #define BIT_SHIFT_TXSC_20M	0
208 #define BIT_MASK_TXSC_20M	0xf
209 #define BIT_TXSC_20M(x)							       \
210 	(((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
211 #define BIT_SHIFT_MAC_CLK_SEL	20
212 #define MAC_CLK_HW_DEF_80M	0
213 #define MAC_CLK_HW_DEF_40M	1
214 #define MAC_CLK_HW_DEF_20M	2
215 #define MAC_CLK_SPEED		80
216 
217 #define REG_CR			0x0100
218 #define REG_TRXFF_BNDY		0x0114
219 #define REG_RXFF_BNDY		0x011C
220 #define REG_FE1IMR		0x0120
221 #define BIT_FS_RXDONE		BIT(16)
222 #define REG_PKTBUF_DBG_CTRL	0x0140
223 #define REG_C2HEVT		0x01A0
224 #define REG_MCUTST_1		0x01C0
225 #define REG_MCUTST_II		0x01C4
226 #define REG_WOWLAN_WAKE_REASON	0x01C7
227 #define REG_HMETFR		0x01CC
228 #define REG_HMEBOX0		0x01D0
229 #define REG_HMEBOX1		0x01D4
230 #define REG_HMEBOX2		0x01D8
231 #define REG_HMEBOX3		0x01DC
232 #define REG_HMEBOX0_EX		0x01F0
233 #define REG_HMEBOX1_EX		0x01F4
234 #define REG_HMEBOX2_EX		0x01F8
235 #define REG_HMEBOX3_EX		0x01FC
236 
237 #define REG_RQPN		0x0200
238 #define BIT_MASK_HPQ		0xff
239 #define BIT_SHIFT_HPQ		0
240 #define BIT_RQPN_HPQ(x)		(((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
241 #define BIT_MASK_LPQ		0xff
242 #define BIT_SHIFT_LPQ		8
243 #define BIT_RQPN_LPQ(x)		(((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
244 #define BIT_MASK_PUBQ		0xff
245 #define BIT_SHIFT_PUBQ		16
246 #define BIT_RQPN_PUBQ(x)	(((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
247 #define BIT_RQPN_HLP(h, l, p)	(BIT_LD_RQPN | BIT_RQPN_HPQ(h) |	       \
248 				 BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p))
249 
250 #define REG_FIFOPAGE_CTRL_2	0x0204
251 #define BIT_BCN_VALID_V1	BIT(15)
252 #define BIT_MASK_BCN_HEAD_1_V1	0xfff
253 #define REG_AUTO_LLT_V1		0x0208
254 #define BIT_AUTO_INIT_LLT_V1	BIT(0)
255 #define REG_DWBCN0_CTRL		0x0208
256 #define BIT_BCN_VALID		BIT(16)
257 #define REG_TXDMA_OFFSET_CHK	0x020C
258 #define BIT_DROP_DATA_EN	BIT(9)
259 #define REG_TXDMA_STATUS	0x0210
260 #define BTI_PAGE_OVF		BIT(2)
261 
262 #define REG_RQPN_NPQ		0x0214
263 #define BIT_MASK_NPQ		0xff
264 #define BIT_SHIFT_NPQ		0
265 #define BIT_MASK_EPQ		0xff
266 #define BIT_SHIFT_EPQ		16
267 #define BIT_RQPN_NPQ(x)		(((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
268 #define BIT_RQPN_EPQ(x)		(((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ)
269 #define BIT_RQPN_NE(n, e)	(BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e))
270 
271 #define REG_AUTO_LLT		0x0224
272 #define BIT_AUTO_INIT_LLT	BIT(16)
273 #define REG_RQPN_CTRL_1		0x0228
274 #define REG_RQPN_CTRL_2		0x022C
275 #define BIT_LD_RQPN		BIT(31)
276 #define REG_FIFOPAGE_INFO_1	0x0230
277 #define REG_FIFOPAGE_INFO_2	0x0234
278 #define REG_FIFOPAGE_INFO_3	0x0238
279 #define REG_FIFOPAGE_INFO_4	0x023C
280 #define REG_FIFOPAGE_INFO_5	0x0240
281 #define REG_H2C_HEAD		0x0244
282 #define REG_H2C_TAIL		0x0248
283 #define REG_H2C_READ_ADDR	0x024C
284 #define REG_H2C_INFO		0x0254
285 #define REG_RXPKT_NUM		0x0284
286 #define BIT_RXDMA_REQ		BIT(19)
287 #define BIT_RW_RELEASE		BIT(18)
288 #define BIT_RXDMA_IDLE		BIT(17)
289 #define REG_RXPKTNUM		0x02B0
290 
291 #define REG_INT_MIG		0x0304
292 #define REG_HCI_MIX_CFG		0x03FC
293 #define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26)
294 
295 #define REG_BCNQ_INFO		0x0418
296 #define BIT_MGQ_CPU_EMPTY	BIT(24)
297 #define REG_FWHW_TXQ_CTRL	0x0420
298 #define BIT_EN_BCNQ_DL		BIT(22)
299 #define BIT_EN_WR_FREE_TAIL	BIT(20)
300 #define REG_HWSEQ_CTRL		0x0423
301 
302 #define REG_BCNQ_BDNY_V1	0x0424
303 #define REG_BCNQ_BDNY		0x0424
304 #define REG_MGQ_BDNY		0x0425
305 #define REG_LIFETIME_EN		0x0426
306 #define BIT_BA_PARSER_EN	BIT(5)
307 #define REG_SPEC_SIFS		0x0428
308 #define REG_RETRY_LIMIT		0x042a
309 #define REG_DARFRC		0x0430
310 #define REG_DARFRCH		0x0434
311 #define REG_RARFRCH		0x043C
312 #define REG_RRSR		0x0440
313 #define BITS_RRSR_RSC		GENMASK(22, 21)
314 #define REG_ARFR0		0x0444
315 #define REG_ARFRH0		0x0448
316 #define REG_ARFR1_V1		0x044C
317 #define REG_ARFRH1_V1		0x0450
318 #define REG_CCK_CHECK		0x0454
319 #define BIT_CHECK_CCK_EN	BIT(7)
320 #define REG_AMPDU_MAX_TIME_V1	0x0455
321 #define REG_BCNQ1_BDNY_V1	0x0456
322 #define REG_AMPDU_MAX_TIME	0x0456
323 #define REG_WMAC_LBK_BF_HD	0x045D
324 #define REG_TX_HANG_CTRL	0x045E
325 #define BIT_EN_GNT_BT_AWAKE	BIT(3)
326 #define BIT_EN_EOF_V1		BIT(2)
327 #define REG_DATA_SC		0x0483
328 #define REG_ARFR4		0x049C
329 #define BIT_WL_RFK		BIT(0)
330 #define REG_ARFRH4		0x04A0
331 #define REG_ARFR5		0x04A4
332 #define REG_ARFRH5		0x04A8
333 #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
334 #define BIT_PRE_TX_CMD		BIT(6)
335 #define REG_QUEUE_CTRL		0x04C6
336 #define BIT_PTA_WL_TX_EN	BIT(4)
337 #define BIT_PTA_EDCCA_EN	BIT(5)
338 #define REG_SINGLE_AMPDU_CTRL	0x04C7
339 #define BIT_EN_SINGLE_APMDU	BIT(7)
340 #define REG_PROT_MODE_CTRL	0x04C8
341 #define REG_MAX_AGGR_NUM	0x04CA
342 #define REG_BAR_MODE_CTRL	0x04CC
343 #define REG_PRECNT_CTRL		0x04E5
344 #define BIT_BTCCA_CTRL		(BIT(0) | BIT(1))
345 #define BIT_EN_PRECNT		BIT(11)
346 #define REG_DUMMY_PAGE4_V1	0x04FC
347 
348 #define REG_EDCA_VO_PARAM	0x0500
349 #define REG_EDCA_VI_PARAM	0x0504
350 #define REG_EDCA_BE_PARAM	0x0508
351 #define REG_EDCA_BK_PARAM	0x050C
352 #define BIT_MASK_TXOP_LMT	GENMASK(26, 16)
353 #define BIT_MASK_CWMAX		GENMASK(15, 12)
354 #define BIT_MASK_CWMIN		GENMASK(11, 8)
355 #define BIT_MASK_AIFS		GENMASK(7, 0)
356 #define REG_PIFS		0x0512
357 #define REG_SIFS		0x0514
358 #define BIT_SHIFT_SIFS_OFDM_CTX	8
359 #define BIT_SHIFT_SIFS_CCK_TRX	16
360 #define BIT_SHIFT_SIFS_OFDM_TRX	24
361 #define REG_AGGR_BREAK_TIME	0x051A
362 #define REG_SLOT		0x051B
363 #define REG_TX_PTCL_CTRL	0x0520
364 #define BIT_DIS_EDCCA		BIT(15)
365 #define BIT_SIFS_BK_EN		BIT(12)
366 #define REG_TXPAUSE		0x0522
367 #define BIT_AC_QUEUE		GENMASK(7, 0)
368 #define REG_RD_CTRL		0x0524
369 #define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
370 #define BIT_DIS_TXOP_CFE	BIT(10)
371 #define BIT_DIS_LSIG_CFE	BIT(9)
372 #define BIT_DIS_STBC_CFE	BIT(8)
373 #define REG_TBTT_PROHIBIT	0x0540
374 #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
375 #define REG_RD_NAV_NXT		0x0544
376 #define REG_NAV_PROT_LEN	0x0546
377 #define REG_BCN_CTRL		0x0550
378 #define BIT_DIS_TSF_UDT		BIT(4)
379 #define BIT_EN_BCN_FUNCTION	BIT(3)
380 #define BIT_EN_TXBCN_RPT	BIT(2)
381 #define REG_BCN_CTRL_CLINT0	0x0551
382 #define REG_DRVERLYINT		0x0558
383 #define REG_BCNDMATIM		0x0559
384 #define REG_ATIMWND		0x055A
385 #define REG_USTIME_TSF		0x055C
386 #define REG_BCN_MAX_ERR		0x055D
387 #define REG_RXTSF_OFFSET_CCK	0x055E
388 #define REG_MISC_CTRL		0x0577
389 #define BIT_EN_FREE_CNT		BIT(3)
390 #define BIT_DIS_SECOND_CCA	(BIT(0) | BIT(1))
391 #define REG_HIQ_NO_LMT_EN	0x5A7
392 #define REG_DTIM_COUNTER_ROOT	0x5A8
393 #define BIT_HIQ_NO_LMT_EN_ROOT	BIT(0)
394 #define REG_TIMER0_SRC_SEL	0x05B4
395 #define BIT_TSFT_SEL_TIMER0	(BIT(4) | BIT(5) | BIT(6))
396 
397 #define REG_TCR			0x0604
398 #define BIT_PWRMGT_HWDATA_EN	BIT(7)
399 #define BIT_TCR_UPDATE_TIMIE	BIT(5)
400 #define REG_RCR			0x0608
401 #define BIT_APP_FCS		BIT(31)
402 #define BIT_APP_MIC		BIT(30)
403 #define BIT_APP_ICV		BIT(29)
404 #define BIT_APP_PHYSTS		BIT(28)
405 #define BIT_APP_BASSN		BIT(27)
406 #define BIT_VHT_DACK		BIT(26)
407 #define BIT_TCPOFLD_EN		BIT(25)
408 #define BIT_ENMBID		BIT(24)
409 #define BIT_LSIGEN		BIT(23)
410 #define BIT_MFBEN		BIT(22)
411 #define BIT_DISCHKPPDLLEN	BIT(21)
412 #define BIT_PKTCTL_DLEN		BIT(20)
413 #define BIT_DISGCLK		BIT(19)
414 #define BIT_TIM_PARSER_EN	BIT(18)
415 #define BIT_BC_MD_EN		BIT(17)
416 #define BIT_UC_MD_EN		BIT(16)
417 #define BIT_RXSK_PERPKT		BIT(15)
418 #define BIT_HTC_LOC_CTRL	BIT(14)
419 #define BIT_RPFM_CAM_ENABLE	BIT(12)
420 #define BIT_TA_BCN		BIT(11)
421 #define BIT_RCR_ADF		BIT(11)
422 #define BIT_DISDECMYPKT		BIT(10)
423 #define BIT_AICV		BIT(9)
424 #define BIT_ACRC32		BIT(8)
425 #define BIT_CBSSID_BCN		BIT(7)
426 #define BIT_CBSSID_DATA		BIT(6)
427 #define BIT_APWRMGT		BIT(5)
428 #define BIT_ADD3		BIT(4)
429 #define BIT_AB			BIT(3)
430 #define BIT_AM			BIT(2)
431 #define BIT_APM			BIT(1)
432 #define BIT_AAP			BIT(0)
433 #define REG_RX_PKT_LIMIT	0x060C
434 #define REG_RX_DRVINFO_SZ	0x060F
435 #define BIT_APP_PHYSTS		BIT(28)
436 #define REG_MAR			0x0620
437 #define REG_USTIME_EDCA		0x0638
438 #define REG_ACKTO_CCK		0x0639
439 #define REG_MAC_SPEC_SIFS	0x063A
440 #define REG_RESP_SIFS_CCK	0x063C
441 #define REG_RESP_SIFS_OFDM	0x063E
442 #define REG_ACKTO		0x0640
443 #define REG_EIFS		0x0642
444 #define REG_NAV_CTRL		0x0650
445 #define REG_WMAC_TRXPTCL_CTL	0x0668
446 #define BIT_RFMOD		(BIT(7) | BIT(8))
447 #define BIT_RFMOD_80M		BIT(8)
448 #define BIT_RFMOD_40M		BIT(7)
449 #define REG_WMAC_TRXPTCL_CTL_H	0x066C
450 #define REG_WKFMCAM_CMD		0x0698
451 #define BIT_WKFCAM_POLLING_V1	BIT(31)
452 #define BIT_WKFCAM_CLR_V1	BIT(30)
453 #define BIT_WKFCAM_WE		BIT(16)
454 #define BIT_SHIFT_WKFCAM_ADDR_V2	8
455 #define BIT_MASK_WKFCAM_ADDR_V2		0xff
456 #define BIT_WKFCAM_ADDR_V2(x)						       \
457 	(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
458 #define REG_WKFMCAM_RWD         0x069C
459 #define BIT_WKFMCAM_VALID	BIT(31)
460 #define BIT_WKFMCAM_BC		BIT(26)
461 #define BIT_WKFMCAM_MC		BIT(25)
462 #define BIT_WKFMCAM_UC		BIT(24)
463 
464 #define REG_RXFLTMAP0		0x06A0
465 #define REG_RXFLTMAP1		0x06A2
466 #define REG_RXFLTMAP2		0x06A4
467 #define REG_RXFLTMAP4		0x068A
468 #define REG_BT_COEX_TABLE0	0x06C0
469 #define REG_BT_COEX_TABLE1	0x06C4
470 #define REG_BT_COEX_BRK_TABLE	0x06C8
471 #define REG_BT_COEX_TABLE_H	0x06CC
472 #define REG_BT_COEX_TABLE_H1	0x06CD
473 #define REG_BT_COEX_TABLE_H2	0x06CE
474 #define REG_BT_COEX_TABLE_H3	0x06CF
475 #define REG_BBPSF_CTRL		0x06DC
476 
477 #define REG_BT_COEX_V2		0x0762
478 #define BIT_GNT_BT_POLARITY	BIT(12)
479 #define BIT_LTE_COEX_EN		BIT(7)
480 #define REG_BT_COEX_ENH_INTR_CTRL	0x76E
481 #define BIT_R_GRANTALL_WLMASK	BIT(3)
482 #define BIT_STATIS_BT_EN	BIT(2)
483 #define REG_BT_ACT_STATISTICS	0x0770
484 #define REG_BT_ACT_STATISTICS_1	0x0774
485 #define REG_BT_STAT_CTRL	0x0778
486 #define REG_BT_TDMA_TIME	0x0790
487 #define BIT_MASK_SAMPLE_RATE	GENMASK(5, 0)
488 #define REG_LTR_IDLE_LATENCY	0x0798
489 #define REG_LTR_ACTIVE_LATENCY	0x079C
490 #define REG_LTR_CTRL_BASIC	0x07A4
491 #define REG_WMAC_OPTION_FUNCTION 0x07D0
492 #define REG_WMAC_OPTION_FUNCTION_1 0x07D4
493 
494 #define REG_FPGA0_RFMOD		0x0800
495 #define BIT_CCKEN		BIT(24)
496 #define BIT_OFDMEN		BIT(25)
497 #define REG_RX_GAIN_EN		0x081c
498 
499 #define REG_RFE_CTRL_E		0x0974
500 #define REG_2ND_CCA_CTRL	0x0976
501 
502 #define REG_CCK0_FAREPORT	0xa2c
503 #define BIT_CCK0_2RX		BIT(18)
504 #define BIT_CCK0_MRC		BIT(22)
505 
506 #define REG_DIS_DPD		0x0a70
507 #define DIS_DPD_MASK		GENMASK(9, 0)
508 #define DIS_DPD_RATE6M		BIT(0)
509 #define DIS_DPD_RATE9M		BIT(1)
510 #define DIS_DPD_RATEMCS0	BIT(2)
511 #define DIS_DPD_RATEMCS1	BIT(3)
512 #define DIS_DPD_RATEMCS8	BIT(4)
513 #define DIS_DPD_RATEMCS9	BIT(5)
514 #define DIS_DPD_RATEVHT1SS_MCS0	BIT(6)
515 #define DIS_DPD_RATEVHT1SS_MCS1	BIT(7)
516 #define DIS_DPD_RATEVHT2SS_MCS0	BIT(8)
517 #define DIS_DPD_RATEVHT2SS_MCS1	BIT(9)
518 #define DIS_DPD_RATEALL		GENMASK(9, 0)
519 
520 #define REG_RFE_CTRL8		0x0cb4
521 #define BIT_MASK_RFE_SEL89	GENMASK(7, 0)
522 #define REG_RFE_INV8		0x0cbd
523 #define BIT_MASK_RFE_INV89	GENMASK(1, 0)
524 #define REG_RFE_INV16		0x0cbe
525 #define BIT_RFE_BUF_EN		BIT(3)
526 
527 #define REG_ANAPAR_XTAL_0	0x1040
528 #define BIT_XCAP_0		GENMASK(23, 10)
529 #define REG_CPU_DMEM_CON	0x1080
530 #define BIT_WL_PLATFORM_RST	BIT(16)
531 #define BIT_WL_SECURITY_CLK	BIT(15)
532 #define BIT_DDMA_EN		BIT(8)
533 
534 #define REG_H2C_PKT_READADDR	0x10D0
535 #define REG_H2C_PKT_WRITEADDR	0x10D4
536 #define REG_FW_DBG7		0x10FC
537 #define FW_KEY_MASK		0xffffff00
538 
539 #define REG_CR_EXT		0x1100
540 
541 #define REG_DDMA_CH0SA		0x1200
542 #define REG_DDMA_CH0DA		0x1204
543 #define REG_DDMA_CH0CTRL	0x1208
544 #define BIT_DDMACH0_OWN		BIT(31)
545 #define BIT_DDMACH0_CHKSUM_EN	BIT(29)
546 #define BIT_DDMACH0_CHKSUM_STS	BIT(27)
547 #define BIT_DDMACH0_DDMA_MODE	BIT(26)
548 #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
549 #define BIT_DDMACH0_CHKSUM_CONT	BIT(24)
550 #define BIT_MASK_DDMACH0_DLEN	0x3ffff
551 
552 #define REG_H2CQ_CSR		0x1330
553 #define BIT_H2CQ_FULL		BIT(31)
554 #define REG_FAST_EDCA_VOVI_SETTING 0x1448
555 #define REG_FAST_EDCA_BEBK_SETTING 0x144C
556 
557 #define REG_RXPSF_CTRL		0x1610
558 #define BIT_RXGCK_FIFOTHR_EN	BIT(28)
559 
560 #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
561 #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
562 #define BIT_RXGCK_VHT_FIFOTHR(x)                                               \
563 	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
564 #define BITS_RXGCK_VHT_FIFOTHR                                                 \
565 	(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
566 
567 #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
568 #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
569 #define BIT_RXGCK_HT_FIFOTHR(x)                                                \
570 	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
571 #define BITS_RXGCK_HT_FIFOTHR                                                  \
572 	(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
573 
574 #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
575 #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
576 #define BIT_RXGCK_OFDM_FIFOTHR(x)                                              \
577 	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
578 #define BITS_RXGCK_OFDM_FIFOTHR                                                \
579 	(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
580 
581 #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
582 #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
583 #define BIT_RXGCK_CCK_FIFOTHR(x)                                               \
584 	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
585 #define BITS_RXGCK_CCK_FIFOTHR                                                 \
586 	(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
587 
588 #define BIT_RXGCK_OFDMCCA_EN BIT(16)
589 
590 #define BIT_SHIFT_RXPSF_PKTLENTHR 13
591 #define BIT_MASK_RXPSF_PKTLENTHR 0x7
592 #define BIT_RXPSF_PKTLENTHR(x)                                                 \
593 	(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
594 #define BITS_RXPSF_PKTLENTHR                                                   \
595 	(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
596 #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
597 #define BIT_SET_RXPSF_PKTLENTHR(x, v)                                          \
598 	(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))
599 
600 #define BIT_RXPSF_CTRLEN	BIT(12)
601 #define BIT_RXPSF_VHTCHKEN	BIT(11)
602 #define BIT_RXPSF_HTCHKEN	BIT(10)
603 #define BIT_RXPSF_OFDMCHKEN	BIT(9)
604 #define BIT_RXPSF_CCKCHKEN	BIT(8)
605 #define BIT_RXPSF_OFDMRST	BIT(7)
606 #define BIT_RXPSF_CCKRST	BIT(6)
607 #define BIT_RXPSF_MHCHKEN	BIT(5)
608 #define BIT_RXPSF_CONT_ERRCHKEN	BIT(4)
609 #define BIT_RXPSF_ALL_ERRCHKEN	BIT(3)
610 
611 #define BIT_SHIFT_RXPSF_ERRTHR 0
612 #define BIT_MASK_RXPSF_ERRTHR 0x7
613 #define BIT_RXPSF_ERRTHR(x)                                                    \
614 	(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
615 #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
616 #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
617 #define BIT_GET_RXPSF_ERRTHR(x)                                                \
618 	(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
619 #define BIT_SET_RXPSF_ERRTHR(x, v)                                             \
620 	(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))
621 
622 #define REG_RXPSF_TYPE_CTRL	0x1614
623 #define REG_GENERAL_OPTION	0x1664
624 #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)
625 
626 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1		0x1700
627 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1	0x1704
628 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1	0x1708
629 #define LTECOEX_READY		BIT(29)
630 #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
631 #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
632 #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
633 
634 #define REG_IGN_GNT_BT1	0x1860
635 
636 #define REG_RFESEL_CTRL	0x1990
637 
638 #define REG_NOMASK_TXBT	0x1ca7
639 #define REG_ANAPAR	0x1c30
640 #define BIT_ANAPAR_BTPS	BIT(22)
641 #define REG_RSTB_SEL	0x1c38
642 #define BIT_DAC_OFF_ENABLE	BIT(4)
643 #define BIT_PI_IGNORE_GNT_BT	BIT(3)
644 #define BIT_NOMASK_TXBT_ENABLE	BIT(3)
645 
646 #define REG_HRCV_MSG	0x1cf
647 
648 #define REG_EDCCA_REPORT	0x2d38
649 #define BIT_EDCCA_FLAG		BIT(24)
650 
651 #define REG_IGN_GNTBT4	0x4160
652 
653 #define RF_MODE		0x00
654 #define RF_MODOPT	0x01
655 #define RF_WLINT	0x01
656 #define RF_WLSEL	0x02
657 #define RF_DTXLOK	0x08
658 #define RF_CFGCH	0x18
659 #define BIT_BAND	GENMASK(18, 16)
660 #define RF_RCK		0x1d
661 #define RF_LUTWA	0x33
662 #define RF_LUTWD1	0x3e
663 #define RF_LUTWD0	0x3f
664 #define BIT_GAIN_EXT	BIT(12)
665 #define BIT_DATA_L	GENMASK(11, 0)
666 #define RF_T_METER	0x42
667 #define RF_BSPAD	0x54
668 #define RF_GAINTX	0x56
669 #define RF_TXATANK	0x64
670 #define RF_TRXIQ	0x66
671 #define RF_RXIQGEN	0x8d
672 #define RF_SYN_PFD	0xb0
673 #define RF_XTALX2	0xb8
674 #define RF_SYN_CTRL	0xbb
675 #define RF_MALSEL	0xbe
676 #define RF_SYN_AAC	0xc9
677 #define RF_AAC_CTRL	0xca
678 #define RF_FAST_LCK	0xcc
679 #define RF_RCKD		0xde
680 #define RF_TXADBG	0xde
681 #define RF_LUTDBG	0xdf
682 #define BIT_TXA_TANK	BIT(4)
683 #define RF_LUTWE2	0xee
684 #define RF_LUTWE	0xef
685 
686 #define LTE_COEX_CTRL	0x38
687 #define LTE_WL_TRX_CTRL	0xa0
688 #define LTE_BT_TRX_CTRL	0xa4
689 
690 #endif
691