1e3037485SYan-Hsuan Chuang /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2e3037485SYan-Hsuan Chuang /* Copyright(c) 2018-2019 Realtek Corporation 3e3037485SYan-Hsuan Chuang */ 4e3037485SYan-Hsuan Chuang 5e3037485SYan-Hsuan Chuang #ifndef __RTW_REG_DEF_H__ 6e3037485SYan-Hsuan Chuang #define __RTW_REG_DEF_H__ 7e3037485SYan-Hsuan Chuang 8e3037485SYan-Hsuan Chuang #define REG_SYS_FUNC_EN 0x0002 9e3037485SYan-Hsuan Chuang #define BIT_FEN_CPUEN BIT(2) 10e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_GLB_RST BIT(1) 11e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_RSTB BIT(0) 12e3037485SYan-Hsuan Chuang #define REG_SYS_PW_CTRL 0x0004 13e3037485SYan-Hsuan Chuang #define REG_SYS_CLK_CTRL 0x0008 14e3037485SYan-Hsuan Chuang #define BIT_CPU_CLK_EN BIT(14) 15e3037485SYan-Hsuan Chuang 16e3037485SYan-Hsuan Chuang #define REG_RSV_CTRL 0x001C 17e3037485SYan-Hsuan Chuang #define DISABLE_PI 0x3 18e3037485SYan-Hsuan Chuang #define ENABLE_PI 0x2 19e3037485SYan-Hsuan Chuang #define BITS_RFC_DIRECT (BIT(31) | BIT(30)) 20e3037485SYan-Hsuan Chuang #define BIT_WLMCU_IOIF BIT(0) 21e3037485SYan-Hsuan Chuang #define REG_RF_CTRL 0x001F 22e3037485SYan-Hsuan Chuang #define BIT_RF_SDM_RSTB BIT(2) 23e3037485SYan-Hsuan Chuang #define BIT_RF_RSTB BIT(1) 24e3037485SYan-Hsuan Chuang #define BIT_RF_EN BIT(0) 25e3037485SYan-Hsuan Chuang 26e3037485SYan-Hsuan Chuang #define REG_AFE_CTRL1 0x0024 27e3037485SYan-Hsuan Chuang #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21)) 28e3037485SYan-Hsuan Chuang #define REG_EFUSE_CTRL 0x0030 29e3037485SYan-Hsuan Chuang #define BIT_EF_FLAG BIT(31) 30e3037485SYan-Hsuan Chuang #define BIT_SHIFT_EF_ADDR 8 31e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_ADDR 0x3ff 32e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_DATA 0xff 33e3037485SYan-Hsuan Chuang #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) 34e3037485SYan-Hsuan Chuang 35e3037485SYan-Hsuan Chuang #define REG_LDO_EFUSE_CTRL 0x0034 36e3037485SYan-Hsuan Chuang #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9)) 37e3037485SYan-Hsuan Chuang 38e3037485SYan-Hsuan Chuang #define REG_GPIO_MUXCFG 0x0040 39e3037485SYan-Hsuan Chuang #define BIT_FSPI_EN BIT(19) 40e3037485SYan-Hsuan Chuang #define BIT_WLRFE_4_5_EN BIT(2) 41e3037485SYan-Hsuan Chuang 42e3037485SYan-Hsuan Chuang #define REG_LED_CFG 0x004C 43e3037485SYan-Hsuan Chuang #define BIT_LNAON_SEL_EN BIT(26) 44e3037485SYan-Hsuan Chuang #define BIT_PAPE_SEL_EN BIT(25) 45e3037485SYan-Hsuan Chuang #define REG_PAD_CTRL1 0x0064 46e3037485SYan-Hsuan Chuang #define BIT_PAPE_WLBT_SEL BIT(29) 47e3037485SYan-Hsuan Chuang #define BIT_LNAON_WLBT_SEL BIT(28) 48e3037485SYan-Hsuan Chuang #define REG_WL_BT_PWR_CTRL 0x0068 49e3037485SYan-Hsuan Chuang #define BIT_BT_FUNC_EN BIT(18) 50e3037485SYan-Hsuan Chuang #define BIT_BT_DIG_CLK_EN BIT(8) 51e3037485SYan-Hsuan Chuang #define REG_HCI_OPT_CTRL 0x0074 52e3037485SYan-Hsuan Chuang 53e3037485SYan-Hsuan Chuang #define REG_MCUFW_CTRL 0x0080 54e3037485SYan-Hsuan Chuang #define BIT_ANA_PORT_EN BIT(22) 55e3037485SYan-Hsuan Chuang #define BIT_MAC_PORT_EN BIT(21) 56e3037485SYan-Hsuan Chuang #define BIT_BOOT_FSPI_EN BIT(20) 57e3037485SYan-Hsuan Chuang #define BIT_FW_INIT_RDY BIT(15) 58e3037485SYan-Hsuan Chuang #define BIT_FW_DW_RDY BIT(14) 59e3037485SYan-Hsuan Chuang #define BIT_RPWM_TOGGLE BIT(7) 60e3037485SYan-Hsuan Chuang #define BIT_DMEM_CHKSUM_OK BIT(6) 61e3037485SYan-Hsuan Chuang #define BIT_DMEM_DW_OK BIT(5) 62e3037485SYan-Hsuan Chuang #define BIT_IMEM_CHKSUM_OK BIT(4) 63e3037485SYan-Hsuan Chuang #define BIT_IMEM_DW_OK BIT(3) 64e3037485SYan-Hsuan Chuang #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2) 65e3037485SYan-Hsuan Chuang #define BIT_MCUFWDL_EN BIT(0) 66e3037485SYan-Hsuan Chuang #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6)) 67e3037485SYan-Hsuan Chuang #define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \ 68e3037485SYan-Hsuan Chuang BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \ 69e3037485SYan-Hsuan Chuang BIT_CHECK_SUM_OK) 70e3037485SYan-Hsuan Chuang #define FW_READY_MASK 0xffff 71e3037485SYan-Hsuan Chuang 72e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 73e3037485SYan-Hsuan Chuang #define REG_SYS_CFG1 0x00F0 74e3037485SYan-Hsuan Chuang #define BIT_RTL_ID BIT(23) 75e3037485SYan-Hsuan Chuang #define BIT_RF_TYPE_ID BIT(27) 76e3037485SYan-Hsuan Chuang #define BIT_SHIFT_VENDOR_ID 16 77e3037485SYan-Hsuan Chuang #define BIT_MASK_VENDOR_ID 0xf 78e3037485SYan-Hsuan Chuang #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) 79e3037485SYan-Hsuan Chuang #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) 80e3037485SYan-Hsuan Chuang #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) 81e3037485SYan-Hsuan Chuang #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) 82e3037485SYan-Hsuan Chuang #define BIT_SHIFT_CHIP_VER 12 83e3037485SYan-Hsuan Chuang #define BIT_MASK_CHIP_VER 0xf 84e3037485SYan-Hsuan Chuang #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) 85e3037485SYan-Hsuan Chuang #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) 86e3037485SYan-Hsuan Chuang #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) 87e3037485SYan-Hsuan Chuang #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) 88e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS1 0x00F4 89e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS2 0x00F8 90e3037485SYan-Hsuan Chuang #define REG_SYS_CFG2 0x00FC 91e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 92e3037485SYan-Hsuan Chuang #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26)) 93e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 94e3037485SYan-Hsuan Chuang #define BIT_32K_CAL_TMR_EN BIT(10) 95e3037485SYan-Hsuan Chuang #define BIT_MAC_SEC_EN BIT(9) 96e3037485SYan-Hsuan Chuang #define BIT_ENSWBCN BIT(8) 97e3037485SYan-Hsuan Chuang #define BIT_MACRXEN BIT(7) 98e3037485SYan-Hsuan Chuang #define BIT_MACTXEN BIT(6) 99e3037485SYan-Hsuan Chuang #define BIT_SCHEDULE_EN BIT(5) 100e3037485SYan-Hsuan Chuang #define BIT_PROTOCOL_EN BIT(4) 101e3037485SYan-Hsuan Chuang #define BIT_RXDMA_EN BIT(3) 102e3037485SYan-Hsuan Chuang #define BIT_TXDMA_EN BIT(2) 103e3037485SYan-Hsuan Chuang #define BIT_HCI_RXDMA_EN BIT(1) 104e3037485SYan-Hsuan Chuang #define BIT_HCI_TXDMA_EN BIT(0) 105e3037485SYan-Hsuan Chuang #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ 106e3037485SYan-Hsuan Chuang BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ 107e3037485SYan-Hsuan Chuang BIT_MACTXEN | BIT_MACRXEN) 108e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VOQ_MAP 4 109e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VOQ_MAP 0x3 110e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VOQ_MAP(x) \ 111e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 112e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VIQ_MAP 6 113e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VIQ_MAP 0x3 114e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VIQ_MAP(x) \ 115e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 116e3037485SYan-Hsuan Chuang #define REG_TXDMA_PQ_MAP 0x010C 117e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BEQ_MAP 8 118e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BEQ_MAP 0x3 119e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BEQ_MAP(x) \ 120e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 121e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BKQ_MAP 10 122e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BKQ_MAP 0x3 123e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BKQ_MAP(x) \ 124e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) 125e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_MGQ_MAP 12 126e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_MGQ_MAP 0x3 127e3037485SYan-Hsuan Chuang #define BIT_TXDMA_MGQ_MAP(x) \ 128e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) 129e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_HIQ_MAP 14 130e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_HIQ_MAP 0x3 131e3037485SYan-Hsuan Chuang #define BIT_TXDMA_HIQ_MAP(x) \ 132e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) 133e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_40M 4 134e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_40M 0xf 135e3037485SYan-Hsuan Chuang #define BIT_TXSC_40M(x) \ 136e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) 137e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_20M 0 138e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_20M 0xf 139e3037485SYan-Hsuan Chuang #define BIT_TXSC_20M(x) \ 140e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) 141e3037485SYan-Hsuan Chuang #define BIT_SHIFT_MAC_CLK_SEL 20 142e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_80M 0 143e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_40M 1 144e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_20M 2 145e3037485SYan-Hsuan Chuang #define MAC_CLK_SPEED 80 146e3037485SYan-Hsuan Chuang 147e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 148e3037485SYan-Hsuan Chuang #define REG_TRXFF_BNDY 0x0114 149e3037485SYan-Hsuan Chuang #define REG_RXFF_BNDY 0x011C 150e3037485SYan-Hsuan Chuang #define REG_PKTBUF_DBG_CTRL 0x0140 151e3037485SYan-Hsuan Chuang #define REG_C2HEVT 0x01A0 152e3037485SYan-Hsuan Chuang #define REG_HMETFR 0x01CC 153e3037485SYan-Hsuan Chuang #define REG_HMEBOX0 0x01D0 154e3037485SYan-Hsuan Chuang #define REG_HMEBOX1 0x01D4 155e3037485SYan-Hsuan Chuang #define REG_HMEBOX2 0x01D8 156e3037485SYan-Hsuan Chuang #define REG_HMEBOX3 0x01DC 157e3037485SYan-Hsuan Chuang #define REG_HMEBOX0_EX 0x01F0 158e3037485SYan-Hsuan Chuang #define REG_HMEBOX1_EX 0x01F4 159e3037485SYan-Hsuan Chuang #define REG_HMEBOX2_EX 0x01F8 160e3037485SYan-Hsuan Chuang #define REG_HMEBOX3_EX 0x01FC 161e3037485SYan-Hsuan Chuang 162e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_CTRL_2 0x0204 163e3037485SYan-Hsuan Chuang #define BIT_BCN_VALID_V1 BIT(15) 164e3037485SYan-Hsuan Chuang #define BIT_MASK_BCN_HEAD_1_V1 0xfff 165e3037485SYan-Hsuan Chuang #define REG_AUTO_LLT_V1 0x0208 166e3037485SYan-Hsuan Chuang #define BIT_AUTO_INIT_LLT_V1 BIT(0) 167e3037485SYan-Hsuan Chuang #define REG_TXDMA_OFFSET_CHK 0x020C 168e3037485SYan-Hsuan Chuang #define REG_TXDMA_STATUS 0x0210 169e3037485SYan-Hsuan Chuang #define BTI_PAGE_OVF BIT(2) 170e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_1 0x0228 171e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_2 0x022C 172e3037485SYan-Hsuan Chuang #define BIT_LD_RQPN BIT(31) 173e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_1 0x0230 174e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_2 0x0234 175e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_3 0x0238 176e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_4 0x023C 177e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_5 0x0240 178e3037485SYan-Hsuan Chuang #define REG_H2C_HEAD 0x0244 179e3037485SYan-Hsuan Chuang #define REG_H2C_TAIL 0x0248 180e3037485SYan-Hsuan Chuang #define REG_H2C_READ_ADDR 0x024C 181e3037485SYan-Hsuan Chuang #define REG_H2C_INFO 0x0254 182e3037485SYan-Hsuan Chuang 183e3037485SYan-Hsuan Chuang #define REG_FWHW_TXQ_CTRL 0x0420 184e3037485SYan-Hsuan Chuang #define BIT_EN_BCNQ_DL BIT(22) 185e3037485SYan-Hsuan Chuang #define BIT_EN_WR_FREE_TAIL BIT(20) 186e3037485SYan-Hsuan Chuang #define REG_BCNQ_BDNY_V1 0x0424 187e3037485SYan-Hsuan Chuang #define REG_LIFETIME_EN 0x0426 188e3037485SYan-Hsuan Chuang #define BIT_BA_PARSER_EN BIT(5) 189e3037485SYan-Hsuan Chuang #define REG_SPEC_SIFS 0x0428 190e3037485SYan-Hsuan Chuang #define REG_DARFRC 0x0430 191e3037485SYan-Hsuan Chuang #define REG_DARFRCH 0x0434 192e3037485SYan-Hsuan Chuang #define REG_RARFRCH 0x043C 193e3037485SYan-Hsuan Chuang #define REG_ARFR0 0x0444 194e3037485SYan-Hsuan Chuang #define REG_ARFRH0 0x0448 195e3037485SYan-Hsuan Chuang #define REG_ARFR1_V1 0x044C 196e3037485SYan-Hsuan Chuang #define REG_ARFRH1_V1 0x0450 197e3037485SYan-Hsuan Chuang #define REG_CCK_CHECK 0x0454 198e3037485SYan-Hsuan Chuang #define BIT_CHECK_CCK_EN BIT(7) 199e3037485SYan-Hsuan Chuang #define REG_AMPDU_MAX_TIME_V1 0x0455 200e3037485SYan-Hsuan Chuang #define REG_BCNQ1_BDNY_V1 0x0456 201e3037485SYan-Hsuan Chuang #define REG_TX_HANG_CTRL 0x045E 202e3037485SYan-Hsuan Chuang #define BIT_EN_EOF_V1 BIT(2) 203e3037485SYan-Hsuan Chuang #define REG_DATA_SC 0x0483 204e3037485SYan-Hsuan Chuang #define REG_ARFR4 0x049C 205e3037485SYan-Hsuan Chuang #define REG_ARFRH4 0x04A0 206e3037485SYan-Hsuan Chuang #define REG_ARFR5 0x04A4 207e3037485SYan-Hsuan Chuang #define REG_ARFRH5 0x04A8 208e3037485SYan-Hsuan Chuang #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC 209e3037485SYan-Hsuan Chuang #define BIT_PRE_TX_CMD BIT(6) 210e3037485SYan-Hsuan Chuang #define REG_PROT_MODE_CTRL 0x04C8 211e3037485SYan-Hsuan Chuang #define REG_BAR_MODE_CTRL 0x04CC 212e3037485SYan-Hsuan Chuang #define REG_PRECNT_CTRL 0x04E5 213e3037485SYan-Hsuan Chuang #define BIT_EN_PRECNT BIT(11) 214e3037485SYan-Hsuan Chuang 215e3037485SYan-Hsuan Chuang #define REG_EDCA_VO_PARAM 0x0500 216e3037485SYan-Hsuan Chuang #define REG_EDCA_VI_PARAM 0x0504 217e3037485SYan-Hsuan Chuang #define REG_EDCA_BE_PARAM 0x0508 218e3037485SYan-Hsuan Chuang #define REG_EDCA_BK_PARAM 0x050C 219e3037485SYan-Hsuan Chuang #define REG_PIFS 0x0512 220e3037485SYan-Hsuan Chuang #define REG_SIFS 0x0514 221e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_CTX 8 222e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_CCK_TRX 16 223e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_TRX 24 224e3037485SYan-Hsuan Chuang #define REG_SLOT 0x051B 225e3037485SYan-Hsuan Chuang #define REG_TX_PTCL_CTRL 0x0520 226e3037485SYan-Hsuan Chuang #define BIT_SIFS_BK_EN BIT(12) 227e3037485SYan-Hsuan Chuang #define REG_TXPAUSE 0x0522 228e3037485SYan-Hsuan Chuang #define REG_RD_CTRL 0x0524 229e3037485SYan-Hsuan Chuang #define BIT_DIS_TXOP_CFE BIT(10) 230e3037485SYan-Hsuan Chuang #define BIT_DIS_LSIG_CFE BIT(9) 231e3037485SYan-Hsuan Chuang #define BIT_DIS_STBC_CFE BIT(8) 232e3037485SYan-Hsuan Chuang #define REG_TBTT_PROHIBIT 0x0540 233e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 234e3037485SYan-Hsuan Chuang #define REG_RD_NAV_NXT 0x0544 235e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL 0x0550 236e3037485SYan-Hsuan Chuang #define BIT_DIS_TSF_UDT BIT(4) 237e3037485SYan-Hsuan Chuang #define BIT_EN_BCN_FUNCTION BIT(3) 238e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL_CLINT0 0x0551 239e3037485SYan-Hsuan Chuang #define REG_DRVERLYINT 0x0558 240e3037485SYan-Hsuan Chuang #define REG_BCNDMATIM 0x0559 241e3037485SYan-Hsuan Chuang #define REG_USTIME_TSF 0x055C 242e3037485SYan-Hsuan Chuang #define REG_BCN_MAX_ERR 0x055D 243e3037485SYan-Hsuan Chuang #define REG_RXTSF_OFFSET_CCK 0x055E 244e3037485SYan-Hsuan Chuang #define REG_MISC_CTRL 0x0577 245e3037485SYan-Hsuan Chuang #define BIT_EN_FREE_CNT BIT(3) 246e3037485SYan-Hsuan Chuang #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1)) 247e3037485SYan-Hsuan Chuang #define REG_TIMER0_SRC_SEL 0x05B4 248e3037485SYan-Hsuan Chuang #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6)) 249e3037485SYan-Hsuan Chuang 250e3037485SYan-Hsuan Chuang #define REG_TCR 0x0604 251e3037485SYan-Hsuan Chuang #define REG_RCR 0x0608 252e3037485SYan-Hsuan Chuang #define BIT_APP_FCS BIT(31) 253e3037485SYan-Hsuan Chuang #define BIT_APP_MIC BIT(30) 254e3037485SYan-Hsuan Chuang #define BIT_APP_ICV BIT(29) 255e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 256e3037485SYan-Hsuan Chuang #define BIT_APP_BASSN BIT(27) 257e3037485SYan-Hsuan Chuang #define BIT_VHT_DACK BIT(26) 258e3037485SYan-Hsuan Chuang #define BIT_TCPOFLD_EN BIT(25) 259e3037485SYan-Hsuan Chuang #define BIT_ENMBID BIT(24) 260e3037485SYan-Hsuan Chuang #define BIT_LSIGEN BIT(23) 261e3037485SYan-Hsuan Chuang #define BIT_MFBEN BIT(22) 262e3037485SYan-Hsuan Chuang #define BIT_DISCHKPPDLLEN BIT(21) 263e3037485SYan-Hsuan Chuang #define BIT_PKTCTL_DLEN BIT(20) 264e3037485SYan-Hsuan Chuang #define BIT_TIM_PARSER_EN BIT(18) 265e3037485SYan-Hsuan Chuang #define BIT_BC_MD_EN BIT(17) 266e3037485SYan-Hsuan Chuang #define BIT_UC_MD_EN BIT(16) 267e3037485SYan-Hsuan Chuang #define BIT_RXSK_PERPKT BIT(15) 268e3037485SYan-Hsuan Chuang #define BIT_HTC_LOC_CTRL BIT(14) 269e3037485SYan-Hsuan Chuang #define BIT_RPFM_CAM_ENABLE BIT(12) 270e3037485SYan-Hsuan Chuang #define BIT_TA_BCN BIT(11) 271e3037485SYan-Hsuan Chuang #define BIT_DISDECMYPKT BIT(10) 272e3037485SYan-Hsuan Chuang #define BIT_AICV BIT(9) 273e3037485SYan-Hsuan Chuang #define BIT_ACRC32 BIT(8) 274e3037485SYan-Hsuan Chuang #define BIT_CBSSID_BCN BIT(7) 275e3037485SYan-Hsuan Chuang #define BIT_CBSSID_DATA BIT(6) 276e3037485SYan-Hsuan Chuang #define BIT_APWRMGT BIT(5) 277e3037485SYan-Hsuan Chuang #define BIT_ADD3 BIT(4) 278e3037485SYan-Hsuan Chuang #define BIT_AB BIT(3) 279e3037485SYan-Hsuan Chuang #define BIT_AM BIT(2) 280e3037485SYan-Hsuan Chuang #define BIT_APM BIT(1) 281e3037485SYan-Hsuan Chuang #define BIT_AAP BIT(0) 282e3037485SYan-Hsuan Chuang #define REG_RX_PKT_LIMIT 0x060C 283e3037485SYan-Hsuan Chuang #define REG_RX_DRVINFO_SZ 0x060F 284e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 285e3037485SYan-Hsuan Chuang #define REG_USTIME_EDCA 0x0638 286e3037485SYan-Hsuan Chuang #define REG_ACKTO_CCK 0x0639 287e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_CCK 0x063C 288e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_OFDM 0x063E 289e3037485SYan-Hsuan Chuang #define REG_ACKTO 0x0640 290e3037485SYan-Hsuan Chuang #define REG_EIFS 0x0642 291e3037485SYan-Hsuan Chuang #define REG_NAV_CTRL 0x0650 292e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL 0x0668 293e3037485SYan-Hsuan Chuang #define BIT_RFMOD (BIT(7) | BIT(8)) 294e3037485SYan-Hsuan Chuang #define BIT_RFMOD_80M BIT(8) 295e3037485SYan-Hsuan Chuang #define BIT_RFMOD_40M BIT(7) 296e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL_H 0x066C 297e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP0 0x06A0 298e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP1 0x06A2 299e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP2 0x06A4 300e3037485SYan-Hsuan Chuang #define REG_BBPSF_CTRL 0x06DC 301e3037485SYan-Hsuan Chuang 302e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION 0x07D0 303e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION_1 0x07D4 304e3037485SYan-Hsuan Chuang 305e3037485SYan-Hsuan Chuang #define REG_ANAPAR_XTAL_0 0x1040 306e3037485SYan-Hsuan Chuang #define REG_CPU_DMEM_CON 0x1080 307e3037485SYan-Hsuan Chuang #define BIT_WL_PLATFORM_RST BIT(16) 308e3037485SYan-Hsuan Chuang #define BIT_WL_SECURITY_CLK BIT(15) 309e3037485SYan-Hsuan Chuang #define BIT_DDMA_EN BIT(8) 310e3037485SYan-Hsuan Chuang 311e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_READADDR 0x10D0 312e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_WRITEADDR 0x10D4 313e3037485SYan-Hsuan Chuang #define REG_FW_DBG7 0x10FC 314e3037485SYan-Hsuan Chuang #define FW_KEY_MASK 0xffffff00 315e3037485SYan-Hsuan Chuang 316e3037485SYan-Hsuan Chuang #define REG_CR_EXT 0x1100 317e3037485SYan-Hsuan Chuang 318e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0SA 0x1200 319e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0DA 0x1204 320e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0CTRL 0x1208 321e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_OWN BIT(31) 322e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_EN BIT(29) 323e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_STS BIT(27) 324e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) 325e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_CONT BIT(24) 326e3037485SYan-Hsuan Chuang #define BIT_MASK_DDMACH0_DLEN 0x3ffff 327e3037485SYan-Hsuan Chuang 328e3037485SYan-Hsuan Chuang #define REG_H2CQ_CSR 0x1330 329e3037485SYan-Hsuan Chuang #define BIT_H2CQ_FULL BIT(31) 330e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_VOVI_SETTING 0x1448 331e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_BEBK_SETTING 0x144C 332e3037485SYan-Hsuan Chuang 333e3037485SYan-Hsuan Chuang #define REG_RXPSF_CTRL 0x1610 334e3037485SYan-Hsuan Chuang #define BIT_RXGCK_FIFOTHR_EN BIT(28) 335e3037485SYan-Hsuan Chuang 336e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 337e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 338e3037485SYan-Hsuan Chuang #define BIT_RXGCK_VHT_FIFOTHR(x) \ 339e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 340e3037485SYan-Hsuan Chuang #define BITS_RXGCK_VHT_FIFOTHR \ 341e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 342e3037485SYan-Hsuan Chuang 343e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 344e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 345e3037485SYan-Hsuan Chuang #define BIT_RXGCK_HT_FIFOTHR(x) \ 346e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) 347e3037485SYan-Hsuan Chuang #define BITS_RXGCK_HT_FIFOTHR \ 348e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) 349e3037485SYan-Hsuan Chuang 350e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 351e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 352e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDM_FIFOTHR(x) \ 353e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 354e3037485SYan-Hsuan Chuang #define BITS_RXGCK_OFDM_FIFOTHR \ 355e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 356e3037485SYan-Hsuan Chuang 357e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 358e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 359e3037485SYan-Hsuan Chuang #define BIT_RXGCK_CCK_FIFOTHR(x) \ 360e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 361e3037485SYan-Hsuan Chuang #define BITS_RXGCK_CCK_FIFOTHR \ 362e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 363e3037485SYan-Hsuan Chuang 364e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDMCCA_EN BIT(16) 365e3037485SYan-Hsuan Chuang 366e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_PKTLENTHR 13 367e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_PKTLENTHR 0x7 368e3037485SYan-Hsuan Chuang #define BIT_RXPSF_PKTLENTHR(x) \ 369e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) 370e3037485SYan-Hsuan Chuang #define BITS_RXPSF_PKTLENTHR \ 371e3037485SYan-Hsuan Chuang (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) 372e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) 373e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_PKTLENTHR(x, v) \ 374e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) 375e3037485SYan-Hsuan Chuang 376e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CTRLEN BIT(12) 377e3037485SYan-Hsuan Chuang #define BIT_RXPSF_VHTCHKEN BIT(11) 378e3037485SYan-Hsuan Chuang #define BIT_RXPSF_HTCHKEN BIT(10) 379e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMCHKEN BIT(9) 380e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKCHKEN BIT(8) 381e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMRST BIT(7) 382e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKRST BIT(6) 383e3037485SYan-Hsuan Chuang #define BIT_RXPSF_MHCHKEN BIT(5) 384e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) 385e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) 386e3037485SYan-Hsuan Chuang 387e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_ERRTHR 0 388e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_ERRTHR 0x7 389e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ERRTHR(x) \ 390e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) 391e3037485SYan-Hsuan Chuang #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) 392e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) 393e3037485SYan-Hsuan Chuang #define BIT_GET_RXPSF_ERRTHR(x) \ 394e3037485SYan-Hsuan Chuang (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) 395e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_ERRTHR(x, v) \ 396e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) 397e3037485SYan-Hsuan Chuang 398e3037485SYan-Hsuan Chuang #define REG_RXPSF_TYPE_CTRL 0x1614 399e3037485SYan-Hsuan Chuang #define REG_GENERAL_OPTION 0x1664 400e3037485SYan-Hsuan Chuang #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) 401e3037485SYan-Hsuan Chuang 402e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 403e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 404e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 405e3037485SYan-Hsuan Chuang #define LTECOEX_READY BIT(29) 406e3037485SYan-Hsuan Chuang #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 407e3037485SYan-Hsuan Chuang #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 408e3037485SYan-Hsuan Chuang #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 409e3037485SYan-Hsuan Chuang 410e3037485SYan-Hsuan Chuang #define RF_DTXLOK 0x08 411e3037485SYan-Hsuan Chuang #define RF_CFGCH 0x18 412e3037485SYan-Hsuan Chuang #define RF_LUTWA 0x33 413e3037485SYan-Hsuan Chuang #define RF_LUTWD1 0x3e 414e3037485SYan-Hsuan Chuang #define RF_LUTWD0 0x3f 415e3037485SYan-Hsuan Chuang #define RF_XTALX2 0xb8 416e3037485SYan-Hsuan Chuang #define RF_MALSEL 0xbe 417e3037485SYan-Hsuan Chuang #define RF_LUTDBG 0xdf 418e3037485SYan-Hsuan Chuang #define RF_LUTWE2 0xee 419e3037485SYan-Hsuan Chuang #define RF_LUTWE 0xef 420e3037485SYan-Hsuan Chuang 421e3037485SYan-Hsuan Chuang #endif 422