1e3037485SYan-Hsuan Chuang /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2e3037485SYan-Hsuan Chuang /* Copyright(c) 2018-2019 Realtek Corporation 3e3037485SYan-Hsuan Chuang */ 4e3037485SYan-Hsuan Chuang 5e3037485SYan-Hsuan Chuang #ifndef __RTW_REG_DEF_H__ 6e3037485SYan-Hsuan Chuang #define __RTW_REG_DEF_H__ 7e3037485SYan-Hsuan Chuang 8e3037485SYan-Hsuan Chuang #define REG_SYS_FUNC_EN 0x0002 975e69fb1SPing-Ke Shih #define BIT_FEN_EN_25_1 BIT(13) 1044baa97cSPing-Ke Shih #define BIT_FEN_ELDR BIT(12) 11e3037485SYan-Hsuan Chuang #define BIT_FEN_CPUEN BIT(2) 12e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_GLB_RST BIT(1) 13e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_RSTB BIT(0) 1444bc17f7SChin-Yen Lee #define BIT_R_DIS_PRST BIT(6) 1544bc17f7SChin-Yen Lee #define BIT_WLOCK_1C_B6 BIT(5) 16e3037485SYan-Hsuan Chuang #define REG_SYS_PW_CTRL 0x0004 174e223a5fSPing-Ke Shih #define BIT_PFM_WOWL BIT(3) 18e3037485SYan-Hsuan Chuang #define REG_SYS_CLK_CTRL 0x0008 19e3037485SYan-Hsuan Chuang #define BIT_CPU_CLK_EN BIT(14) 20e3037485SYan-Hsuan Chuang 2144baa97cSPing-Ke Shih #define REG_SYS_CLKR 0x0008 2244baa97cSPing-Ke Shih #define BIT_ANA8M BIT(1) 234e223a5fSPing-Ke Shih #define BIT_WAKEPAD_EN BIT(3) 2444baa97cSPing-Ke Shih #define BIT_LOADER_CLK_EN BIT(5) 2544baa97cSPing-Ke Shih 26e3037485SYan-Hsuan Chuang #define REG_RSV_CTRL 0x001C 27e3037485SYan-Hsuan Chuang #define DISABLE_PI 0x3 28e3037485SYan-Hsuan Chuang #define ENABLE_PI 0x2 29e3037485SYan-Hsuan Chuang #define BITS_RFC_DIRECT (BIT(31) | BIT(30)) 30e3037485SYan-Hsuan Chuang #define BIT_WLMCU_IOIF BIT(0) 31e3037485SYan-Hsuan Chuang #define REG_RF_CTRL 0x001F 32e3037485SYan-Hsuan Chuang #define BIT_RF_SDM_RSTB BIT(2) 33e3037485SYan-Hsuan Chuang #define BIT_RF_RSTB BIT(1) 34e3037485SYan-Hsuan Chuang #define BIT_RF_EN BIT(0) 35e3037485SYan-Hsuan Chuang 36e3037485SYan-Hsuan Chuang #define REG_AFE_CTRL1 0x0024 37e3037485SYan-Hsuan Chuang #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21)) 38e3037485SYan-Hsuan Chuang #define REG_EFUSE_CTRL 0x0030 39e3037485SYan-Hsuan Chuang #define BIT_EF_FLAG BIT(31) 40e3037485SYan-Hsuan Chuang #define BIT_SHIFT_EF_ADDR 8 41e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_ADDR 0x3ff 42e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_DATA 0xff 43e3037485SYan-Hsuan Chuang #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) 4475e69fb1SPing-Ke Shih #define BITS_PLL 0xf0 4575e69fb1SPing-Ke Shih 46769a29ceSTzu-En Huang #define REG_AFE_XTAL_CTRL 0x24 47769a29ceSTzu-En Huang #define REG_AFE_PLL_CTRL 0x28 4875e69fb1SPing-Ke Shih #define REG_AFE_CTRL3 0x2c 4975e69fb1SPing-Ke Shih #define BIT_MASK_XTAL 0x00FFF000 5075e69fb1SPing-Ke Shih #define BIT_XTAL_GMP_BIT4 BIT(28) 51e3037485SYan-Hsuan Chuang 52e3037485SYan-Hsuan Chuang #define REG_LDO_EFUSE_CTRL 0x0034 53e3037485SYan-Hsuan Chuang #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9)) 54e3037485SYan-Hsuan Chuang 551afb5eb7SPing-Ke Shih #define BIT_LDO25_VOLTAGE_V25 0x03 561afb5eb7SPing-Ke Shih #define BIT_MASK_LDO25_VOLTAGE GENMASK(6, 4) 571afb5eb7SPing-Ke Shih #define BIT_SHIFT_LDO25_VOLTAGE 4 581afb5eb7SPing-Ke Shih #define BIT_LDO25_EN BIT(7) 591afb5eb7SPing-Ke Shih 60e3037485SYan-Hsuan Chuang #define REG_GPIO_MUXCFG 0x0040 61e3037485SYan-Hsuan Chuang #define BIT_FSPI_EN BIT(19) 624e223a5fSPing-Ke Shih #define BIT_EN_SIC BIT(12) 633f3fef5fSChing-Te Ku 647b080e08SPing-Cheng Chen #define BIT_PO_BT_PTA_PINS BIT(9) 654136214fSYan-Hsuan Chuang #define BIT_BT_PTA_EN BIT(5) 66e3037485SYan-Hsuan Chuang #define BIT_WLRFE_4_5_EN BIT(2) 67e3037485SYan-Hsuan Chuang 68e3037485SYan-Hsuan Chuang #define REG_LED_CFG 0x004C 69e3037485SYan-Hsuan Chuang #define BIT_LNAON_SEL_EN BIT(26) 70e3037485SYan-Hsuan Chuang #define BIT_PAPE_SEL_EN BIT(25) 714136214fSYan-Hsuan Chuang #define BIT_DPDT_WL_SEL BIT(24) 724136214fSYan-Hsuan Chuang #define BIT_DPDT_SEL_EN BIT(23) 7375e69fb1SPing-Ke Shih #define REG_LEDCFG2 0x004E 74e3037485SYan-Hsuan Chuang #define REG_PAD_CTRL1 0x0064 751d229e88SPing-Ke Shih #define BIT_BT_BTG_SEL BIT(31) 76e3037485SYan-Hsuan Chuang #define BIT_PAPE_WLBT_SEL BIT(29) 77e3037485SYan-Hsuan Chuang #define BIT_LNAON_WLBT_SEL BIT(28) 784136214fSYan-Hsuan Chuang #define BIT_BTGP_JTAG_EN BIT(24) 794136214fSYan-Hsuan Chuang #define BIT_BTGP_SPI_EN BIT(20) 804136214fSYan-Hsuan Chuang #define BIT_LED1DIS BIT(15) 814136214fSYan-Hsuan Chuang #define BIT_SW_DPDT_SEL_DATA BIT(0) 82e3037485SYan-Hsuan Chuang #define REG_WL_BT_PWR_CTRL 0x0068 83e3037485SYan-Hsuan Chuang #define BIT_BT_FUNC_EN BIT(18) 84e3037485SYan-Hsuan Chuang #define BIT_BT_DIG_CLK_EN BIT(8) 854136214fSYan-Hsuan Chuang #define REG_SYS_SDIO_CTRL 0x0070 864136214fSYan-Hsuan Chuang #define BIT_DBG_GNT_WL_BT BIT(27) 874136214fSYan-Hsuan Chuang #define BIT_LTE_MUX_CTRL_PATH BIT(26) 88e3037485SYan-Hsuan Chuang #define REG_HCI_OPT_CTRL 0x0074 8905202746SPing-Ke Shih #define BIT_USB_SUS_DIS BIT(8) 90e3037485SYan-Hsuan Chuang 9175e69fb1SPing-Ke Shih #define REG_AFE_CTRL_4 0x0078 9275e69fb1SPing-Ke Shih #define BIT_CK320M_AFE_EN BIT(4) 9375e69fb1SPing-Ke Shih #define BIT_EN_SYN BIT(15) 9475e69fb1SPing-Ke Shih 954e223a5fSPing-Ke Shih #define REG_LDO_SWR_CTRL 0x007C 964e223a5fSPing-Ke Shih #define LDO_SEL 0xC3 974e223a5fSPing-Ke Shih #define SPS_SEL 0x83 9875e69fb1SPing-Ke Shih #define BIT_XTA1 BIT(29) 9975e69fb1SPing-Ke Shih #define BIT_XTA0 BIT(28) 1004e223a5fSPing-Ke Shih 101e3037485SYan-Hsuan Chuang #define REG_MCUFW_CTRL 0x0080 102e3037485SYan-Hsuan Chuang #define BIT_ANA_PORT_EN BIT(22) 103e3037485SYan-Hsuan Chuang #define BIT_MAC_PORT_EN BIT(21) 104e3037485SYan-Hsuan Chuang #define BIT_BOOT_FSPI_EN BIT(20) 10515d2fcc6SPing-Ke Shih #define BIT_ROM_DLEN BIT(19) 10615d2fcc6SPing-Ke Shih #define BIT_ROM_PGE GENMASK(18, 16) /* legacy only */ 10715d2fcc6SPing-Ke Shih #define BIT_SHIFT_ROM_PGE 16 108e3037485SYan-Hsuan Chuang #define BIT_FW_INIT_RDY BIT(15) 109e3037485SYan-Hsuan Chuang #define BIT_FW_DW_RDY BIT(14) 110e3037485SYan-Hsuan Chuang #define BIT_RPWM_TOGGLE BIT(7) 11115d2fcc6SPing-Ke Shih #define BIT_RAM_DL_SEL BIT(7) /* legacy only */ 112e3037485SYan-Hsuan Chuang #define BIT_DMEM_CHKSUM_OK BIT(6) 11315d2fcc6SPing-Ke Shih #define BIT_WINTINI_RDY BIT(6) /* legacy only */ 114e3037485SYan-Hsuan Chuang #define BIT_DMEM_DW_OK BIT(5) 115e3037485SYan-Hsuan Chuang #define BIT_IMEM_CHKSUM_OK BIT(4) 116e3037485SYan-Hsuan Chuang #define BIT_IMEM_DW_OK BIT(3) 117e3037485SYan-Hsuan Chuang #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2) 11815d2fcc6SPing-Ke Shih #define BIT_FWDL_CHK_RPT BIT(2) /* legacy only */ 11915d2fcc6SPing-Ke Shih #define BIT_MCUFWDL_RDY BIT(1) /* legacy only */ 120e3037485SYan-Hsuan Chuang #define BIT_MCUFWDL_EN BIT(0) 121e3037485SYan-Hsuan Chuang #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6)) 122e3037485SYan-Hsuan Chuang #define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \ 123e3037485SYan-Hsuan Chuang BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \ 124e3037485SYan-Hsuan Chuang BIT_CHECK_SUM_OK) 12515d2fcc6SPing-Ke Shih #define FW_READY_LEGACY (BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT | \ 12615d2fcc6SPing-Ke Shih BIT_WINTINI_RDY | BIT_RAM_DL_SEL) 127e3037485SYan-Hsuan Chuang #define FW_READY_MASK 0xffff 128e3037485SYan-Hsuan Chuang 1295c831644STzu-En Huang #define REG_MCU_TST_CFG 0x84 1305c831644STzu-En Huang #define VAL_FW_TRIGGER 0x1 1315c831644STzu-En Huang 132056b239fSGuo-Feng Fan #define REG_PMC_DBG_CTRL1 0xa8 133056b239fSGuo-Feng Fan #define BITS_PMC_BT_IQK_STS GENMASK(22, 21) 134056b239fSGuo-Feng Fan 13544baa97cSPing-Ke Shih #define REG_EFUSE_ACCESS 0x00CF 13644baa97cSPing-Ke Shih #define EFUSE_ACCESS_ON 0x69 13744baa97cSPing-Ke Shih #define EFUSE_ACCESS_OFF 0x00 13844baa97cSPing-Ke Shih 139e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 1404136214fSYan-Hsuan Chuang #define REG_WIFI_BT_INFO 0x00AA 1414136214fSYan-Hsuan Chuang #define BIT_BT_INT_EN BIT(15) 142e3037485SYan-Hsuan Chuang #define REG_SYS_CFG1 0x00F0 143e3037485SYan-Hsuan Chuang #define BIT_RTL_ID BIT(23) 1444e223a5fSPing-Ke Shih #define BIT_LDO BIT(24) 145e3037485SYan-Hsuan Chuang #define BIT_RF_TYPE_ID BIT(27) 146e3037485SYan-Hsuan Chuang #define BIT_SHIFT_VENDOR_ID 16 147e3037485SYan-Hsuan Chuang #define BIT_MASK_VENDOR_ID 0xf 148e3037485SYan-Hsuan Chuang #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) 149e3037485SYan-Hsuan Chuang #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) 150e3037485SYan-Hsuan Chuang #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) 151e3037485SYan-Hsuan Chuang #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) 152e3037485SYan-Hsuan Chuang #define BIT_SHIFT_CHIP_VER 12 153e3037485SYan-Hsuan Chuang #define BIT_MASK_CHIP_VER 0xf 154e3037485SYan-Hsuan Chuang #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) 155e3037485SYan-Hsuan Chuang #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) 156e3037485SYan-Hsuan Chuang #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) 157e3037485SYan-Hsuan Chuang #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) 158e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS1 0x00F4 159e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS2 0x00F8 160e3037485SYan-Hsuan Chuang #define REG_SYS_CFG2 0x00FC 161e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 162e3037485SYan-Hsuan Chuang #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26)) 163e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 164e3037485SYan-Hsuan Chuang #define BIT_32K_CAL_TMR_EN BIT(10) 165e3037485SYan-Hsuan Chuang #define BIT_MAC_SEC_EN BIT(9) 166e3037485SYan-Hsuan Chuang #define BIT_ENSWBCN BIT(8) 167e3037485SYan-Hsuan Chuang #define BIT_MACRXEN BIT(7) 168e3037485SYan-Hsuan Chuang #define BIT_MACTXEN BIT(6) 169e3037485SYan-Hsuan Chuang #define BIT_SCHEDULE_EN BIT(5) 170e3037485SYan-Hsuan Chuang #define BIT_PROTOCOL_EN BIT(4) 171e3037485SYan-Hsuan Chuang #define BIT_RXDMA_EN BIT(3) 172e3037485SYan-Hsuan Chuang #define BIT_TXDMA_EN BIT(2) 173e3037485SYan-Hsuan Chuang #define BIT_HCI_RXDMA_EN BIT(1) 174e3037485SYan-Hsuan Chuang #define BIT_HCI_TXDMA_EN BIT(0) 175e3037485SYan-Hsuan Chuang #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ 176e3037485SYan-Hsuan Chuang BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ 177e3037485SYan-Hsuan Chuang BIT_MACTXEN | BIT_MACRXEN) 178e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VOQ_MAP 4 179e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VOQ_MAP 0x3 180e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VOQ_MAP(x) \ 181e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 182e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VIQ_MAP 6 183e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VIQ_MAP 0x3 184e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VIQ_MAP(x) \ 185e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 186e3037485SYan-Hsuan Chuang #define REG_TXDMA_PQ_MAP 0x010C 187e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BEQ_MAP 8 188e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BEQ_MAP 0x3 189e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BEQ_MAP(x) \ 190e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 191e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BKQ_MAP 10 192e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BKQ_MAP 0x3 193e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BKQ_MAP(x) \ 194e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) 195e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_MGQ_MAP 12 196e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_MGQ_MAP 0x3 197e3037485SYan-Hsuan Chuang #define BIT_TXDMA_MGQ_MAP(x) \ 198e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) 199e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_HIQ_MAP 14 200e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_HIQ_MAP 0x3 201e3037485SYan-Hsuan Chuang #define BIT_TXDMA_HIQ_MAP(x) \ 202e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) 203e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_40M 4 204e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_40M 0xf 205e3037485SYan-Hsuan Chuang #define BIT_TXSC_40M(x) \ 206e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) 207e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_20M 0 208e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_20M 0xf 209e3037485SYan-Hsuan Chuang #define BIT_TXSC_20M(x) \ 210e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) 211e3037485SYan-Hsuan Chuang #define BIT_SHIFT_MAC_CLK_SEL 20 212e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_80M 0 213e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_40M 1 214e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_20M 2 215e3037485SYan-Hsuan Chuang #define MAC_CLK_SPEED 80 216e3037485SYan-Hsuan Chuang 217e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 218e3037485SYan-Hsuan Chuang #define REG_TRXFF_BNDY 0x0114 219e3037485SYan-Hsuan Chuang #define REG_RXFF_BNDY 0x011C 22044bc17f7SChin-Yen Lee #define REG_FE1IMR 0x0120 22144bc17f7SChin-Yen Lee #define BIT_FS_RXDONE BIT(16) 222e3037485SYan-Hsuan Chuang #define REG_PKTBUF_DBG_CTRL 0x0140 223e3037485SYan-Hsuan Chuang #define REG_C2HEVT 0x01A0 22475e69fb1SPing-Ke Shih #define REG_MCUTST_1 0x01C0 22544bc17f7SChin-Yen Lee #define REG_MCUTST_II 0x01C4 22644bc17f7SChin-Yen Lee #define REG_WOWLAN_WAKE_REASON 0x01C7 227e3037485SYan-Hsuan Chuang #define REG_HMETFR 0x01CC 228e3037485SYan-Hsuan Chuang #define REG_HMEBOX0 0x01D0 229e3037485SYan-Hsuan Chuang #define REG_HMEBOX1 0x01D4 230e3037485SYan-Hsuan Chuang #define REG_HMEBOX2 0x01D8 231e3037485SYan-Hsuan Chuang #define REG_HMEBOX3 0x01DC 232e3037485SYan-Hsuan Chuang #define REG_HMEBOX0_EX 0x01F0 233e3037485SYan-Hsuan Chuang #define REG_HMEBOX1_EX 0x01F4 234e3037485SYan-Hsuan Chuang #define REG_HMEBOX2_EX 0x01F8 235e3037485SYan-Hsuan Chuang #define REG_HMEBOX3_EX 0x01FC 236e3037485SYan-Hsuan Chuang 237d91277deSPing-Ke Shih #define REG_RQPN 0x0200 238d91277deSPing-Ke Shih #define BIT_MASK_HPQ 0xff 239d91277deSPing-Ke Shih #define BIT_SHIFT_HPQ 0 240d91277deSPing-Ke Shih #define BIT_RQPN_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) 241d91277deSPing-Ke Shih #define BIT_MASK_LPQ 0xff 242d91277deSPing-Ke Shih #define BIT_SHIFT_LPQ 8 243d91277deSPing-Ke Shih #define BIT_RQPN_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) 244d91277deSPing-Ke Shih #define BIT_MASK_PUBQ 0xff 245d91277deSPing-Ke Shih #define BIT_SHIFT_PUBQ 16 246d91277deSPing-Ke Shih #define BIT_RQPN_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) 247d91277deSPing-Ke Shih #define BIT_RQPN_HLP(h, l, p) (BIT_LD_RQPN | BIT_RQPN_HPQ(h) | \ 248d91277deSPing-Ke Shih BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p)) 249d91277deSPing-Ke Shih 250e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_CTRL_2 0x0204 251e3037485SYan-Hsuan Chuang #define BIT_BCN_VALID_V1 BIT(15) 252e3037485SYan-Hsuan Chuang #define BIT_MASK_BCN_HEAD_1_V1 0xfff 253e3037485SYan-Hsuan Chuang #define REG_AUTO_LLT_V1 0x0208 254e3037485SYan-Hsuan Chuang #define BIT_AUTO_INIT_LLT_V1 BIT(0) 25515d2fcc6SPing-Ke Shih #define REG_DWBCN0_CTRL 0x0208 25615d2fcc6SPing-Ke Shih #define BIT_BCN_VALID BIT(16) 257e3037485SYan-Hsuan Chuang #define REG_TXDMA_OFFSET_CHK 0x020C 25875e69fb1SPing-Ke Shih #define BIT_DROP_DATA_EN BIT(9) 259e3037485SYan-Hsuan Chuang #define REG_TXDMA_STATUS 0x0210 260e3037485SYan-Hsuan Chuang #define BTI_PAGE_OVF BIT(2) 261d91277deSPing-Ke Shih 262d91277deSPing-Ke Shih #define REG_RQPN_NPQ 0x0214 263d91277deSPing-Ke Shih #define BIT_MASK_NPQ 0xff 264d91277deSPing-Ke Shih #define BIT_SHIFT_NPQ 0 265d91277deSPing-Ke Shih #define BIT_MASK_EPQ 0xff 266d91277deSPing-Ke Shih #define BIT_SHIFT_EPQ 16 267d91277deSPing-Ke Shih #define BIT_RQPN_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) 268d91277deSPing-Ke Shih #define BIT_RQPN_EPQ(x) (((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ) 269d91277deSPing-Ke Shih #define BIT_RQPN_NE(n, e) (BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e)) 270d91277deSPing-Ke Shih 271d91277deSPing-Ke Shih #define REG_AUTO_LLT 0x0224 272d91277deSPing-Ke Shih #define BIT_AUTO_INIT_LLT BIT(16) 273e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_1 0x0228 274e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_2 0x022C 275e3037485SYan-Hsuan Chuang #define BIT_LD_RQPN BIT(31) 276e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_1 0x0230 277e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_2 0x0234 278e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_3 0x0238 279e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_4 0x023C 280e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_5 0x0240 281e3037485SYan-Hsuan Chuang #define REG_H2C_HEAD 0x0244 282e3037485SYan-Hsuan Chuang #define REG_H2C_TAIL 0x0248 283e3037485SYan-Hsuan Chuang #define REG_H2C_READ_ADDR 0x024C 284e3037485SYan-Hsuan Chuang #define REG_H2C_INFO 0x0254 28544bc17f7SChin-Yen Lee #define REG_RXPKT_NUM 0x0284 28644bc17f7SChin-Yen Lee #define BIT_RXDMA_REQ BIT(19) 28744bc17f7SChin-Yen Lee #define BIT_RW_RELEASE BIT(18) 28844bc17f7SChin-Yen Lee #define BIT_RXDMA_IDLE BIT(17) 28944bc17f7SChin-Yen Lee #define REG_RXPKTNUM 0x02B0 290e3037485SYan-Hsuan Chuang 291bc61ae96STsang-Shian Lin #define REG_INT_MIG 0x0304 29278622104SYan-Hsuan Chuang #define REG_HCI_MIX_CFG 0x03FC 29378622104SYan-Hsuan Chuang #define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26) 294bc61ae96STsang-Shian Lin 29544bc17f7SChin-Yen Lee #define REG_BCNQ_INFO 0x0418 29644bc17f7SChin-Yen Lee #define BIT_MGQ_CPU_EMPTY BIT(24) 297e3037485SYan-Hsuan Chuang #define REG_FWHW_TXQ_CTRL 0x0420 298e3037485SYan-Hsuan Chuang #define BIT_EN_BCNQ_DL BIT(22) 299e3037485SYan-Hsuan Chuang #define BIT_EN_WR_FREE_TAIL BIT(20) 3004e223a5fSPing-Ke Shih #define REG_HWSEQ_CTRL 0x0423 3014e223a5fSPing-Ke Shih 302e3037485SYan-Hsuan Chuang #define REG_BCNQ_BDNY_V1 0x0424 303d91277deSPing-Ke Shih #define REG_BCNQ_BDNY 0x0424 304d91277deSPing-Ke Shih #define REG_MGQ_BDNY 0x0425 305e3037485SYan-Hsuan Chuang #define REG_LIFETIME_EN 0x0426 306e3037485SYan-Hsuan Chuang #define BIT_BA_PARSER_EN BIT(5) 307e3037485SYan-Hsuan Chuang #define REG_SPEC_SIFS 0x0428 3084136214fSYan-Hsuan Chuang #define REG_RETRY_LIMIT 0x042a 309e3037485SYan-Hsuan Chuang #define REG_DARFRC 0x0430 310e3037485SYan-Hsuan Chuang #define REG_DARFRCH 0x0434 311e3037485SYan-Hsuan Chuang #define REG_RARFRCH 0x043C 31248308726SPo-Hao Huang #define REG_RRSR 0x0440 31348308726SPo-Hao Huang #define BITS_RRSR_RSC GENMASK(22, 21) 314e3037485SYan-Hsuan Chuang #define REG_ARFR0 0x0444 315e3037485SYan-Hsuan Chuang #define REG_ARFRH0 0x0448 316e3037485SYan-Hsuan Chuang #define REG_ARFR1_V1 0x044C 317e3037485SYan-Hsuan Chuang #define REG_ARFRH1_V1 0x0450 318e3037485SYan-Hsuan Chuang #define REG_CCK_CHECK 0x0454 319e3037485SYan-Hsuan Chuang #define BIT_CHECK_CCK_EN BIT(7) 320e3037485SYan-Hsuan Chuang #define REG_AMPDU_MAX_TIME_V1 0x0455 321e3037485SYan-Hsuan Chuang #define REG_BCNQ1_BDNY_V1 0x0456 32275e69fb1SPing-Ke Shih #define REG_AMPDU_MAX_TIME 0x0456 323d91277deSPing-Ke Shih #define REG_WMAC_LBK_BF_HD 0x045D 324e3037485SYan-Hsuan Chuang #define REG_TX_HANG_CTRL 0x045E 3254136214fSYan-Hsuan Chuang #define BIT_EN_GNT_BT_AWAKE BIT(3) 326e3037485SYan-Hsuan Chuang #define BIT_EN_EOF_V1 BIT(2) 327e3037485SYan-Hsuan Chuang #define REG_DATA_SC 0x0483 328e3037485SYan-Hsuan Chuang #define REG_ARFR4 0x049C 3294136214fSYan-Hsuan Chuang #define BIT_WL_RFK BIT(0) 330e3037485SYan-Hsuan Chuang #define REG_ARFRH4 0x04A0 331e3037485SYan-Hsuan Chuang #define REG_ARFR5 0x04A4 332e3037485SYan-Hsuan Chuang #define REG_ARFRH5 0x04A8 333e3037485SYan-Hsuan Chuang #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC 334e3037485SYan-Hsuan Chuang #define BIT_PRE_TX_CMD BIT(6) 3354136214fSYan-Hsuan Chuang #define REG_QUEUE_CTRL 0x04C6 3364136214fSYan-Hsuan Chuang #define BIT_PTA_WL_TX_EN BIT(4) 3374136214fSYan-Hsuan Chuang #define BIT_PTA_EDCCA_EN BIT(5) 33875e69fb1SPing-Ke Shih #define REG_SINGLE_AMPDU_CTRL 0x04C7 33975e69fb1SPing-Ke Shih #define BIT_EN_SINGLE_APMDU BIT(7) 340e3037485SYan-Hsuan Chuang #define REG_PROT_MODE_CTRL 0x04C8 34175e69fb1SPing-Ke Shih #define REG_MAX_AGGR_NUM 0x04CA 342e3037485SYan-Hsuan Chuang #define REG_BAR_MODE_CTRL 0x04CC 343e3037485SYan-Hsuan Chuang #define REG_PRECNT_CTRL 0x04E5 3444136214fSYan-Hsuan Chuang #define BIT_BTCCA_CTRL (BIT(0) | BIT(1)) 345e3037485SYan-Hsuan Chuang #define BIT_EN_PRECNT BIT(11) 3464136214fSYan-Hsuan Chuang #define REG_DUMMY_PAGE4_V1 0x04FC 347e3037485SYan-Hsuan Chuang 348e3037485SYan-Hsuan Chuang #define REG_EDCA_VO_PARAM 0x0500 349e3037485SYan-Hsuan Chuang #define REG_EDCA_VI_PARAM 0x0504 350e3037485SYan-Hsuan Chuang #define REG_EDCA_BE_PARAM 0x0508 351e3037485SYan-Hsuan Chuang #define REG_EDCA_BK_PARAM 0x050C 352bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_TXOP_LMT GENMASK(26, 16) 353bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_CWMAX GENMASK(15, 12) 354bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_CWMIN GENMASK(11, 8) 355bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_AIFS GENMASK(7, 0) 356e3037485SYan-Hsuan Chuang #define REG_PIFS 0x0512 357e3037485SYan-Hsuan Chuang #define REG_SIFS 0x0514 358e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_CTX 8 359e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_CCK_TRX 16 360e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_TRX 24 36175e69fb1SPing-Ke Shih #define REG_AGGR_BREAK_TIME 0x051A 362e3037485SYan-Hsuan Chuang #define REG_SLOT 0x051B 363e3037485SYan-Hsuan Chuang #define REG_TX_PTCL_CTRL 0x0520 3647285eb96SZong-Zhe Yang #define BIT_DIS_EDCCA BIT(15) 365e3037485SYan-Hsuan Chuang #define BIT_SIFS_BK_EN BIT(12) 366e3037485SYan-Hsuan Chuang #define REG_TXPAUSE 0x0522 367056b239fSGuo-Feng Fan #define BIT_AC_QUEUE GENMASK(7, 0) 368e3037485SYan-Hsuan Chuang #define REG_RD_CTRL 0x0524 3697285eb96SZong-Zhe Yang #define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) 370e3037485SYan-Hsuan Chuang #define BIT_DIS_TXOP_CFE BIT(10) 371e3037485SYan-Hsuan Chuang #define BIT_DIS_LSIG_CFE BIT(9) 372e3037485SYan-Hsuan Chuang #define BIT_DIS_STBC_CFE BIT(8) 373e3037485SYan-Hsuan Chuang #define REG_TBTT_PROHIBIT 0x0540 374e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 375e3037485SYan-Hsuan Chuang #define REG_RD_NAV_NXT 0x0544 37675e69fb1SPing-Ke Shih #define REG_NAV_PROT_LEN 0x0546 377e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL 0x0550 378e3037485SYan-Hsuan Chuang #define BIT_DIS_TSF_UDT BIT(4) 379e3037485SYan-Hsuan Chuang #define BIT_EN_BCN_FUNCTION BIT(3) 38075e69fb1SPing-Ke Shih #define BIT_EN_TXBCN_RPT BIT(2) 381e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL_CLINT0 0x0551 382e3037485SYan-Hsuan Chuang #define REG_DRVERLYINT 0x0558 383e3037485SYan-Hsuan Chuang #define REG_BCNDMATIM 0x0559 38475e69fb1SPing-Ke Shih #define REG_ATIMWND 0x055A 385e3037485SYan-Hsuan Chuang #define REG_USTIME_TSF 0x055C 386e3037485SYan-Hsuan Chuang #define REG_BCN_MAX_ERR 0x055D 387e3037485SYan-Hsuan Chuang #define REG_RXTSF_OFFSET_CCK 0x055E 388e3037485SYan-Hsuan Chuang #define REG_MISC_CTRL 0x0577 389e3037485SYan-Hsuan Chuang #define BIT_EN_FREE_CNT BIT(3) 390e3037485SYan-Hsuan Chuang #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1)) 39175e69fb1SPing-Ke Shih #define REG_HIQ_NO_LMT_EN 0x5A7 39275e69fb1SPing-Ke Shih #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) 393e3037485SYan-Hsuan Chuang #define REG_TIMER0_SRC_SEL 0x05B4 394e3037485SYan-Hsuan Chuang #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6)) 395e3037485SYan-Hsuan Chuang 396e3037485SYan-Hsuan Chuang #define REG_TCR 0x0604 3973a2dd6b7SChin-Yen Lee #define BIT_PWRMGT_HWDATA_EN BIT(7) 398e3037485SYan-Hsuan Chuang #define REG_RCR 0x0608 399e3037485SYan-Hsuan Chuang #define BIT_APP_FCS BIT(31) 400e3037485SYan-Hsuan Chuang #define BIT_APP_MIC BIT(30) 401e3037485SYan-Hsuan Chuang #define BIT_APP_ICV BIT(29) 402e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 403e3037485SYan-Hsuan Chuang #define BIT_APP_BASSN BIT(27) 404e3037485SYan-Hsuan Chuang #define BIT_VHT_DACK BIT(26) 405e3037485SYan-Hsuan Chuang #define BIT_TCPOFLD_EN BIT(25) 406e3037485SYan-Hsuan Chuang #define BIT_ENMBID BIT(24) 407e3037485SYan-Hsuan Chuang #define BIT_LSIGEN BIT(23) 408e3037485SYan-Hsuan Chuang #define BIT_MFBEN BIT(22) 409e3037485SYan-Hsuan Chuang #define BIT_DISCHKPPDLLEN BIT(21) 410e3037485SYan-Hsuan Chuang #define BIT_PKTCTL_DLEN BIT(20) 411*c5a8e907SZong-Zhe Yang #define BIT_DISGCLK BIT(19) 412e3037485SYan-Hsuan Chuang #define BIT_TIM_PARSER_EN BIT(18) 413e3037485SYan-Hsuan Chuang #define BIT_BC_MD_EN BIT(17) 414e3037485SYan-Hsuan Chuang #define BIT_UC_MD_EN BIT(16) 415e3037485SYan-Hsuan Chuang #define BIT_RXSK_PERPKT BIT(15) 416e3037485SYan-Hsuan Chuang #define BIT_HTC_LOC_CTRL BIT(14) 417e3037485SYan-Hsuan Chuang #define BIT_RPFM_CAM_ENABLE BIT(12) 418e3037485SYan-Hsuan Chuang #define BIT_TA_BCN BIT(11) 41975e69fb1SPing-Ke Shih #define BIT_RCR_ADF BIT(11) 420e3037485SYan-Hsuan Chuang #define BIT_DISDECMYPKT BIT(10) 421e3037485SYan-Hsuan Chuang #define BIT_AICV BIT(9) 422e3037485SYan-Hsuan Chuang #define BIT_ACRC32 BIT(8) 423e3037485SYan-Hsuan Chuang #define BIT_CBSSID_BCN BIT(7) 424e3037485SYan-Hsuan Chuang #define BIT_CBSSID_DATA BIT(6) 425e3037485SYan-Hsuan Chuang #define BIT_APWRMGT BIT(5) 426e3037485SYan-Hsuan Chuang #define BIT_ADD3 BIT(4) 427e3037485SYan-Hsuan Chuang #define BIT_AB BIT(3) 428e3037485SYan-Hsuan Chuang #define BIT_AM BIT(2) 429e3037485SYan-Hsuan Chuang #define BIT_APM BIT(1) 430e3037485SYan-Hsuan Chuang #define BIT_AAP BIT(0) 431e3037485SYan-Hsuan Chuang #define REG_RX_PKT_LIMIT 0x060C 432e3037485SYan-Hsuan Chuang #define REG_RX_DRVINFO_SZ 0x060F 433e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 43427c65bfcSTzu-En Huang #define REG_MAR 0x0620 435e3037485SYan-Hsuan Chuang #define REG_USTIME_EDCA 0x0638 436e3037485SYan-Hsuan Chuang #define REG_ACKTO_CCK 0x0639 43775e69fb1SPing-Ke Shih #define REG_MAC_SPEC_SIFS 0x063A 438e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_CCK 0x063C 439e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_OFDM 0x063E 440e3037485SYan-Hsuan Chuang #define REG_ACKTO 0x0640 441e3037485SYan-Hsuan Chuang #define REG_EIFS 0x0642 442e3037485SYan-Hsuan Chuang #define REG_NAV_CTRL 0x0650 443e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL 0x0668 444e3037485SYan-Hsuan Chuang #define BIT_RFMOD (BIT(7) | BIT(8)) 445e3037485SYan-Hsuan Chuang #define BIT_RFMOD_80M BIT(8) 446e3037485SYan-Hsuan Chuang #define BIT_RFMOD_40M BIT(7) 447e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL_H 0x066C 448e3e400dfSChin-Yen Lee #define REG_WKFMCAM_CMD 0x0698 449e3e400dfSChin-Yen Lee #define BIT_WKFCAM_POLLING_V1 BIT(31) 450e3e400dfSChin-Yen Lee #define BIT_WKFCAM_CLR_V1 BIT(30) 451e3e400dfSChin-Yen Lee #define BIT_WKFCAM_WE BIT(16) 452e3e400dfSChin-Yen Lee #define BIT_SHIFT_WKFCAM_ADDR_V2 8 453e3e400dfSChin-Yen Lee #define BIT_MASK_WKFCAM_ADDR_V2 0xff 454e3e400dfSChin-Yen Lee #define BIT_WKFCAM_ADDR_V2(x) \ 455e3e400dfSChin-Yen Lee (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) 456e3e400dfSChin-Yen Lee #define REG_WKFMCAM_RWD 0x069C 457e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_VALID BIT(31) 458e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_BC BIT(26) 459e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_MC BIT(25) 460e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_UC BIT(24) 461e3e400dfSChin-Yen Lee 462e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP0 0x06A0 463e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP1 0x06A2 464e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP2 0x06A4 4650bd95573STzu-En Huang #define REG_RXFLTMAP4 0x068A 4664136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE0 0x06C0 4674136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE1 0x06C4 4684136214fSYan-Hsuan Chuang #define REG_BT_COEX_BRK_TABLE 0x06C8 4694136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H 0x06CC 4704136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H1 0x06CD 4714136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H2 0x06CE 4724136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H3 0x06CF 473e3037485SYan-Hsuan Chuang #define REG_BBPSF_CTRL 0x06DC 474e3037485SYan-Hsuan Chuang 4753f3fef5fSChing-Te Ku #define REG_BT_COEX_V2 0x0762 4763f3fef5fSChing-Te Ku #define BIT_GNT_BT_POLARITY BIT(12) 4774136214fSYan-Hsuan Chuang #define BIT_LTE_COEX_EN BIT(7) 4781d82c497SChing-Te Ku #define REG_BT_COEX_ENH_INTR_CTRL 0x76E 4791d82c497SChing-Te Ku #define BIT_R_GRANTALL_WLMASK BIT(3) 4801d82c497SChing-Te Ku #define BIT_STATIS_BT_EN BIT(2) 4811d82c497SChing-Te Ku #define REG_BT_ACT_STATISTICS 0x0770 4821d82c497SChing-Te Ku #define REG_BT_ACT_STATISTICS_1 0x0774 4834136214fSYan-Hsuan Chuang #define REG_BT_STAT_CTRL 0x0778 4844136214fSYan-Hsuan Chuang #define REG_BT_TDMA_TIME 0x0790 4853f3fef5fSChing-Te Ku #define BIT_MASK_SAMPLE_RATE GENMASK(5, 0) 48675e69fb1SPing-Ke Shih #define REG_LTR_IDLE_LATENCY 0x0798 48775e69fb1SPing-Ke Shih #define REG_LTR_ACTIVE_LATENCY 0x079C 48875e69fb1SPing-Ke Shih #define REG_LTR_CTRL_BASIC 0x07A4 489e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION 0x07D0 490e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION_1 0x07D4 491e3037485SYan-Hsuan Chuang 49275e69fb1SPing-Ke Shih #define REG_FPGA0_RFMOD 0x0800 49375e69fb1SPing-Ke Shih #define BIT_CCKEN BIT(24) 49475e69fb1SPing-Ke Shih #define BIT_OFDMEN BIT(25) 4954136214fSYan-Hsuan Chuang #define REG_RX_GAIN_EN 0x081c 4964136214fSYan-Hsuan Chuang 4974136214fSYan-Hsuan Chuang #define REG_RFE_CTRL_E 0x0974 49875e69fb1SPing-Ke Shih #define REG_2ND_CCA_CTRL 0x0976 4994136214fSYan-Hsuan Chuang 500769a29ceSTzu-En Huang #define REG_CCK0_FAREPORT 0xa2c 501760bb2abSPing-Ke Shih #define BIT_CCK0_2RX BIT(18) 502760bb2abSPing-Ke Shih #define BIT_CCK0_MRC BIT(22) 503769a29ceSTzu-En Huang 5045227c2eeSTzu-En Huang #define REG_DIS_DPD 0x0a70 5055227c2eeSTzu-En Huang #define DIS_DPD_MASK GENMASK(9, 0) 5065227c2eeSTzu-En Huang #define DIS_DPD_RATE6M BIT(0) 5075227c2eeSTzu-En Huang #define DIS_DPD_RATE9M BIT(1) 5085227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS0 BIT(2) 5095227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS1 BIT(3) 5105227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS8 BIT(4) 5115227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS9 BIT(5) 5125227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT1SS_MCS0 BIT(6) 5135227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT1SS_MCS1 BIT(7) 5145227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT2SS_MCS0 BIT(8) 5155227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9) 5165227c2eeSTzu-En Huang #define DIS_DPD_RATEALL GENMASK(9, 0) 5175227c2eeSTzu-En Huang 5184136214fSYan-Hsuan Chuang #define REG_RFE_CTRL8 0x0cb4 5194136214fSYan-Hsuan Chuang #define BIT_MASK_RFE_SEL89 GENMASK(7, 0) 5204136214fSYan-Hsuan Chuang #define REG_RFE_INV8 0x0cbd 5214136214fSYan-Hsuan Chuang #define BIT_MASK_RFE_INV89 GENMASK(1, 0) 5224136214fSYan-Hsuan Chuang #define REG_RFE_INV16 0x0cbe 5234136214fSYan-Hsuan Chuang #define BIT_RFE_BUF_EN BIT(3) 5244136214fSYan-Hsuan Chuang 525e3037485SYan-Hsuan Chuang #define REG_ANAPAR_XTAL_0 0x1040 526fb8517f4SPo-Hao Huang #define BIT_XCAP_0 GENMASK(23, 10) 527e3037485SYan-Hsuan Chuang #define REG_CPU_DMEM_CON 0x1080 528e3037485SYan-Hsuan Chuang #define BIT_WL_PLATFORM_RST BIT(16) 529e3037485SYan-Hsuan Chuang #define BIT_WL_SECURITY_CLK BIT(15) 530e3037485SYan-Hsuan Chuang #define BIT_DDMA_EN BIT(8) 531e3037485SYan-Hsuan Chuang 532e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_READADDR 0x10D0 533e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_WRITEADDR 0x10D4 534e3037485SYan-Hsuan Chuang #define REG_FW_DBG7 0x10FC 535e3037485SYan-Hsuan Chuang #define FW_KEY_MASK 0xffffff00 536e3037485SYan-Hsuan Chuang 537e3037485SYan-Hsuan Chuang #define REG_CR_EXT 0x1100 538e3037485SYan-Hsuan Chuang 539e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0SA 0x1200 540e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0DA 0x1204 541e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0CTRL 0x1208 542e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_OWN BIT(31) 543e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_EN BIT(29) 544e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_STS BIT(27) 54513ce240aSZong-Zhe Yang #define BIT_DDMACH0_DDMA_MODE BIT(26) 546e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) 547e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_CONT BIT(24) 548e3037485SYan-Hsuan Chuang #define BIT_MASK_DDMACH0_DLEN 0x3ffff 549e3037485SYan-Hsuan Chuang 550e3037485SYan-Hsuan Chuang #define REG_H2CQ_CSR 0x1330 551e3037485SYan-Hsuan Chuang #define BIT_H2CQ_FULL BIT(31) 552e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_VOVI_SETTING 0x1448 553e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_BEBK_SETTING 0x144C 554e3037485SYan-Hsuan Chuang 555e3037485SYan-Hsuan Chuang #define REG_RXPSF_CTRL 0x1610 556e3037485SYan-Hsuan Chuang #define BIT_RXGCK_FIFOTHR_EN BIT(28) 557e3037485SYan-Hsuan Chuang 558e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 559e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 560e3037485SYan-Hsuan Chuang #define BIT_RXGCK_VHT_FIFOTHR(x) \ 561e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 562e3037485SYan-Hsuan Chuang #define BITS_RXGCK_VHT_FIFOTHR \ 563e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 564e3037485SYan-Hsuan Chuang 565e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 566e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 567e3037485SYan-Hsuan Chuang #define BIT_RXGCK_HT_FIFOTHR(x) \ 568e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) 569e3037485SYan-Hsuan Chuang #define BITS_RXGCK_HT_FIFOTHR \ 570e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) 571e3037485SYan-Hsuan Chuang 572e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 573e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 574e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDM_FIFOTHR(x) \ 575e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 576e3037485SYan-Hsuan Chuang #define BITS_RXGCK_OFDM_FIFOTHR \ 577e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 578e3037485SYan-Hsuan Chuang 579e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 580e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 581e3037485SYan-Hsuan Chuang #define BIT_RXGCK_CCK_FIFOTHR(x) \ 582e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 583e3037485SYan-Hsuan Chuang #define BITS_RXGCK_CCK_FIFOTHR \ 584e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 585e3037485SYan-Hsuan Chuang 586e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDMCCA_EN BIT(16) 587e3037485SYan-Hsuan Chuang 588e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_PKTLENTHR 13 589e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_PKTLENTHR 0x7 590e3037485SYan-Hsuan Chuang #define BIT_RXPSF_PKTLENTHR(x) \ 591e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) 592e3037485SYan-Hsuan Chuang #define BITS_RXPSF_PKTLENTHR \ 593e3037485SYan-Hsuan Chuang (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) 594e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) 595e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_PKTLENTHR(x, v) \ 596e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) 597e3037485SYan-Hsuan Chuang 598e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CTRLEN BIT(12) 599e3037485SYan-Hsuan Chuang #define BIT_RXPSF_VHTCHKEN BIT(11) 600e3037485SYan-Hsuan Chuang #define BIT_RXPSF_HTCHKEN BIT(10) 601e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMCHKEN BIT(9) 602e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKCHKEN BIT(8) 603e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMRST BIT(7) 604e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKRST BIT(6) 605e3037485SYan-Hsuan Chuang #define BIT_RXPSF_MHCHKEN BIT(5) 606e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) 607e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) 608e3037485SYan-Hsuan Chuang 609e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_ERRTHR 0 610e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_ERRTHR 0x7 611e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ERRTHR(x) \ 612e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) 613e3037485SYan-Hsuan Chuang #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) 614e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) 615e3037485SYan-Hsuan Chuang #define BIT_GET_RXPSF_ERRTHR(x) \ 616e3037485SYan-Hsuan Chuang (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) 617e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_ERRTHR(x, v) \ 618e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) 619e3037485SYan-Hsuan Chuang 620e3037485SYan-Hsuan Chuang #define REG_RXPSF_TYPE_CTRL 0x1614 621e3037485SYan-Hsuan Chuang #define REG_GENERAL_OPTION 0x1664 622e3037485SYan-Hsuan Chuang #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) 623e3037485SYan-Hsuan Chuang 624e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 625e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 626e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 627e3037485SYan-Hsuan Chuang #define LTECOEX_READY BIT(29) 628e3037485SYan-Hsuan Chuang #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 629e3037485SYan-Hsuan Chuang #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 630e3037485SYan-Hsuan Chuang #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 631e3037485SYan-Hsuan Chuang 6324136214fSYan-Hsuan Chuang #define REG_IGN_GNT_BT1 0x1860 6334136214fSYan-Hsuan Chuang 6344136214fSYan-Hsuan Chuang #define REG_RFESEL_CTRL 0x1990 6354136214fSYan-Hsuan Chuang 6364136214fSYan-Hsuan Chuang #define REG_NOMASK_TXBT 0x1ca7 6374136214fSYan-Hsuan Chuang #define REG_ANAPAR 0x1c30 6384136214fSYan-Hsuan Chuang #define BIT_ANAPAR_BTPS BIT(22) 6394136214fSYan-Hsuan Chuang #define REG_RSTB_SEL 0x1c38 6401d82c497SChing-Te Ku #define BIT_DAC_OFF_ENABLE BIT(4) 6411d82c497SChing-Te Ku #define BIT_PI_IGNORE_GNT_BT BIT(3) 6421d82c497SChing-Te Ku #define BIT_NOMASK_TXBT_ENABLE BIT(3) 6434136214fSYan-Hsuan Chuang 644714f71f9STzu-En Huang #define REG_HRCV_MSG 0x1cf 645714f71f9STzu-En Huang 646fe7bc23aSChin-Yen Lee #define REG_EDCCA_REPORT 0x2d38 647fe7bc23aSChin-Yen Lee #define BIT_EDCCA_FLAG BIT(24) 648fe7bc23aSChin-Yen Lee 6494136214fSYan-Hsuan Chuang #define REG_IGN_GNTBT4 0x4160 6504136214fSYan-Hsuan Chuang 6511d229e88SPing-Ke Shih #define RF_MODE 0x00 6524136214fSYan-Hsuan Chuang #define RF_MODOPT 0x01 6531d229e88SPing-Ke Shih #define RF_WLINT 0x01 6541d229e88SPing-Ke Shih #define RF_WLSEL 0x02 655e3037485SYan-Hsuan Chuang #define RF_DTXLOK 0x08 656e3037485SYan-Hsuan Chuang #define RF_CFGCH 0x18 657056b239fSGuo-Feng Fan #define BIT_BAND GENMASK(18, 16) 6584136214fSYan-Hsuan Chuang #define RF_RCK 0x1d 659e3037485SYan-Hsuan Chuang #define RF_LUTWA 0x33 660e3037485SYan-Hsuan Chuang #define RF_LUTWD1 0x3e 661e3037485SYan-Hsuan Chuang #define RF_LUTWD0 0x3f 662056b239fSGuo-Feng Fan #define BIT_GAIN_EXT BIT(12) 663056b239fSGuo-Feng Fan #define BIT_DATA_L GENMASK(11, 0) 6645227c2eeSTzu-En Huang #define RF_T_METER 0x42 6651d229e88SPing-Ke Shih #define RF_BSPAD 0x54 6661d229e88SPing-Ke Shih #define RF_GAINTX 0x56 6671d229e88SPing-Ke Shih #define RF_TXATANK 0x64 6681d229e88SPing-Ke Shih #define RF_TRXIQ 0x66 6691d229e88SPing-Ke Shih #define RF_RXIQGEN 0x8d 6707ae7784eSPo-Hao Huang #define RF_SYN_PFD 0xb0 671e3037485SYan-Hsuan Chuang #define RF_XTALX2 0xb8 6727ae7784eSPo-Hao Huang #define RF_SYN_CTRL 0xbb 673e3037485SYan-Hsuan Chuang #define RF_MALSEL 0xbe 6747ae7784eSPo-Hao Huang #define RF_SYN_AAC 0xc9 6757ae7784eSPo-Hao Huang #define RF_AAC_CTRL 0xca 6767ae7784eSPo-Hao Huang #define RF_FAST_LCK 0xcc 6774136214fSYan-Hsuan Chuang #define RF_RCKD 0xde 6781d229e88SPing-Ke Shih #define RF_TXADBG 0xde 679e3037485SYan-Hsuan Chuang #define RF_LUTDBG 0xdf 680056b239fSGuo-Feng Fan #define BIT_TXA_TANK BIT(4) 681e3037485SYan-Hsuan Chuang #define RF_LUTWE2 0xee 682e3037485SYan-Hsuan Chuang #define RF_LUTWE 0xef 683e3037485SYan-Hsuan Chuang 6844136214fSYan-Hsuan Chuang #define LTE_COEX_CTRL 0x38 6854136214fSYan-Hsuan Chuang #define LTE_WL_TRX_CTRL 0xa0 6864136214fSYan-Hsuan Chuang #define LTE_BT_TRX_CTRL 0xa4 6874136214fSYan-Hsuan Chuang 688e3037485SYan-Hsuan Chuang #endif 689