1e3037485SYan-Hsuan Chuang /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2e3037485SYan-Hsuan Chuang /* Copyright(c) 2018-2019 Realtek Corporation 3e3037485SYan-Hsuan Chuang */ 4e3037485SYan-Hsuan Chuang 5e3037485SYan-Hsuan Chuang #ifndef __RTW_REG_DEF_H__ 6e3037485SYan-Hsuan Chuang #define __RTW_REG_DEF_H__ 7e3037485SYan-Hsuan Chuang 8e3037485SYan-Hsuan Chuang #define REG_SYS_FUNC_EN 0x0002 9e3037485SYan-Hsuan Chuang #define BIT_FEN_CPUEN BIT(2) 10e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_GLB_RST BIT(1) 11e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_RSTB BIT(0) 12e3037485SYan-Hsuan Chuang #define REG_SYS_PW_CTRL 0x0004 13e3037485SYan-Hsuan Chuang #define REG_SYS_CLK_CTRL 0x0008 14e3037485SYan-Hsuan Chuang #define BIT_CPU_CLK_EN BIT(14) 15e3037485SYan-Hsuan Chuang 16e3037485SYan-Hsuan Chuang #define REG_RSV_CTRL 0x001C 17e3037485SYan-Hsuan Chuang #define DISABLE_PI 0x3 18e3037485SYan-Hsuan Chuang #define ENABLE_PI 0x2 19e3037485SYan-Hsuan Chuang #define BITS_RFC_DIRECT (BIT(31) | BIT(30)) 20e3037485SYan-Hsuan Chuang #define BIT_WLMCU_IOIF BIT(0) 21e3037485SYan-Hsuan Chuang #define REG_RF_CTRL 0x001F 22e3037485SYan-Hsuan Chuang #define BIT_RF_SDM_RSTB BIT(2) 23e3037485SYan-Hsuan Chuang #define BIT_RF_RSTB BIT(1) 24e3037485SYan-Hsuan Chuang #define BIT_RF_EN BIT(0) 25e3037485SYan-Hsuan Chuang 26e3037485SYan-Hsuan Chuang #define REG_AFE_CTRL1 0x0024 27e3037485SYan-Hsuan Chuang #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21)) 28e3037485SYan-Hsuan Chuang #define REG_EFUSE_CTRL 0x0030 29e3037485SYan-Hsuan Chuang #define BIT_EF_FLAG BIT(31) 30e3037485SYan-Hsuan Chuang #define BIT_SHIFT_EF_ADDR 8 31e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_ADDR 0x3ff 32e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_DATA 0xff 33e3037485SYan-Hsuan Chuang #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) 34e3037485SYan-Hsuan Chuang 35e3037485SYan-Hsuan Chuang #define REG_LDO_EFUSE_CTRL 0x0034 36e3037485SYan-Hsuan Chuang #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9)) 37e3037485SYan-Hsuan Chuang 38e3037485SYan-Hsuan Chuang #define REG_GPIO_MUXCFG 0x0040 39e3037485SYan-Hsuan Chuang #define BIT_FSPI_EN BIT(19) 404136214fSYan-Hsuan Chuang #define BIT_BT_AOD_GPIO3 BIT(9) 414136214fSYan-Hsuan Chuang #define BIT_BT_PTA_EN BIT(5) 42e3037485SYan-Hsuan Chuang #define BIT_WLRFE_4_5_EN BIT(2) 43e3037485SYan-Hsuan Chuang 44e3037485SYan-Hsuan Chuang #define REG_LED_CFG 0x004C 45e3037485SYan-Hsuan Chuang #define BIT_LNAON_SEL_EN BIT(26) 46e3037485SYan-Hsuan Chuang #define BIT_PAPE_SEL_EN BIT(25) 474136214fSYan-Hsuan Chuang #define BIT_DPDT_WL_SEL BIT(24) 484136214fSYan-Hsuan Chuang #define BIT_DPDT_SEL_EN BIT(23) 49e3037485SYan-Hsuan Chuang #define REG_PAD_CTRL1 0x0064 50e3037485SYan-Hsuan Chuang #define BIT_PAPE_WLBT_SEL BIT(29) 51e3037485SYan-Hsuan Chuang #define BIT_LNAON_WLBT_SEL BIT(28) 524136214fSYan-Hsuan Chuang #define BIT_BTGP_JTAG_EN BIT(24) 534136214fSYan-Hsuan Chuang #define BIT_BTGP_SPI_EN BIT(20) 544136214fSYan-Hsuan Chuang #define BIT_LED1DIS BIT(15) 554136214fSYan-Hsuan Chuang #define BIT_SW_DPDT_SEL_DATA BIT(0) 56e3037485SYan-Hsuan Chuang #define REG_WL_BT_PWR_CTRL 0x0068 57e3037485SYan-Hsuan Chuang #define BIT_BT_FUNC_EN BIT(18) 58e3037485SYan-Hsuan Chuang #define BIT_BT_DIG_CLK_EN BIT(8) 594136214fSYan-Hsuan Chuang #define REG_SYS_SDIO_CTRL 0x0070 604136214fSYan-Hsuan Chuang #define BIT_DBG_GNT_WL_BT BIT(27) 614136214fSYan-Hsuan Chuang #define BIT_LTE_MUX_CTRL_PATH BIT(26) 62e3037485SYan-Hsuan Chuang #define REG_HCI_OPT_CTRL 0x0074 63e3037485SYan-Hsuan Chuang 64e3037485SYan-Hsuan Chuang #define REG_MCUFW_CTRL 0x0080 65e3037485SYan-Hsuan Chuang #define BIT_ANA_PORT_EN BIT(22) 66e3037485SYan-Hsuan Chuang #define BIT_MAC_PORT_EN BIT(21) 67e3037485SYan-Hsuan Chuang #define BIT_BOOT_FSPI_EN BIT(20) 68e3037485SYan-Hsuan Chuang #define BIT_FW_INIT_RDY BIT(15) 69e3037485SYan-Hsuan Chuang #define BIT_FW_DW_RDY BIT(14) 70e3037485SYan-Hsuan Chuang #define BIT_RPWM_TOGGLE BIT(7) 71e3037485SYan-Hsuan Chuang #define BIT_DMEM_CHKSUM_OK BIT(6) 72e3037485SYan-Hsuan Chuang #define BIT_DMEM_DW_OK BIT(5) 73e3037485SYan-Hsuan Chuang #define BIT_IMEM_CHKSUM_OK BIT(4) 74e3037485SYan-Hsuan Chuang #define BIT_IMEM_DW_OK BIT(3) 75e3037485SYan-Hsuan Chuang #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2) 76e3037485SYan-Hsuan Chuang #define BIT_MCUFWDL_EN BIT(0) 77e3037485SYan-Hsuan Chuang #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6)) 78e3037485SYan-Hsuan Chuang #define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \ 79e3037485SYan-Hsuan Chuang BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \ 80e3037485SYan-Hsuan Chuang BIT_CHECK_SUM_OK) 81e3037485SYan-Hsuan Chuang #define FW_READY_MASK 0xffff 82e3037485SYan-Hsuan Chuang 83e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 844136214fSYan-Hsuan Chuang #define REG_WIFI_BT_INFO 0x00AA 854136214fSYan-Hsuan Chuang #define BIT_BT_INT_EN BIT(15) 86e3037485SYan-Hsuan Chuang #define REG_SYS_CFG1 0x00F0 87e3037485SYan-Hsuan Chuang #define BIT_RTL_ID BIT(23) 88e3037485SYan-Hsuan Chuang #define BIT_RF_TYPE_ID BIT(27) 89e3037485SYan-Hsuan Chuang #define BIT_SHIFT_VENDOR_ID 16 90e3037485SYan-Hsuan Chuang #define BIT_MASK_VENDOR_ID 0xf 91e3037485SYan-Hsuan Chuang #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) 92e3037485SYan-Hsuan Chuang #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) 93e3037485SYan-Hsuan Chuang #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) 94e3037485SYan-Hsuan Chuang #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) 95e3037485SYan-Hsuan Chuang #define BIT_SHIFT_CHIP_VER 12 96e3037485SYan-Hsuan Chuang #define BIT_MASK_CHIP_VER 0xf 97e3037485SYan-Hsuan Chuang #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) 98e3037485SYan-Hsuan Chuang #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) 99e3037485SYan-Hsuan Chuang #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) 100e3037485SYan-Hsuan Chuang #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) 101e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS1 0x00F4 102e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS2 0x00F8 103e3037485SYan-Hsuan Chuang #define REG_SYS_CFG2 0x00FC 104e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 105e3037485SYan-Hsuan Chuang #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26)) 106e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 107e3037485SYan-Hsuan Chuang #define BIT_32K_CAL_TMR_EN BIT(10) 108e3037485SYan-Hsuan Chuang #define BIT_MAC_SEC_EN BIT(9) 109e3037485SYan-Hsuan Chuang #define BIT_ENSWBCN BIT(8) 110e3037485SYan-Hsuan Chuang #define BIT_MACRXEN BIT(7) 111e3037485SYan-Hsuan Chuang #define BIT_MACTXEN BIT(6) 112e3037485SYan-Hsuan Chuang #define BIT_SCHEDULE_EN BIT(5) 113e3037485SYan-Hsuan Chuang #define BIT_PROTOCOL_EN BIT(4) 114e3037485SYan-Hsuan Chuang #define BIT_RXDMA_EN BIT(3) 115e3037485SYan-Hsuan Chuang #define BIT_TXDMA_EN BIT(2) 116e3037485SYan-Hsuan Chuang #define BIT_HCI_RXDMA_EN BIT(1) 117e3037485SYan-Hsuan Chuang #define BIT_HCI_TXDMA_EN BIT(0) 118e3037485SYan-Hsuan Chuang #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ 119e3037485SYan-Hsuan Chuang BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ 120e3037485SYan-Hsuan Chuang BIT_MACTXEN | BIT_MACRXEN) 121e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VOQ_MAP 4 122e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VOQ_MAP 0x3 123e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VOQ_MAP(x) \ 124e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 125e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VIQ_MAP 6 126e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VIQ_MAP 0x3 127e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VIQ_MAP(x) \ 128e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 129e3037485SYan-Hsuan Chuang #define REG_TXDMA_PQ_MAP 0x010C 130e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BEQ_MAP 8 131e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BEQ_MAP 0x3 132e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BEQ_MAP(x) \ 133e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 134e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BKQ_MAP 10 135e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BKQ_MAP 0x3 136e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BKQ_MAP(x) \ 137e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) 138e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_MGQ_MAP 12 139e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_MGQ_MAP 0x3 140e3037485SYan-Hsuan Chuang #define BIT_TXDMA_MGQ_MAP(x) \ 141e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) 142e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_HIQ_MAP 14 143e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_HIQ_MAP 0x3 144e3037485SYan-Hsuan Chuang #define BIT_TXDMA_HIQ_MAP(x) \ 145e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) 146e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_40M 4 147e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_40M 0xf 148e3037485SYan-Hsuan Chuang #define BIT_TXSC_40M(x) \ 149e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) 150e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_20M 0 151e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_20M 0xf 152e3037485SYan-Hsuan Chuang #define BIT_TXSC_20M(x) \ 153e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) 154e3037485SYan-Hsuan Chuang #define BIT_SHIFT_MAC_CLK_SEL 20 155e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_80M 0 156e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_40M 1 157e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_20M 2 158e3037485SYan-Hsuan Chuang #define MAC_CLK_SPEED 80 159e3037485SYan-Hsuan Chuang 160e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 161e3037485SYan-Hsuan Chuang #define REG_TRXFF_BNDY 0x0114 162e3037485SYan-Hsuan Chuang #define REG_RXFF_BNDY 0x011C 163e3037485SYan-Hsuan Chuang #define REG_PKTBUF_DBG_CTRL 0x0140 164e3037485SYan-Hsuan Chuang #define REG_C2HEVT 0x01A0 165e3037485SYan-Hsuan Chuang #define REG_HMETFR 0x01CC 166e3037485SYan-Hsuan Chuang #define REG_HMEBOX0 0x01D0 167e3037485SYan-Hsuan Chuang #define REG_HMEBOX1 0x01D4 168e3037485SYan-Hsuan Chuang #define REG_HMEBOX2 0x01D8 169e3037485SYan-Hsuan Chuang #define REG_HMEBOX3 0x01DC 170e3037485SYan-Hsuan Chuang #define REG_HMEBOX0_EX 0x01F0 171e3037485SYan-Hsuan Chuang #define REG_HMEBOX1_EX 0x01F4 172e3037485SYan-Hsuan Chuang #define REG_HMEBOX2_EX 0x01F8 173e3037485SYan-Hsuan Chuang #define REG_HMEBOX3_EX 0x01FC 174e3037485SYan-Hsuan Chuang 175e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_CTRL_2 0x0204 176e3037485SYan-Hsuan Chuang #define BIT_BCN_VALID_V1 BIT(15) 177e3037485SYan-Hsuan Chuang #define BIT_MASK_BCN_HEAD_1_V1 0xfff 178e3037485SYan-Hsuan Chuang #define REG_AUTO_LLT_V1 0x0208 179e3037485SYan-Hsuan Chuang #define BIT_AUTO_INIT_LLT_V1 BIT(0) 180e3037485SYan-Hsuan Chuang #define REG_TXDMA_OFFSET_CHK 0x020C 181e3037485SYan-Hsuan Chuang #define REG_TXDMA_STATUS 0x0210 182e3037485SYan-Hsuan Chuang #define BTI_PAGE_OVF BIT(2) 183e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_1 0x0228 184e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_2 0x022C 185e3037485SYan-Hsuan Chuang #define BIT_LD_RQPN BIT(31) 186e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_1 0x0230 187e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_2 0x0234 188e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_3 0x0238 189e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_4 0x023C 190e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_5 0x0240 191e3037485SYan-Hsuan Chuang #define REG_H2C_HEAD 0x0244 192e3037485SYan-Hsuan Chuang #define REG_H2C_TAIL 0x0248 193e3037485SYan-Hsuan Chuang #define REG_H2C_READ_ADDR 0x024C 194e3037485SYan-Hsuan Chuang #define REG_H2C_INFO 0x0254 195e3037485SYan-Hsuan Chuang 196bc61ae96STsang-Shian Lin #define REG_INT_MIG 0x0304 197bc61ae96STsang-Shian Lin 198e3037485SYan-Hsuan Chuang #define REG_FWHW_TXQ_CTRL 0x0420 199e3037485SYan-Hsuan Chuang #define BIT_EN_BCNQ_DL BIT(22) 200e3037485SYan-Hsuan Chuang #define BIT_EN_WR_FREE_TAIL BIT(20) 201e3037485SYan-Hsuan Chuang #define REG_BCNQ_BDNY_V1 0x0424 202e3037485SYan-Hsuan Chuang #define REG_LIFETIME_EN 0x0426 203e3037485SYan-Hsuan Chuang #define BIT_BA_PARSER_EN BIT(5) 204e3037485SYan-Hsuan Chuang #define REG_SPEC_SIFS 0x0428 2054136214fSYan-Hsuan Chuang #define REG_RETRY_LIMIT 0x042a 206e3037485SYan-Hsuan Chuang #define REG_DARFRC 0x0430 207e3037485SYan-Hsuan Chuang #define REG_DARFRCH 0x0434 208e3037485SYan-Hsuan Chuang #define REG_RARFRCH 0x043C 209e3037485SYan-Hsuan Chuang #define REG_ARFR0 0x0444 210e3037485SYan-Hsuan Chuang #define REG_ARFRH0 0x0448 211e3037485SYan-Hsuan Chuang #define REG_ARFR1_V1 0x044C 212e3037485SYan-Hsuan Chuang #define REG_ARFRH1_V1 0x0450 213e3037485SYan-Hsuan Chuang #define REG_CCK_CHECK 0x0454 214e3037485SYan-Hsuan Chuang #define BIT_CHECK_CCK_EN BIT(7) 215e3037485SYan-Hsuan Chuang #define REG_AMPDU_MAX_TIME_V1 0x0455 216e3037485SYan-Hsuan Chuang #define REG_BCNQ1_BDNY_V1 0x0456 217e3037485SYan-Hsuan Chuang #define REG_TX_HANG_CTRL 0x045E 2184136214fSYan-Hsuan Chuang #define BIT_EN_GNT_BT_AWAKE BIT(3) 219e3037485SYan-Hsuan Chuang #define BIT_EN_EOF_V1 BIT(2) 220e3037485SYan-Hsuan Chuang #define REG_DATA_SC 0x0483 221e3037485SYan-Hsuan Chuang #define REG_ARFR4 0x049C 2224136214fSYan-Hsuan Chuang #define BIT_WL_RFK BIT(0) 223e3037485SYan-Hsuan Chuang #define REG_ARFRH4 0x04A0 224e3037485SYan-Hsuan Chuang #define REG_ARFR5 0x04A4 225e3037485SYan-Hsuan Chuang #define REG_ARFRH5 0x04A8 226e3037485SYan-Hsuan Chuang #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC 227e3037485SYan-Hsuan Chuang #define BIT_PRE_TX_CMD BIT(6) 2284136214fSYan-Hsuan Chuang #define REG_QUEUE_CTRL 0x04C6 2294136214fSYan-Hsuan Chuang #define BIT_PTA_WL_TX_EN BIT(4) 2304136214fSYan-Hsuan Chuang #define BIT_PTA_EDCCA_EN BIT(5) 231e3037485SYan-Hsuan Chuang #define REG_PROT_MODE_CTRL 0x04C8 232e3037485SYan-Hsuan Chuang #define REG_BAR_MODE_CTRL 0x04CC 233e3037485SYan-Hsuan Chuang #define REG_PRECNT_CTRL 0x04E5 2344136214fSYan-Hsuan Chuang #define BIT_BTCCA_CTRL (BIT(0) | BIT(1)) 235e3037485SYan-Hsuan Chuang #define BIT_EN_PRECNT BIT(11) 2364136214fSYan-Hsuan Chuang #define REG_DUMMY_PAGE4_V1 0x04FC 237e3037485SYan-Hsuan Chuang 238e3037485SYan-Hsuan Chuang #define REG_EDCA_VO_PARAM 0x0500 239e3037485SYan-Hsuan Chuang #define REG_EDCA_VI_PARAM 0x0504 240e3037485SYan-Hsuan Chuang #define REG_EDCA_BE_PARAM 0x0508 241e3037485SYan-Hsuan Chuang #define REG_EDCA_BK_PARAM 0x050C 242e3037485SYan-Hsuan Chuang #define REG_PIFS 0x0512 243e3037485SYan-Hsuan Chuang #define REG_SIFS 0x0514 244e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_CTX 8 245e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_CCK_TRX 16 246e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_TRX 24 247e3037485SYan-Hsuan Chuang #define REG_SLOT 0x051B 248e3037485SYan-Hsuan Chuang #define REG_TX_PTCL_CTRL 0x0520 249e3037485SYan-Hsuan Chuang #define BIT_SIFS_BK_EN BIT(12) 250e3037485SYan-Hsuan Chuang #define REG_TXPAUSE 0x0522 251e3037485SYan-Hsuan Chuang #define REG_RD_CTRL 0x0524 252e3037485SYan-Hsuan Chuang #define BIT_DIS_TXOP_CFE BIT(10) 253e3037485SYan-Hsuan Chuang #define BIT_DIS_LSIG_CFE BIT(9) 254e3037485SYan-Hsuan Chuang #define BIT_DIS_STBC_CFE BIT(8) 255e3037485SYan-Hsuan Chuang #define REG_TBTT_PROHIBIT 0x0540 256e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 257e3037485SYan-Hsuan Chuang #define REG_RD_NAV_NXT 0x0544 258e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL 0x0550 259e3037485SYan-Hsuan Chuang #define BIT_DIS_TSF_UDT BIT(4) 260e3037485SYan-Hsuan Chuang #define BIT_EN_BCN_FUNCTION BIT(3) 261e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL_CLINT0 0x0551 262e3037485SYan-Hsuan Chuang #define REG_DRVERLYINT 0x0558 263e3037485SYan-Hsuan Chuang #define REG_BCNDMATIM 0x0559 264e3037485SYan-Hsuan Chuang #define REG_USTIME_TSF 0x055C 265e3037485SYan-Hsuan Chuang #define REG_BCN_MAX_ERR 0x055D 266e3037485SYan-Hsuan Chuang #define REG_RXTSF_OFFSET_CCK 0x055E 267e3037485SYan-Hsuan Chuang #define REG_MISC_CTRL 0x0577 268e3037485SYan-Hsuan Chuang #define BIT_EN_FREE_CNT BIT(3) 269e3037485SYan-Hsuan Chuang #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1)) 270e3037485SYan-Hsuan Chuang #define REG_TIMER0_SRC_SEL 0x05B4 271e3037485SYan-Hsuan Chuang #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6)) 272e3037485SYan-Hsuan Chuang 273e3037485SYan-Hsuan Chuang #define REG_TCR 0x0604 274e3037485SYan-Hsuan Chuang #define REG_RCR 0x0608 275e3037485SYan-Hsuan Chuang #define BIT_APP_FCS BIT(31) 276e3037485SYan-Hsuan Chuang #define BIT_APP_MIC BIT(30) 277e3037485SYan-Hsuan Chuang #define BIT_APP_ICV BIT(29) 278e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 279e3037485SYan-Hsuan Chuang #define BIT_APP_BASSN BIT(27) 280e3037485SYan-Hsuan Chuang #define BIT_VHT_DACK BIT(26) 281e3037485SYan-Hsuan Chuang #define BIT_TCPOFLD_EN BIT(25) 282e3037485SYan-Hsuan Chuang #define BIT_ENMBID BIT(24) 283e3037485SYan-Hsuan Chuang #define BIT_LSIGEN BIT(23) 284e3037485SYan-Hsuan Chuang #define BIT_MFBEN BIT(22) 285e3037485SYan-Hsuan Chuang #define BIT_DISCHKPPDLLEN BIT(21) 286e3037485SYan-Hsuan Chuang #define BIT_PKTCTL_DLEN BIT(20) 287e3037485SYan-Hsuan Chuang #define BIT_TIM_PARSER_EN BIT(18) 288e3037485SYan-Hsuan Chuang #define BIT_BC_MD_EN BIT(17) 289e3037485SYan-Hsuan Chuang #define BIT_UC_MD_EN BIT(16) 290e3037485SYan-Hsuan Chuang #define BIT_RXSK_PERPKT BIT(15) 291e3037485SYan-Hsuan Chuang #define BIT_HTC_LOC_CTRL BIT(14) 292e3037485SYan-Hsuan Chuang #define BIT_RPFM_CAM_ENABLE BIT(12) 293e3037485SYan-Hsuan Chuang #define BIT_TA_BCN BIT(11) 294e3037485SYan-Hsuan Chuang #define BIT_DISDECMYPKT BIT(10) 295e3037485SYan-Hsuan Chuang #define BIT_AICV BIT(9) 296e3037485SYan-Hsuan Chuang #define BIT_ACRC32 BIT(8) 297e3037485SYan-Hsuan Chuang #define BIT_CBSSID_BCN BIT(7) 298e3037485SYan-Hsuan Chuang #define BIT_CBSSID_DATA BIT(6) 299e3037485SYan-Hsuan Chuang #define BIT_APWRMGT BIT(5) 300e3037485SYan-Hsuan Chuang #define BIT_ADD3 BIT(4) 301e3037485SYan-Hsuan Chuang #define BIT_AB BIT(3) 302e3037485SYan-Hsuan Chuang #define BIT_AM BIT(2) 303e3037485SYan-Hsuan Chuang #define BIT_APM BIT(1) 304e3037485SYan-Hsuan Chuang #define BIT_AAP BIT(0) 305e3037485SYan-Hsuan Chuang #define REG_RX_PKT_LIMIT 0x060C 306e3037485SYan-Hsuan Chuang #define REG_RX_DRVINFO_SZ 0x060F 307e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 308e3037485SYan-Hsuan Chuang #define REG_USTIME_EDCA 0x0638 309e3037485SYan-Hsuan Chuang #define REG_ACKTO_CCK 0x0639 310e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_CCK 0x063C 311e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_OFDM 0x063E 312e3037485SYan-Hsuan Chuang #define REG_ACKTO 0x0640 313e3037485SYan-Hsuan Chuang #define REG_EIFS 0x0642 314e3037485SYan-Hsuan Chuang #define REG_NAV_CTRL 0x0650 315e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL 0x0668 316e3037485SYan-Hsuan Chuang #define BIT_RFMOD (BIT(7) | BIT(8)) 317e3037485SYan-Hsuan Chuang #define BIT_RFMOD_80M BIT(8) 318e3037485SYan-Hsuan Chuang #define BIT_RFMOD_40M BIT(7) 319e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL_H 0x066C 320e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP0 0x06A0 321e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP1 0x06A2 322e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP2 0x06A4 3234136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE0 0x06C0 3244136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE1 0x06C4 3254136214fSYan-Hsuan Chuang #define REG_BT_COEX_BRK_TABLE 0x06C8 3264136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H 0x06CC 3274136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H1 0x06CD 3284136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H2 0x06CE 3294136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H3 0x06CF 330e3037485SYan-Hsuan Chuang #define REG_BBPSF_CTRL 0x06DC 331e3037485SYan-Hsuan Chuang 3324136214fSYan-Hsuan Chuang #define REG_BT_COEX_V2 0x0763 3334136214fSYan-Hsuan Chuang #define BIT_GNT_BT_POLARITY BIT(4) 3344136214fSYan-Hsuan Chuang #define BIT_LTE_COEX_EN BIT(7) 3354136214fSYan-Hsuan Chuang #define REG_BT_STAT_CTRL 0x0778 3364136214fSYan-Hsuan Chuang #define REG_BT_TDMA_TIME 0x0790 337e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION 0x07D0 338e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION_1 0x07D4 339e3037485SYan-Hsuan Chuang 3404136214fSYan-Hsuan Chuang #define REG_RX_GAIN_EN 0x081c 3414136214fSYan-Hsuan Chuang 3424136214fSYan-Hsuan Chuang #define REG_RFE_CTRL_E 0x0974 3434136214fSYan-Hsuan Chuang 3445227c2eeSTzu-En Huang #define REG_DIS_DPD 0x0a70 3455227c2eeSTzu-En Huang #define DIS_DPD_MASK GENMASK(9, 0) 3465227c2eeSTzu-En Huang #define DIS_DPD_RATE6M BIT(0) 3475227c2eeSTzu-En Huang #define DIS_DPD_RATE9M BIT(1) 3485227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS0 BIT(2) 3495227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS1 BIT(3) 3505227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS8 BIT(4) 3515227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS9 BIT(5) 3525227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT1SS_MCS0 BIT(6) 3535227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT1SS_MCS1 BIT(7) 3545227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT2SS_MCS0 BIT(8) 3555227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9) 3565227c2eeSTzu-En Huang #define DIS_DPD_RATEALL GENMASK(9, 0) 3575227c2eeSTzu-En Huang 3584136214fSYan-Hsuan Chuang #define REG_RFE_CTRL8 0x0cb4 3594136214fSYan-Hsuan Chuang #define BIT_MASK_RFE_SEL89 GENMASK(7, 0) 3604136214fSYan-Hsuan Chuang #define REG_RFE_INV8 0x0cbd 3614136214fSYan-Hsuan Chuang #define BIT_MASK_RFE_INV89 GENMASK(1, 0) 3624136214fSYan-Hsuan Chuang #define REG_RFE_INV16 0x0cbe 3634136214fSYan-Hsuan Chuang #define BIT_RFE_BUF_EN BIT(3) 3644136214fSYan-Hsuan Chuang 365e3037485SYan-Hsuan Chuang #define REG_ANAPAR_XTAL_0 0x1040 366e3037485SYan-Hsuan Chuang #define REG_CPU_DMEM_CON 0x1080 367e3037485SYan-Hsuan Chuang #define BIT_WL_PLATFORM_RST BIT(16) 368e3037485SYan-Hsuan Chuang #define BIT_WL_SECURITY_CLK BIT(15) 369e3037485SYan-Hsuan Chuang #define BIT_DDMA_EN BIT(8) 370e3037485SYan-Hsuan Chuang 371e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_READADDR 0x10D0 372e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_WRITEADDR 0x10D4 373e3037485SYan-Hsuan Chuang #define REG_FW_DBG7 0x10FC 374e3037485SYan-Hsuan Chuang #define FW_KEY_MASK 0xffffff00 375e3037485SYan-Hsuan Chuang 376e3037485SYan-Hsuan Chuang #define REG_CR_EXT 0x1100 377e3037485SYan-Hsuan Chuang 378e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0SA 0x1200 379e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0DA 0x1204 380e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0CTRL 0x1208 381e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_OWN BIT(31) 382e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_EN BIT(29) 383e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_STS BIT(27) 384e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) 385e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_CONT BIT(24) 386e3037485SYan-Hsuan Chuang #define BIT_MASK_DDMACH0_DLEN 0x3ffff 387e3037485SYan-Hsuan Chuang 388e3037485SYan-Hsuan Chuang #define REG_H2CQ_CSR 0x1330 389e3037485SYan-Hsuan Chuang #define BIT_H2CQ_FULL BIT(31) 390e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_VOVI_SETTING 0x1448 391e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_BEBK_SETTING 0x144C 392e3037485SYan-Hsuan Chuang 393e3037485SYan-Hsuan Chuang #define REG_RXPSF_CTRL 0x1610 394e3037485SYan-Hsuan Chuang #define BIT_RXGCK_FIFOTHR_EN BIT(28) 395e3037485SYan-Hsuan Chuang 396e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 397e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 398e3037485SYan-Hsuan Chuang #define BIT_RXGCK_VHT_FIFOTHR(x) \ 399e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 400e3037485SYan-Hsuan Chuang #define BITS_RXGCK_VHT_FIFOTHR \ 401e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 402e3037485SYan-Hsuan Chuang 403e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 404e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 405e3037485SYan-Hsuan Chuang #define BIT_RXGCK_HT_FIFOTHR(x) \ 406e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) 407e3037485SYan-Hsuan Chuang #define BITS_RXGCK_HT_FIFOTHR \ 408e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) 409e3037485SYan-Hsuan Chuang 410e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 411e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 412e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDM_FIFOTHR(x) \ 413e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 414e3037485SYan-Hsuan Chuang #define BITS_RXGCK_OFDM_FIFOTHR \ 415e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 416e3037485SYan-Hsuan Chuang 417e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 418e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 419e3037485SYan-Hsuan Chuang #define BIT_RXGCK_CCK_FIFOTHR(x) \ 420e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 421e3037485SYan-Hsuan Chuang #define BITS_RXGCK_CCK_FIFOTHR \ 422e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 423e3037485SYan-Hsuan Chuang 424e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDMCCA_EN BIT(16) 425e3037485SYan-Hsuan Chuang 426e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_PKTLENTHR 13 427e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_PKTLENTHR 0x7 428e3037485SYan-Hsuan Chuang #define BIT_RXPSF_PKTLENTHR(x) \ 429e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) 430e3037485SYan-Hsuan Chuang #define BITS_RXPSF_PKTLENTHR \ 431e3037485SYan-Hsuan Chuang (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) 432e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) 433e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_PKTLENTHR(x, v) \ 434e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) 435e3037485SYan-Hsuan Chuang 436e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CTRLEN BIT(12) 437e3037485SYan-Hsuan Chuang #define BIT_RXPSF_VHTCHKEN BIT(11) 438e3037485SYan-Hsuan Chuang #define BIT_RXPSF_HTCHKEN BIT(10) 439e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMCHKEN BIT(9) 440e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKCHKEN BIT(8) 441e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMRST BIT(7) 442e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKRST BIT(6) 443e3037485SYan-Hsuan Chuang #define BIT_RXPSF_MHCHKEN BIT(5) 444e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) 445e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) 446e3037485SYan-Hsuan Chuang 447e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_ERRTHR 0 448e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_ERRTHR 0x7 449e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ERRTHR(x) \ 450e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) 451e3037485SYan-Hsuan Chuang #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) 452e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) 453e3037485SYan-Hsuan Chuang #define BIT_GET_RXPSF_ERRTHR(x) \ 454e3037485SYan-Hsuan Chuang (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) 455e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_ERRTHR(x, v) \ 456e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) 457e3037485SYan-Hsuan Chuang 458e3037485SYan-Hsuan Chuang #define REG_RXPSF_TYPE_CTRL 0x1614 459e3037485SYan-Hsuan Chuang #define REG_GENERAL_OPTION 0x1664 460e3037485SYan-Hsuan Chuang #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) 461e3037485SYan-Hsuan Chuang 462e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 463e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 464e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 465e3037485SYan-Hsuan Chuang #define LTECOEX_READY BIT(29) 466e3037485SYan-Hsuan Chuang #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 467e3037485SYan-Hsuan Chuang #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 468e3037485SYan-Hsuan Chuang #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 469e3037485SYan-Hsuan Chuang 4704136214fSYan-Hsuan Chuang #define REG_IGN_GNT_BT1 0x1860 4714136214fSYan-Hsuan Chuang 4724136214fSYan-Hsuan Chuang #define REG_RFESEL_CTRL 0x1990 4734136214fSYan-Hsuan Chuang 4744136214fSYan-Hsuan Chuang #define REG_NOMASK_TXBT 0x1ca7 4754136214fSYan-Hsuan Chuang #define REG_ANAPAR 0x1c30 4764136214fSYan-Hsuan Chuang #define BIT_ANAPAR_BTPS BIT(22) 4774136214fSYan-Hsuan Chuang #define REG_RSTB_SEL 0x1c38 4784136214fSYan-Hsuan Chuang 4794136214fSYan-Hsuan Chuang #define REG_IGN_GNTBT4 0x4160 4804136214fSYan-Hsuan Chuang 4814136214fSYan-Hsuan Chuang #define RF_MODOPT 0x01 482e3037485SYan-Hsuan Chuang #define RF_DTXLOK 0x08 483e3037485SYan-Hsuan Chuang #define RF_CFGCH 0x18 4844136214fSYan-Hsuan Chuang #define RF_RCK 0x1d 485e3037485SYan-Hsuan Chuang #define RF_LUTWA 0x33 486e3037485SYan-Hsuan Chuang #define RF_LUTWD1 0x3e 487e3037485SYan-Hsuan Chuang #define RF_LUTWD0 0x3f 4885227c2eeSTzu-En Huang #define RF_T_METER 0x42 489e3037485SYan-Hsuan Chuang #define RF_XTALX2 0xb8 490e3037485SYan-Hsuan Chuang #define RF_MALSEL 0xbe 4914136214fSYan-Hsuan Chuang #define RF_RCKD 0xde 492e3037485SYan-Hsuan Chuang #define RF_LUTDBG 0xdf 493e3037485SYan-Hsuan Chuang #define RF_LUTWE2 0xee 494e3037485SYan-Hsuan Chuang #define RF_LUTWE 0xef 495e3037485SYan-Hsuan Chuang 4964136214fSYan-Hsuan Chuang #define LTE_COEX_CTRL 0x38 4974136214fSYan-Hsuan Chuang #define LTE_WL_TRX_CTRL 0xa0 4984136214fSYan-Hsuan Chuang #define LTE_BT_TRX_CTRL 0xa4 4994136214fSYan-Hsuan Chuang 500e3037485SYan-Hsuan Chuang #endif 501