1e3037485SYan-Hsuan Chuang /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2e3037485SYan-Hsuan Chuang /* Copyright(c) 2018-2019 Realtek Corporation 3e3037485SYan-Hsuan Chuang */ 4e3037485SYan-Hsuan Chuang 5e3037485SYan-Hsuan Chuang #ifndef __RTW_REG_DEF_H__ 6e3037485SYan-Hsuan Chuang #define __RTW_REG_DEF_H__ 7e3037485SYan-Hsuan Chuang 8e3037485SYan-Hsuan Chuang #define REG_SYS_FUNC_EN 0x0002 944baa97cSPing-Ke Shih #define BIT_FEN_ELDR BIT(12) 10e3037485SYan-Hsuan Chuang #define BIT_FEN_CPUEN BIT(2) 11e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_GLB_RST BIT(1) 12e3037485SYan-Hsuan Chuang #define BIT_FEN_BB_RSTB BIT(0) 1344bc17f7SChin-Yen Lee #define BIT_R_DIS_PRST BIT(6) 1444bc17f7SChin-Yen Lee #define BIT_WLOCK_1C_B6 BIT(5) 15e3037485SYan-Hsuan Chuang #define REG_SYS_PW_CTRL 0x0004 16e3037485SYan-Hsuan Chuang #define REG_SYS_CLK_CTRL 0x0008 17e3037485SYan-Hsuan Chuang #define BIT_CPU_CLK_EN BIT(14) 18e3037485SYan-Hsuan Chuang 1944baa97cSPing-Ke Shih #define REG_SYS_CLKR 0x0008 2044baa97cSPing-Ke Shih #define BIT_ANA8M BIT(1) 2144baa97cSPing-Ke Shih #define BIT_LOADER_CLK_EN BIT(5) 2244baa97cSPing-Ke Shih 23e3037485SYan-Hsuan Chuang #define REG_RSV_CTRL 0x001C 24e3037485SYan-Hsuan Chuang #define DISABLE_PI 0x3 25e3037485SYan-Hsuan Chuang #define ENABLE_PI 0x2 26e3037485SYan-Hsuan Chuang #define BITS_RFC_DIRECT (BIT(31) | BIT(30)) 27e3037485SYan-Hsuan Chuang #define BIT_WLMCU_IOIF BIT(0) 28e3037485SYan-Hsuan Chuang #define REG_RF_CTRL 0x001F 29e3037485SYan-Hsuan Chuang #define BIT_RF_SDM_RSTB BIT(2) 30e3037485SYan-Hsuan Chuang #define BIT_RF_RSTB BIT(1) 31e3037485SYan-Hsuan Chuang #define BIT_RF_EN BIT(0) 32e3037485SYan-Hsuan Chuang 33e3037485SYan-Hsuan Chuang #define REG_AFE_CTRL1 0x0024 34e3037485SYan-Hsuan Chuang #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21)) 35e3037485SYan-Hsuan Chuang #define REG_EFUSE_CTRL 0x0030 36e3037485SYan-Hsuan Chuang #define BIT_EF_FLAG BIT(31) 37e3037485SYan-Hsuan Chuang #define BIT_SHIFT_EF_ADDR 8 38e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_ADDR 0x3ff 39e3037485SYan-Hsuan Chuang #define BIT_MASK_EF_DATA 0xff 40e3037485SYan-Hsuan Chuang #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) 41e3037485SYan-Hsuan Chuang 42e3037485SYan-Hsuan Chuang #define REG_LDO_EFUSE_CTRL 0x0034 43e3037485SYan-Hsuan Chuang #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9)) 44e3037485SYan-Hsuan Chuang 451afb5eb7SPing-Ke Shih #define BIT_LDO25_VOLTAGE_V25 0x03 461afb5eb7SPing-Ke Shih #define BIT_MASK_LDO25_VOLTAGE GENMASK(6, 4) 471afb5eb7SPing-Ke Shih #define BIT_SHIFT_LDO25_VOLTAGE 4 481afb5eb7SPing-Ke Shih #define BIT_LDO25_EN BIT(7) 491afb5eb7SPing-Ke Shih 50e3037485SYan-Hsuan Chuang #define REG_GPIO_MUXCFG 0x0040 51e3037485SYan-Hsuan Chuang #define BIT_FSPI_EN BIT(19) 524136214fSYan-Hsuan Chuang #define BIT_BT_AOD_GPIO3 BIT(9) 534136214fSYan-Hsuan Chuang #define BIT_BT_PTA_EN BIT(5) 54e3037485SYan-Hsuan Chuang #define BIT_WLRFE_4_5_EN BIT(2) 55e3037485SYan-Hsuan Chuang 56e3037485SYan-Hsuan Chuang #define REG_LED_CFG 0x004C 57e3037485SYan-Hsuan Chuang #define BIT_LNAON_SEL_EN BIT(26) 58e3037485SYan-Hsuan Chuang #define BIT_PAPE_SEL_EN BIT(25) 594136214fSYan-Hsuan Chuang #define BIT_DPDT_WL_SEL BIT(24) 604136214fSYan-Hsuan Chuang #define BIT_DPDT_SEL_EN BIT(23) 61e3037485SYan-Hsuan Chuang #define REG_PAD_CTRL1 0x0064 62e3037485SYan-Hsuan Chuang #define BIT_PAPE_WLBT_SEL BIT(29) 63e3037485SYan-Hsuan Chuang #define BIT_LNAON_WLBT_SEL BIT(28) 644136214fSYan-Hsuan Chuang #define BIT_BTGP_JTAG_EN BIT(24) 654136214fSYan-Hsuan Chuang #define BIT_BTGP_SPI_EN BIT(20) 664136214fSYan-Hsuan Chuang #define BIT_LED1DIS BIT(15) 674136214fSYan-Hsuan Chuang #define BIT_SW_DPDT_SEL_DATA BIT(0) 68e3037485SYan-Hsuan Chuang #define REG_WL_BT_PWR_CTRL 0x0068 69e3037485SYan-Hsuan Chuang #define BIT_BT_FUNC_EN BIT(18) 70e3037485SYan-Hsuan Chuang #define BIT_BT_DIG_CLK_EN BIT(8) 714136214fSYan-Hsuan Chuang #define REG_SYS_SDIO_CTRL 0x0070 724136214fSYan-Hsuan Chuang #define BIT_DBG_GNT_WL_BT BIT(27) 734136214fSYan-Hsuan Chuang #define BIT_LTE_MUX_CTRL_PATH BIT(26) 74e3037485SYan-Hsuan Chuang #define REG_HCI_OPT_CTRL 0x0074 75e3037485SYan-Hsuan Chuang 76e3037485SYan-Hsuan Chuang #define REG_MCUFW_CTRL 0x0080 77e3037485SYan-Hsuan Chuang #define BIT_ANA_PORT_EN BIT(22) 78e3037485SYan-Hsuan Chuang #define BIT_MAC_PORT_EN BIT(21) 79e3037485SYan-Hsuan Chuang #define BIT_BOOT_FSPI_EN BIT(20) 8015d2fcc6SPing-Ke Shih #define BIT_ROM_DLEN BIT(19) 8115d2fcc6SPing-Ke Shih #define BIT_ROM_PGE GENMASK(18, 16) /* legacy only */ 8215d2fcc6SPing-Ke Shih #define BIT_SHIFT_ROM_PGE 16 83e3037485SYan-Hsuan Chuang #define BIT_FW_INIT_RDY BIT(15) 84e3037485SYan-Hsuan Chuang #define BIT_FW_DW_RDY BIT(14) 85e3037485SYan-Hsuan Chuang #define BIT_RPWM_TOGGLE BIT(7) 8615d2fcc6SPing-Ke Shih #define BIT_RAM_DL_SEL BIT(7) /* legacy only */ 87e3037485SYan-Hsuan Chuang #define BIT_DMEM_CHKSUM_OK BIT(6) 8815d2fcc6SPing-Ke Shih #define BIT_WINTINI_RDY BIT(6) /* legacy only */ 89e3037485SYan-Hsuan Chuang #define BIT_DMEM_DW_OK BIT(5) 90e3037485SYan-Hsuan Chuang #define BIT_IMEM_CHKSUM_OK BIT(4) 91e3037485SYan-Hsuan Chuang #define BIT_IMEM_DW_OK BIT(3) 92e3037485SYan-Hsuan Chuang #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2) 9315d2fcc6SPing-Ke Shih #define BIT_FWDL_CHK_RPT BIT(2) /* legacy only */ 9415d2fcc6SPing-Ke Shih #define BIT_MCUFWDL_RDY BIT(1) /* legacy only */ 95e3037485SYan-Hsuan Chuang #define BIT_MCUFWDL_EN BIT(0) 96e3037485SYan-Hsuan Chuang #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6)) 97e3037485SYan-Hsuan Chuang #define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \ 98e3037485SYan-Hsuan Chuang BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \ 99e3037485SYan-Hsuan Chuang BIT_CHECK_SUM_OK) 10015d2fcc6SPing-Ke Shih #define FW_READY_LEGACY (BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT | \ 10115d2fcc6SPing-Ke Shih BIT_WINTINI_RDY | BIT_RAM_DL_SEL) 102e3037485SYan-Hsuan Chuang #define FW_READY_MASK 0xffff 103e3037485SYan-Hsuan Chuang 10444baa97cSPing-Ke Shih #define REG_EFUSE_ACCESS 0x00CF 10544baa97cSPing-Ke Shih #define EFUSE_ACCESS_ON 0x69 10644baa97cSPing-Ke Shih #define EFUSE_ACCESS_OFF 0x00 10744baa97cSPing-Ke Shih 108e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 1094136214fSYan-Hsuan Chuang #define REG_WIFI_BT_INFO 0x00AA 1104136214fSYan-Hsuan Chuang #define BIT_BT_INT_EN BIT(15) 111e3037485SYan-Hsuan Chuang #define REG_SYS_CFG1 0x00F0 112e3037485SYan-Hsuan Chuang #define BIT_RTL_ID BIT(23) 113e3037485SYan-Hsuan Chuang #define BIT_RF_TYPE_ID BIT(27) 114e3037485SYan-Hsuan Chuang #define BIT_SHIFT_VENDOR_ID 16 115e3037485SYan-Hsuan Chuang #define BIT_MASK_VENDOR_ID 0xf 116e3037485SYan-Hsuan Chuang #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) 117e3037485SYan-Hsuan Chuang #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) 118e3037485SYan-Hsuan Chuang #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) 119e3037485SYan-Hsuan Chuang #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) 120e3037485SYan-Hsuan Chuang #define BIT_SHIFT_CHIP_VER 12 121e3037485SYan-Hsuan Chuang #define BIT_MASK_CHIP_VER 0xf 122e3037485SYan-Hsuan Chuang #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) 123e3037485SYan-Hsuan Chuang #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) 124e3037485SYan-Hsuan Chuang #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) 125e3037485SYan-Hsuan Chuang #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) 126e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS1 0x00F4 127e3037485SYan-Hsuan Chuang #define REG_SYS_STATUS2 0x00F8 128e3037485SYan-Hsuan Chuang #define REG_SYS_CFG2 0x00FC 129e3037485SYan-Hsuan Chuang #define REG_WLRF1 0x00EC 130e3037485SYan-Hsuan Chuang #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26)) 131e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 132e3037485SYan-Hsuan Chuang #define BIT_32K_CAL_TMR_EN BIT(10) 133e3037485SYan-Hsuan Chuang #define BIT_MAC_SEC_EN BIT(9) 134e3037485SYan-Hsuan Chuang #define BIT_ENSWBCN BIT(8) 135e3037485SYan-Hsuan Chuang #define BIT_MACRXEN BIT(7) 136e3037485SYan-Hsuan Chuang #define BIT_MACTXEN BIT(6) 137e3037485SYan-Hsuan Chuang #define BIT_SCHEDULE_EN BIT(5) 138e3037485SYan-Hsuan Chuang #define BIT_PROTOCOL_EN BIT(4) 139e3037485SYan-Hsuan Chuang #define BIT_RXDMA_EN BIT(3) 140e3037485SYan-Hsuan Chuang #define BIT_TXDMA_EN BIT(2) 141e3037485SYan-Hsuan Chuang #define BIT_HCI_RXDMA_EN BIT(1) 142e3037485SYan-Hsuan Chuang #define BIT_HCI_TXDMA_EN BIT(0) 143e3037485SYan-Hsuan Chuang #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ 144e3037485SYan-Hsuan Chuang BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ 145e3037485SYan-Hsuan Chuang BIT_MACTXEN | BIT_MACRXEN) 146e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VOQ_MAP 4 147e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VOQ_MAP 0x3 148e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VOQ_MAP(x) \ 149e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 150e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_VIQ_MAP 6 151e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_VIQ_MAP 0x3 152e3037485SYan-Hsuan Chuang #define BIT_TXDMA_VIQ_MAP(x) \ 153e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 154e3037485SYan-Hsuan Chuang #define REG_TXDMA_PQ_MAP 0x010C 155e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BEQ_MAP 8 156e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BEQ_MAP 0x3 157e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BEQ_MAP(x) \ 158e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 159e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_BKQ_MAP 10 160e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_BKQ_MAP 0x3 161e3037485SYan-Hsuan Chuang #define BIT_TXDMA_BKQ_MAP(x) \ 162e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) 163e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_MGQ_MAP 12 164e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_MGQ_MAP 0x3 165e3037485SYan-Hsuan Chuang #define BIT_TXDMA_MGQ_MAP(x) \ 166e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) 167e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXDMA_HIQ_MAP 14 168e3037485SYan-Hsuan Chuang #define BIT_MASK_TXDMA_HIQ_MAP 0x3 169e3037485SYan-Hsuan Chuang #define BIT_TXDMA_HIQ_MAP(x) \ 170e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) 171e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_40M 4 172e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_40M 0xf 173e3037485SYan-Hsuan Chuang #define BIT_TXSC_40M(x) \ 174e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) 175e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TXSC_20M 0 176e3037485SYan-Hsuan Chuang #define BIT_MASK_TXSC_20M 0xf 177e3037485SYan-Hsuan Chuang #define BIT_TXSC_20M(x) \ 178e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) 179e3037485SYan-Hsuan Chuang #define BIT_SHIFT_MAC_CLK_SEL 20 180e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_80M 0 181e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_40M 1 182e3037485SYan-Hsuan Chuang #define MAC_CLK_HW_DEF_20M 2 183e3037485SYan-Hsuan Chuang #define MAC_CLK_SPEED 80 184e3037485SYan-Hsuan Chuang 185e3037485SYan-Hsuan Chuang #define REG_CR 0x0100 186e3037485SYan-Hsuan Chuang #define REG_TRXFF_BNDY 0x0114 187e3037485SYan-Hsuan Chuang #define REG_RXFF_BNDY 0x011C 18844bc17f7SChin-Yen Lee #define REG_FE1IMR 0x0120 18944bc17f7SChin-Yen Lee #define BIT_FS_RXDONE BIT(16) 190e3037485SYan-Hsuan Chuang #define REG_PKTBUF_DBG_CTRL 0x0140 191e3037485SYan-Hsuan Chuang #define REG_C2HEVT 0x01A0 19244bc17f7SChin-Yen Lee #define REG_MCUTST_II 0x01C4 19344bc17f7SChin-Yen Lee #define REG_WOWLAN_WAKE_REASON 0x01C7 194e3037485SYan-Hsuan Chuang #define REG_HMETFR 0x01CC 195e3037485SYan-Hsuan Chuang #define REG_HMEBOX0 0x01D0 196e3037485SYan-Hsuan Chuang #define REG_HMEBOX1 0x01D4 197e3037485SYan-Hsuan Chuang #define REG_HMEBOX2 0x01D8 198e3037485SYan-Hsuan Chuang #define REG_HMEBOX3 0x01DC 199e3037485SYan-Hsuan Chuang #define REG_HMEBOX0_EX 0x01F0 200e3037485SYan-Hsuan Chuang #define REG_HMEBOX1_EX 0x01F4 201e3037485SYan-Hsuan Chuang #define REG_HMEBOX2_EX 0x01F8 202e3037485SYan-Hsuan Chuang #define REG_HMEBOX3_EX 0x01FC 203e3037485SYan-Hsuan Chuang 204e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_CTRL_2 0x0204 205e3037485SYan-Hsuan Chuang #define BIT_BCN_VALID_V1 BIT(15) 206e3037485SYan-Hsuan Chuang #define BIT_MASK_BCN_HEAD_1_V1 0xfff 207e3037485SYan-Hsuan Chuang #define REG_AUTO_LLT_V1 0x0208 208e3037485SYan-Hsuan Chuang #define BIT_AUTO_INIT_LLT_V1 BIT(0) 20915d2fcc6SPing-Ke Shih #define REG_DWBCN0_CTRL 0x0208 21015d2fcc6SPing-Ke Shih #define BIT_BCN_VALID BIT(16) 211e3037485SYan-Hsuan Chuang #define REG_TXDMA_OFFSET_CHK 0x020C 212e3037485SYan-Hsuan Chuang #define REG_TXDMA_STATUS 0x0210 213e3037485SYan-Hsuan Chuang #define BTI_PAGE_OVF BIT(2) 214e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_1 0x0228 215e3037485SYan-Hsuan Chuang #define REG_RQPN_CTRL_2 0x022C 216e3037485SYan-Hsuan Chuang #define BIT_LD_RQPN BIT(31) 217e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_1 0x0230 218e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_2 0x0234 219e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_3 0x0238 220e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_4 0x023C 221e3037485SYan-Hsuan Chuang #define REG_FIFOPAGE_INFO_5 0x0240 222e3037485SYan-Hsuan Chuang #define REG_H2C_HEAD 0x0244 223e3037485SYan-Hsuan Chuang #define REG_H2C_TAIL 0x0248 224e3037485SYan-Hsuan Chuang #define REG_H2C_READ_ADDR 0x024C 225e3037485SYan-Hsuan Chuang #define REG_H2C_INFO 0x0254 22644bc17f7SChin-Yen Lee #define REG_RXPKT_NUM 0x0284 22744bc17f7SChin-Yen Lee #define BIT_RXDMA_REQ BIT(19) 22844bc17f7SChin-Yen Lee #define BIT_RW_RELEASE BIT(18) 22944bc17f7SChin-Yen Lee #define BIT_RXDMA_IDLE BIT(17) 23044bc17f7SChin-Yen Lee #define REG_RXPKTNUM 0x02B0 231e3037485SYan-Hsuan Chuang 232bc61ae96STsang-Shian Lin #define REG_INT_MIG 0x0304 23378622104SYan-Hsuan Chuang #define REG_HCI_MIX_CFG 0x03FC 23478622104SYan-Hsuan Chuang #define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26) 235bc61ae96STsang-Shian Lin 23644bc17f7SChin-Yen Lee #define REG_BCNQ_INFO 0x0418 23744bc17f7SChin-Yen Lee #define BIT_MGQ_CPU_EMPTY BIT(24) 238e3037485SYan-Hsuan Chuang #define REG_FWHW_TXQ_CTRL 0x0420 239e3037485SYan-Hsuan Chuang #define BIT_EN_BCNQ_DL BIT(22) 240e3037485SYan-Hsuan Chuang #define BIT_EN_WR_FREE_TAIL BIT(20) 241e3037485SYan-Hsuan Chuang #define REG_BCNQ_BDNY_V1 0x0424 242e3037485SYan-Hsuan Chuang #define REG_LIFETIME_EN 0x0426 243e3037485SYan-Hsuan Chuang #define BIT_BA_PARSER_EN BIT(5) 244e3037485SYan-Hsuan Chuang #define REG_SPEC_SIFS 0x0428 2454136214fSYan-Hsuan Chuang #define REG_RETRY_LIMIT 0x042a 246e3037485SYan-Hsuan Chuang #define REG_DARFRC 0x0430 247e3037485SYan-Hsuan Chuang #define REG_DARFRCH 0x0434 248e3037485SYan-Hsuan Chuang #define REG_RARFRCH 0x043C 249e3037485SYan-Hsuan Chuang #define REG_ARFR0 0x0444 250e3037485SYan-Hsuan Chuang #define REG_ARFRH0 0x0448 251e3037485SYan-Hsuan Chuang #define REG_ARFR1_V1 0x044C 252e3037485SYan-Hsuan Chuang #define REG_ARFRH1_V1 0x0450 253e3037485SYan-Hsuan Chuang #define REG_CCK_CHECK 0x0454 254e3037485SYan-Hsuan Chuang #define BIT_CHECK_CCK_EN BIT(7) 255e3037485SYan-Hsuan Chuang #define REG_AMPDU_MAX_TIME_V1 0x0455 256e3037485SYan-Hsuan Chuang #define REG_BCNQ1_BDNY_V1 0x0456 257e3037485SYan-Hsuan Chuang #define REG_TX_HANG_CTRL 0x045E 2584136214fSYan-Hsuan Chuang #define BIT_EN_GNT_BT_AWAKE BIT(3) 259e3037485SYan-Hsuan Chuang #define BIT_EN_EOF_V1 BIT(2) 260e3037485SYan-Hsuan Chuang #define REG_DATA_SC 0x0483 261e3037485SYan-Hsuan Chuang #define REG_ARFR4 0x049C 2624136214fSYan-Hsuan Chuang #define BIT_WL_RFK BIT(0) 263e3037485SYan-Hsuan Chuang #define REG_ARFRH4 0x04A0 264e3037485SYan-Hsuan Chuang #define REG_ARFR5 0x04A4 265e3037485SYan-Hsuan Chuang #define REG_ARFRH5 0x04A8 266e3037485SYan-Hsuan Chuang #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC 267e3037485SYan-Hsuan Chuang #define BIT_PRE_TX_CMD BIT(6) 2684136214fSYan-Hsuan Chuang #define REG_QUEUE_CTRL 0x04C6 2694136214fSYan-Hsuan Chuang #define BIT_PTA_WL_TX_EN BIT(4) 2704136214fSYan-Hsuan Chuang #define BIT_PTA_EDCCA_EN BIT(5) 271e3037485SYan-Hsuan Chuang #define REG_PROT_MODE_CTRL 0x04C8 272e3037485SYan-Hsuan Chuang #define REG_BAR_MODE_CTRL 0x04CC 273e3037485SYan-Hsuan Chuang #define REG_PRECNT_CTRL 0x04E5 2744136214fSYan-Hsuan Chuang #define BIT_BTCCA_CTRL (BIT(0) | BIT(1)) 275e3037485SYan-Hsuan Chuang #define BIT_EN_PRECNT BIT(11) 2764136214fSYan-Hsuan Chuang #define REG_DUMMY_PAGE4_V1 0x04FC 277e3037485SYan-Hsuan Chuang 278e3037485SYan-Hsuan Chuang #define REG_EDCA_VO_PARAM 0x0500 279e3037485SYan-Hsuan Chuang #define REG_EDCA_VI_PARAM 0x0504 280e3037485SYan-Hsuan Chuang #define REG_EDCA_BE_PARAM 0x0508 281e3037485SYan-Hsuan Chuang #define REG_EDCA_BK_PARAM 0x050C 282bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_TXOP_LMT GENMASK(26, 16) 283bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_CWMAX GENMASK(15, 12) 284bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_CWMIN GENMASK(11, 8) 285bf06c7ecSYan-Hsuan Chuang #define BIT_MASK_AIFS GENMASK(7, 0) 286e3037485SYan-Hsuan Chuang #define REG_PIFS 0x0512 287e3037485SYan-Hsuan Chuang #define REG_SIFS 0x0514 288e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_CTX 8 289e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_CCK_TRX 16 290e3037485SYan-Hsuan Chuang #define BIT_SHIFT_SIFS_OFDM_TRX 24 291e3037485SYan-Hsuan Chuang #define REG_SLOT 0x051B 292e3037485SYan-Hsuan Chuang #define REG_TX_PTCL_CTRL 0x0520 293e3037485SYan-Hsuan Chuang #define BIT_SIFS_BK_EN BIT(12) 294e3037485SYan-Hsuan Chuang #define REG_TXPAUSE 0x0522 295e3037485SYan-Hsuan Chuang #define REG_RD_CTRL 0x0524 296e3037485SYan-Hsuan Chuang #define BIT_DIS_TXOP_CFE BIT(10) 297e3037485SYan-Hsuan Chuang #define BIT_DIS_LSIG_CFE BIT(9) 298e3037485SYan-Hsuan Chuang #define BIT_DIS_STBC_CFE BIT(8) 299e3037485SYan-Hsuan Chuang #define REG_TBTT_PROHIBIT 0x0540 300e3037485SYan-Hsuan Chuang #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 301e3037485SYan-Hsuan Chuang #define REG_RD_NAV_NXT 0x0544 302e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL 0x0550 303e3037485SYan-Hsuan Chuang #define BIT_DIS_TSF_UDT BIT(4) 304e3037485SYan-Hsuan Chuang #define BIT_EN_BCN_FUNCTION BIT(3) 305e3037485SYan-Hsuan Chuang #define REG_BCN_CTRL_CLINT0 0x0551 306e3037485SYan-Hsuan Chuang #define REG_DRVERLYINT 0x0558 307e3037485SYan-Hsuan Chuang #define REG_BCNDMATIM 0x0559 308e3037485SYan-Hsuan Chuang #define REG_USTIME_TSF 0x055C 309e3037485SYan-Hsuan Chuang #define REG_BCN_MAX_ERR 0x055D 310e3037485SYan-Hsuan Chuang #define REG_RXTSF_OFFSET_CCK 0x055E 311e3037485SYan-Hsuan Chuang #define REG_MISC_CTRL 0x0577 312e3037485SYan-Hsuan Chuang #define BIT_EN_FREE_CNT BIT(3) 313e3037485SYan-Hsuan Chuang #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1)) 314e3037485SYan-Hsuan Chuang #define REG_TIMER0_SRC_SEL 0x05B4 315e3037485SYan-Hsuan Chuang #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6)) 316e3037485SYan-Hsuan Chuang 317e3037485SYan-Hsuan Chuang #define REG_TCR 0x0604 3183a2dd6b7SChin-Yen Lee #define BIT_PWRMGT_HWDATA_EN BIT(7) 319e3037485SYan-Hsuan Chuang #define REG_RCR 0x0608 320e3037485SYan-Hsuan Chuang #define BIT_APP_FCS BIT(31) 321e3037485SYan-Hsuan Chuang #define BIT_APP_MIC BIT(30) 322e3037485SYan-Hsuan Chuang #define BIT_APP_ICV BIT(29) 323e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 324e3037485SYan-Hsuan Chuang #define BIT_APP_BASSN BIT(27) 325e3037485SYan-Hsuan Chuang #define BIT_VHT_DACK BIT(26) 326e3037485SYan-Hsuan Chuang #define BIT_TCPOFLD_EN BIT(25) 327e3037485SYan-Hsuan Chuang #define BIT_ENMBID BIT(24) 328e3037485SYan-Hsuan Chuang #define BIT_LSIGEN BIT(23) 329e3037485SYan-Hsuan Chuang #define BIT_MFBEN BIT(22) 330e3037485SYan-Hsuan Chuang #define BIT_DISCHKPPDLLEN BIT(21) 331e3037485SYan-Hsuan Chuang #define BIT_PKTCTL_DLEN BIT(20) 332e3037485SYan-Hsuan Chuang #define BIT_TIM_PARSER_EN BIT(18) 333e3037485SYan-Hsuan Chuang #define BIT_BC_MD_EN BIT(17) 334e3037485SYan-Hsuan Chuang #define BIT_UC_MD_EN BIT(16) 335e3037485SYan-Hsuan Chuang #define BIT_RXSK_PERPKT BIT(15) 336e3037485SYan-Hsuan Chuang #define BIT_HTC_LOC_CTRL BIT(14) 337e3037485SYan-Hsuan Chuang #define BIT_RPFM_CAM_ENABLE BIT(12) 338e3037485SYan-Hsuan Chuang #define BIT_TA_BCN BIT(11) 339e3037485SYan-Hsuan Chuang #define BIT_DISDECMYPKT BIT(10) 340e3037485SYan-Hsuan Chuang #define BIT_AICV BIT(9) 341e3037485SYan-Hsuan Chuang #define BIT_ACRC32 BIT(8) 342e3037485SYan-Hsuan Chuang #define BIT_CBSSID_BCN BIT(7) 343e3037485SYan-Hsuan Chuang #define BIT_CBSSID_DATA BIT(6) 344e3037485SYan-Hsuan Chuang #define BIT_APWRMGT BIT(5) 345e3037485SYan-Hsuan Chuang #define BIT_ADD3 BIT(4) 346e3037485SYan-Hsuan Chuang #define BIT_AB BIT(3) 347e3037485SYan-Hsuan Chuang #define BIT_AM BIT(2) 348e3037485SYan-Hsuan Chuang #define BIT_APM BIT(1) 349e3037485SYan-Hsuan Chuang #define BIT_AAP BIT(0) 350e3037485SYan-Hsuan Chuang #define REG_RX_PKT_LIMIT 0x060C 351e3037485SYan-Hsuan Chuang #define REG_RX_DRVINFO_SZ 0x060F 352e3037485SYan-Hsuan Chuang #define BIT_APP_PHYSTS BIT(28) 35327c65bfcSTzu-En Huang #define REG_MAR 0x0620 354e3037485SYan-Hsuan Chuang #define REG_USTIME_EDCA 0x0638 355e3037485SYan-Hsuan Chuang #define REG_ACKTO_CCK 0x0639 356e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_CCK 0x063C 357e3037485SYan-Hsuan Chuang #define REG_RESP_SIFS_OFDM 0x063E 358e3037485SYan-Hsuan Chuang #define REG_ACKTO 0x0640 359e3037485SYan-Hsuan Chuang #define REG_EIFS 0x0642 360e3037485SYan-Hsuan Chuang #define REG_NAV_CTRL 0x0650 361e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL 0x0668 362e3037485SYan-Hsuan Chuang #define BIT_RFMOD (BIT(7) | BIT(8)) 363e3037485SYan-Hsuan Chuang #define BIT_RFMOD_80M BIT(8) 364e3037485SYan-Hsuan Chuang #define BIT_RFMOD_40M BIT(7) 365e3037485SYan-Hsuan Chuang #define REG_WMAC_TRXPTCL_CTL_H 0x066C 366e3e400dfSChin-Yen Lee #define REG_WKFMCAM_CMD 0x0698 367e3e400dfSChin-Yen Lee #define BIT_WKFCAM_POLLING_V1 BIT(31) 368e3e400dfSChin-Yen Lee #define BIT_WKFCAM_CLR_V1 BIT(30) 369e3e400dfSChin-Yen Lee #define BIT_WKFCAM_WE BIT(16) 370e3e400dfSChin-Yen Lee #define BIT_SHIFT_WKFCAM_ADDR_V2 8 371e3e400dfSChin-Yen Lee #define BIT_MASK_WKFCAM_ADDR_V2 0xff 372e3e400dfSChin-Yen Lee #define BIT_WKFCAM_ADDR_V2(x) \ 373e3e400dfSChin-Yen Lee (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) 374e3e400dfSChin-Yen Lee #define REG_WKFMCAM_RWD 0x069C 375e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_VALID BIT(31) 376e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_BC BIT(26) 377e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_MC BIT(25) 378e3e400dfSChin-Yen Lee #define BIT_WKFMCAM_UC BIT(24) 379e3e400dfSChin-Yen Lee 380e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP0 0x06A0 381e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP1 0x06A2 382e3037485SYan-Hsuan Chuang #define REG_RXFLTMAP2 0x06A4 3830bd95573STzu-En Huang #define REG_RXFLTMAP4 0x068A 3844136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE0 0x06C0 3854136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE1 0x06C4 3864136214fSYan-Hsuan Chuang #define REG_BT_COEX_BRK_TABLE 0x06C8 3874136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H 0x06CC 3884136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H1 0x06CD 3894136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H2 0x06CE 3904136214fSYan-Hsuan Chuang #define REG_BT_COEX_TABLE_H3 0x06CF 391e3037485SYan-Hsuan Chuang #define REG_BBPSF_CTRL 0x06DC 392e3037485SYan-Hsuan Chuang 3934136214fSYan-Hsuan Chuang #define REG_BT_COEX_V2 0x0763 3944136214fSYan-Hsuan Chuang #define BIT_GNT_BT_POLARITY BIT(4) 3954136214fSYan-Hsuan Chuang #define BIT_LTE_COEX_EN BIT(7) 3964136214fSYan-Hsuan Chuang #define REG_BT_STAT_CTRL 0x0778 3974136214fSYan-Hsuan Chuang #define REG_BT_TDMA_TIME 0x0790 398e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION 0x07D0 399e3037485SYan-Hsuan Chuang #define REG_WMAC_OPTION_FUNCTION_1 0x07D4 400e3037485SYan-Hsuan Chuang 4014136214fSYan-Hsuan Chuang #define REG_RX_GAIN_EN 0x081c 4024136214fSYan-Hsuan Chuang 4034136214fSYan-Hsuan Chuang #define REG_RFE_CTRL_E 0x0974 4044136214fSYan-Hsuan Chuang 4055227c2eeSTzu-En Huang #define REG_DIS_DPD 0x0a70 4065227c2eeSTzu-En Huang #define DIS_DPD_MASK GENMASK(9, 0) 4075227c2eeSTzu-En Huang #define DIS_DPD_RATE6M BIT(0) 4085227c2eeSTzu-En Huang #define DIS_DPD_RATE9M BIT(1) 4095227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS0 BIT(2) 4105227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS1 BIT(3) 4115227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS8 BIT(4) 4125227c2eeSTzu-En Huang #define DIS_DPD_RATEMCS9 BIT(5) 4135227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT1SS_MCS0 BIT(6) 4145227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT1SS_MCS1 BIT(7) 4155227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT2SS_MCS0 BIT(8) 4165227c2eeSTzu-En Huang #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9) 4175227c2eeSTzu-En Huang #define DIS_DPD_RATEALL GENMASK(9, 0) 4185227c2eeSTzu-En Huang 4194136214fSYan-Hsuan Chuang #define REG_RFE_CTRL8 0x0cb4 4204136214fSYan-Hsuan Chuang #define BIT_MASK_RFE_SEL89 GENMASK(7, 0) 4214136214fSYan-Hsuan Chuang #define REG_RFE_INV8 0x0cbd 4224136214fSYan-Hsuan Chuang #define BIT_MASK_RFE_INV89 GENMASK(1, 0) 4234136214fSYan-Hsuan Chuang #define REG_RFE_INV16 0x0cbe 4244136214fSYan-Hsuan Chuang #define BIT_RFE_BUF_EN BIT(3) 4254136214fSYan-Hsuan Chuang 426e3037485SYan-Hsuan Chuang #define REG_ANAPAR_XTAL_0 0x1040 427e3037485SYan-Hsuan Chuang #define REG_CPU_DMEM_CON 0x1080 428e3037485SYan-Hsuan Chuang #define BIT_WL_PLATFORM_RST BIT(16) 429e3037485SYan-Hsuan Chuang #define BIT_WL_SECURITY_CLK BIT(15) 430e3037485SYan-Hsuan Chuang #define BIT_DDMA_EN BIT(8) 431e3037485SYan-Hsuan Chuang 432e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_READADDR 0x10D0 433e3037485SYan-Hsuan Chuang #define REG_H2C_PKT_WRITEADDR 0x10D4 434e3037485SYan-Hsuan Chuang #define REG_FW_DBG7 0x10FC 435e3037485SYan-Hsuan Chuang #define FW_KEY_MASK 0xffffff00 436e3037485SYan-Hsuan Chuang 437e3037485SYan-Hsuan Chuang #define REG_CR_EXT 0x1100 438e3037485SYan-Hsuan Chuang 439e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0SA 0x1200 440e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0DA 0x1204 441e3037485SYan-Hsuan Chuang #define REG_DDMA_CH0CTRL 0x1208 442e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_OWN BIT(31) 443e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_EN BIT(29) 444e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_STS BIT(27) 445e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) 446e3037485SYan-Hsuan Chuang #define BIT_DDMACH0_CHKSUM_CONT BIT(24) 447e3037485SYan-Hsuan Chuang #define BIT_MASK_DDMACH0_DLEN 0x3ffff 448e3037485SYan-Hsuan Chuang 449e3037485SYan-Hsuan Chuang #define REG_H2CQ_CSR 0x1330 450e3037485SYan-Hsuan Chuang #define BIT_H2CQ_FULL BIT(31) 451e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_VOVI_SETTING 0x1448 452e3037485SYan-Hsuan Chuang #define REG_FAST_EDCA_BEBK_SETTING 0x144C 453e3037485SYan-Hsuan Chuang 454e3037485SYan-Hsuan Chuang #define REG_RXPSF_CTRL 0x1610 455e3037485SYan-Hsuan Chuang #define BIT_RXGCK_FIFOTHR_EN BIT(28) 456e3037485SYan-Hsuan Chuang 457e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 458e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 459e3037485SYan-Hsuan Chuang #define BIT_RXGCK_VHT_FIFOTHR(x) \ 460e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 461e3037485SYan-Hsuan Chuang #define BITS_RXGCK_VHT_FIFOTHR \ 462e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) 463e3037485SYan-Hsuan Chuang 464e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 465e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 466e3037485SYan-Hsuan Chuang #define BIT_RXGCK_HT_FIFOTHR(x) \ 467e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) 468e3037485SYan-Hsuan Chuang #define BITS_RXGCK_HT_FIFOTHR \ 469e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) 470e3037485SYan-Hsuan Chuang 471e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 472e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 473e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDM_FIFOTHR(x) \ 474e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 475e3037485SYan-Hsuan Chuang #define BITS_RXGCK_OFDM_FIFOTHR \ 476e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) 477e3037485SYan-Hsuan Chuang 478e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 479e3037485SYan-Hsuan Chuang #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 480e3037485SYan-Hsuan Chuang #define BIT_RXGCK_CCK_FIFOTHR(x) \ 481e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 482e3037485SYan-Hsuan Chuang #define BITS_RXGCK_CCK_FIFOTHR \ 483e3037485SYan-Hsuan Chuang (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) 484e3037485SYan-Hsuan Chuang 485e3037485SYan-Hsuan Chuang #define BIT_RXGCK_OFDMCCA_EN BIT(16) 486e3037485SYan-Hsuan Chuang 487e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_PKTLENTHR 13 488e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_PKTLENTHR 0x7 489e3037485SYan-Hsuan Chuang #define BIT_RXPSF_PKTLENTHR(x) \ 490e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) 491e3037485SYan-Hsuan Chuang #define BITS_RXPSF_PKTLENTHR \ 492e3037485SYan-Hsuan Chuang (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) 493e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) 494e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_PKTLENTHR(x, v) \ 495e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) 496e3037485SYan-Hsuan Chuang 497e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CTRLEN BIT(12) 498e3037485SYan-Hsuan Chuang #define BIT_RXPSF_VHTCHKEN BIT(11) 499e3037485SYan-Hsuan Chuang #define BIT_RXPSF_HTCHKEN BIT(10) 500e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMCHKEN BIT(9) 501e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKCHKEN BIT(8) 502e3037485SYan-Hsuan Chuang #define BIT_RXPSF_OFDMRST BIT(7) 503e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CCKRST BIT(6) 504e3037485SYan-Hsuan Chuang #define BIT_RXPSF_MHCHKEN BIT(5) 505e3037485SYan-Hsuan Chuang #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) 506e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) 507e3037485SYan-Hsuan Chuang 508e3037485SYan-Hsuan Chuang #define BIT_SHIFT_RXPSF_ERRTHR 0 509e3037485SYan-Hsuan Chuang #define BIT_MASK_RXPSF_ERRTHR 0x7 510e3037485SYan-Hsuan Chuang #define BIT_RXPSF_ERRTHR(x) \ 511e3037485SYan-Hsuan Chuang (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) 512e3037485SYan-Hsuan Chuang #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) 513e3037485SYan-Hsuan Chuang #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) 514e3037485SYan-Hsuan Chuang #define BIT_GET_RXPSF_ERRTHR(x) \ 515e3037485SYan-Hsuan Chuang (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) 516e3037485SYan-Hsuan Chuang #define BIT_SET_RXPSF_ERRTHR(x, v) \ 517e3037485SYan-Hsuan Chuang (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) 518e3037485SYan-Hsuan Chuang 519e3037485SYan-Hsuan Chuang #define REG_RXPSF_TYPE_CTRL 0x1614 520e3037485SYan-Hsuan Chuang #define REG_GENERAL_OPTION 0x1664 521e3037485SYan-Hsuan Chuang #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) 522e3037485SYan-Hsuan Chuang 523e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 524e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 525e3037485SYan-Hsuan Chuang #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 526e3037485SYan-Hsuan Chuang #define LTECOEX_READY BIT(29) 527e3037485SYan-Hsuan Chuang #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 528e3037485SYan-Hsuan Chuang #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 529e3037485SYan-Hsuan Chuang #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 530e3037485SYan-Hsuan Chuang 5314136214fSYan-Hsuan Chuang #define REG_IGN_GNT_BT1 0x1860 5324136214fSYan-Hsuan Chuang 5334136214fSYan-Hsuan Chuang #define REG_RFESEL_CTRL 0x1990 5344136214fSYan-Hsuan Chuang 5354136214fSYan-Hsuan Chuang #define REG_NOMASK_TXBT 0x1ca7 5364136214fSYan-Hsuan Chuang #define REG_ANAPAR 0x1c30 5374136214fSYan-Hsuan Chuang #define BIT_ANAPAR_BTPS BIT(22) 5384136214fSYan-Hsuan Chuang #define REG_RSTB_SEL 0x1c38 5394136214fSYan-Hsuan Chuang 5404136214fSYan-Hsuan Chuang #define REG_IGN_GNTBT4 0x4160 5414136214fSYan-Hsuan Chuang 5424136214fSYan-Hsuan Chuang #define RF_MODOPT 0x01 543e3037485SYan-Hsuan Chuang #define RF_DTXLOK 0x08 544e3037485SYan-Hsuan Chuang #define RF_CFGCH 0x18 5454136214fSYan-Hsuan Chuang #define RF_RCK 0x1d 546e3037485SYan-Hsuan Chuang #define RF_LUTWA 0x33 547e3037485SYan-Hsuan Chuang #define RF_LUTWD1 0x3e 548e3037485SYan-Hsuan Chuang #define RF_LUTWD0 0x3f 5495227c2eeSTzu-En Huang #define RF_T_METER 0x42 550e3037485SYan-Hsuan Chuang #define RF_XTALX2 0xb8 551e3037485SYan-Hsuan Chuang #define RF_MALSEL 0xbe 5524136214fSYan-Hsuan Chuang #define RF_RCKD 0xde 553e3037485SYan-Hsuan Chuang #define RF_LUTDBG 0xdf 554e3037485SYan-Hsuan Chuang #define RF_LUTWE2 0xee 555e3037485SYan-Hsuan Chuang #define RF_LUTWE 0xef 556e3037485SYan-Hsuan Chuang 5574136214fSYan-Hsuan Chuang #define LTE_COEX_CTRL 0x38 5584136214fSYan-Hsuan Chuang #define LTE_WL_TRX_CTRL 0xa0 5594136214fSYan-Hsuan Chuang #define LTE_BT_TRX_CTRL 0xa4 5604136214fSYan-Hsuan Chuang 561e3037485SYan-Hsuan Chuang #endif 562