1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_PHY_H_ 6 #define __RTW_PHY_H_ 7 8 #include "debug.h" 9 10 extern u8 rtw_cck_rates[]; 11 extern u8 rtw_ofdm_rates[]; 12 extern u8 rtw_ht_1s_rates[]; 13 extern u8 rtw_ht_2s_rates[]; 14 extern u8 rtw_vht_1s_rates[]; 15 extern u8 rtw_vht_2s_rates[]; 16 extern u8 *rtw_rate_section[]; 17 extern u8 rtw_rate_size[]; 18 19 void rtw_phy_init(struct rtw_dev *rtwdev); 20 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev); 21 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num); 22 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 23 u32 addr, u32 mask); 24 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 25 u32 addr, u32 mask, u32 data); 26 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 27 u32 addr, u32 mask, u32 data); 28 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 29 u32 addr, u32 mask, u32 data); 30 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg); 31 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 32 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 33 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 34 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 35 u32 addr, u32 data); 36 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 37 u32 addr, u32 data); 38 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 39 u32 addr, u32 data); 40 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 41 u32 addr, u32 data); 42 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev); 43 void rtw_phy_load_tables(struct rtw_dev *rtwdev); 44 u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate, 45 enum rtw_bandwidth bw, u8 channel, u8 regd); 46 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel); 47 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal); 48 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal); 49 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path); 50 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal, 51 u8 path); 52 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path); 53 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev, 54 struct rtw_swing_table *swing_table, 55 u8 tbl_path, u8 therm_path, u8 delta); 56 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev); 57 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev, 58 struct rtw_swing_table *swing_table); 59 60 struct rtw_txpwr_lmt_cfg_pair { 61 u8 regd; 62 u8 band; 63 u8 bw; 64 u8 rs; 65 u8 ch; 66 s8 txpwr_lmt; 67 }; 68 69 struct rtw_phy_pg_cfg_pair { 70 u32 band; 71 u32 rf_path; 72 u32 tx_num; 73 u32 addr; 74 u32 bitmask; 75 u32 data; 76 }; 77 78 #define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \ 79 const struct rtw_table name ## _tbl = { \ 80 .data = name, \ 81 .size = ARRAY_SIZE(name), \ 82 .parse = rtw_parse_tbl_phy_cond, \ 83 .do_cfg = cfg, \ 84 .rf_path = path, \ 85 } 86 87 #define RTW_DECL_TABLE_PHY_COND(name, cfg) \ 88 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0) 89 90 #define RTW_DECL_TABLE_RF_RADIO(name, path) \ 91 RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path) 92 93 #define RTW_DECL_TABLE_BB_PG(name) \ 94 const struct rtw_table name ## _tbl = { \ 95 .data = name, \ 96 .size = ARRAY_SIZE(name), \ 97 .parse = rtw_parse_tbl_bb_pg, \ 98 } 99 100 #define RTW_DECL_TABLE_TXPWR_LMT(name) \ 101 const struct rtw_table name ## _tbl = { \ 102 .data = name, \ 103 .size = ARRAY_SIZE(name), \ 104 .parse = rtw_parse_tbl_txpwr_lmt, \ 105 } 106 107 static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev) 108 { 109 struct rtw_chip_info *chip = rtwdev->chip; 110 struct rtw_efuse *efuse = &rtwdev->efuse; 111 const struct rtw_rfe_def *rfe_def = NULL; 112 113 if (chip->rfe_defs_size == 0) 114 return NULL; 115 116 if (efuse->rfe_option < chip->rfe_defs_size) 117 rfe_def = &chip->rfe_defs[efuse->rfe_option]; 118 119 rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option); 120 return rfe_def; 121 } 122 123 static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev) 124 { 125 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 126 127 if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) { 128 rtw_err(rtwdev, "rfe %d isn't supported\n", 129 rtwdev->efuse.rfe_option); 130 return -ENODEV; 131 } 132 133 return 0; 134 } 135 136 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi); 137 138 struct rtw_power_params { 139 u8 pwr_base; 140 s8 pwr_offset; 141 s8 pwr_limit; 142 }; 143 144 void 145 rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, 146 u8 rate, u8 bw, u8 ch, u8 regd, 147 struct rtw_power_params *pwr_param); 148 149 enum rtw_phy_cck_pd_lv { 150 CCK_PD_LV0, 151 CCK_PD_LV1, 152 CCK_PD_LV2, 153 CCK_PD_LV3, 154 CCK_PD_LV4, 155 CCK_PD_LV_MAX, 156 }; 157 158 #define MASKBYTE0 0xff 159 #define MASKBYTE1 0xff00 160 #define MASKBYTE2 0xff0000 161 #define MASKBYTE3 0xff000000 162 #define MASKHWORD 0xffff0000 163 #define MASKLWORD 0x0000ffff 164 #define MASKDWORD 0xffffffff 165 #define RFREG_MASK 0xfffff 166 167 #define MASK7BITS 0x7f 168 #define MASK12BITS 0xfff 169 #define MASKH4BITS 0xf0000000 170 #define MASK20BITS 0xfffff 171 #define MASK24BITS 0xffffff 172 173 #define MASKH3BYTES 0xffffff00 174 #define MASKL3BYTES 0x00ffffff 175 #define MASKBYTE2HIGHNIBBLE 0x00f00000 176 #define MASKBYTE3LOWNIBBLE 0x0f000000 177 #define MASKL3BYTES 0x00ffffff 178 179 #define CCK_FA_AVG_RESET 0xffffffff 180 181 #endif 182