1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_PHY_H_ 6 #define __RTW_PHY_H_ 7 8 #include "debug.h" 9 10 extern u8 rtw_cck_rates[]; 11 extern u8 rtw_ofdm_rates[]; 12 extern u8 rtw_ht_1s_rates[]; 13 extern u8 rtw_ht_2s_rates[]; 14 extern u8 rtw_vht_1s_rates[]; 15 extern u8 rtw_vht_2s_rates[]; 16 extern u8 *rtw_rate_section[]; 17 extern u8 rtw_rate_size[]; 18 19 void rtw_phy_init(struct rtw_dev *rtwdev); 20 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev); 21 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num); 22 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 23 u32 addr, u32 mask); 24 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 25 u32 addr, u32 mask, u32 data); 26 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 27 u32 addr, u32 mask, u32 data); 28 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 29 u32 addr, u32 mask, u32 data); 30 void phy_store_tx_power_by_rate(void *adapter, u32 band, u32 rfpath, u32 txnum, 31 u32 regaddr, u32 bitmask, u32 data); 32 void phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band, 33 u8 bw, u8 rs, u8 ch, s8 pwr_limit); 34 void phy_set_tx_power_index_by_rs(void *adapter, u8 ch, u8 path, u8 rs); 35 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg); 36 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 37 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 38 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 39 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 40 u32 addr, u32 data); 41 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 42 u32 addr, u32 data); 43 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 44 u32 addr, u32 data); 45 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 46 u32 addr, u32 data); 47 void rtw_hw_init_tx_power(struct rtw_hal *hal); 48 void rtw_phy_load_tables(struct rtw_dev *rtwdev); 49 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel); 50 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal); 51 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal); 52 53 #define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \ 54 const struct rtw_table name ## _tbl = { \ 55 .data = name, \ 56 .size = ARRAY_SIZE(name), \ 57 .parse = rtw_parse_tbl_phy_cond, \ 58 .do_cfg = cfg, \ 59 .rf_path = path, \ 60 } 61 62 #define RTW_DECL_TABLE_PHY_COND(name, cfg) \ 63 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0) 64 65 #define RTW_DECL_TABLE_RF_RADIO(name, path) \ 66 RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path) 67 68 #define RTW_DECL_TABLE_BB_PG(name) \ 69 const struct rtw_table name ## _tbl = { \ 70 .data = name, \ 71 .size = ARRAY_SIZE(name), \ 72 .parse = rtw_parse_tbl_bb_pg, \ 73 } 74 75 #define RTW_DECL_TABLE_TXPWR_LMT(name) \ 76 const struct rtw_table name ## _tbl = { \ 77 .data = name, \ 78 .size = ARRAY_SIZE(name), \ 79 .parse = rtw_parse_tbl_txpwr_lmt, \ 80 } 81 82 static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev) 83 { 84 struct rtw_chip_info *chip = rtwdev->chip; 85 struct rtw_efuse *efuse = &rtwdev->efuse; 86 const struct rtw_rfe_def *rfe_def = NULL; 87 88 if (chip->rfe_defs_size == 0) 89 return NULL; 90 91 if (efuse->rfe_option < chip->rfe_defs_size) 92 rfe_def = &chip->rfe_defs[efuse->rfe_option]; 93 94 rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option); 95 return rfe_def; 96 } 97 98 static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev) 99 { 100 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 101 102 if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) { 103 rtw_err(rtwdev, "rfe %d isn't supported\n", 104 rtwdev->efuse.rfe_option); 105 return -ENODEV; 106 } 107 108 return 0; 109 } 110 111 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi); 112 113 #define MASKBYTE0 0xff 114 #define MASKBYTE1 0xff00 115 #define MASKBYTE2 0xff0000 116 #define MASKBYTE3 0xff000000 117 #define MASKHWORD 0xffff0000 118 #define MASKLWORD 0x0000ffff 119 #define MASKDWORD 0xffffffff 120 #define RFREG_MASK 0xfffff 121 122 #define MASK7BITS 0x7f 123 #define MASK12BITS 0xfff 124 #define MASKH4BITS 0xf0000000 125 #define MASK20BITS 0xfffff 126 #define MASK24BITS 0xffffff 127 128 #define MASKH3BYTES 0xffffff00 129 #define MASKL3BYTES 0x00ffffff 130 #define MASKBYTE2HIGHNIBBLE 0x00f00000 131 #define MASKBYTE3LOWNIBBLE 0x0f000000 132 #define MASKL3BYTES 0x00ffffff 133 134 #endif 135