1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #include <linux/bcd.h>
6 
7 #include "main.h"
8 #include "reg.h"
9 #include "fw.h"
10 #include "phy.h"
11 #include "debug.h"
12 
13 struct phy_cfg_pair {
14 	u32 addr;
15 	u32 data;
16 };
17 
18 union phy_table_tile {
19 	struct rtw_phy_cond cond;
20 	struct phy_cfg_pair cfg;
21 };
22 
23 static const u32 db_invert_table[12][8] = {
24 	{10,		13,		16,		20,
25 	 25,		32,		40,		50},
26 	{64,		80,		101,		128,
27 	 160,		201,		256,		318},
28 	{401,		505,		635,		800,
29 	 1007,		1268,		1596,		2010},
30 	{316,		398,		501,		631,
31 	 794,		1000,		1259,		1585},
32 	{1995,		2512,		3162,		3981,
33 	 5012,		6310,		7943,		10000},
34 	{12589,		15849,		19953,		25119,
35 	 31623,		39811,		50119,		63098},
36 	{79433,		100000,		125893,		158489,
37 	 199526,	251189,		316228,		398107},
38 	{501187,	630957,		794328,		1000000,
39 	 1258925,	1584893,	1995262,	2511886},
40 	{3162278,	3981072,	5011872,	6309573,
41 	 7943282,	1000000,	12589254,	15848932},
42 	{19952623,	25118864,	31622777,	39810717,
43 	 50118723,	63095734,	79432823,	100000000},
44 	{125892541,	158489319,	199526232,	251188643,
45 	 316227766,	398107171,	501187234,	630957345},
46 	{794328235,	1000000000,	1258925412,	1584893192,
47 	 1995262315,	2511886432U,	3162277660U,	3981071706U}
48 };
49 
50 u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M };
51 u8 rtw_ofdm_rates[] = {
52 	DESC_RATE6M,  DESC_RATE9M,  DESC_RATE12M,
53 	DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
54 	DESC_RATE48M, DESC_RATE54M
55 };
56 u8 rtw_ht_1s_rates[] = {
57 	DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
58 	DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
59 	DESC_RATEMCS6, DESC_RATEMCS7
60 };
61 u8 rtw_ht_2s_rates[] = {
62 	DESC_RATEMCS8,  DESC_RATEMCS9,  DESC_RATEMCS10,
63 	DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13,
64 	DESC_RATEMCS14, DESC_RATEMCS15
65 };
66 u8 rtw_vht_1s_rates[] = {
67 	DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
68 	DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
69 	DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
70 	DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
71 	DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9
72 };
73 u8 rtw_vht_2s_rates[] = {
74 	DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
75 	DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
76 	DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
77 	DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
78 	DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9
79 };
80 u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = {
81 	rtw_cck_rates, rtw_ofdm_rates,
82 	rtw_ht_1s_rates, rtw_ht_2s_rates,
83 	rtw_vht_1s_rates, rtw_vht_2s_rates
84 };
85 EXPORT_SYMBOL(rtw_rate_section);
86 
87 u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = {
88 	ARRAY_SIZE(rtw_cck_rates),
89 	ARRAY_SIZE(rtw_ofdm_rates),
90 	ARRAY_SIZE(rtw_ht_1s_rates),
91 	ARRAY_SIZE(rtw_ht_2s_rates),
92 	ARRAY_SIZE(rtw_vht_1s_rates),
93 	ARRAY_SIZE(rtw_vht_2s_rates)
94 };
95 EXPORT_SYMBOL(rtw_rate_size);
96 
97 static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates);
98 static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates);
99 static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates);
100 static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates);
101 static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates);
102 static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates);
103 
104 enum rtw_phy_band_type {
105 	PHY_BAND_2G	= 0,
106 	PHY_BAND_5G	= 1,
107 };
108 
109 static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev)
110 {
111 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
112 	u8 i, j;
113 
114 	for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) {
115 		for (j = 0; j < RTW_RF_PATH_MAX; j++)
116 			dm_info->cck_pd_lv[i][j] = CCK_PD_LV0;
117 	}
118 
119 	dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
120 }
121 
122 void rtw_phy_init(struct rtw_dev *rtwdev)
123 {
124 	struct rtw_chip_info *chip = rtwdev->chip;
125 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
126 	u32 addr, mask;
127 
128 	dm_info->fa_history[3] = 0;
129 	dm_info->fa_history[2] = 0;
130 	dm_info->fa_history[1] = 0;
131 	dm_info->fa_history[0] = 0;
132 	dm_info->igi_bitmap = 0;
133 	dm_info->igi_history[3] = 0;
134 	dm_info->igi_history[2] = 0;
135 	dm_info->igi_history[1] = 0;
136 
137 	addr = chip->dig[0].addr;
138 	mask = chip->dig[0].mask;
139 	dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
140 	rtw_phy_cck_pd_init(rtwdev);
141 
142 	dm_info->iqk.done = false;
143 }
144 EXPORT_SYMBOL(rtw_phy_init);
145 
146 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
147 {
148 	struct rtw_chip_info *chip = rtwdev->chip;
149 	struct rtw_hal *hal = &rtwdev->hal;
150 	u32 addr, mask;
151 	u8 path;
152 
153 	if (chip->dig_cck) {
154 		const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
155 		rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
156 	}
157 
158 	for (path = 0; path < hal->rf_path_num; path++) {
159 		addr = chip->dig[path].addr;
160 		mask = chip->dig[path].mask;
161 		rtw_write32_mask(rtwdev, addr, mask, igi);
162 	}
163 }
164 
165 static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)
166 {
167 	struct rtw_chip_info *chip = rtwdev->chip;
168 
169 	chip->ops->false_alarm_statistics(rtwdev);
170 }
171 
172 #define RA_FLOOR_TABLE_SIZE	7
173 #define RA_FLOOR_UP_GAP		3
174 
175 static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi)
176 {
177 	u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
178 	u8 new_level = 0;
179 	int i;
180 
181 	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
182 		if (i >= old_level)
183 			table[i] += RA_FLOOR_UP_GAP;
184 
185 	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
186 		if (rssi < table[i]) {
187 			new_level = i;
188 			break;
189 		}
190 	}
191 
192 	return new_level;
193 }
194 
195 struct rtw_phy_stat_iter_data {
196 	struct rtw_dev *rtwdev;
197 	u8 min_rssi;
198 };
199 
200 static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta)
201 {
202 	struct rtw_phy_stat_iter_data *iter_data = data;
203 	struct rtw_dev *rtwdev = iter_data->rtwdev;
204 	struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
205 	u8 rssi;
206 
207 	rssi = ewma_rssi_read(&si->avg_rssi);
208 	si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi);
209 
210 	rtw_fw_send_rssi_info(rtwdev, si);
211 
212 	iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi);
213 }
214 
215 static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev)
216 {
217 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
218 	struct rtw_phy_stat_iter_data data = {};
219 
220 	data.rtwdev = rtwdev;
221 	data.min_rssi = U8_MAX;
222 	rtw_iterate_stas_atomic(rtwdev, rtw_phy_stat_rssi_iter, &data);
223 
224 	dm_info->pre_min_rssi = dm_info->min_rssi;
225 	dm_info->min_rssi = data.min_rssi;
226 }
227 
228 static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev)
229 {
230 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
231 
232 	dm_info->last_pkt_count = dm_info->cur_pkt_count;
233 	memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count));
234 }
235 
236 static void rtw_phy_statistics(struct rtw_dev *rtwdev)
237 {
238 	rtw_phy_stat_rssi(rtwdev);
239 	rtw_phy_stat_false_alarm(rtwdev);
240 	rtw_phy_stat_rate_cnt(rtwdev);
241 }
242 
243 #define DIG_PERF_FA_TH_LOW			250
244 #define DIG_PERF_FA_TH_HIGH			500
245 #define DIG_PERF_FA_TH_EXTRA_HIGH		750
246 #define DIG_PERF_MAX				0x5a
247 #define DIG_PERF_MID				0x40
248 #define DIG_CVRG_FA_TH_LOW			2000
249 #define DIG_CVRG_FA_TH_HIGH			4000
250 #define DIG_CVRG_FA_TH_EXTRA_HIGH		5000
251 #define DIG_CVRG_MAX				0x2a
252 #define DIG_CVRG_MID				0x26
253 #define DIG_CVRG_MIN				0x1c
254 #define DIG_RSSI_GAIN_OFFSET			15
255 
256 static bool
257 rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info)
258 {
259 	u16 fa_lo = DIG_PERF_FA_TH_LOW;
260 	u16 fa_hi = DIG_PERF_FA_TH_HIGH;
261 	u16 *fa_history;
262 	u8 *igi_history;
263 	u8 damping_rssi;
264 	u8 min_rssi;
265 	u8 diff;
266 	u8 igi_bitmap;
267 	bool damping = false;
268 
269 	min_rssi = dm_info->min_rssi;
270 	if (dm_info->damping) {
271 		damping_rssi = dm_info->damping_rssi;
272 		diff = min_rssi > damping_rssi ? min_rssi - damping_rssi :
273 						 damping_rssi - min_rssi;
274 		if (diff > 3 || dm_info->damping_cnt++ > 20) {
275 			dm_info->damping = false;
276 			return false;
277 		}
278 
279 		return true;
280 	}
281 
282 	igi_history = dm_info->igi_history;
283 	fa_history = dm_info->fa_history;
284 	igi_bitmap = dm_info->igi_bitmap & 0xf;
285 	switch (igi_bitmap) {
286 	case 5:
287 		/* down -> up -> down -> up */
288 		if (igi_history[0] > igi_history[1] &&
289 		    igi_history[2] > igi_history[3] &&
290 		    igi_history[0] - igi_history[1] >= 2 &&
291 		    igi_history[2] - igi_history[3] >= 2 &&
292 		    fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
293 		    fa_history[2] > fa_hi && fa_history[3] < fa_lo)
294 			damping = true;
295 		break;
296 	case 9:
297 		/* up -> down -> down -> up */
298 		if (igi_history[0] > igi_history[1] &&
299 		    igi_history[3] > igi_history[2] &&
300 		    igi_history[0] - igi_history[1] >= 4 &&
301 		    igi_history[3] - igi_history[2] >= 2 &&
302 		    fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
303 		    fa_history[2] < fa_lo && fa_history[3] > fa_hi)
304 			damping = true;
305 		break;
306 	default:
307 		return false;
308 	}
309 
310 	if (damping) {
311 		dm_info->damping = true;
312 		dm_info->damping_cnt = 0;
313 		dm_info->damping_rssi = min_rssi;
314 	}
315 
316 	return damping;
317 }
318 
319 static void rtw_phy_dig_get_boundary(struct rtw_dm_info *dm_info,
320 				     u8 *upper, u8 *lower, bool linked)
321 {
322 	u8 dig_max, dig_min, dig_mid;
323 	u8 min_rssi;
324 
325 	if (linked) {
326 		dig_max = DIG_PERF_MAX;
327 		dig_mid = DIG_PERF_MID;
328 		/* 22B=0x1c, 22C=0x20 */
329 		dig_min = 0x1c;
330 		min_rssi = max_t(u8, dm_info->min_rssi, dig_min);
331 	} else {
332 		dig_max = DIG_CVRG_MAX;
333 		dig_mid = DIG_CVRG_MID;
334 		dig_min = DIG_CVRG_MIN;
335 		min_rssi = dig_min;
336 	}
337 
338 	/* DIG MAX should be bounded by minimum RSSI with offset +15 */
339 	dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET);
340 
341 	*lower = clamp_t(u8, min_rssi, dig_min, dig_mid);
342 	*upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max);
343 }
344 
345 static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info,
346 				      u16 *fa_th, u8 *step, bool linked)
347 {
348 	u8 min_rssi, pre_min_rssi;
349 
350 	min_rssi = dm_info->min_rssi;
351 	pre_min_rssi = dm_info->pre_min_rssi;
352 	step[0] = 4;
353 	step[1] = 3;
354 	step[2] = 2;
355 
356 	if (linked) {
357 		fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
358 		fa_th[1] = DIG_PERF_FA_TH_HIGH;
359 		fa_th[2] = DIG_PERF_FA_TH_LOW;
360 		if (pre_min_rssi > min_rssi) {
361 			step[0] = 6;
362 			step[1] = 4;
363 			step[2] = 2;
364 		}
365 	} else {
366 		fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
367 		fa_th[1] = DIG_CVRG_FA_TH_HIGH;
368 		fa_th[2] = DIG_CVRG_FA_TH_LOW;
369 	}
370 }
371 
372 static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa)
373 {
374 	u8 *igi_history;
375 	u16 *fa_history;
376 	u8 igi_bitmap;
377 	bool up;
378 
379 	igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
380 	igi_history = dm_info->igi_history;
381 	fa_history = dm_info->fa_history;
382 
383 	up = igi > igi_history[0];
384 	igi_bitmap |= up;
385 
386 	igi_history[3] = igi_history[2];
387 	igi_history[2] = igi_history[1];
388 	igi_history[1] = igi_history[0];
389 	igi_history[0] = igi;
390 
391 	fa_history[3] = fa_history[2];
392 	fa_history[2] = fa_history[1];
393 	fa_history[1] = fa_history[0];
394 	fa_history[0] = fa;
395 
396 	dm_info->igi_bitmap = igi_bitmap;
397 }
398 
399 static void rtw_phy_dig(struct rtw_dev *rtwdev)
400 {
401 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
402 	u8 upper_bound, lower_bound;
403 	u8 pre_igi, cur_igi;
404 	u16 fa_th[3], fa_cnt;
405 	u8 level;
406 	u8 step[3];
407 	bool linked;
408 
409 	if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags))
410 		return;
411 
412 	if (rtw_phy_dig_check_damping(dm_info))
413 		return;
414 
415 	linked = !!rtwdev->sta_cnt;
416 
417 	fa_cnt = dm_info->total_fa_cnt;
418 	pre_igi = dm_info->igi_history[0];
419 
420 	rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked);
421 
422 	/* test the false alarm count from the highest threshold level first,
423 	 * and increase it by corresponding step size
424 	 *
425 	 * note that the step size is offset by -2, compensate it afterall
426 	 */
427 	cur_igi = pre_igi;
428 	for (level = 0; level < 3; level++) {
429 		if (fa_cnt > fa_th[level]) {
430 			cur_igi += step[level];
431 			break;
432 		}
433 	}
434 	cur_igi -= 2;
435 
436 	/* calculate the upper/lower bound by the minimum rssi we have among
437 	 * the peers connected with us, meanwhile make sure the igi value does
438 	 * not beyond the hardware limitation
439 	 */
440 	rtw_phy_dig_get_boundary(dm_info, &upper_bound, &lower_bound, linked);
441 	cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound);
442 
443 	/* record current igi value and false alarm statistics for further
444 	 * damping checks, and record the trend of igi values
445 	 */
446 	rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt);
447 
448 	if (cur_igi != pre_igi)
449 		rtw_phy_dig_write(rtwdev, cur_igi);
450 }
451 
452 static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta)
453 {
454 	struct rtw_dev *rtwdev = data;
455 	struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
456 
457 	rtw_update_sta_info(rtwdev, si);
458 }
459 
460 static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev)
461 {
462 	if (rtwdev->watch_dog_cnt & 0x3)
463 		return;
464 
465 	rtw_iterate_stas_atomic(rtwdev, rtw_phy_ra_info_update_iter, rtwdev);
466 }
467 
468 static void rtw_phy_dpk_track(struct rtw_dev *rtwdev)
469 {
470 	struct rtw_chip_info *chip = rtwdev->chip;
471 
472 	if (chip->ops->dpk_track)
473 		chip->ops->dpk_track(rtwdev);
474 }
475 
476 #define CCK_PD_FA_LV1_MIN	1000
477 #define CCK_PD_FA_LV0_MAX	500
478 
479 static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev)
480 {
481 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
482 	u32 cck_fa_avg = dm_info->cck_fa_avg;
483 
484 	if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
485 		return CCK_PD_LV1;
486 
487 	if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
488 		return CCK_PD_LV0;
489 
490 	return CCK_PD_LV_MAX;
491 }
492 
493 #define CCK_PD_IGI_LV4_VAL 0x38
494 #define CCK_PD_IGI_LV3_VAL 0x2a
495 #define CCK_PD_IGI_LV2_VAL 0x24
496 #define CCK_PD_RSSI_LV4_VAL 32
497 #define CCK_PD_RSSI_LV3_VAL 32
498 #define CCK_PD_RSSI_LV2_VAL 24
499 
500 static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev)
501 {
502 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
503 	u8 igi = dm_info->igi_history[0];
504 	u8 rssi = dm_info->min_rssi;
505 	u32 cck_fa_avg = dm_info->cck_fa_avg;
506 
507 	if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL)
508 		return CCK_PD_LV4;
509 	if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL)
510 		return CCK_PD_LV3;
511 	if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL)
512 		return CCK_PD_LV2;
513 	if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
514 		return CCK_PD_LV1;
515 	if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
516 		return CCK_PD_LV0;
517 
518 	return CCK_PD_LV_MAX;
519 }
520 
521 static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev)
522 {
523 	if (!rtw_is_assoc(rtwdev))
524 		return rtw_phy_cck_pd_lv_unlink(rtwdev);
525 	else
526 		return rtw_phy_cck_pd_lv_link(rtwdev);
527 }
528 
529 static void rtw_phy_cck_pd(struct rtw_dev *rtwdev)
530 {
531 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
532 	struct rtw_chip_info *chip = rtwdev->chip;
533 	u32 cck_fa = dm_info->cck_fa_cnt;
534 	u8 level;
535 
536 	if (rtwdev->hal.current_band_type != RTW_BAND_2G)
537 		return;
538 
539 	if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET)
540 		dm_info->cck_fa_avg = cck_fa;
541 	else
542 		dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2;
543 
544 	rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n",
545 		dm_info->igi_history[0], dm_info->min_rssi,
546 		dm_info->fa_history[0]);
547 	rtw_dbg(rtwdev, RTW_DBG_PHY, "cck_fa_avg=%d, cck_pd_default=%d\n",
548 		dm_info->cck_fa_avg, dm_info->cck_pd_default);
549 
550 	level = rtw_phy_cck_pd_lv(rtwdev);
551 
552 	if (level >= CCK_PD_LV_MAX)
553 		return;
554 
555 	if (chip->ops->cck_pd_set)
556 		chip->ops->cck_pd_set(rtwdev, level);
557 }
558 
559 static void rtw_phy_pwr_track(struct rtw_dev *rtwdev)
560 {
561 	rtwdev->chip->ops->pwr_track(rtwdev);
562 }
563 
564 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev)
565 {
566 	/* for further calculation */
567 	rtw_phy_statistics(rtwdev);
568 	rtw_phy_dig(rtwdev);
569 	rtw_phy_cck_pd(rtwdev);
570 	rtw_phy_ra_info_update(rtwdev);
571 	rtw_phy_dpk_track(rtwdev);
572 	rtw_phy_pwr_track(rtwdev);
573 }
574 
575 #define FRAC_BITS 3
576 
577 static u8 rtw_phy_power_2_db(s8 power)
578 {
579 	if (power <= -100 || power >= 20)
580 		return 0;
581 	else if (power >= 0)
582 		return 100;
583 	else
584 		return 100 + power;
585 }
586 
587 static u64 rtw_phy_db_2_linear(u8 power_db)
588 {
589 	u8 i, j;
590 	u64 linear;
591 
592 	if (power_db > 96)
593 		power_db = 96;
594 	else if (power_db < 1)
595 		return 1;
596 
597 	/* 1dB ~ 96dB */
598 	i = (power_db - 1) >> 3;
599 	j = (power_db - 1) - (i << 3);
600 
601 	linear = db_invert_table[i][j];
602 	linear = i > 2 ? linear << FRAC_BITS : linear;
603 
604 	return linear;
605 }
606 
607 static u8 rtw_phy_linear_2_db(u64 linear)
608 {
609 	u8 i;
610 	u8 j;
611 	u32 dB;
612 
613 	if (linear >= db_invert_table[11][7])
614 		return 96; /* maximum 96 dB */
615 
616 	for (i = 0; i < 12; i++) {
617 		if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7])
618 			break;
619 		else if (i > 2 && linear <= db_invert_table[i][7])
620 			break;
621 	}
622 
623 	for (j = 0; j < 8; j++) {
624 		if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
625 			break;
626 		else if (i > 2 && linear <= db_invert_table[i][j])
627 			break;
628 	}
629 
630 	if (j == 0 && i == 0)
631 		goto end;
632 
633 	if (j == 0) {
634 		if (i != 3) {
635 			if (db_invert_table[i][0] - linear >
636 			    linear - db_invert_table[i - 1][7]) {
637 				i = i - 1;
638 				j = 7;
639 			}
640 		} else {
641 			if (db_invert_table[3][0] - linear >
642 			    linear - db_invert_table[2][7]) {
643 				i = 2;
644 				j = 7;
645 			}
646 		}
647 	} else {
648 		if (db_invert_table[i][j] - linear >
649 		    linear - db_invert_table[i][j - 1]) {
650 			j = j - 1;
651 		}
652 	}
653 end:
654 	dB = (i << 3) + j + 1;
655 
656 	return dB;
657 }
658 
659 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num)
660 {
661 	s8 power;
662 	u8 power_db;
663 	u64 linear;
664 	u64 sum = 0;
665 	u8 path;
666 
667 	for (path = 0; path < path_num; path++) {
668 		power = rf_power[path];
669 		power_db = rtw_phy_power_2_db(power);
670 		linear = rtw_phy_db_2_linear(power_db);
671 		sum += linear;
672 	}
673 
674 	sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
675 	switch (path_num) {
676 	case 2:
677 		sum >>= 1;
678 		break;
679 	case 3:
680 		sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5;
681 		break;
682 	case 4:
683 		sum >>= 2;
684 		break;
685 	default:
686 		break;
687 	}
688 
689 	return rtw_phy_linear_2_db(sum);
690 }
691 EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi);
692 
693 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
694 		    u32 addr, u32 mask)
695 {
696 	struct rtw_hal *hal = &rtwdev->hal;
697 	struct rtw_chip_info *chip = rtwdev->chip;
698 	const u32 *base_addr = chip->rf_base_addr;
699 	u32 val, direct_addr;
700 
701 	if (rf_path >= hal->rf_phy_num) {
702 		rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
703 		return INV_RF_DATA;
704 	}
705 
706 	addr &= 0xff;
707 	direct_addr = base_addr[rf_path] + (addr << 2);
708 	mask &= RFREG_MASK;
709 
710 	val = rtw_read32_mask(rtwdev, direct_addr, mask);
711 
712 	return val;
713 }
714 EXPORT_SYMBOL(rtw_phy_read_rf);
715 
716 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
717 			 u32 addr, u32 mask)
718 {
719 	struct rtw_hal *hal = &rtwdev->hal;
720 	struct rtw_chip_info *chip = rtwdev->chip;
721 	const struct rtw_rf_sipi_addr *rf_sipi_addr;
722 	const struct rtw_rf_sipi_addr *rf_sipi_addr_a;
723 	u32 val32;
724 	u32 en_pi;
725 	u32 r_addr;
726 	u32 shift;
727 
728 	if (rf_path >= hal->rf_phy_num) {
729 		rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
730 		return INV_RF_DATA;
731 	}
732 
733 	if (!chip->rf_sipi_read_addr) {
734 		rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n");
735 		return INV_RF_DATA;
736 	}
737 
738 	rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path];
739 	rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A];
740 
741 	addr &= 0xff;
742 
743 	val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2);
744 	val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23);
745 	rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32);
746 
747 	/* toggle read edge of path A */
748 	val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2);
749 	rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK);
750 	rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK);
751 
752 	udelay(120);
753 
754 	en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8));
755 	r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read;
756 
757 	val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK);
758 
759 	shift = __ffs(mask);
760 
761 	return (val32 & mask) >> shift;
762 }
763 EXPORT_SYMBOL(rtw_phy_read_rf_sipi);
764 
765 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
766 			       u32 addr, u32 mask, u32 data)
767 {
768 	struct rtw_hal *hal = &rtwdev->hal;
769 	struct rtw_chip_info *chip = rtwdev->chip;
770 	u32 *sipi_addr = chip->rf_sipi_addr;
771 	u32 data_and_addr;
772 	u32 old_data = 0;
773 	u32 shift;
774 
775 	if (rf_path >= hal->rf_phy_num) {
776 		rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
777 		return false;
778 	}
779 
780 	addr &= 0xff;
781 	mask &= RFREG_MASK;
782 
783 	if (mask != RFREG_MASK) {
784 		old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK);
785 
786 		if (old_data == INV_RF_DATA) {
787 			rtw_err(rtwdev, "Write fail, rf is disabled\n");
788 			return false;
789 		}
790 
791 		shift = __ffs(mask);
792 		data = ((old_data) & (~mask)) | (data << shift);
793 	}
794 
795 	data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
796 
797 	rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr);
798 
799 	udelay(13);
800 
801 	return true;
802 }
803 EXPORT_SYMBOL(rtw_phy_write_rf_reg_sipi);
804 
805 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
806 			  u32 addr, u32 mask, u32 data)
807 {
808 	struct rtw_hal *hal = &rtwdev->hal;
809 	struct rtw_chip_info *chip = rtwdev->chip;
810 	const u32 *base_addr = chip->rf_base_addr;
811 	u32 direct_addr;
812 
813 	if (rf_path >= hal->rf_phy_num) {
814 		rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
815 		return false;
816 	}
817 
818 	addr &= 0xff;
819 	direct_addr = base_addr[rf_path] + (addr << 2);
820 	mask &= RFREG_MASK;
821 
822 	rtw_write32_mask(rtwdev, direct_addr, mask, data);
823 
824 	udelay(1);
825 
826 	return true;
827 }
828 
829 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
830 			      u32 addr, u32 mask, u32 data)
831 {
832 	if (addr != 0x00)
833 		return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data);
834 
835 	return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data);
836 }
837 EXPORT_SYMBOL(rtw_phy_write_rf_reg_mix);
838 
839 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg)
840 {
841 	struct rtw_hal *hal = &rtwdev->hal;
842 	struct rtw_efuse *efuse = &rtwdev->efuse;
843 	struct rtw_phy_cond cond = {0};
844 
845 	cond.cut = hal->cut_version ? hal->cut_version : 15;
846 	cond.pkg = pkg ? pkg : 15;
847 	cond.plat = 0x04;
848 	cond.rfe = efuse->rfe_option;
849 
850 	switch (rtw_hci_type(rtwdev)) {
851 	case RTW_HCI_TYPE_USB:
852 		cond.intf = INTF_USB;
853 		break;
854 	case RTW_HCI_TYPE_SDIO:
855 		cond.intf = INTF_SDIO;
856 		break;
857 	case RTW_HCI_TYPE_PCIE:
858 	default:
859 		cond.intf = INTF_PCIE;
860 		break;
861 	}
862 
863 	hal->phy_cond = cond;
864 
865 	rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond));
866 }
867 
868 static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond)
869 {
870 	struct rtw_hal *hal = &rtwdev->hal;
871 	struct rtw_phy_cond drv_cond = hal->phy_cond;
872 
873 	if (cond.cut && cond.cut != drv_cond.cut)
874 		return false;
875 
876 	if (cond.pkg && cond.pkg != drv_cond.pkg)
877 		return false;
878 
879 	if (cond.intf && cond.intf != drv_cond.intf)
880 		return false;
881 
882 	if (cond.rfe != drv_cond.rfe)
883 		return false;
884 
885 	return true;
886 }
887 
888 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
889 {
890 	const union phy_table_tile *p = tbl->data;
891 	const union phy_table_tile *end = p + tbl->size / 2;
892 	struct rtw_phy_cond pos_cond = {0};
893 	bool is_matched = true, is_skipped = false;
894 
895 	BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair));
896 
897 	for (; p < end; p++) {
898 		if (p->cond.pos) {
899 			switch (p->cond.branch) {
900 			case BRANCH_ENDIF:
901 				is_matched = true;
902 				is_skipped = false;
903 				break;
904 			case BRANCH_ELSE:
905 				is_matched = is_skipped ? false : true;
906 				break;
907 			case BRANCH_IF:
908 			case BRANCH_ELIF:
909 			default:
910 				pos_cond = p->cond;
911 				break;
912 			}
913 		} else if (p->cond.neg) {
914 			if (!is_skipped) {
915 				if (check_positive(rtwdev, pos_cond)) {
916 					is_matched = true;
917 					is_skipped = true;
918 				} else {
919 					is_matched = false;
920 					is_skipped = false;
921 				}
922 			} else {
923 				is_matched = false;
924 			}
925 		} else if (is_matched) {
926 			(*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data);
927 		}
928 	}
929 }
930 EXPORT_SYMBOL(rtw_parse_tbl_phy_cond);
931 
932 #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8))
933 
934 static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i)
935 {
936 	if (rtwdev->chip->is_pwr_by_rate_dec)
937 		return bcd_to_dec_pwr_by_rate(hex, i);
938 
939 	return (hex >> (i * 8)) & 0xFF;
940 }
941 
942 static void
943 rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev,
944 					 u32 addr, u32 mask, u32 val, u8 *rate,
945 					 u8 *pwr_by_rate, u8 *rate_num)
946 {
947 	int i;
948 
949 	switch (addr) {
950 	case 0xE00:
951 	case 0x830:
952 		rate[0] = DESC_RATE6M;
953 		rate[1] = DESC_RATE9M;
954 		rate[2] = DESC_RATE12M;
955 		rate[3] = DESC_RATE18M;
956 		for (i = 0; i < 4; ++i)
957 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
958 		*rate_num = 4;
959 		break;
960 	case 0xE04:
961 	case 0x834:
962 		rate[0] = DESC_RATE24M;
963 		rate[1] = DESC_RATE36M;
964 		rate[2] = DESC_RATE48M;
965 		rate[3] = DESC_RATE54M;
966 		for (i = 0; i < 4; ++i)
967 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
968 		*rate_num = 4;
969 		break;
970 	case 0xE08:
971 		rate[0] = DESC_RATE1M;
972 		pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1);
973 		*rate_num = 1;
974 		break;
975 	case 0x86C:
976 		if (mask == 0xffffff00) {
977 			rate[0] = DESC_RATE2M;
978 			rate[1] = DESC_RATE5_5M;
979 			rate[2] = DESC_RATE11M;
980 			for (i = 1; i < 4; ++i)
981 				pwr_by_rate[i - 1] =
982 					tbl_to_dec_pwr_by_rate(rtwdev, val, i);
983 			*rate_num = 3;
984 		} else if (mask == 0x000000ff) {
985 			rate[0] = DESC_RATE11M;
986 			pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0);
987 			*rate_num = 1;
988 		}
989 		break;
990 	case 0xE10:
991 	case 0x83C:
992 		rate[0] = DESC_RATEMCS0;
993 		rate[1] = DESC_RATEMCS1;
994 		rate[2] = DESC_RATEMCS2;
995 		rate[3] = DESC_RATEMCS3;
996 		for (i = 0; i < 4; ++i)
997 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
998 		*rate_num = 4;
999 		break;
1000 	case 0xE14:
1001 	case 0x848:
1002 		rate[0] = DESC_RATEMCS4;
1003 		rate[1] = DESC_RATEMCS5;
1004 		rate[2] = DESC_RATEMCS6;
1005 		rate[3] = DESC_RATEMCS7;
1006 		for (i = 0; i < 4; ++i)
1007 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1008 		*rate_num = 4;
1009 		break;
1010 	case 0xE18:
1011 	case 0x84C:
1012 		rate[0] = DESC_RATEMCS8;
1013 		rate[1] = DESC_RATEMCS9;
1014 		rate[2] = DESC_RATEMCS10;
1015 		rate[3] = DESC_RATEMCS11;
1016 		for (i = 0; i < 4; ++i)
1017 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1018 		*rate_num = 4;
1019 		break;
1020 	case 0xE1C:
1021 	case 0x868:
1022 		rate[0] = DESC_RATEMCS12;
1023 		rate[1] = DESC_RATEMCS13;
1024 		rate[2] = DESC_RATEMCS14;
1025 		rate[3] = DESC_RATEMCS15;
1026 		for (i = 0; i < 4; ++i)
1027 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1028 		*rate_num = 4;
1029 		break;
1030 	case 0x838:
1031 		rate[0] = DESC_RATE1M;
1032 		rate[1] = DESC_RATE2M;
1033 		rate[2] = DESC_RATE5_5M;
1034 		for (i = 1; i < 4; ++i)
1035 			pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev,
1036 								    val, i);
1037 		*rate_num = 3;
1038 		break;
1039 	case 0xC20:
1040 	case 0xE20:
1041 	case 0x1820:
1042 	case 0x1A20:
1043 		rate[0] = DESC_RATE1M;
1044 		rate[1] = DESC_RATE2M;
1045 		rate[2] = DESC_RATE5_5M;
1046 		rate[3] = DESC_RATE11M;
1047 		for (i = 0; i < 4; ++i)
1048 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1049 		*rate_num = 4;
1050 		break;
1051 	case 0xC24:
1052 	case 0xE24:
1053 	case 0x1824:
1054 	case 0x1A24:
1055 		rate[0] = DESC_RATE6M;
1056 		rate[1] = DESC_RATE9M;
1057 		rate[2] = DESC_RATE12M;
1058 		rate[3] = DESC_RATE18M;
1059 		for (i = 0; i < 4; ++i)
1060 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1061 		*rate_num = 4;
1062 		break;
1063 	case 0xC28:
1064 	case 0xE28:
1065 	case 0x1828:
1066 	case 0x1A28:
1067 		rate[0] = DESC_RATE24M;
1068 		rate[1] = DESC_RATE36M;
1069 		rate[2] = DESC_RATE48M;
1070 		rate[3] = DESC_RATE54M;
1071 		for (i = 0; i < 4; ++i)
1072 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1073 		*rate_num = 4;
1074 		break;
1075 	case 0xC2C:
1076 	case 0xE2C:
1077 	case 0x182C:
1078 	case 0x1A2C:
1079 		rate[0] = DESC_RATEMCS0;
1080 		rate[1] = DESC_RATEMCS1;
1081 		rate[2] = DESC_RATEMCS2;
1082 		rate[3] = DESC_RATEMCS3;
1083 		for (i = 0; i < 4; ++i)
1084 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1085 		*rate_num = 4;
1086 		break;
1087 	case 0xC30:
1088 	case 0xE30:
1089 	case 0x1830:
1090 	case 0x1A30:
1091 		rate[0] = DESC_RATEMCS4;
1092 		rate[1] = DESC_RATEMCS5;
1093 		rate[2] = DESC_RATEMCS6;
1094 		rate[3] = DESC_RATEMCS7;
1095 		for (i = 0; i < 4; ++i)
1096 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1097 		*rate_num = 4;
1098 		break;
1099 	case 0xC34:
1100 	case 0xE34:
1101 	case 0x1834:
1102 	case 0x1A34:
1103 		rate[0] = DESC_RATEMCS8;
1104 		rate[1] = DESC_RATEMCS9;
1105 		rate[2] = DESC_RATEMCS10;
1106 		rate[3] = DESC_RATEMCS11;
1107 		for (i = 0; i < 4; ++i)
1108 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1109 		*rate_num = 4;
1110 		break;
1111 	case 0xC38:
1112 	case 0xE38:
1113 	case 0x1838:
1114 	case 0x1A38:
1115 		rate[0] = DESC_RATEMCS12;
1116 		rate[1] = DESC_RATEMCS13;
1117 		rate[2] = DESC_RATEMCS14;
1118 		rate[3] = DESC_RATEMCS15;
1119 		for (i = 0; i < 4; ++i)
1120 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1121 		*rate_num = 4;
1122 		break;
1123 	case 0xC3C:
1124 	case 0xE3C:
1125 	case 0x183C:
1126 	case 0x1A3C:
1127 		rate[0] = DESC_RATEVHT1SS_MCS0;
1128 		rate[1] = DESC_RATEVHT1SS_MCS1;
1129 		rate[2] = DESC_RATEVHT1SS_MCS2;
1130 		rate[3] = DESC_RATEVHT1SS_MCS3;
1131 		for (i = 0; i < 4; ++i)
1132 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1133 		*rate_num = 4;
1134 		break;
1135 	case 0xC40:
1136 	case 0xE40:
1137 	case 0x1840:
1138 	case 0x1A40:
1139 		rate[0] = DESC_RATEVHT1SS_MCS4;
1140 		rate[1] = DESC_RATEVHT1SS_MCS5;
1141 		rate[2] = DESC_RATEVHT1SS_MCS6;
1142 		rate[3] = DESC_RATEVHT1SS_MCS7;
1143 		for (i = 0; i < 4; ++i)
1144 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1145 		*rate_num = 4;
1146 		break;
1147 	case 0xC44:
1148 	case 0xE44:
1149 	case 0x1844:
1150 	case 0x1A44:
1151 		rate[0] = DESC_RATEVHT1SS_MCS8;
1152 		rate[1] = DESC_RATEVHT1SS_MCS9;
1153 		rate[2] = DESC_RATEVHT2SS_MCS0;
1154 		rate[3] = DESC_RATEVHT2SS_MCS1;
1155 		for (i = 0; i < 4; ++i)
1156 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1157 		*rate_num = 4;
1158 		break;
1159 	case 0xC48:
1160 	case 0xE48:
1161 	case 0x1848:
1162 	case 0x1A48:
1163 		rate[0] = DESC_RATEVHT2SS_MCS2;
1164 		rate[1] = DESC_RATEVHT2SS_MCS3;
1165 		rate[2] = DESC_RATEVHT2SS_MCS4;
1166 		rate[3] = DESC_RATEVHT2SS_MCS5;
1167 		for (i = 0; i < 4; ++i)
1168 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1169 		*rate_num = 4;
1170 		break;
1171 	case 0xC4C:
1172 	case 0xE4C:
1173 	case 0x184C:
1174 	case 0x1A4C:
1175 		rate[0] = DESC_RATEVHT2SS_MCS6;
1176 		rate[1] = DESC_RATEVHT2SS_MCS7;
1177 		rate[2] = DESC_RATEVHT2SS_MCS8;
1178 		rate[3] = DESC_RATEVHT2SS_MCS9;
1179 		for (i = 0; i < 4; ++i)
1180 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1181 		*rate_num = 4;
1182 		break;
1183 	case 0xCD8:
1184 	case 0xED8:
1185 	case 0x18D8:
1186 	case 0x1AD8:
1187 		rate[0] = DESC_RATEMCS16;
1188 		rate[1] = DESC_RATEMCS17;
1189 		rate[2] = DESC_RATEMCS18;
1190 		rate[3] = DESC_RATEMCS19;
1191 		for (i = 0; i < 4; ++i)
1192 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1193 		*rate_num = 4;
1194 		break;
1195 	case 0xCDC:
1196 	case 0xEDC:
1197 	case 0x18DC:
1198 	case 0x1ADC:
1199 		rate[0] = DESC_RATEMCS20;
1200 		rate[1] = DESC_RATEMCS21;
1201 		rate[2] = DESC_RATEMCS22;
1202 		rate[3] = DESC_RATEMCS23;
1203 		for (i = 0; i < 4; ++i)
1204 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1205 		*rate_num = 4;
1206 		break;
1207 	case 0xCE0:
1208 	case 0xEE0:
1209 	case 0x18E0:
1210 	case 0x1AE0:
1211 		rate[0] = DESC_RATEVHT3SS_MCS0;
1212 		rate[1] = DESC_RATEVHT3SS_MCS1;
1213 		rate[2] = DESC_RATEVHT3SS_MCS2;
1214 		rate[3] = DESC_RATEVHT3SS_MCS3;
1215 		for (i = 0; i < 4; ++i)
1216 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1217 		*rate_num = 4;
1218 		break;
1219 	case 0xCE4:
1220 	case 0xEE4:
1221 	case 0x18E4:
1222 	case 0x1AE4:
1223 		rate[0] = DESC_RATEVHT3SS_MCS4;
1224 		rate[1] = DESC_RATEVHT3SS_MCS5;
1225 		rate[2] = DESC_RATEVHT3SS_MCS6;
1226 		rate[3] = DESC_RATEVHT3SS_MCS7;
1227 		for (i = 0; i < 4; ++i)
1228 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1229 		*rate_num = 4;
1230 		break;
1231 	case 0xCE8:
1232 	case 0xEE8:
1233 	case 0x18E8:
1234 	case 0x1AE8:
1235 		rate[0] = DESC_RATEVHT3SS_MCS8;
1236 		rate[1] = DESC_RATEVHT3SS_MCS9;
1237 		for (i = 0; i < 2; ++i)
1238 			pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1239 		*rate_num = 2;
1240 		break;
1241 	default:
1242 		rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1243 		break;
1244 	}
1245 }
1246 
1247 static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev,
1248 					   u32 band, u32 rfpath, u32 txnum,
1249 					   u32 regaddr, u32 bitmask, u32 data)
1250 {
1251 	struct rtw_hal *hal = &rtwdev->hal;
1252 	u8 rate_num = 0;
1253 	u8 rate;
1254 	u8 rates[RTW_RF_PATH_MAX] = {0};
1255 	s8 offset;
1256 	s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0};
1257 	int i;
1258 
1259 	rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data,
1260 						 rates, pwr_by_rate, &rate_num);
1261 
1262 	if (WARN_ON(rfpath >= RTW_RF_PATH_MAX ||
1263 		    (band != PHY_BAND_2G && band != PHY_BAND_5G) ||
1264 		    rate_num > RTW_RF_PATH_MAX))
1265 		return;
1266 
1267 	for (i = 0; i < rate_num; i++) {
1268 		offset = pwr_by_rate[i];
1269 		rate = rates[i];
1270 		if (band == PHY_BAND_2G)
1271 			hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1272 		else if (band == PHY_BAND_5G)
1273 			hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1274 		else
1275 			continue;
1276 	}
1277 }
1278 
1279 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1280 {
1281 	const struct rtw_phy_pg_cfg_pair *p = tbl->data;
1282 	const struct rtw_phy_pg_cfg_pair *end = p + tbl->size;
1283 
1284 	for (; p < end; p++) {
1285 		if (p->addr == 0xfe || p->addr == 0xffe) {
1286 			msleep(50);
1287 			continue;
1288 		}
1289 		rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path,
1290 					       p->tx_num, p->addr, p->bitmask,
1291 					       p->data);
1292 	}
1293 }
1294 EXPORT_SYMBOL(rtw_parse_tbl_bb_pg);
1295 
1296 static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = {
1297 	36,  38,  40,  42,  44,  46,  48, /* Band 1 */
1298 	52,  54,  56,  58,  60,  62,  64, /* Band 2 */
1299 	100, 102, 104, 106, 108, 110, 112, /* Band 3 */
1300 	116, 118, 120, 122, 124, 126, 128, /* Band 3 */
1301 	132, 134, 136, 138, 140, 142, 144, /* Band 3 */
1302 	149, 151, 153, 155, 157, 159, 161, /* Band 4 */
1303 	165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
1304 
1305 static int rtw_channel_to_idx(u8 band, u8 channel)
1306 {
1307 	int ch_idx;
1308 	u8 n_channel;
1309 
1310 	if (band == PHY_BAND_2G) {
1311 		ch_idx = channel - 1;
1312 		n_channel = RTW_MAX_CHANNEL_NUM_2G;
1313 	} else if (band == PHY_BAND_5G) {
1314 		n_channel = RTW_MAX_CHANNEL_NUM_5G;
1315 		for (ch_idx = 0; ch_idx < n_channel; ch_idx++)
1316 			if (rtw_channel_idx_5g[ch_idx] == channel)
1317 				break;
1318 	} else {
1319 		return -1;
1320 	}
1321 
1322 	if (ch_idx >= n_channel)
1323 		return -1;
1324 
1325 	return ch_idx;
1326 }
1327 
1328 static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band,
1329 				       u8 bw, u8 rs, u8 ch, s8 pwr_limit)
1330 {
1331 	struct rtw_hal *hal = &rtwdev->hal;
1332 	u8 max_power_index = rtwdev->chip->max_power_index;
1333 	s8 ww;
1334 	int ch_idx;
1335 
1336 	pwr_limit = clamp_t(s8, pwr_limit,
1337 			    -max_power_index, max_power_index);
1338 	ch_idx = rtw_channel_to_idx(band, ch);
1339 
1340 	if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1341 	    rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) {
1342 		WARN(1,
1343 		     "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1344 		     regd, band, bw, rs, ch_idx, pwr_limit);
1345 		return;
1346 	}
1347 
1348 	if (band == PHY_BAND_2G) {
1349 		hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1350 		ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1351 		ww = min_t(s8, ww, pwr_limit);
1352 		hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1353 	} else if (band == PHY_BAND_5G) {
1354 		hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1355 		ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1356 		ww = min_t(s8, ww, pwr_limit);
1357 		hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1358 	}
1359 }
1360 
1361 /* cross-reference 5G power limits if values are not assigned */
1362 static void
1363 rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd,
1364 		      u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht)
1365 {
1366 	struct rtw_hal *hal = &rtwdev->hal;
1367 	u8 max_power_index = rtwdev->chip->max_power_index;
1368 	s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1369 	s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1370 
1371 	if (lmt_ht == lmt_vht)
1372 		return;
1373 
1374 	if (lmt_ht == max_power_index)
1375 		hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1376 
1377 	else if (lmt_vht == max_power_index)
1378 		hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1379 }
1380 
1381 /* cross-reference power limits for ht and vht */
1382 static void
1383 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1384 {
1385 	u8 rs_idx, rs_ht, rs_vht;
1386 	u8 rs_cmp[2][2] = {{RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S},
1387 			   {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S} };
1388 
1389 	for (rs_idx = 0; rs_idx < 2; rs_idx++) {
1390 		rs_ht = rs_cmp[rs_idx][0];
1391 		rs_vht = rs_cmp[rs_idx][1];
1392 
1393 		rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1394 	}
1395 }
1396 
1397 /* cross-reference power limits for 5G channels */
1398 static void
1399 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1400 {
1401 	u8 ch_idx;
1402 
1403 	for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++)
1404 		rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1405 }
1406 
1407 /* cross-reference power limits for 20/40M bandwidth */
1408 static void
1409 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd)
1410 {
1411 	u8 bw;
1412 
1413 	for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++)
1414 		rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1415 }
1416 
1417 /* cross-reference power limits */
1418 static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev)
1419 {
1420 	u8 regd;
1421 
1422 	for (regd = 0; regd < RTW_REGD_MAX; regd++)
1423 		rtw_xref_txpwr_lmt_by_bw(rtwdev, regd);
1424 }
1425 
1426 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev,
1427 			     const struct rtw_table *tbl)
1428 {
1429 	const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data;
1430 	const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size;
1431 
1432 	for (; p < end; p++) {
1433 		rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band,
1434 					   p->bw, p->rs, p->ch, p->txpwr_lmt);
1435 	}
1436 
1437 	rtw_xref_txpwr_lmt(rtwdev);
1438 }
1439 EXPORT_SYMBOL(rtw_parse_tbl_txpwr_lmt);
1440 
1441 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1442 		     u32 addr, u32 data)
1443 {
1444 	rtw_write8(rtwdev, addr, data);
1445 }
1446 EXPORT_SYMBOL(rtw_phy_cfg_mac);
1447 
1448 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1449 		     u32 addr, u32 data)
1450 {
1451 	rtw_write32(rtwdev, addr, data);
1452 }
1453 EXPORT_SYMBOL(rtw_phy_cfg_agc);
1454 
1455 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1456 		    u32 addr, u32 data)
1457 {
1458 	if (addr == 0xfe)
1459 		msleep(50);
1460 	else if (addr == 0xfd)
1461 		mdelay(5);
1462 	else if (addr == 0xfc)
1463 		mdelay(1);
1464 	else if (addr == 0xfb)
1465 		usleep_range(50, 60);
1466 	else if (addr == 0xfa)
1467 		udelay(5);
1468 	else if (addr == 0xf9)
1469 		udelay(1);
1470 	else
1471 		rtw_write32(rtwdev, addr, data);
1472 }
1473 EXPORT_SYMBOL(rtw_phy_cfg_bb);
1474 
1475 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1476 		    u32 addr, u32 data)
1477 {
1478 	if (addr == 0xffe) {
1479 		msleep(50);
1480 	} else if (addr == 0xfe) {
1481 		usleep_range(100, 110);
1482 	} else {
1483 		rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data);
1484 		udelay(1);
1485 	}
1486 }
1487 EXPORT_SYMBOL(rtw_phy_cfg_rf);
1488 
1489 static void rtw_load_rfk_table(struct rtw_dev *rtwdev)
1490 {
1491 	struct rtw_chip_info *chip = rtwdev->chip;
1492 	struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
1493 
1494 	if (!chip->rfk_init_tbl)
1495 		return;
1496 
1497 	rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1);
1498 	rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1);
1499 	rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1);
1500 	rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1);
1501 	rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0);
1502 
1503 	rtw_load_table(rtwdev, chip->rfk_init_tbl);
1504 
1505 	dpk_info->is_dpk_pwr_on = true;
1506 }
1507 
1508 void rtw_phy_load_tables(struct rtw_dev *rtwdev)
1509 {
1510 	struct rtw_chip_info *chip = rtwdev->chip;
1511 	u8 rf_path;
1512 
1513 	rtw_load_table(rtwdev, chip->mac_tbl);
1514 	rtw_load_table(rtwdev, chip->bb_tbl);
1515 	rtw_load_table(rtwdev, chip->agc_tbl);
1516 	rtw_load_rfk_table(rtwdev);
1517 
1518 	for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1519 		const struct rtw_table *tbl;
1520 
1521 		tbl = chip->rf_tbl[rf_path];
1522 		rtw_load_table(rtwdev, tbl);
1523 	}
1524 }
1525 EXPORT_SYMBOL(rtw_phy_load_tables);
1526 
1527 static u8 rtw_get_channel_group(u8 channel)
1528 {
1529 	switch (channel) {
1530 	default:
1531 		WARN_ON(1);
1532 		fallthrough;
1533 	case 1:
1534 	case 2:
1535 	case 36:
1536 	case 38:
1537 	case 40:
1538 	case 42:
1539 		return 0;
1540 	case 3:
1541 	case 4:
1542 	case 5:
1543 	case 44:
1544 	case 46:
1545 	case 48:
1546 	case 50:
1547 		return 1;
1548 	case 6:
1549 	case 7:
1550 	case 8:
1551 	case 52:
1552 	case 54:
1553 	case 56:
1554 	case 58:
1555 		return 2;
1556 	case 9:
1557 	case 10:
1558 	case 11:
1559 	case 60:
1560 	case 62:
1561 	case 64:
1562 		return 3;
1563 	case 12:
1564 	case 13:
1565 	case 100:
1566 	case 102:
1567 	case 104:
1568 	case 106:
1569 		return 4;
1570 	case 14:
1571 	case 108:
1572 	case 110:
1573 	case 112:
1574 	case 114:
1575 		return 5;
1576 	case 116:
1577 	case 118:
1578 	case 120:
1579 	case 122:
1580 		return 6;
1581 	case 124:
1582 	case 126:
1583 	case 128:
1584 	case 130:
1585 		return 7;
1586 	case 132:
1587 	case 134:
1588 	case 136:
1589 	case 138:
1590 		return 8;
1591 	case 140:
1592 	case 142:
1593 	case 144:
1594 		return 9;
1595 	case 149:
1596 	case 151:
1597 	case 153:
1598 	case 155:
1599 		return 10;
1600 	case 157:
1601 	case 159:
1602 	case 161:
1603 		return 11;
1604 	case 165:
1605 	case 167:
1606 	case 169:
1607 	case 171:
1608 		return 12;
1609 	case 173:
1610 	case 175:
1611 	case 177:
1612 		return 13;
1613 	}
1614 }
1615 
1616 static s8 rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev *rtwdev, u16 rate)
1617 {
1618 	struct rtw_chip_info *chip = rtwdev->chip;
1619 	s8 dpd_diff = 0;
1620 
1621 	if (!chip->en_dis_dpd)
1622 		return 0;
1623 
1624 #define RTW_DPD_RATE_CHECK(_rate)					\
1625 	case DESC_RATE ## _rate:					\
1626 	if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask)			\
1627 		dpd_diff = -6 * chip->txgi_factor;			\
1628 	break
1629 
1630 	switch (rate) {
1631 	RTW_DPD_RATE_CHECK(6M);
1632 	RTW_DPD_RATE_CHECK(9M);
1633 	RTW_DPD_RATE_CHECK(MCS0);
1634 	RTW_DPD_RATE_CHECK(MCS1);
1635 	RTW_DPD_RATE_CHECK(MCS8);
1636 	RTW_DPD_RATE_CHECK(MCS9);
1637 	RTW_DPD_RATE_CHECK(VHT1SS_MCS0);
1638 	RTW_DPD_RATE_CHECK(VHT1SS_MCS1);
1639 	RTW_DPD_RATE_CHECK(VHT2SS_MCS0);
1640 	RTW_DPD_RATE_CHECK(VHT2SS_MCS1);
1641 	}
1642 #undef RTW_DPD_RATE_CHECK
1643 
1644 	return dpd_diff;
1645 }
1646 
1647 static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev,
1648 					struct rtw_2g_txpwr_idx *pwr_idx_2g,
1649 					enum rtw_bandwidth bandwidth,
1650 					u8 rate, u8 group)
1651 {
1652 	struct rtw_chip_info *chip = rtwdev->chip;
1653 	u8 tx_power;
1654 	bool mcs_rate;
1655 	bool above_2ss;
1656 	u8 factor = chip->txgi_factor;
1657 
1658 	if (rate <= DESC_RATE11M)
1659 		tx_power = pwr_idx_2g->cck_base[group];
1660 	else
1661 		tx_power = pwr_idx_2g->bw40_base[group];
1662 
1663 	if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
1664 		tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor;
1665 
1666 	mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
1667 		   (rate >= DESC_RATEVHT1SS_MCS0 &&
1668 		    rate <= DESC_RATEVHT2SS_MCS9);
1669 	above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
1670 		    (rate >= DESC_RATEVHT2SS_MCS0);
1671 
1672 	if (!mcs_rate)
1673 		return tx_power;
1674 
1675 	switch (bandwidth) {
1676 	default:
1677 		WARN_ON(1);
1678 		fallthrough;
1679 	case RTW_CHANNEL_WIDTH_20:
1680 		tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor;
1681 		if (above_2ss)
1682 			tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor;
1683 		break;
1684 	case RTW_CHANNEL_WIDTH_40:
1685 		/* bw40 is the base power */
1686 		if (above_2ss)
1687 			tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor;
1688 		break;
1689 	}
1690 
1691 	return tx_power;
1692 }
1693 
1694 static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev,
1695 					struct rtw_5g_txpwr_idx *pwr_idx_5g,
1696 					enum rtw_bandwidth bandwidth,
1697 					u8 rate, u8 group)
1698 {
1699 	struct rtw_chip_info *chip = rtwdev->chip;
1700 	u8 tx_power;
1701 	u8 upper, lower;
1702 	bool mcs_rate;
1703 	bool above_2ss;
1704 	u8 factor = chip->txgi_factor;
1705 
1706 	tx_power = pwr_idx_5g->bw40_base[group];
1707 
1708 	mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
1709 		   (rate >= DESC_RATEVHT1SS_MCS0 &&
1710 		    rate <= DESC_RATEVHT2SS_MCS9);
1711 	above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
1712 		    (rate >= DESC_RATEVHT2SS_MCS0);
1713 
1714 	if (!mcs_rate) {
1715 		tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor;
1716 		return tx_power;
1717 	}
1718 
1719 	switch (bandwidth) {
1720 	default:
1721 		WARN_ON(1);
1722 		fallthrough;
1723 	case RTW_CHANNEL_WIDTH_20:
1724 		tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor;
1725 		if (above_2ss)
1726 			tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor;
1727 		break;
1728 	case RTW_CHANNEL_WIDTH_40:
1729 		/* bw40 is the base power */
1730 		if (above_2ss)
1731 			tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor;
1732 		break;
1733 	case RTW_CHANNEL_WIDTH_80:
1734 		/* the base idx of bw80 is the average of bw40+/bw40- */
1735 		lower = pwr_idx_5g->bw40_base[group];
1736 		upper = pwr_idx_5g->bw40_base[group + 1];
1737 
1738 		tx_power = (lower + upper) / 2;
1739 		tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor;
1740 		if (above_2ss)
1741 			tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor;
1742 		break;
1743 	}
1744 
1745 	return tx_power;
1746 }
1747 
1748 static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band,
1749 				     enum rtw_bandwidth bw, u8 rf_path,
1750 				     u8 rate, u8 channel, u8 regd)
1751 {
1752 	struct rtw_hal *hal = &rtwdev->hal;
1753 	u8 *cch_by_bw = hal->cch_by_bw;
1754 	s8 power_limit = (s8)rtwdev->chip->max_power_index;
1755 	u8 rs;
1756 	int ch_idx;
1757 	u8 cur_bw, cur_ch;
1758 	s8 cur_lmt;
1759 
1760 	if (regd > RTW_REGD_WW)
1761 		return power_limit;
1762 
1763 	if (rate >= DESC_RATE1M && rate <= DESC_RATE11M)
1764 		rs = RTW_RATE_SECTION_CCK;
1765 	else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
1766 		rs = RTW_RATE_SECTION_OFDM;
1767 	else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7)
1768 		rs = RTW_RATE_SECTION_HT_1S;
1769 	else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15)
1770 		rs = RTW_RATE_SECTION_HT_2S;
1771 	else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9)
1772 		rs = RTW_RATE_SECTION_VHT_1S;
1773 	else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9)
1774 		rs = RTW_RATE_SECTION_VHT_2S;
1775 	else
1776 		goto err;
1777 
1778 	/* only 20M BW with cck and ofdm */
1779 	if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM)
1780 		bw = RTW_CHANNEL_WIDTH_20;
1781 
1782 	/* only 20/40M BW with ht */
1783 	if (rs == RTW_RATE_SECTION_HT_1S || rs == RTW_RATE_SECTION_HT_2S)
1784 		bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40);
1785 
1786 	/* select min power limit among [20M BW ~ current BW] */
1787 	for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) {
1788 		cur_ch = cch_by_bw[cur_bw];
1789 
1790 		ch_idx = rtw_channel_to_idx(band, cur_ch);
1791 		if (ch_idx < 0)
1792 			goto err;
1793 
1794 		cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ?
1795 			hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
1796 			hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
1797 
1798 		power_limit = min_t(s8, cur_lmt, power_limit);
1799 	}
1800 
1801 	return power_limit;
1802 
1803 err:
1804 	WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
1805 	     band, bw, rf_path, rate, channel);
1806 	return (s8)rtwdev->chip->max_power_index;
1807 }
1808 
1809 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw,
1810 			     u8 ch, u8 regd, struct rtw_power_params *pwr_param)
1811 {
1812 	struct rtw_hal *hal = &rtwdev->hal;
1813 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1814 	struct rtw_txpwr_idx *pwr_idx;
1815 	u8 group, band;
1816 	u8 *base = &pwr_param->pwr_base;
1817 	s8 *offset = &pwr_param->pwr_offset;
1818 	s8 *limit = &pwr_param->pwr_limit;
1819 	s8 *remnant = &pwr_param->pwr_remnant;
1820 
1821 	pwr_idx = &rtwdev->efuse.txpwr_idx_table[path];
1822 	group = rtw_get_channel_group(ch);
1823 
1824 	/* base power index for 2.4G/5G */
1825 	if (IS_CH_2G_BAND(ch)) {
1826 		band = PHY_BAND_2G;
1827 		*base = rtw_phy_get_2g_tx_power_index(rtwdev,
1828 						      &pwr_idx->pwr_idx_2g,
1829 						      bw, rate, group);
1830 		*offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
1831 	} else {
1832 		band = PHY_BAND_5G;
1833 		*base = rtw_phy_get_5g_tx_power_index(rtwdev,
1834 						      &pwr_idx->pwr_idx_5g,
1835 						      bw, rate, group);
1836 		*offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
1837 	}
1838 
1839 	*limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path,
1840 					    rate, ch, regd);
1841 	*remnant = (rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck :
1842 		    dm_info->txagc_remnant_ofdm);
1843 }
1844 
1845 u8
1846 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
1847 			   enum rtw_bandwidth bandwidth, u8 channel, u8 regd)
1848 {
1849 	struct rtw_power_params pwr_param = {0};
1850 	u8 tx_power;
1851 	s8 offset;
1852 
1853 	rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth,
1854 				channel, regd, &pwr_param);
1855 
1856 	tx_power = pwr_param.pwr_base;
1857 	offset = min_t(s8, pwr_param.pwr_offset, pwr_param.pwr_limit);
1858 
1859 	if (rtwdev->chip->en_dis_dpd)
1860 		offset += rtw_phy_get_dis_dpd_by_rate_diff(rtwdev, rate);
1861 
1862 	tx_power += offset + pwr_param.pwr_remnant;
1863 
1864 	if (tx_power > rtwdev->chip->max_power_index)
1865 		tx_power = rtwdev->chip->max_power_index;
1866 
1867 	return tx_power;
1868 }
1869 EXPORT_SYMBOL(rtw_phy_get_tx_power_index);
1870 
1871 static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev,
1872 					     u8 ch, u8 path, u8 rs)
1873 {
1874 	struct rtw_hal *hal = &rtwdev->hal;
1875 	u8 regd = rtwdev->regd.txpwr_regd;
1876 	u8 *rates;
1877 	u8 size;
1878 	u8 rate;
1879 	u8 pwr_idx;
1880 	u8 bw;
1881 	int i;
1882 
1883 	if (rs >= RTW_RATE_SECTION_MAX)
1884 		return;
1885 
1886 	rates = rtw_rate_section[rs];
1887 	size = rtw_rate_size[rs];
1888 	bw = hal->current_band_width;
1889 	for (i = 0; i < size; i++) {
1890 		rate = rates[i];
1891 		pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate,
1892 						     bw, ch, regd);
1893 		hal->tx_pwr_tbl[path][rate] = pwr_idx;
1894 	}
1895 }
1896 
1897 /* set tx power level by path for each rates, note that the order of the rates
1898  * are *very* important, bacause 8822B/8821C combines every four bytes of tx
1899  * power index into a four-byte power index register, and calls set_tx_agc to
1900  * write these values into hardware
1901  */
1902 static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev,
1903 					       u8 ch, u8 path)
1904 {
1905 	struct rtw_hal *hal = &rtwdev->hal;
1906 	u8 rs;
1907 
1908 	/* do not need cck rates if we are not in 2.4G */
1909 	if (hal->current_band_type == RTW_BAND_2G)
1910 		rs = RTW_RATE_SECTION_CCK;
1911 	else
1912 		rs = RTW_RATE_SECTION_OFDM;
1913 
1914 	for (; rs < RTW_RATE_SECTION_MAX; rs++)
1915 		rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs);
1916 }
1917 
1918 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel)
1919 {
1920 	struct rtw_chip_info *chip = rtwdev->chip;
1921 	struct rtw_hal *hal = &rtwdev->hal;
1922 	u8 path;
1923 
1924 	mutex_lock(&hal->tx_power_mutex);
1925 
1926 	for (path = 0; path < hal->rf_path_num; path++)
1927 		rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path);
1928 
1929 	chip->ops->set_tx_power_index(rtwdev);
1930 	mutex_unlock(&hal->tx_power_mutex);
1931 }
1932 EXPORT_SYMBOL(rtw_phy_set_tx_power_level);
1933 
1934 static void
1935 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
1936 					u8 rs, u8 size, u8 *rates)
1937 {
1938 	u8 rate;
1939 	u8 base_idx, rate_idx;
1940 	s8 base_2g, base_5g;
1941 
1942 	if (rs >= RTW_RATE_SECTION_VHT_1S)
1943 		base_idx = rates[size - 3];
1944 	else
1945 		base_idx = rates[size - 1];
1946 	base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
1947 	base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
1948 	hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
1949 	hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
1950 	for (rate = 0; rate < size; rate++) {
1951 		rate_idx = rates[rate];
1952 		hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
1953 		hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
1954 	}
1955 }
1956 
1957 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
1958 {
1959 	u8 path;
1960 
1961 	for (path = 0; path < RTW_RF_PATH_MAX; path++) {
1962 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1963 				RTW_RATE_SECTION_CCK,
1964 				rtw_cck_size, rtw_cck_rates);
1965 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1966 				RTW_RATE_SECTION_OFDM,
1967 				rtw_ofdm_size, rtw_ofdm_rates);
1968 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1969 				RTW_RATE_SECTION_HT_1S,
1970 				rtw_ht_1s_size, rtw_ht_1s_rates);
1971 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1972 				RTW_RATE_SECTION_HT_2S,
1973 				rtw_ht_2s_size, rtw_ht_2s_rates);
1974 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1975 				RTW_RATE_SECTION_VHT_1S,
1976 				rtw_vht_1s_size, rtw_vht_1s_rates);
1977 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,
1978 				RTW_RATE_SECTION_VHT_2S,
1979 				rtw_vht_2s_size, rtw_vht_2s_rates);
1980 	}
1981 }
1982 
1983 static void
1984 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
1985 {
1986 	s8 base;
1987 	u8 ch;
1988 
1989 	for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) {
1990 		base = hal->tx_pwr_by_rate_base_2g[0][rs];
1991 		hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
1992 	}
1993 
1994 	for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) {
1995 		base = hal->tx_pwr_by_rate_base_5g[0][rs];
1996 		hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
1997 	}
1998 }
1999 
2000 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
2001 {
2002 	u8 regd, bw, rs;
2003 
2004 	/* default at channel 1 */
2005 	hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
2006 
2007 	for (regd = 0; regd < RTW_REGD_MAX; regd++)
2008 		for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2009 			for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2010 				__rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2011 }
2012 
2013 static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev,
2014 					u8 regd, u8 bw, u8 rs)
2015 {
2016 	struct rtw_hal *hal = &rtwdev->hal;
2017 	s8 max_power_index = (s8)rtwdev->chip->max_power_index;
2018 	u8 ch;
2019 
2020 	/* 2.4G channels */
2021 	for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
2022 		hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2023 
2024 	/* 5G channels */
2025 	for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
2026 		hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2027 }
2028 
2029 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev)
2030 {
2031 	struct rtw_hal *hal = &rtwdev->hal;
2032 	u8 regd, path, rate, rs, bw;
2033 
2034 	/* init tx power by rate offset */
2035 	for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2036 		for (rate = 0; rate < DESC_RATE_MAX; rate++) {
2037 			hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2038 			hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2039 		}
2040 	}
2041 
2042 	/* init tx power limit */
2043 	for (regd = 0; regd < RTW_REGD_MAX; regd++)
2044 		for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2045 			for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2046 				rtw_phy_init_tx_power_limit(rtwdev, regd, bw,
2047 							    rs);
2048 }
2049 
2050 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
2051 				struct rtw_swing_table *swing_table)
2052 {
2053 	const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl;
2054 	u8 channel = rtwdev->hal.current_channel;
2055 
2056 	if (IS_CH_2G_BAND(channel)) {
2057 		if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) {
2058 			swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p;
2059 			swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n;
2060 			swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p;
2061 			swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n;
2062 		} else {
2063 			swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2064 			swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2065 			swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2066 			swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2067 		}
2068 	} else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
2069 		swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1];
2070 		swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1];
2071 		swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1];
2072 		swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1];
2073 	} else if (IS_CH_5G_BAND_3(channel)) {
2074 		swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2];
2075 		swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2];
2076 		swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2];
2077 		swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2];
2078 	} else if (IS_CH_5G_BAND_4(channel)) {
2079 		swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3];
2080 		swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3];
2081 		swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3];
2082 		swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3];
2083 	} else {
2084 		swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2085 		swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2086 		swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2087 		swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2088 	}
2089 }
2090 EXPORT_SYMBOL(rtw_phy_config_swing_table);
2091 
2092 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path)
2093 {
2094 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2095 
2096 	ewma_thermal_add(&dm_info->avg_thermal[path], thermal);
2097 	dm_info->thermal_avg[path] =
2098 		ewma_thermal_read(&dm_info->avg_thermal[path]);
2099 }
2100 EXPORT_SYMBOL(rtw_phy_pwrtrack_avg);
2101 
2102 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
2103 				      u8 path)
2104 {
2105 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2106 	u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]);
2107 
2108 	if (avg == thermal)
2109 		return false;
2110 
2111 	return true;
2112 }
2113 EXPORT_SYMBOL(rtw_phy_pwrtrack_thermal_changed);
2114 
2115 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path)
2116 {
2117 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2118 	u8 therm_avg, therm_efuse, therm_delta;
2119 
2120 	therm_avg = dm_info->thermal_avg[path];
2121 	therm_efuse = rtwdev->efuse.thermal_meter[path];
2122 	therm_delta = abs(therm_avg - therm_efuse);
2123 
2124 	return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1);
2125 }
2126 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_delta);
2127 
2128 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
2129 			       struct rtw_swing_table *swing_table,
2130 			       u8 tbl_path, u8 therm_path, u8 delta)
2131 {
2132 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2133 	const u8 *delta_swing_table_idx_pos;
2134 	const u8 *delta_swing_table_idx_neg;
2135 
2136 	if (delta >= RTW_PWR_TRK_TBL_SZ) {
2137 		rtw_warn(rtwdev, "power track table overflow\n");
2138 		return 0;
2139 	}
2140 
2141 	if (!swing_table) {
2142 		rtw_warn(rtwdev, "swing table not configured\n");
2143 		return 0;
2144 	}
2145 
2146 	delta_swing_table_idx_pos = swing_table->p[tbl_path];
2147 	delta_swing_table_idx_neg = swing_table->n[tbl_path];
2148 
2149 	if (!delta_swing_table_idx_pos || !delta_swing_table_idx_neg) {
2150 		rtw_warn(rtwdev, "invalid swing table index\n");
2151 		return 0;
2152 	}
2153 
2154 	if (dm_info->thermal_avg[therm_path] >
2155 	    rtwdev->efuse.thermal_meter[therm_path])
2156 		return delta_swing_table_idx_pos[delta];
2157 	else
2158 		return -delta_swing_table_idx_neg[delta];
2159 }
2160 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_pwridx);
2161 
2162 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev)
2163 {
2164 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2165 	u8 delta_iqk;
2166 
2167 	delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k);
2168 	if (delta_iqk >= rtwdev->chip->iqk_threshold) {
2169 		dm_info->thermal_meter_k = dm_info->thermal_avg[0];
2170 		return true;
2171 	}
2172 	return false;
2173 }
2174 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_iqk);
2175