1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/bcd.h> 6 7 #include "main.h" 8 #include "reg.h" 9 #include "fw.h" 10 #include "phy.h" 11 #include "debug.h" 12 13 struct phy_cfg_pair { 14 u32 addr; 15 u32 data; 16 }; 17 18 union phy_table_tile { 19 struct rtw_phy_cond cond; 20 struct phy_cfg_pair cfg; 21 }; 22 23 static const u32 db_invert_table[12][8] = { 24 {10, 13, 16, 20, 25 25, 32, 40, 50}, 26 {64, 80, 101, 128, 27 160, 201, 256, 318}, 28 {401, 505, 635, 800, 29 1007, 1268, 1596, 2010}, 30 {316, 398, 501, 631, 31 794, 1000, 1259, 1585}, 32 {1995, 2512, 3162, 3981, 33 5012, 6310, 7943, 10000}, 34 {12589, 15849, 19953, 25119, 35 31623, 39811, 50119, 63098}, 36 {79433, 100000, 125893, 158489, 37 199526, 251189, 316228, 398107}, 38 {501187, 630957, 794328, 1000000, 39 1258925, 1584893, 1995262, 2511886}, 40 {3162278, 3981072, 5011872, 6309573, 41 7943282, 1000000, 12589254, 15848932}, 42 {19952623, 25118864, 31622777, 39810717, 43 50118723, 63095734, 79432823, 100000000}, 44 {125892541, 158489319, 199526232, 251188643, 45 316227766, 398107171, 501187234, 630957345}, 46 {794328235, 1000000000, 1258925412, 1584893192, 47 1995262315, 2511886432U, 3162277660U, 3981071706U} 48 }; 49 50 u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M }; 51 u8 rtw_ofdm_rates[] = { 52 DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, 53 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M, 54 DESC_RATE48M, DESC_RATE54M 55 }; 56 u8 rtw_ht_1s_rates[] = { 57 DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, 58 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5, 59 DESC_RATEMCS6, DESC_RATEMCS7 60 }; 61 u8 rtw_ht_2s_rates[] = { 62 DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, 63 DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13, 64 DESC_RATEMCS14, DESC_RATEMCS15 65 }; 66 u8 rtw_vht_1s_rates[] = { 67 DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, 68 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, 69 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5, 70 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, 71 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9 72 }; 73 u8 rtw_vht_2s_rates[] = { 74 DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, 75 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, 76 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5, 77 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, 78 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9 79 }; 80 u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = { 81 rtw_cck_rates, rtw_ofdm_rates, 82 rtw_ht_1s_rates, rtw_ht_2s_rates, 83 rtw_vht_1s_rates, rtw_vht_2s_rates 84 }; 85 EXPORT_SYMBOL(rtw_rate_section); 86 87 u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = { 88 ARRAY_SIZE(rtw_cck_rates), 89 ARRAY_SIZE(rtw_ofdm_rates), 90 ARRAY_SIZE(rtw_ht_1s_rates), 91 ARRAY_SIZE(rtw_ht_2s_rates), 92 ARRAY_SIZE(rtw_vht_1s_rates), 93 ARRAY_SIZE(rtw_vht_2s_rates) 94 }; 95 EXPORT_SYMBOL(rtw_rate_size); 96 97 static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates); 98 static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates); 99 static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates); 100 static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates); 101 static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates); 102 static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates); 103 104 enum rtw_phy_band_type { 105 PHY_BAND_2G = 0, 106 PHY_BAND_5G = 1, 107 }; 108 109 static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev) 110 { 111 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 112 u8 i, j; 113 114 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) { 115 for (j = 0; j < RTW_RF_PATH_MAX; j++) 116 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0; 117 } 118 119 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 120 } 121 122 void rtw_phy_init(struct rtw_dev *rtwdev) 123 { 124 struct rtw_chip_info *chip = rtwdev->chip; 125 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 126 u32 addr, mask; 127 128 dm_info->fa_history[3] = 0; 129 dm_info->fa_history[2] = 0; 130 dm_info->fa_history[1] = 0; 131 dm_info->fa_history[0] = 0; 132 dm_info->igi_bitmap = 0; 133 dm_info->igi_history[3] = 0; 134 dm_info->igi_history[2] = 0; 135 dm_info->igi_history[1] = 0; 136 137 addr = chip->dig[0].addr; 138 mask = chip->dig[0].mask; 139 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask); 140 rtw_phy_cck_pd_init(rtwdev); 141 142 dm_info->iqk.done = false; 143 } 144 EXPORT_SYMBOL(rtw_phy_init); 145 146 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi) 147 { 148 struct rtw_chip_info *chip = rtwdev->chip; 149 struct rtw_hal *hal = &rtwdev->hal; 150 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0]; 151 u32 addr, mask; 152 u8 path; 153 154 if (dig_cck) 155 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1); 156 157 for (path = 0; path < hal->rf_path_num; path++) { 158 addr = chip->dig[path].addr; 159 mask = chip->dig[path].mask; 160 rtw_write32_mask(rtwdev, addr, mask, igi); 161 } 162 } 163 164 static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev) 165 { 166 struct rtw_chip_info *chip = rtwdev->chip; 167 168 chip->ops->false_alarm_statistics(rtwdev); 169 } 170 171 #define RA_FLOOR_TABLE_SIZE 7 172 #define RA_FLOOR_UP_GAP 3 173 174 static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi) 175 { 176 u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; 177 u8 new_level = 0; 178 int i; 179 180 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) 181 if (i >= old_level) 182 table[i] += RA_FLOOR_UP_GAP; 183 184 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 185 if (rssi < table[i]) { 186 new_level = i; 187 break; 188 } 189 } 190 191 return new_level; 192 } 193 194 struct rtw_phy_stat_iter_data { 195 struct rtw_dev *rtwdev; 196 u8 min_rssi; 197 }; 198 199 static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta) 200 { 201 struct rtw_phy_stat_iter_data *iter_data = data; 202 struct rtw_dev *rtwdev = iter_data->rtwdev; 203 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 204 u8 rssi; 205 206 rssi = ewma_rssi_read(&si->avg_rssi); 207 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi); 208 209 rtw_fw_send_rssi_info(rtwdev, si); 210 211 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi); 212 } 213 214 static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev) 215 { 216 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 217 struct rtw_phy_stat_iter_data data = {}; 218 219 data.rtwdev = rtwdev; 220 data.min_rssi = U8_MAX; 221 rtw_iterate_stas_atomic(rtwdev, rtw_phy_stat_rssi_iter, &data); 222 223 dm_info->pre_min_rssi = dm_info->min_rssi; 224 dm_info->min_rssi = data.min_rssi; 225 } 226 227 static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev) 228 { 229 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 230 231 dm_info->last_pkt_count = dm_info->cur_pkt_count; 232 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count)); 233 } 234 235 static void rtw_phy_statistics(struct rtw_dev *rtwdev) 236 { 237 rtw_phy_stat_rssi(rtwdev); 238 rtw_phy_stat_false_alarm(rtwdev); 239 rtw_phy_stat_rate_cnt(rtwdev); 240 } 241 242 #define DIG_PERF_FA_TH_LOW 250 243 #define DIG_PERF_FA_TH_HIGH 500 244 #define DIG_PERF_FA_TH_EXTRA_HIGH 750 245 #define DIG_PERF_MAX 0x5a 246 #define DIG_PERF_MID 0x40 247 #define DIG_CVRG_FA_TH_LOW 2000 248 #define DIG_CVRG_FA_TH_HIGH 4000 249 #define DIG_CVRG_FA_TH_EXTRA_HIGH 5000 250 #define DIG_CVRG_MAX 0x2a 251 #define DIG_CVRG_MID 0x26 252 #define DIG_CVRG_MIN 0x1c 253 #define DIG_RSSI_GAIN_OFFSET 15 254 255 static bool 256 rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info) 257 { 258 u16 fa_lo = DIG_PERF_FA_TH_LOW; 259 u16 fa_hi = DIG_PERF_FA_TH_HIGH; 260 u16 *fa_history; 261 u8 *igi_history; 262 u8 damping_rssi; 263 u8 min_rssi; 264 u8 diff; 265 u8 igi_bitmap; 266 bool damping = false; 267 268 min_rssi = dm_info->min_rssi; 269 if (dm_info->damping) { 270 damping_rssi = dm_info->damping_rssi; 271 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi : 272 damping_rssi - min_rssi; 273 if (diff > 3 || dm_info->damping_cnt++ > 20) { 274 dm_info->damping = false; 275 return false; 276 } 277 278 return true; 279 } 280 281 igi_history = dm_info->igi_history; 282 fa_history = dm_info->fa_history; 283 igi_bitmap = dm_info->igi_bitmap & 0xf; 284 switch (igi_bitmap) { 285 case 5: 286 /* down -> up -> down -> up */ 287 if (igi_history[0] > igi_history[1] && 288 igi_history[2] > igi_history[3] && 289 igi_history[0] - igi_history[1] >= 2 && 290 igi_history[2] - igi_history[3] >= 2 && 291 fa_history[0] > fa_hi && fa_history[1] < fa_lo && 292 fa_history[2] > fa_hi && fa_history[3] < fa_lo) 293 damping = true; 294 break; 295 case 9: 296 /* up -> down -> down -> up */ 297 if (igi_history[0] > igi_history[1] && 298 igi_history[3] > igi_history[2] && 299 igi_history[0] - igi_history[1] >= 4 && 300 igi_history[3] - igi_history[2] >= 2 && 301 fa_history[0] > fa_hi && fa_history[1] < fa_lo && 302 fa_history[2] < fa_lo && fa_history[3] > fa_hi) 303 damping = true; 304 break; 305 default: 306 return false; 307 } 308 309 if (damping) { 310 dm_info->damping = true; 311 dm_info->damping_cnt = 0; 312 dm_info->damping_rssi = min_rssi; 313 } 314 315 return damping; 316 } 317 318 static void rtw_phy_dig_get_boundary(struct rtw_dm_info *dm_info, 319 u8 *upper, u8 *lower, bool linked) 320 { 321 u8 dig_max, dig_min, dig_mid; 322 u8 min_rssi; 323 324 if (linked) { 325 dig_max = DIG_PERF_MAX; 326 dig_mid = DIG_PERF_MID; 327 /* 22B=0x1c, 22C=0x20 */ 328 dig_min = 0x1c; 329 min_rssi = max_t(u8, dm_info->min_rssi, dig_min); 330 } else { 331 dig_max = DIG_CVRG_MAX; 332 dig_mid = DIG_CVRG_MID; 333 dig_min = DIG_CVRG_MIN; 334 min_rssi = dig_min; 335 } 336 337 /* DIG MAX should be bounded by minimum RSSI with offset +15 */ 338 dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET); 339 340 *lower = clamp_t(u8, min_rssi, dig_min, dig_mid); 341 *upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max); 342 } 343 344 static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info, 345 u16 *fa_th, u8 *step, bool linked) 346 { 347 u8 min_rssi, pre_min_rssi; 348 349 min_rssi = dm_info->min_rssi; 350 pre_min_rssi = dm_info->pre_min_rssi; 351 step[0] = 4; 352 step[1] = 3; 353 step[2] = 2; 354 355 if (linked) { 356 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH; 357 fa_th[1] = DIG_PERF_FA_TH_HIGH; 358 fa_th[2] = DIG_PERF_FA_TH_LOW; 359 if (pre_min_rssi > min_rssi) { 360 step[0] = 6; 361 step[1] = 4; 362 step[2] = 2; 363 } 364 } else { 365 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH; 366 fa_th[1] = DIG_CVRG_FA_TH_HIGH; 367 fa_th[2] = DIG_CVRG_FA_TH_LOW; 368 } 369 } 370 371 static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa) 372 { 373 u8 *igi_history; 374 u16 *fa_history; 375 u8 igi_bitmap; 376 bool up; 377 378 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe; 379 igi_history = dm_info->igi_history; 380 fa_history = dm_info->fa_history; 381 382 up = igi > igi_history[0]; 383 igi_bitmap |= up; 384 385 igi_history[3] = igi_history[2]; 386 igi_history[2] = igi_history[1]; 387 igi_history[1] = igi_history[0]; 388 igi_history[0] = igi; 389 390 fa_history[3] = fa_history[2]; 391 fa_history[2] = fa_history[1]; 392 fa_history[1] = fa_history[0]; 393 fa_history[0] = fa; 394 395 dm_info->igi_bitmap = igi_bitmap; 396 } 397 398 static void rtw_phy_dig(struct rtw_dev *rtwdev) 399 { 400 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 401 u8 upper_bound, lower_bound; 402 u8 pre_igi, cur_igi; 403 u16 fa_th[3], fa_cnt; 404 u8 level; 405 u8 step[3]; 406 bool linked; 407 408 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags)) 409 return; 410 411 if (rtw_phy_dig_check_damping(dm_info)) 412 return; 413 414 linked = !!rtwdev->sta_cnt; 415 416 fa_cnt = dm_info->total_fa_cnt; 417 pre_igi = dm_info->igi_history[0]; 418 419 rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked); 420 421 /* test the false alarm count from the highest threshold level first, 422 * and increase it by corresponding step size 423 * 424 * note that the step size is offset by -2, compensate it afterall 425 */ 426 cur_igi = pre_igi; 427 for (level = 0; level < 3; level++) { 428 if (fa_cnt > fa_th[level]) { 429 cur_igi += step[level]; 430 break; 431 } 432 } 433 cur_igi -= 2; 434 435 /* calculate the upper/lower bound by the minimum rssi we have among 436 * the peers connected with us, meanwhile make sure the igi value does 437 * not beyond the hardware limitation 438 */ 439 rtw_phy_dig_get_boundary(dm_info, &upper_bound, &lower_bound, linked); 440 cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound); 441 442 /* record current igi value and false alarm statistics for further 443 * damping checks, and record the trend of igi values 444 */ 445 rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt); 446 447 if (cur_igi != pre_igi) 448 rtw_phy_dig_write(rtwdev, cur_igi); 449 } 450 451 static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta) 452 { 453 struct rtw_dev *rtwdev = data; 454 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 455 456 rtw_update_sta_info(rtwdev, si); 457 } 458 459 static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev) 460 { 461 if (rtwdev->watch_dog_cnt & 0x3) 462 return; 463 464 rtw_iterate_stas_atomic(rtwdev, rtw_phy_ra_info_update_iter, rtwdev); 465 } 466 467 static void rtw_phy_dpk_track(struct rtw_dev *rtwdev) 468 { 469 struct rtw_chip_info *chip = rtwdev->chip; 470 471 if (chip->ops->dpk_track) 472 chip->ops->dpk_track(rtwdev); 473 } 474 475 #define CCK_PD_FA_LV1_MIN 1000 476 #define CCK_PD_FA_LV0_MAX 500 477 478 static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev) 479 { 480 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 481 u32 cck_fa_avg = dm_info->cck_fa_avg; 482 483 if (cck_fa_avg > CCK_PD_FA_LV1_MIN) 484 return CCK_PD_LV1; 485 486 if (cck_fa_avg < CCK_PD_FA_LV0_MAX) 487 return CCK_PD_LV0; 488 489 return CCK_PD_LV_MAX; 490 } 491 492 #define CCK_PD_IGI_LV4_VAL 0x38 493 #define CCK_PD_IGI_LV3_VAL 0x2a 494 #define CCK_PD_IGI_LV2_VAL 0x24 495 #define CCK_PD_RSSI_LV4_VAL 32 496 #define CCK_PD_RSSI_LV3_VAL 32 497 #define CCK_PD_RSSI_LV2_VAL 24 498 499 static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev) 500 { 501 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 502 u8 igi = dm_info->igi_history[0]; 503 u8 rssi = dm_info->min_rssi; 504 u32 cck_fa_avg = dm_info->cck_fa_avg; 505 506 if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL) 507 return CCK_PD_LV4; 508 if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL) 509 return CCK_PD_LV3; 510 if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL) 511 return CCK_PD_LV2; 512 if (cck_fa_avg > CCK_PD_FA_LV1_MIN) 513 return CCK_PD_LV1; 514 if (cck_fa_avg < CCK_PD_FA_LV0_MAX) 515 return CCK_PD_LV0; 516 517 return CCK_PD_LV_MAX; 518 } 519 520 static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev) 521 { 522 if (!rtw_is_assoc(rtwdev)) 523 return rtw_phy_cck_pd_lv_unlink(rtwdev); 524 else 525 return rtw_phy_cck_pd_lv_link(rtwdev); 526 } 527 528 static void rtw_phy_cck_pd(struct rtw_dev *rtwdev) 529 { 530 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 531 struct rtw_chip_info *chip = rtwdev->chip; 532 u32 cck_fa = dm_info->cck_fa_cnt; 533 u8 level; 534 535 if (rtwdev->hal.current_band_type != RTW_BAND_2G) 536 return; 537 538 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET) 539 dm_info->cck_fa_avg = cck_fa; 540 else 541 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2; 542 543 level = rtw_phy_cck_pd_lv(rtwdev); 544 545 if (level >= CCK_PD_LV_MAX) 546 return; 547 548 if (chip->ops->cck_pd_set) 549 chip->ops->cck_pd_set(rtwdev, level); 550 } 551 552 static void rtw_phy_pwr_track(struct rtw_dev *rtwdev) 553 { 554 rtwdev->chip->ops->pwr_track(rtwdev); 555 } 556 557 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev) 558 { 559 /* for further calculation */ 560 rtw_phy_statistics(rtwdev); 561 rtw_phy_dig(rtwdev); 562 rtw_phy_cck_pd(rtwdev); 563 rtw_phy_ra_info_update(rtwdev); 564 rtw_phy_dpk_track(rtwdev); 565 rtw_phy_pwr_track(rtwdev); 566 } 567 568 #define FRAC_BITS 3 569 570 static u8 rtw_phy_power_2_db(s8 power) 571 { 572 if (power <= -100 || power >= 20) 573 return 0; 574 else if (power >= 0) 575 return 100; 576 else 577 return 100 + power; 578 } 579 580 static u64 rtw_phy_db_2_linear(u8 power_db) 581 { 582 u8 i, j; 583 u64 linear; 584 585 if (power_db > 96) 586 power_db = 96; 587 else if (power_db < 1) 588 return 1; 589 590 /* 1dB ~ 96dB */ 591 i = (power_db - 1) >> 3; 592 j = (power_db - 1) - (i << 3); 593 594 linear = db_invert_table[i][j]; 595 linear = i > 2 ? linear << FRAC_BITS : linear; 596 597 return linear; 598 } 599 600 static u8 rtw_phy_linear_2_db(u64 linear) 601 { 602 u8 i; 603 u8 j; 604 u32 dB; 605 606 if (linear >= db_invert_table[11][7]) 607 return 96; /* maximum 96 dB */ 608 609 for (i = 0; i < 12; i++) { 610 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7]) 611 break; 612 else if (i > 2 && linear <= db_invert_table[i][7]) 613 break; 614 } 615 616 for (j = 0; j < 8; j++) { 617 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j]) 618 break; 619 else if (i > 2 && linear <= db_invert_table[i][j]) 620 break; 621 } 622 623 if (j == 0 && i == 0) 624 goto end; 625 626 if (j == 0) { 627 if (i != 3) { 628 if (db_invert_table[i][0] - linear > 629 linear - db_invert_table[i - 1][7]) { 630 i = i - 1; 631 j = 7; 632 } 633 } else { 634 if (db_invert_table[3][0] - linear > 635 linear - db_invert_table[2][7]) { 636 i = 2; 637 j = 7; 638 } 639 } 640 } else { 641 if (db_invert_table[i][j] - linear > 642 linear - db_invert_table[i][j - 1]) { 643 j = j - 1; 644 } 645 } 646 end: 647 dB = (i << 3) + j + 1; 648 649 return dB; 650 } 651 652 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num) 653 { 654 s8 power; 655 u8 power_db; 656 u64 linear; 657 u64 sum = 0; 658 u8 path; 659 660 for (path = 0; path < path_num; path++) { 661 power = rf_power[path]; 662 power_db = rtw_phy_power_2_db(power); 663 linear = rtw_phy_db_2_linear(power_db); 664 sum += linear; 665 } 666 667 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; 668 switch (path_num) { 669 case 2: 670 sum >>= 1; 671 break; 672 case 3: 673 sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5; 674 break; 675 case 4: 676 sum >>= 2; 677 break; 678 default: 679 break; 680 } 681 682 return rtw_phy_linear_2_db(sum); 683 } 684 EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi); 685 686 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 687 u32 addr, u32 mask) 688 { 689 struct rtw_hal *hal = &rtwdev->hal; 690 struct rtw_chip_info *chip = rtwdev->chip; 691 const u32 *base_addr = chip->rf_base_addr; 692 u32 val, direct_addr; 693 694 if (rf_path >= hal->rf_phy_num) { 695 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 696 return INV_RF_DATA; 697 } 698 699 addr &= 0xff; 700 direct_addr = base_addr[rf_path] + (addr << 2); 701 mask &= RFREG_MASK; 702 703 val = rtw_read32_mask(rtwdev, direct_addr, mask); 704 705 return val; 706 } 707 EXPORT_SYMBOL(rtw_phy_read_rf); 708 709 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 710 u32 addr, u32 mask) 711 { 712 struct rtw_hal *hal = &rtwdev->hal; 713 struct rtw_chip_info *chip = rtwdev->chip; 714 const struct rtw_rf_sipi_addr *rf_sipi_addr; 715 const struct rtw_rf_sipi_addr *rf_sipi_addr_a; 716 u32 val32; 717 u32 en_pi; 718 u32 r_addr; 719 u32 shift; 720 721 if (rf_path >= hal->rf_phy_num) { 722 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 723 return INV_RF_DATA; 724 } 725 726 if (!chip->rf_sipi_read_addr) { 727 rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n"); 728 return INV_RF_DATA; 729 } 730 731 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path]; 732 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A]; 733 734 addr &= 0xff; 735 736 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2); 737 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23); 738 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32); 739 740 /* toggle read edge of path A */ 741 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2); 742 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK); 743 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK); 744 745 udelay(120); 746 747 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8)); 748 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read; 749 750 val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK); 751 752 shift = __ffs(mask); 753 754 return (val32 & mask) >> shift; 755 } 756 EXPORT_SYMBOL(rtw_phy_read_rf_sipi); 757 758 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 759 u32 addr, u32 mask, u32 data) 760 { 761 struct rtw_hal *hal = &rtwdev->hal; 762 struct rtw_chip_info *chip = rtwdev->chip; 763 u32 *sipi_addr = chip->rf_sipi_addr; 764 u32 data_and_addr; 765 u32 old_data = 0; 766 u32 shift; 767 768 if (rf_path >= hal->rf_phy_num) { 769 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 770 return false; 771 } 772 773 addr &= 0xff; 774 mask &= RFREG_MASK; 775 776 if (mask != RFREG_MASK) { 777 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK); 778 779 if (old_data == INV_RF_DATA) { 780 rtw_err(rtwdev, "Write fail, rf is disabled\n"); 781 return false; 782 } 783 784 shift = __ffs(mask); 785 data = ((old_data) & (~mask)) | (data << shift); 786 } 787 788 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff; 789 790 rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr); 791 792 udelay(13); 793 794 return true; 795 } 796 EXPORT_SYMBOL(rtw_phy_write_rf_reg_sipi); 797 798 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 799 u32 addr, u32 mask, u32 data) 800 { 801 struct rtw_hal *hal = &rtwdev->hal; 802 struct rtw_chip_info *chip = rtwdev->chip; 803 const u32 *base_addr = chip->rf_base_addr; 804 u32 direct_addr; 805 806 if (rf_path >= hal->rf_phy_num) { 807 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 808 return false; 809 } 810 811 addr &= 0xff; 812 direct_addr = base_addr[rf_path] + (addr << 2); 813 mask &= RFREG_MASK; 814 815 rtw_write32_mask(rtwdev, direct_addr, mask, data); 816 817 udelay(1); 818 819 return true; 820 } 821 822 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 823 u32 addr, u32 mask, u32 data) 824 { 825 if (addr != 0x00) 826 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data); 827 828 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data); 829 } 830 EXPORT_SYMBOL(rtw_phy_write_rf_reg_mix); 831 832 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg) 833 { 834 struct rtw_hal *hal = &rtwdev->hal; 835 struct rtw_efuse *efuse = &rtwdev->efuse; 836 struct rtw_phy_cond cond = {0}; 837 838 cond.cut = hal->cut_version ? hal->cut_version : 15; 839 cond.pkg = pkg ? pkg : 15; 840 cond.plat = 0x04; 841 cond.rfe = efuse->rfe_option; 842 843 switch (rtw_hci_type(rtwdev)) { 844 case RTW_HCI_TYPE_USB: 845 cond.intf = INTF_USB; 846 break; 847 case RTW_HCI_TYPE_SDIO: 848 cond.intf = INTF_SDIO; 849 break; 850 case RTW_HCI_TYPE_PCIE: 851 default: 852 cond.intf = INTF_PCIE; 853 break; 854 } 855 856 hal->phy_cond = cond; 857 858 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond)); 859 } 860 861 static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond) 862 { 863 struct rtw_hal *hal = &rtwdev->hal; 864 struct rtw_phy_cond drv_cond = hal->phy_cond; 865 866 if (cond.cut && cond.cut != drv_cond.cut) 867 return false; 868 869 if (cond.pkg && cond.pkg != drv_cond.pkg) 870 return false; 871 872 if (cond.intf && cond.intf != drv_cond.intf) 873 return false; 874 875 if (cond.rfe != drv_cond.rfe) 876 return false; 877 878 return true; 879 } 880 881 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl) 882 { 883 const union phy_table_tile *p = tbl->data; 884 const union phy_table_tile *end = p + tbl->size / 2; 885 struct rtw_phy_cond pos_cond = {0}; 886 bool is_matched = true, is_skipped = false; 887 888 BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair)); 889 890 for (; p < end; p++) { 891 if (p->cond.pos) { 892 switch (p->cond.branch) { 893 case BRANCH_ENDIF: 894 is_matched = true; 895 is_skipped = false; 896 break; 897 case BRANCH_ELSE: 898 is_matched = is_skipped ? false : true; 899 break; 900 case BRANCH_IF: 901 case BRANCH_ELIF: 902 default: 903 pos_cond = p->cond; 904 break; 905 } 906 } else if (p->cond.neg) { 907 if (!is_skipped) { 908 if (check_positive(rtwdev, pos_cond)) { 909 is_matched = true; 910 is_skipped = true; 911 } else { 912 is_matched = false; 913 is_skipped = false; 914 } 915 } else { 916 is_matched = false; 917 } 918 } else if (is_matched) { 919 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data); 920 } 921 } 922 } 923 EXPORT_SYMBOL(rtw_parse_tbl_phy_cond); 924 925 #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8)) 926 927 static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i) 928 { 929 if (rtwdev->chip->is_pwr_by_rate_dec) 930 return bcd_to_dec_pwr_by_rate(hex, i); 931 932 return (hex >> (i * 8)) & 0xFF; 933 } 934 935 static void 936 rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev, 937 u32 addr, u32 mask, u32 val, u8 *rate, 938 u8 *pwr_by_rate, u8 *rate_num) 939 { 940 int i; 941 942 switch (addr) { 943 case 0xE00: 944 case 0x830: 945 rate[0] = DESC_RATE6M; 946 rate[1] = DESC_RATE9M; 947 rate[2] = DESC_RATE12M; 948 rate[3] = DESC_RATE18M; 949 for (i = 0; i < 4; ++i) 950 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 951 *rate_num = 4; 952 break; 953 case 0xE04: 954 case 0x834: 955 rate[0] = DESC_RATE24M; 956 rate[1] = DESC_RATE36M; 957 rate[2] = DESC_RATE48M; 958 rate[3] = DESC_RATE54M; 959 for (i = 0; i < 4; ++i) 960 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 961 *rate_num = 4; 962 break; 963 case 0xE08: 964 rate[0] = DESC_RATE1M; 965 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1); 966 *rate_num = 1; 967 break; 968 case 0x86C: 969 if (mask == 0xffffff00) { 970 rate[0] = DESC_RATE2M; 971 rate[1] = DESC_RATE5_5M; 972 rate[2] = DESC_RATE11M; 973 for (i = 1; i < 4; ++i) 974 pwr_by_rate[i - 1] = 975 tbl_to_dec_pwr_by_rate(rtwdev, val, i); 976 *rate_num = 3; 977 } else if (mask == 0x000000ff) { 978 rate[0] = DESC_RATE11M; 979 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0); 980 *rate_num = 1; 981 } 982 break; 983 case 0xE10: 984 case 0x83C: 985 rate[0] = DESC_RATEMCS0; 986 rate[1] = DESC_RATEMCS1; 987 rate[2] = DESC_RATEMCS2; 988 rate[3] = DESC_RATEMCS3; 989 for (i = 0; i < 4; ++i) 990 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 991 *rate_num = 4; 992 break; 993 case 0xE14: 994 case 0x848: 995 rate[0] = DESC_RATEMCS4; 996 rate[1] = DESC_RATEMCS5; 997 rate[2] = DESC_RATEMCS6; 998 rate[3] = DESC_RATEMCS7; 999 for (i = 0; i < 4; ++i) 1000 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1001 *rate_num = 4; 1002 break; 1003 case 0xE18: 1004 case 0x84C: 1005 rate[0] = DESC_RATEMCS8; 1006 rate[1] = DESC_RATEMCS9; 1007 rate[2] = DESC_RATEMCS10; 1008 rate[3] = DESC_RATEMCS11; 1009 for (i = 0; i < 4; ++i) 1010 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1011 *rate_num = 4; 1012 break; 1013 case 0xE1C: 1014 case 0x868: 1015 rate[0] = DESC_RATEMCS12; 1016 rate[1] = DESC_RATEMCS13; 1017 rate[2] = DESC_RATEMCS14; 1018 rate[3] = DESC_RATEMCS15; 1019 for (i = 0; i < 4; ++i) 1020 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1021 *rate_num = 4; 1022 break; 1023 case 0x838: 1024 rate[0] = DESC_RATE1M; 1025 rate[1] = DESC_RATE2M; 1026 rate[2] = DESC_RATE5_5M; 1027 for (i = 1; i < 4; ++i) 1028 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev, 1029 val, i); 1030 *rate_num = 3; 1031 break; 1032 case 0xC20: 1033 case 0xE20: 1034 case 0x1820: 1035 case 0x1A20: 1036 rate[0] = DESC_RATE1M; 1037 rate[1] = DESC_RATE2M; 1038 rate[2] = DESC_RATE5_5M; 1039 rate[3] = DESC_RATE11M; 1040 for (i = 0; i < 4; ++i) 1041 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1042 *rate_num = 4; 1043 break; 1044 case 0xC24: 1045 case 0xE24: 1046 case 0x1824: 1047 case 0x1A24: 1048 rate[0] = DESC_RATE6M; 1049 rate[1] = DESC_RATE9M; 1050 rate[2] = DESC_RATE12M; 1051 rate[3] = DESC_RATE18M; 1052 for (i = 0; i < 4; ++i) 1053 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1054 *rate_num = 4; 1055 break; 1056 case 0xC28: 1057 case 0xE28: 1058 case 0x1828: 1059 case 0x1A28: 1060 rate[0] = DESC_RATE24M; 1061 rate[1] = DESC_RATE36M; 1062 rate[2] = DESC_RATE48M; 1063 rate[3] = DESC_RATE54M; 1064 for (i = 0; i < 4; ++i) 1065 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1066 *rate_num = 4; 1067 break; 1068 case 0xC2C: 1069 case 0xE2C: 1070 case 0x182C: 1071 case 0x1A2C: 1072 rate[0] = DESC_RATEMCS0; 1073 rate[1] = DESC_RATEMCS1; 1074 rate[2] = DESC_RATEMCS2; 1075 rate[3] = DESC_RATEMCS3; 1076 for (i = 0; i < 4; ++i) 1077 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1078 *rate_num = 4; 1079 break; 1080 case 0xC30: 1081 case 0xE30: 1082 case 0x1830: 1083 case 0x1A30: 1084 rate[0] = DESC_RATEMCS4; 1085 rate[1] = DESC_RATEMCS5; 1086 rate[2] = DESC_RATEMCS6; 1087 rate[3] = DESC_RATEMCS7; 1088 for (i = 0; i < 4; ++i) 1089 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1090 *rate_num = 4; 1091 break; 1092 case 0xC34: 1093 case 0xE34: 1094 case 0x1834: 1095 case 0x1A34: 1096 rate[0] = DESC_RATEMCS8; 1097 rate[1] = DESC_RATEMCS9; 1098 rate[2] = DESC_RATEMCS10; 1099 rate[3] = DESC_RATEMCS11; 1100 for (i = 0; i < 4; ++i) 1101 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1102 *rate_num = 4; 1103 break; 1104 case 0xC38: 1105 case 0xE38: 1106 case 0x1838: 1107 case 0x1A38: 1108 rate[0] = DESC_RATEMCS12; 1109 rate[1] = DESC_RATEMCS13; 1110 rate[2] = DESC_RATEMCS14; 1111 rate[3] = DESC_RATEMCS15; 1112 for (i = 0; i < 4; ++i) 1113 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1114 *rate_num = 4; 1115 break; 1116 case 0xC3C: 1117 case 0xE3C: 1118 case 0x183C: 1119 case 0x1A3C: 1120 rate[0] = DESC_RATEVHT1SS_MCS0; 1121 rate[1] = DESC_RATEVHT1SS_MCS1; 1122 rate[2] = DESC_RATEVHT1SS_MCS2; 1123 rate[3] = DESC_RATEVHT1SS_MCS3; 1124 for (i = 0; i < 4; ++i) 1125 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1126 *rate_num = 4; 1127 break; 1128 case 0xC40: 1129 case 0xE40: 1130 case 0x1840: 1131 case 0x1A40: 1132 rate[0] = DESC_RATEVHT1SS_MCS4; 1133 rate[1] = DESC_RATEVHT1SS_MCS5; 1134 rate[2] = DESC_RATEVHT1SS_MCS6; 1135 rate[3] = DESC_RATEVHT1SS_MCS7; 1136 for (i = 0; i < 4; ++i) 1137 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1138 *rate_num = 4; 1139 break; 1140 case 0xC44: 1141 case 0xE44: 1142 case 0x1844: 1143 case 0x1A44: 1144 rate[0] = DESC_RATEVHT1SS_MCS8; 1145 rate[1] = DESC_RATEVHT1SS_MCS9; 1146 rate[2] = DESC_RATEVHT2SS_MCS0; 1147 rate[3] = DESC_RATEVHT2SS_MCS1; 1148 for (i = 0; i < 4; ++i) 1149 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1150 *rate_num = 4; 1151 break; 1152 case 0xC48: 1153 case 0xE48: 1154 case 0x1848: 1155 case 0x1A48: 1156 rate[0] = DESC_RATEVHT2SS_MCS2; 1157 rate[1] = DESC_RATEVHT2SS_MCS3; 1158 rate[2] = DESC_RATEVHT2SS_MCS4; 1159 rate[3] = DESC_RATEVHT2SS_MCS5; 1160 for (i = 0; i < 4; ++i) 1161 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1162 *rate_num = 4; 1163 break; 1164 case 0xC4C: 1165 case 0xE4C: 1166 case 0x184C: 1167 case 0x1A4C: 1168 rate[0] = DESC_RATEVHT2SS_MCS6; 1169 rate[1] = DESC_RATEVHT2SS_MCS7; 1170 rate[2] = DESC_RATEVHT2SS_MCS8; 1171 rate[3] = DESC_RATEVHT2SS_MCS9; 1172 for (i = 0; i < 4; ++i) 1173 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1174 *rate_num = 4; 1175 break; 1176 case 0xCD8: 1177 case 0xED8: 1178 case 0x18D8: 1179 case 0x1AD8: 1180 rate[0] = DESC_RATEMCS16; 1181 rate[1] = DESC_RATEMCS17; 1182 rate[2] = DESC_RATEMCS18; 1183 rate[3] = DESC_RATEMCS19; 1184 for (i = 0; i < 4; ++i) 1185 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1186 *rate_num = 4; 1187 break; 1188 case 0xCDC: 1189 case 0xEDC: 1190 case 0x18DC: 1191 case 0x1ADC: 1192 rate[0] = DESC_RATEMCS20; 1193 rate[1] = DESC_RATEMCS21; 1194 rate[2] = DESC_RATEMCS22; 1195 rate[3] = DESC_RATEMCS23; 1196 for (i = 0; i < 4; ++i) 1197 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1198 *rate_num = 4; 1199 break; 1200 case 0xCE0: 1201 case 0xEE0: 1202 case 0x18E0: 1203 case 0x1AE0: 1204 rate[0] = DESC_RATEVHT3SS_MCS0; 1205 rate[1] = DESC_RATEVHT3SS_MCS1; 1206 rate[2] = DESC_RATEVHT3SS_MCS2; 1207 rate[3] = DESC_RATEVHT3SS_MCS3; 1208 for (i = 0; i < 4; ++i) 1209 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1210 *rate_num = 4; 1211 break; 1212 case 0xCE4: 1213 case 0xEE4: 1214 case 0x18E4: 1215 case 0x1AE4: 1216 rate[0] = DESC_RATEVHT3SS_MCS4; 1217 rate[1] = DESC_RATEVHT3SS_MCS5; 1218 rate[2] = DESC_RATEVHT3SS_MCS6; 1219 rate[3] = DESC_RATEVHT3SS_MCS7; 1220 for (i = 0; i < 4; ++i) 1221 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1222 *rate_num = 4; 1223 break; 1224 case 0xCE8: 1225 case 0xEE8: 1226 case 0x18E8: 1227 case 0x1AE8: 1228 rate[0] = DESC_RATEVHT3SS_MCS8; 1229 rate[1] = DESC_RATEVHT3SS_MCS9; 1230 for (i = 0; i < 2; ++i) 1231 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1232 *rate_num = 2; 1233 break; 1234 default: 1235 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr); 1236 break; 1237 } 1238 } 1239 1240 static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev, 1241 u32 band, u32 rfpath, u32 txnum, 1242 u32 regaddr, u32 bitmask, u32 data) 1243 { 1244 struct rtw_hal *hal = &rtwdev->hal; 1245 u8 rate_num = 0; 1246 u8 rate; 1247 u8 rates[RTW_RF_PATH_MAX] = {0}; 1248 s8 offset; 1249 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0}; 1250 int i; 1251 1252 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data, 1253 rates, pwr_by_rate, &rate_num); 1254 1255 if (WARN_ON(rfpath >= RTW_RF_PATH_MAX || 1256 (band != PHY_BAND_2G && band != PHY_BAND_5G) || 1257 rate_num > RTW_RF_PATH_MAX)) 1258 return; 1259 1260 for (i = 0; i < rate_num; i++) { 1261 offset = pwr_by_rate[i]; 1262 rate = rates[i]; 1263 if (band == PHY_BAND_2G) 1264 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset; 1265 else if (band == PHY_BAND_5G) 1266 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset; 1267 else 1268 continue; 1269 } 1270 } 1271 1272 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl) 1273 { 1274 const struct rtw_phy_pg_cfg_pair *p = tbl->data; 1275 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size; 1276 1277 for (; p < end; p++) { 1278 if (p->addr == 0xfe || p->addr == 0xffe) { 1279 msleep(50); 1280 continue; 1281 } 1282 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path, 1283 p->tx_num, p->addr, p->bitmask, 1284 p->data); 1285 } 1286 } 1287 EXPORT_SYMBOL(rtw_parse_tbl_bb_pg); 1288 1289 static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = { 1290 36, 38, 40, 42, 44, 46, 48, /* Band 1 */ 1291 52, 54, 56, 58, 60, 62, 64, /* Band 2 */ 1292 100, 102, 104, 106, 108, 110, 112, /* Band 3 */ 1293 116, 118, 120, 122, 124, 126, 128, /* Band 3 */ 1294 132, 134, 136, 138, 140, 142, 144, /* Band 3 */ 1295 149, 151, 153, 155, 157, 159, 161, /* Band 4 */ 1296 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */ 1297 1298 static int rtw_channel_to_idx(u8 band, u8 channel) 1299 { 1300 int ch_idx; 1301 u8 n_channel; 1302 1303 if (band == PHY_BAND_2G) { 1304 ch_idx = channel - 1; 1305 n_channel = RTW_MAX_CHANNEL_NUM_2G; 1306 } else if (band == PHY_BAND_5G) { 1307 n_channel = RTW_MAX_CHANNEL_NUM_5G; 1308 for (ch_idx = 0; ch_idx < n_channel; ch_idx++) 1309 if (rtw_channel_idx_5g[ch_idx] == channel) 1310 break; 1311 } else { 1312 return -1; 1313 } 1314 1315 if (ch_idx >= n_channel) 1316 return -1; 1317 1318 return ch_idx; 1319 } 1320 1321 static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band, 1322 u8 bw, u8 rs, u8 ch, s8 pwr_limit) 1323 { 1324 struct rtw_hal *hal = &rtwdev->hal; 1325 u8 max_power_index = rtwdev->chip->max_power_index; 1326 s8 ww; 1327 int ch_idx; 1328 1329 pwr_limit = clamp_t(s8, pwr_limit, 1330 -max_power_index, max_power_index); 1331 ch_idx = rtw_channel_to_idx(band, ch); 1332 1333 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX || 1334 rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) { 1335 WARN(1, 1336 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n", 1337 regd, band, bw, rs, ch_idx, pwr_limit); 1338 return; 1339 } 1340 1341 if (band == PHY_BAND_2G) { 1342 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; 1343 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; 1344 ww = min_t(s8, ww, pwr_limit); 1345 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; 1346 } else if (band == PHY_BAND_5G) { 1347 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; 1348 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; 1349 ww = min_t(s8, ww, pwr_limit); 1350 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; 1351 } 1352 } 1353 1354 /* cross-reference 5G power limits if values are not assigned */ 1355 static void 1356 rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd, 1357 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht) 1358 { 1359 struct rtw_hal *hal = &rtwdev->hal; 1360 u8 max_power_index = rtwdev->chip->max_power_index; 1361 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx]; 1362 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx]; 1363 1364 if (lmt_ht == lmt_vht) 1365 return; 1366 1367 if (lmt_ht == max_power_index) 1368 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht; 1369 1370 else if (lmt_vht == max_power_index) 1371 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht; 1372 } 1373 1374 /* cross-reference power limits for ht and vht */ 1375 static void 1376 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx) 1377 { 1378 u8 rs_idx, rs_ht, rs_vht; 1379 u8 rs_cmp[2][2] = {{RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S}, 1380 {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S} }; 1381 1382 for (rs_idx = 0; rs_idx < 2; rs_idx++) { 1383 rs_ht = rs_cmp[rs_idx][0]; 1384 rs_vht = rs_cmp[rs_idx][1]; 1385 1386 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht); 1387 } 1388 } 1389 1390 /* cross-reference power limits for 5G channels */ 1391 static void 1392 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw) 1393 { 1394 u8 ch_idx; 1395 1396 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++) 1397 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx); 1398 } 1399 1400 /* cross-reference power limits for 20/40M bandwidth */ 1401 static void 1402 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd) 1403 { 1404 u8 bw; 1405 1406 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++) 1407 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw); 1408 } 1409 1410 /* cross-reference power limits */ 1411 static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev) 1412 { 1413 u8 regd; 1414 1415 for (regd = 0; regd < RTW_REGD_MAX; regd++) 1416 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd); 1417 } 1418 1419 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, 1420 const struct rtw_table *tbl) 1421 { 1422 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data; 1423 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size; 1424 1425 for (; p < end; p++) { 1426 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band, 1427 p->bw, p->rs, p->ch, p->txpwr_lmt); 1428 } 1429 1430 rtw_xref_txpwr_lmt(rtwdev); 1431 } 1432 EXPORT_SYMBOL(rtw_parse_tbl_txpwr_lmt); 1433 1434 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1435 u32 addr, u32 data) 1436 { 1437 rtw_write8(rtwdev, addr, data); 1438 } 1439 EXPORT_SYMBOL(rtw_phy_cfg_mac); 1440 1441 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1442 u32 addr, u32 data) 1443 { 1444 rtw_write32(rtwdev, addr, data); 1445 } 1446 EXPORT_SYMBOL(rtw_phy_cfg_agc); 1447 1448 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1449 u32 addr, u32 data) 1450 { 1451 if (addr == 0xfe) 1452 msleep(50); 1453 else if (addr == 0xfd) 1454 mdelay(5); 1455 else if (addr == 0xfc) 1456 mdelay(1); 1457 else if (addr == 0xfb) 1458 usleep_range(50, 60); 1459 else if (addr == 0xfa) 1460 udelay(5); 1461 else if (addr == 0xf9) 1462 udelay(1); 1463 else 1464 rtw_write32(rtwdev, addr, data); 1465 } 1466 EXPORT_SYMBOL(rtw_phy_cfg_bb); 1467 1468 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1469 u32 addr, u32 data) 1470 { 1471 if (addr == 0xffe) { 1472 msleep(50); 1473 } else if (addr == 0xfe) { 1474 usleep_range(100, 110); 1475 } else { 1476 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data); 1477 udelay(1); 1478 } 1479 } 1480 EXPORT_SYMBOL(rtw_phy_cfg_rf); 1481 1482 static void rtw_load_rfk_table(struct rtw_dev *rtwdev) 1483 { 1484 struct rtw_chip_info *chip = rtwdev->chip; 1485 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 1486 1487 if (!chip->rfk_init_tbl) 1488 return; 1489 1490 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1); 1491 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1); 1492 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1); 1493 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1); 1494 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0); 1495 1496 rtw_load_table(rtwdev, chip->rfk_init_tbl); 1497 1498 dpk_info->is_dpk_pwr_on = true; 1499 } 1500 1501 void rtw_phy_load_tables(struct rtw_dev *rtwdev) 1502 { 1503 struct rtw_chip_info *chip = rtwdev->chip; 1504 u8 rf_path; 1505 1506 rtw_load_table(rtwdev, chip->mac_tbl); 1507 rtw_load_table(rtwdev, chip->bb_tbl); 1508 rtw_load_table(rtwdev, chip->agc_tbl); 1509 rtw_load_rfk_table(rtwdev); 1510 1511 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) { 1512 const struct rtw_table *tbl; 1513 1514 tbl = chip->rf_tbl[rf_path]; 1515 rtw_load_table(rtwdev, tbl); 1516 } 1517 } 1518 EXPORT_SYMBOL(rtw_phy_load_tables); 1519 1520 static u8 rtw_get_channel_group(u8 channel) 1521 { 1522 switch (channel) { 1523 default: 1524 WARN_ON(1); 1525 /* fall through */ 1526 case 1: 1527 case 2: 1528 case 36: 1529 case 38: 1530 case 40: 1531 case 42: 1532 return 0; 1533 case 3: 1534 case 4: 1535 case 5: 1536 case 44: 1537 case 46: 1538 case 48: 1539 case 50: 1540 return 1; 1541 case 6: 1542 case 7: 1543 case 8: 1544 case 52: 1545 case 54: 1546 case 56: 1547 case 58: 1548 return 2; 1549 case 9: 1550 case 10: 1551 case 11: 1552 case 60: 1553 case 62: 1554 case 64: 1555 return 3; 1556 case 12: 1557 case 13: 1558 case 100: 1559 case 102: 1560 case 104: 1561 case 106: 1562 return 4; 1563 case 14: 1564 case 108: 1565 case 110: 1566 case 112: 1567 case 114: 1568 return 5; 1569 case 116: 1570 case 118: 1571 case 120: 1572 case 122: 1573 return 6; 1574 case 124: 1575 case 126: 1576 case 128: 1577 case 130: 1578 return 7; 1579 case 132: 1580 case 134: 1581 case 136: 1582 case 138: 1583 return 8; 1584 case 140: 1585 case 142: 1586 case 144: 1587 return 9; 1588 case 149: 1589 case 151: 1590 case 153: 1591 case 155: 1592 return 10; 1593 case 157: 1594 case 159: 1595 case 161: 1596 return 11; 1597 case 165: 1598 case 167: 1599 case 169: 1600 case 171: 1601 return 12; 1602 case 173: 1603 case 175: 1604 case 177: 1605 return 13; 1606 } 1607 } 1608 1609 static s8 rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev *rtwdev, u16 rate) 1610 { 1611 struct rtw_chip_info *chip = rtwdev->chip; 1612 s8 dpd_diff = 0; 1613 1614 if (!chip->en_dis_dpd) 1615 return 0; 1616 1617 #define RTW_DPD_RATE_CHECK(_rate) \ 1618 case DESC_RATE ## _rate: \ 1619 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \ 1620 dpd_diff = -6 * chip->txgi_factor; \ 1621 break 1622 1623 switch (rate) { 1624 RTW_DPD_RATE_CHECK(6M); 1625 RTW_DPD_RATE_CHECK(9M); 1626 RTW_DPD_RATE_CHECK(MCS0); 1627 RTW_DPD_RATE_CHECK(MCS1); 1628 RTW_DPD_RATE_CHECK(MCS8); 1629 RTW_DPD_RATE_CHECK(MCS9); 1630 RTW_DPD_RATE_CHECK(VHT1SS_MCS0); 1631 RTW_DPD_RATE_CHECK(VHT1SS_MCS1); 1632 RTW_DPD_RATE_CHECK(VHT2SS_MCS0); 1633 RTW_DPD_RATE_CHECK(VHT2SS_MCS1); 1634 } 1635 #undef RTW_DPD_RATE_CHECK 1636 1637 return dpd_diff; 1638 } 1639 1640 static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev, 1641 struct rtw_2g_txpwr_idx *pwr_idx_2g, 1642 enum rtw_bandwidth bandwidth, 1643 u8 rate, u8 group) 1644 { 1645 struct rtw_chip_info *chip = rtwdev->chip; 1646 u8 tx_power; 1647 bool mcs_rate; 1648 bool above_2ss; 1649 u8 factor = chip->txgi_factor; 1650 1651 if (rate <= DESC_RATE11M) 1652 tx_power = pwr_idx_2g->cck_base[group]; 1653 else 1654 tx_power = pwr_idx_2g->bw40_base[group]; 1655 1656 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) 1657 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor; 1658 1659 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) || 1660 (rate >= DESC_RATEVHT1SS_MCS0 && 1661 rate <= DESC_RATEVHT2SS_MCS9); 1662 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) || 1663 (rate >= DESC_RATEVHT2SS_MCS0); 1664 1665 if (!mcs_rate) 1666 return tx_power; 1667 1668 switch (bandwidth) { 1669 default: 1670 WARN_ON(1); 1671 /* fall through */ 1672 case RTW_CHANNEL_WIDTH_20: 1673 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor; 1674 if (above_2ss) 1675 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor; 1676 break; 1677 case RTW_CHANNEL_WIDTH_40: 1678 /* bw40 is the base power */ 1679 if (above_2ss) 1680 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor; 1681 break; 1682 } 1683 1684 return tx_power; 1685 } 1686 1687 static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev, 1688 struct rtw_5g_txpwr_idx *pwr_idx_5g, 1689 enum rtw_bandwidth bandwidth, 1690 u8 rate, u8 group) 1691 { 1692 struct rtw_chip_info *chip = rtwdev->chip; 1693 u8 tx_power; 1694 u8 upper, lower; 1695 bool mcs_rate; 1696 bool above_2ss; 1697 u8 factor = chip->txgi_factor; 1698 1699 tx_power = pwr_idx_5g->bw40_base[group]; 1700 1701 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) || 1702 (rate >= DESC_RATEVHT1SS_MCS0 && 1703 rate <= DESC_RATEVHT2SS_MCS9); 1704 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) || 1705 (rate >= DESC_RATEVHT2SS_MCS0); 1706 1707 if (!mcs_rate) { 1708 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor; 1709 return tx_power; 1710 } 1711 1712 switch (bandwidth) { 1713 default: 1714 WARN_ON(1); 1715 /* fall through */ 1716 case RTW_CHANNEL_WIDTH_20: 1717 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor; 1718 if (above_2ss) 1719 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor; 1720 break; 1721 case RTW_CHANNEL_WIDTH_40: 1722 /* bw40 is the base power */ 1723 if (above_2ss) 1724 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor; 1725 break; 1726 case RTW_CHANNEL_WIDTH_80: 1727 /* the base idx of bw80 is the average of bw40+/bw40- */ 1728 lower = pwr_idx_5g->bw40_base[group]; 1729 upper = pwr_idx_5g->bw40_base[group + 1]; 1730 1731 tx_power = (lower + upper) / 2; 1732 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor; 1733 if (above_2ss) 1734 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor; 1735 break; 1736 } 1737 1738 return tx_power; 1739 } 1740 1741 static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band, 1742 enum rtw_bandwidth bw, u8 rf_path, 1743 u8 rate, u8 channel, u8 regd) 1744 { 1745 struct rtw_hal *hal = &rtwdev->hal; 1746 u8 *cch_by_bw = hal->cch_by_bw; 1747 s8 power_limit = (s8)rtwdev->chip->max_power_index; 1748 u8 rs; 1749 int ch_idx; 1750 u8 cur_bw, cur_ch; 1751 s8 cur_lmt; 1752 1753 if (regd > RTW_REGD_WW) 1754 return power_limit; 1755 1756 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M) 1757 rs = RTW_RATE_SECTION_CCK; 1758 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) 1759 rs = RTW_RATE_SECTION_OFDM; 1760 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7) 1761 rs = RTW_RATE_SECTION_HT_1S; 1762 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) 1763 rs = RTW_RATE_SECTION_HT_2S; 1764 else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9) 1765 rs = RTW_RATE_SECTION_VHT_1S; 1766 else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9) 1767 rs = RTW_RATE_SECTION_VHT_2S; 1768 else 1769 goto err; 1770 1771 /* only 20M BW with cck and ofdm */ 1772 if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM) 1773 bw = RTW_CHANNEL_WIDTH_20; 1774 1775 /* only 20/40M BW with ht */ 1776 if (rs == RTW_RATE_SECTION_HT_1S || rs == RTW_RATE_SECTION_HT_2S) 1777 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40); 1778 1779 /* select min power limit among [20M BW ~ current BW] */ 1780 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) { 1781 cur_ch = cch_by_bw[cur_bw]; 1782 1783 ch_idx = rtw_channel_to_idx(band, cur_ch); 1784 if (ch_idx < 0) 1785 goto err; 1786 1787 cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ? 1788 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] : 1789 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx]; 1790 1791 power_limit = min_t(s8, cur_lmt, power_limit); 1792 } 1793 1794 return power_limit; 1795 1796 err: 1797 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n", 1798 band, bw, rf_path, rate, channel); 1799 return (s8)rtwdev->chip->max_power_index; 1800 } 1801 1802 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw, 1803 u8 ch, u8 regd, struct rtw_power_params *pwr_param) 1804 { 1805 struct rtw_hal *hal = &rtwdev->hal; 1806 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1807 struct rtw_txpwr_idx *pwr_idx; 1808 u8 group, band; 1809 u8 *base = &pwr_param->pwr_base; 1810 s8 *offset = &pwr_param->pwr_offset; 1811 s8 *limit = &pwr_param->pwr_limit; 1812 s8 *remnant = &pwr_param->pwr_remnant; 1813 1814 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path]; 1815 group = rtw_get_channel_group(ch); 1816 1817 /* base power index for 2.4G/5G */ 1818 if (IS_CH_2G_BAND(ch)) { 1819 band = PHY_BAND_2G; 1820 *base = rtw_phy_get_2g_tx_power_index(rtwdev, 1821 &pwr_idx->pwr_idx_2g, 1822 bw, rate, group); 1823 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate]; 1824 } else { 1825 band = PHY_BAND_5G; 1826 *base = rtw_phy_get_5g_tx_power_index(rtwdev, 1827 &pwr_idx->pwr_idx_5g, 1828 bw, rate, group); 1829 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate]; 1830 } 1831 1832 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path, 1833 rate, ch, regd); 1834 *remnant = (rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck : 1835 dm_info->txagc_remnant_ofdm); 1836 } 1837 1838 u8 1839 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate, 1840 enum rtw_bandwidth bandwidth, u8 channel, u8 regd) 1841 { 1842 struct rtw_power_params pwr_param = {0}; 1843 u8 tx_power; 1844 s8 offset; 1845 1846 rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth, 1847 channel, regd, &pwr_param); 1848 1849 tx_power = pwr_param.pwr_base; 1850 offset = min_t(s8, pwr_param.pwr_offset, pwr_param.pwr_limit); 1851 1852 if (rtwdev->chip->en_dis_dpd) 1853 offset += rtw_phy_get_dis_dpd_by_rate_diff(rtwdev, rate); 1854 1855 tx_power += offset + pwr_param.pwr_remnant; 1856 1857 if (tx_power > rtwdev->chip->max_power_index) 1858 tx_power = rtwdev->chip->max_power_index; 1859 1860 return tx_power; 1861 } 1862 EXPORT_SYMBOL(rtw_phy_get_tx_power_index); 1863 1864 static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev, 1865 u8 ch, u8 path, u8 rs) 1866 { 1867 struct rtw_hal *hal = &rtwdev->hal; 1868 u8 regd = rtwdev->regd.txpwr_regd; 1869 u8 *rates; 1870 u8 size; 1871 u8 rate; 1872 u8 pwr_idx; 1873 u8 bw; 1874 int i; 1875 1876 if (rs >= RTW_RATE_SECTION_MAX) 1877 return; 1878 1879 rates = rtw_rate_section[rs]; 1880 size = rtw_rate_size[rs]; 1881 bw = hal->current_band_width; 1882 for (i = 0; i < size; i++) { 1883 rate = rates[i]; 1884 pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate, 1885 bw, ch, regd); 1886 hal->tx_pwr_tbl[path][rate] = pwr_idx; 1887 } 1888 } 1889 1890 /* set tx power level by path for each rates, note that the order of the rates 1891 * are *very* important, bacause 8822B/8821C combines every four bytes of tx 1892 * power index into a four-byte power index register, and calls set_tx_agc to 1893 * write these values into hardware 1894 */ 1895 static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev, 1896 u8 ch, u8 path) 1897 { 1898 struct rtw_hal *hal = &rtwdev->hal; 1899 u8 rs; 1900 1901 /* do not need cck rates if we are not in 2.4G */ 1902 if (hal->current_band_type == RTW_BAND_2G) 1903 rs = RTW_RATE_SECTION_CCK; 1904 else 1905 rs = RTW_RATE_SECTION_OFDM; 1906 1907 for (; rs < RTW_RATE_SECTION_MAX; rs++) 1908 rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs); 1909 } 1910 1911 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel) 1912 { 1913 struct rtw_chip_info *chip = rtwdev->chip; 1914 struct rtw_hal *hal = &rtwdev->hal; 1915 u8 path; 1916 1917 mutex_lock(&hal->tx_power_mutex); 1918 1919 for (path = 0; path < hal->rf_path_num; path++) 1920 rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path); 1921 1922 chip->ops->set_tx_power_index(rtwdev); 1923 mutex_unlock(&hal->tx_power_mutex); 1924 } 1925 EXPORT_SYMBOL(rtw_phy_set_tx_power_level); 1926 1927 static void 1928 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path, 1929 u8 rs, u8 size, u8 *rates) 1930 { 1931 u8 rate; 1932 u8 base_idx, rate_idx; 1933 s8 base_2g, base_5g; 1934 1935 if (rs >= RTW_RATE_SECTION_VHT_1S) 1936 base_idx = rates[size - 3]; 1937 else 1938 base_idx = rates[size - 1]; 1939 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx]; 1940 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx]; 1941 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g; 1942 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g; 1943 for (rate = 0; rate < size; rate++) { 1944 rate_idx = rates[rate]; 1945 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g; 1946 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g; 1947 } 1948 } 1949 1950 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal) 1951 { 1952 u8 path; 1953 1954 for (path = 0; path < RTW_RF_PATH_MAX; path++) { 1955 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 1956 RTW_RATE_SECTION_CCK, 1957 rtw_cck_size, rtw_cck_rates); 1958 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 1959 RTW_RATE_SECTION_OFDM, 1960 rtw_ofdm_size, rtw_ofdm_rates); 1961 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 1962 RTW_RATE_SECTION_HT_1S, 1963 rtw_ht_1s_size, rtw_ht_1s_rates); 1964 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 1965 RTW_RATE_SECTION_HT_2S, 1966 rtw_ht_2s_size, rtw_ht_2s_rates); 1967 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 1968 RTW_RATE_SECTION_VHT_1S, 1969 rtw_vht_1s_size, rtw_vht_1s_rates); 1970 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 1971 RTW_RATE_SECTION_VHT_2S, 1972 rtw_vht_2s_size, rtw_vht_2s_rates); 1973 } 1974 } 1975 1976 static void 1977 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs) 1978 { 1979 s8 base; 1980 u8 ch; 1981 1982 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) { 1983 base = hal->tx_pwr_by_rate_base_2g[0][rs]; 1984 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base; 1985 } 1986 1987 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) { 1988 base = hal->tx_pwr_by_rate_base_5g[0][rs]; 1989 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base; 1990 } 1991 } 1992 1993 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal) 1994 { 1995 u8 regd, bw, rs; 1996 1997 /* default at channel 1 */ 1998 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1; 1999 2000 for (regd = 0; regd < RTW_REGD_MAX; regd++) 2001 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) 2002 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 2003 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs); 2004 } 2005 2006 static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev, 2007 u8 regd, u8 bw, u8 rs) 2008 { 2009 struct rtw_hal *hal = &rtwdev->hal; 2010 s8 max_power_index = (s8)rtwdev->chip->max_power_index; 2011 u8 ch; 2012 2013 /* 2.4G channels */ 2014 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) 2015 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index; 2016 2017 /* 5G channels */ 2018 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) 2019 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index; 2020 } 2021 2022 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev) 2023 { 2024 struct rtw_hal *hal = &rtwdev->hal; 2025 u8 regd, path, rate, rs, bw; 2026 2027 /* init tx power by rate offset */ 2028 for (path = 0; path < RTW_RF_PATH_MAX; path++) { 2029 for (rate = 0; rate < DESC_RATE_MAX; rate++) { 2030 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0; 2031 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0; 2032 } 2033 } 2034 2035 /* init tx power limit */ 2036 for (regd = 0; regd < RTW_REGD_MAX; regd++) 2037 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) 2038 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 2039 rtw_phy_init_tx_power_limit(rtwdev, regd, bw, 2040 rs); 2041 } 2042 2043 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev, 2044 struct rtw_swing_table *swing_table) 2045 { 2046 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; 2047 u8 channel = rtwdev->hal.current_channel; 2048 2049 if (IS_CH_2G_BAND(channel)) { 2050 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) { 2051 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p; 2052 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n; 2053 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p; 2054 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n; 2055 } else { 2056 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; 2057 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; 2058 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; 2059 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; 2060 } 2061 } else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 2062 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1]; 2063 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1]; 2064 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1]; 2065 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1]; 2066 } else if (IS_CH_5G_BAND_3(channel)) { 2067 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2]; 2068 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2]; 2069 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2]; 2070 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2]; 2071 } else if (IS_CH_5G_BAND_4(channel)) { 2072 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3]; 2073 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3]; 2074 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3]; 2075 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3]; 2076 } else { 2077 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; 2078 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; 2079 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; 2080 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; 2081 } 2082 } 2083 EXPORT_SYMBOL(rtw_phy_config_swing_table); 2084 2085 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path) 2086 { 2087 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2088 2089 ewma_thermal_add(&dm_info->avg_thermal[path], thermal); 2090 dm_info->thermal_avg[path] = 2091 ewma_thermal_read(&dm_info->avg_thermal[path]); 2092 } 2093 EXPORT_SYMBOL(rtw_phy_pwrtrack_avg); 2094 2095 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal, 2096 u8 path) 2097 { 2098 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2099 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]); 2100 2101 if (avg == thermal) 2102 return false; 2103 2104 return true; 2105 } 2106 EXPORT_SYMBOL(rtw_phy_pwrtrack_thermal_changed); 2107 2108 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path) 2109 { 2110 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2111 u8 therm_avg, therm_efuse, therm_delta; 2112 2113 therm_avg = dm_info->thermal_avg[path]; 2114 therm_efuse = rtwdev->efuse.thermal_meter[path]; 2115 therm_delta = abs(therm_avg - therm_efuse); 2116 2117 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1); 2118 } 2119 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_delta); 2120 2121 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev, 2122 struct rtw_swing_table *swing_table, 2123 u8 tbl_path, u8 therm_path, u8 delta) 2124 { 2125 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2126 const u8 *delta_swing_table_idx_pos; 2127 const u8 *delta_swing_table_idx_neg; 2128 2129 if (delta >= RTW_PWR_TRK_TBL_SZ) { 2130 rtw_warn(rtwdev, "power track table overflow\n"); 2131 return 0; 2132 } 2133 2134 if (!swing_table) { 2135 rtw_warn(rtwdev, "swing table not configured\n"); 2136 return 0; 2137 } 2138 2139 delta_swing_table_idx_pos = swing_table->p[tbl_path]; 2140 delta_swing_table_idx_neg = swing_table->n[tbl_path]; 2141 2142 if (!delta_swing_table_idx_pos || !delta_swing_table_idx_neg) { 2143 rtw_warn(rtwdev, "invalid swing table index\n"); 2144 return 0; 2145 } 2146 2147 if (dm_info->thermal_avg[therm_path] > 2148 rtwdev->efuse.thermal_meter[therm_path]) 2149 return delta_swing_table_idx_pos[delta]; 2150 else 2151 return -delta_swing_table_idx_neg[delta]; 2152 } 2153 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_pwridx); 2154 2155 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev) 2156 { 2157 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2158 u8 delta_iqk; 2159 2160 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k); 2161 if (delta_iqk >= rtwdev->chip->iqk_threshold) { 2162 dm_info->thermal_meter_k = dm_info->thermal_avg[0]; 2163 return true; 2164 } 2165 return false; 2166 } 2167 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_iqk); 2168