1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_PCI_H_ 6 #define __RTK_PCI_H_ 7 8 #include "main.h" 9 10 #define RTK_DEFAULT_TX_DESC_NUM 128 11 #define RTK_BEQ_TX_DESC_NUM 256 12 13 #define RTK_MAX_RX_DESC_NUM 512 14 /* 11K + rx desc size */ 15 #define RTK_PCI_RX_BUF_SIZE (11454 + 24) 16 17 #define RTK_PCI_CTRL 0x300 18 #define BIT_RST_TRXDMA_INTF BIT(20) 19 #define BIT_RX_TAG_EN BIT(15) 20 #define REG_DBI_WDATA_V1 0x03E8 21 #define REG_DBI_RDATA_V1 0x03EC 22 #define REG_DBI_FLAG_V1 0x03F0 23 #define BIT_DBI_RFLAG BIT(17) 24 #define BIT_DBI_WFLAG BIT(16) 25 #define BITS_DBI_WREN GENMASK(15, 12) 26 #define BITS_DBI_ADDR_MASK GENMASK(11, 2) 27 28 #define REG_MDIO_V1 0x03F4 29 #define REG_PCIE_MIX_CFG 0x03F8 30 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0) 31 #define BIT_MDIO_WFLAG_V1 BIT(5) 32 #define RTW_PCI_MDIO_PG_SZ BIT(5) 33 #define RTW_PCI_MDIO_PG_OFFS_G1 0 34 #define RTW_PCI_MDIO_PG_OFFS_G2 2 35 #define RTW_PCI_WR_RETRY_CNT 20 36 37 #define RTK_PCIE_LINK_CFG 0x0719 38 #define BIT_CLKREQ_SW_EN BIT(4) 39 #define BIT_L1_SW_EN BIT(3) 40 #define RTK_PCIE_CLKDLY_CTRL 0x0725 41 42 #define BIT_PCI_BCNQ_FLAG BIT(4) 43 #define RTK_PCI_TXBD_DESA_BCNQ 0x308 44 #define RTK_PCI_TXBD_DESA_H2CQ 0x1320 45 #define RTK_PCI_TXBD_DESA_MGMTQ 0x310 46 #define RTK_PCI_TXBD_DESA_BKQ 0x330 47 #define RTK_PCI_TXBD_DESA_BEQ 0x328 48 #define RTK_PCI_TXBD_DESA_VIQ 0x320 49 #define RTK_PCI_TXBD_DESA_VOQ 0x318 50 #define RTK_PCI_TXBD_DESA_HI0Q 0x340 51 #define RTK_PCI_RXBD_DESA_MPDUQ 0x338 52 53 #define TRX_BD_IDX_MASK GENMASK(11, 0) 54 #define TRX_BD_HW_IDX_MASK GENMASK(27, 16) 55 56 /* BCNQ is specialized for rsvd page, does not need to specify a number */ 57 #define RTK_PCI_TXBD_NUM_H2CQ 0x1328 58 #define RTK_PCI_TXBD_NUM_MGMTQ 0x380 59 #define RTK_PCI_TXBD_NUM_BKQ 0x38A 60 #define RTK_PCI_TXBD_NUM_BEQ 0x388 61 #define RTK_PCI_TXBD_NUM_VIQ 0x386 62 #define RTK_PCI_TXBD_NUM_VOQ 0x384 63 #define RTK_PCI_TXBD_NUM_HI0Q 0x38C 64 #define RTK_PCI_RXBD_NUM_MPDUQ 0x382 65 #define RTK_PCI_TXBD_IDX_H2CQ 0x132C 66 #define RTK_PCI_TXBD_IDX_MGMTQ 0x3B0 67 #define RTK_PCI_TXBD_IDX_BKQ 0x3AC 68 #define RTK_PCI_TXBD_IDX_BEQ 0x3A8 69 #define RTK_PCI_TXBD_IDX_VIQ 0x3A4 70 #define RTK_PCI_TXBD_IDX_VOQ 0x3A0 71 #define RTK_PCI_TXBD_IDX_HI0Q 0x3B8 72 #define RTK_PCI_RXBD_IDX_MPDUQ 0x3B4 73 74 #define RTK_PCI_TXBD_RWPTR_CLR 0x39C 75 #define RTK_PCI_TXBD_H2CQ_CSR 0x1330 76 77 #define BIT_CLR_H2CQ_HOST_IDX BIT(16) 78 #define BIT_CLR_H2CQ_HW_IDX BIT(8) 79 80 #define RTK_PCI_HIMR0 0x0B0 81 #define RTK_PCI_HISR0 0x0B4 82 #define RTK_PCI_HIMR1 0x0B8 83 #define RTK_PCI_HISR1 0x0BC 84 #define RTK_PCI_HIMR2 0x10B0 85 #define RTK_PCI_HISR2 0x10B4 86 #define RTK_PCI_HIMR3 0x10B8 87 #define RTK_PCI_HISR3 0x10BC 88 /* IMR 0 */ 89 #define IMR_TIMER2 BIT(31) 90 #define IMR_TIMER1 BIT(30) 91 #define IMR_PSTIMEOUT BIT(29) 92 #define IMR_GTINT4 BIT(28) 93 #define IMR_GTINT3 BIT(27) 94 #define IMR_TBDER BIT(26) 95 #define IMR_TBDOK BIT(25) 96 #define IMR_TSF_BIT32_TOGGLE BIT(24) 97 #define IMR_BCNDMAINT0 BIT(20) 98 #define IMR_BCNDOK0 BIT(16) 99 #define IMR_HSISR_IND_ON_INT BIT(15) 100 #define IMR_BCNDMAINT_E BIT(14) 101 #define IMR_ATIMEND BIT(12) 102 #define IMR_HISR1_IND_INT BIT(11) 103 #define IMR_C2HCMD BIT(10) 104 #define IMR_CPWM2 BIT(9) 105 #define IMR_CPWM BIT(8) 106 #define IMR_HIGHDOK BIT(7) 107 #define IMR_MGNTDOK BIT(6) 108 #define IMR_BKDOK BIT(5) 109 #define IMR_BEDOK BIT(4) 110 #define IMR_VIDOK BIT(3) 111 #define IMR_VODOK BIT(2) 112 #define IMR_RDU BIT(1) 113 #define IMR_ROK BIT(0) 114 /* IMR 1 */ 115 #define IMR_TXFIFO_TH_INT BIT(30) 116 #define IMR_BTON_STS_UPDATE BIT(29) 117 #define IMR_MCUERR BIT(28) 118 #define IMR_BCNDMAINT7 BIT(27) 119 #define IMR_BCNDMAINT6 BIT(26) 120 #define IMR_BCNDMAINT5 BIT(25) 121 #define IMR_BCNDMAINT4 BIT(24) 122 #define IMR_BCNDMAINT3 BIT(23) 123 #define IMR_BCNDMAINT2 BIT(22) 124 #define IMR_BCNDMAINT1 BIT(21) 125 #define IMR_BCNDOK7 BIT(20) 126 #define IMR_BCNDOK6 BIT(19) 127 #define IMR_BCNDOK5 BIT(18) 128 #define IMR_BCNDOK4 BIT(17) 129 #define IMR_BCNDOK3 BIT(16) 130 #define IMR_BCNDOK2 BIT(15) 131 #define IMR_BCNDOK1 BIT(14) 132 #define IMR_ATIMEND_E BIT(13) 133 #define IMR_ATIMEND BIT(12) 134 #define IMR_TXERR BIT(11) 135 #define IMR_RXERR BIT(10) 136 #define IMR_TXFOVW BIT(9) 137 #define IMR_RXFOVW BIT(8) 138 #define IMR_CPU_MGQ_TXDONE BIT(5) 139 #define IMR_PS_TIMER_C BIT(4) 140 #define IMR_PS_TIMER_B BIT(3) 141 #define IMR_PS_TIMER_A BIT(2) 142 #define IMR_CPUMGQ_TX_TIMER BIT(1) 143 /* IMR 3 */ 144 #define IMR_H2CDOK BIT(16) 145 146 enum rtw_pci_flags { 147 RTW_PCI_FLAG_NAPI_RUNNING, 148 149 NUM_OF_RTW_PCI_FLAGS, 150 }; 151 152 /* one element is reserved to know if the ring is closed */ 153 static inline int avail_desc(u32 wp, u32 rp, u32 len) 154 { 155 if (rp > wp) 156 return rp - wp - 1; 157 else 158 return len - wp + rp - 1; 159 } 160 161 #define RTK_PCI_TXBD_OWN_OFFSET 15 162 #define RTK_PCI_TXBD_BCN_WORK 0x383 163 164 struct rtw_pci_tx_buffer_desc { 165 __le16 buf_size; 166 __le16 psb_len; 167 __le32 dma; 168 }; 169 170 struct rtw_pci_tx_data { 171 dma_addr_t dma; 172 u8 sn; 173 }; 174 175 struct rtw_pci_ring { 176 u8 *head; 177 dma_addr_t dma; 178 179 u8 desc_size; 180 181 u32 len; 182 u32 wp; 183 u32 rp; 184 }; 185 186 struct rtw_pci_tx_ring { 187 struct rtw_pci_ring r; 188 struct sk_buff_head queue; 189 bool queue_stopped; 190 }; 191 192 struct rtw_pci_rx_buffer_desc { 193 __le16 buf_size; 194 __le16 total_pkt_size; 195 __le32 dma; 196 }; 197 198 struct rtw_pci_rx_ring { 199 struct rtw_pci_ring r; 200 struct sk_buff *buf[RTK_MAX_RX_DESC_NUM]; 201 }; 202 203 #define RX_TAG_MAX 8192 204 205 struct rtw_pci { 206 struct pci_dev *pdev; 207 208 /* Used for PCI interrupt. */ 209 spinlock_t hwirq_lock; 210 /* Used for PCI TX ring/queueing, and enable INT. */ 211 spinlock_t irq_lock; 212 u32 irq_mask[4]; 213 bool irq_enabled; 214 215 /* napi structure */ 216 struct net_device netdev; 217 struct napi_struct napi; 218 219 u16 rx_tag; 220 DECLARE_BITMAP(tx_queued, RTK_MAX_TX_QUEUE_NUM); 221 struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM]; 222 struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM]; 223 u16 link_ctrl; 224 DECLARE_BITMAP(flags, NUM_OF_RTW_PCI_FLAGS); 225 226 void __iomem *mmap; 227 }; 228 229 extern const struct dev_pm_ops rtw_pm_ops; 230 231 int rtw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 232 void rtw_pci_remove(struct pci_dev *pdev); 233 void rtw_pci_shutdown(struct pci_dev *pdev); 234 235 static inline u32 max_num_of_tx_queue(u8 queue) 236 { 237 u32 max_num; 238 239 switch (queue) { 240 case RTW_TX_QUEUE_BE: 241 max_num = RTK_BEQ_TX_DESC_NUM; 242 break; 243 case RTW_TX_QUEUE_BCN: 244 max_num = 1; 245 break; 246 default: 247 max_num = RTK_DEFAULT_TX_DESC_NUM; 248 break; 249 } 250 251 return max_num; 252 } 253 254 static inline struct 255 rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb) 256 { 257 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 258 259 BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) > 260 sizeof(info->status.status_driver_data)); 261 262 return (struct rtw_pci_tx_data *)info->status.status_driver_data; 263 } 264 265 static inline 266 struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring, 267 u32 size) 268 { 269 u8 *buf_desc; 270 271 buf_desc = ring->r.head + ring->r.wp * size; 272 return (struct rtw_pci_tx_buffer_desc *)buf_desc; 273 } 274 275 #endif 276