1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_PCI_H_ 6 #define __RTK_PCI_H_ 7 8 #include "main.h" 9 10 #define RTK_DEFAULT_TX_DESC_NUM 128 11 #define RTK_BEQ_TX_DESC_NUM 256 12 13 #define RTK_MAX_RX_DESC_NUM 512 14 /* 11K + rx desc size */ 15 #define RTK_PCI_RX_BUF_SIZE (11454 + 24) 16 17 #define RTK_PCI_CTRL 0x300 18 #define BIT_RST_TRXDMA_INTF BIT(20) 19 #define BIT_RX_TAG_EN BIT(15) 20 #define REG_DBI_WDATA_V1 0x03E8 21 #define REG_DBI_RDATA_V1 0x03EC 22 #define REG_DBI_FLAG_V1 0x03F0 23 #define BIT_DBI_RFLAG BIT(17) 24 #define BIT_DBI_WFLAG BIT(16) 25 #define BITS_DBI_WREN GENMASK(15, 12) 26 #define BITS_DBI_ADDR_MASK GENMASK(11, 2) 27 28 #define REG_MDIO_V1 0x03F4 29 #define REG_PCIE_MIX_CFG 0x03F8 30 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0) 31 #define BIT_MDIO_WFLAG_V1 BIT(5) 32 #define RTW_PCI_MDIO_PG_SZ BIT(5) 33 #define RTW_PCI_MDIO_PG_OFFS_G1 0 34 #define RTW_PCI_MDIO_PG_OFFS_G2 2 35 #define RTW_PCI_WR_RETRY_CNT 20 36 37 #define RTK_PCIE_LINK_CFG 0x0719 38 #define BIT_CLKREQ_SW_EN BIT(4) 39 #define BIT_L1_SW_EN BIT(3) 40 #define RTK_PCIE_CLKDLY_CTRL 0x0725 41 42 #define BIT_PCI_BCNQ_FLAG BIT(4) 43 #define RTK_PCI_TXBD_DESA_BCNQ 0x308 44 #define RTK_PCI_TXBD_DESA_H2CQ 0x1320 45 #define RTK_PCI_TXBD_DESA_MGMTQ 0x310 46 #define RTK_PCI_TXBD_DESA_BKQ 0x330 47 #define RTK_PCI_TXBD_DESA_BEQ 0x328 48 #define RTK_PCI_TXBD_DESA_VIQ 0x320 49 #define RTK_PCI_TXBD_DESA_VOQ 0x318 50 #define RTK_PCI_TXBD_DESA_HI0Q 0x340 51 #define RTK_PCI_RXBD_DESA_MPDUQ 0x338 52 53 #define TRX_BD_IDX_MASK GENMASK(11, 0) 54 55 /* BCNQ is specialized for rsvd page, does not need to specify a number */ 56 #define RTK_PCI_TXBD_NUM_H2CQ 0x1328 57 #define RTK_PCI_TXBD_NUM_MGMTQ 0x380 58 #define RTK_PCI_TXBD_NUM_BKQ 0x38A 59 #define RTK_PCI_TXBD_NUM_BEQ 0x388 60 #define RTK_PCI_TXBD_NUM_VIQ 0x386 61 #define RTK_PCI_TXBD_NUM_VOQ 0x384 62 #define RTK_PCI_TXBD_NUM_HI0Q 0x38C 63 #define RTK_PCI_RXBD_NUM_MPDUQ 0x382 64 #define RTK_PCI_TXBD_IDX_H2CQ 0x132C 65 #define RTK_PCI_TXBD_IDX_MGMTQ 0x3B0 66 #define RTK_PCI_TXBD_IDX_BKQ 0x3AC 67 #define RTK_PCI_TXBD_IDX_BEQ 0x3A8 68 #define RTK_PCI_TXBD_IDX_VIQ 0x3A4 69 #define RTK_PCI_TXBD_IDX_VOQ 0x3A0 70 #define RTK_PCI_TXBD_IDX_HI0Q 0x3B8 71 #define RTK_PCI_RXBD_IDX_MPDUQ 0x3B4 72 73 #define RTK_PCI_TXBD_RWPTR_CLR 0x39C 74 #define RTK_PCI_TXBD_H2CQ_CSR 0x1330 75 76 #define BIT_CLR_H2CQ_HOST_IDX BIT(16) 77 #define BIT_CLR_H2CQ_HW_IDX BIT(8) 78 79 #define RTK_PCI_HIMR0 0x0B0 80 #define RTK_PCI_HISR0 0x0B4 81 #define RTK_PCI_HIMR1 0x0B8 82 #define RTK_PCI_HISR1 0x0BC 83 #define RTK_PCI_HIMR2 0x10B0 84 #define RTK_PCI_HISR2 0x10B4 85 #define RTK_PCI_HIMR3 0x10B8 86 #define RTK_PCI_HISR3 0x10BC 87 /* IMR 0 */ 88 #define IMR_TIMER2 BIT(31) 89 #define IMR_TIMER1 BIT(30) 90 #define IMR_PSTIMEOUT BIT(29) 91 #define IMR_GTINT4 BIT(28) 92 #define IMR_GTINT3 BIT(27) 93 #define IMR_TBDER BIT(26) 94 #define IMR_TBDOK BIT(25) 95 #define IMR_TSF_BIT32_TOGGLE BIT(24) 96 #define IMR_BCNDMAINT0 BIT(20) 97 #define IMR_BCNDOK0 BIT(16) 98 #define IMR_HSISR_IND_ON_INT BIT(15) 99 #define IMR_BCNDMAINT_E BIT(14) 100 #define IMR_ATIMEND BIT(12) 101 #define IMR_HISR1_IND_INT BIT(11) 102 #define IMR_C2HCMD BIT(10) 103 #define IMR_CPWM2 BIT(9) 104 #define IMR_CPWM BIT(8) 105 #define IMR_HIGHDOK BIT(7) 106 #define IMR_MGNTDOK BIT(6) 107 #define IMR_BKDOK BIT(5) 108 #define IMR_BEDOK BIT(4) 109 #define IMR_VIDOK BIT(3) 110 #define IMR_VODOK BIT(2) 111 #define IMR_RDU BIT(1) 112 #define IMR_ROK BIT(0) 113 /* IMR 1 */ 114 #define IMR_TXFIFO_TH_INT BIT(30) 115 #define IMR_BTON_STS_UPDATE BIT(29) 116 #define IMR_MCUERR BIT(28) 117 #define IMR_BCNDMAINT7 BIT(27) 118 #define IMR_BCNDMAINT6 BIT(26) 119 #define IMR_BCNDMAINT5 BIT(25) 120 #define IMR_BCNDMAINT4 BIT(24) 121 #define IMR_BCNDMAINT3 BIT(23) 122 #define IMR_BCNDMAINT2 BIT(22) 123 #define IMR_BCNDMAINT1 BIT(21) 124 #define IMR_BCNDOK7 BIT(20) 125 #define IMR_BCNDOK6 BIT(19) 126 #define IMR_BCNDOK5 BIT(18) 127 #define IMR_BCNDOK4 BIT(17) 128 #define IMR_BCNDOK3 BIT(16) 129 #define IMR_BCNDOK2 BIT(15) 130 #define IMR_BCNDOK1 BIT(14) 131 #define IMR_ATIMEND_E BIT(13) 132 #define IMR_ATIMEND BIT(12) 133 #define IMR_TXERR BIT(11) 134 #define IMR_RXERR BIT(10) 135 #define IMR_TXFOVW BIT(9) 136 #define IMR_RXFOVW BIT(8) 137 #define IMR_CPU_MGQ_TXDONE BIT(5) 138 #define IMR_PS_TIMER_C BIT(4) 139 #define IMR_PS_TIMER_B BIT(3) 140 #define IMR_PS_TIMER_A BIT(2) 141 #define IMR_CPUMGQ_TX_TIMER BIT(1) 142 /* IMR 3 */ 143 #define IMR_H2CDOK BIT(16) 144 145 /* one element is reserved to know if the ring is closed */ 146 static inline int avail_desc(u32 wp, u32 rp, u32 len) 147 { 148 if (rp > wp) 149 return rp - wp - 1; 150 else 151 return len - wp + rp - 1; 152 } 153 154 #define RTK_PCI_TXBD_OWN_OFFSET 15 155 #define RTK_PCI_TXBD_BCN_WORK 0x383 156 157 struct rtw_pci_tx_buffer_desc { 158 __le16 buf_size; 159 __le16 psb_len; 160 __le32 dma; 161 }; 162 163 struct rtw_pci_tx_data { 164 dma_addr_t dma; 165 u8 sn; 166 }; 167 168 struct rtw_pci_ring { 169 u8 *head; 170 dma_addr_t dma; 171 172 u8 desc_size; 173 174 u32 len; 175 u32 wp; 176 u32 rp; 177 }; 178 179 struct rtw_pci_tx_ring { 180 struct rtw_pci_ring r; 181 struct sk_buff_head queue; 182 bool queue_stopped; 183 }; 184 185 struct rtw_pci_rx_buffer_desc { 186 __le16 buf_size; 187 __le16 total_pkt_size; 188 __le32 dma; 189 }; 190 191 struct rtw_pci_rx_ring { 192 struct rtw_pci_ring r; 193 struct sk_buff *buf[RTK_MAX_RX_DESC_NUM]; 194 }; 195 196 #define RX_TAG_MAX 8192 197 198 struct rtw_pci { 199 struct pci_dev *pdev; 200 201 /* Used for PCI interrupt. */ 202 spinlock_t hwirq_lock; 203 /* Used for PCI TX queueing. */ 204 spinlock_t irq_lock; 205 u32 irq_mask[4]; 206 bool irq_enabled; 207 208 u16 rx_tag; 209 DECLARE_BITMAP(tx_queued, RTK_MAX_TX_QUEUE_NUM); 210 struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM]; 211 struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM]; 212 u16 link_ctrl; 213 214 void __iomem *mmap; 215 }; 216 217 extern const struct dev_pm_ops rtw_pm_ops; 218 219 int rtw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 220 void rtw_pci_remove(struct pci_dev *pdev); 221 void rtw_pci_shutdown(struct pci_dev *pdev); 222 223 static inline u32 max_num_of_tx_queue(u8 queue) 224 { 225 u32 max_num; 226 227 switch (queue) { 228 case RTW_TX_QUEUE_BE: 229 max_num = RTK_BEQ_TX_DESC_NUM; 230 break; 231 case RTW_TX_QUEUE_BCN: 232 max_num = 1; 233 break; 234 default: 235 max_num = RTK_DEFAULT_TX_DESC_NUM; 236 break; 237 } 238 239 return max_num; 240 } 241 242 static inline struct 243 rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb) 244 { 245 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 246 247 BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) > 248 sizeof(info->status.status_driver_data)); 249 250 return (struct rtw_pci_tx_data *)info->status.status_driver_data; 251 } 252 253 static inline 254 struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring, 255 u32 size) 256 { 257 u8 *buf_desc; 258 259 buf_desc = ring->r.head + ring->r.wp * size; 260 return (struct rtw_pci_tx_buffer_desc *)buf_desc; 261 } 262 263 #endif 264