1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTK_PCI_H_
6 #define __RTK_PCI_H_
7 
8 #define RTK_DEFAULT_TX_DESC_NUM 128
9 #define RTK_BEQ_TX_DESC_NUM	256
10 
11 #define RTK_MAX_RX_DESC_NUM	512
12 /* 11K + rx desc size */
13 #define RTK_PCI_RX_BUF_SIZE	(11454 + 24)
14 
15 #define RTK_PCI_CTRL		0x300
16 #define BIT_RST_TRXDMA_INTF	BIT(20)
17 #define BIT_RX_TAG_EN		BIT(15)
18 #define REG_DBI_WDATA_V1	0x03E8
19 #define REG_DBI_RDATA_V1	0x03EC
20 #define REG_DBI_FLAG_V1		0x03F0
21 #define BIT_DBI_RFLAG		BIT(17)
22 #define BIT_DBI_WFLAG		BIT(16)
23 #define BITS_DBI_WREN		GENMASK(15, 12)
24 #define BITS_DBI_ADDR_MASK	GENMASK(11, 2)
25 
26 #define REG_MDIO_V1		0x03F4
27 #define REG_PCIE_MIX_CFG	0x03F8
28 #define BITS_MDIO_ADDR_MASK	GENMASK(4, 0)
29 #define BIT_MDIO_WFLAG_V1	BIT(5)
30 #define RTW_PCI_MDIO_PG_SZ	BIT(5)
31 #define RTW_PCI_MDIO_PG_OFFS_G1	0
32 #define RTW_PCI_MDIO_PG_OFFS_G2	2
33 #define RTW_PCI_WR_RETRY_CNT	20
34 
35 #define RTK_PCIE_LINK_CFG	0x0719
36 #define BIT_CLKREQ_SW_EN	BIT(4)
37 #define BIT_L1_SW_EN		BIT(3)
38 #define RTK_PCIE_CLKDLY_CTRL	0x0725
39 
40 #define BIT_PCI_BCNQ_FLAG	BIT(4)
41 #define RTK_PCI_TXBD_DESA_BCNQ	0x308
42 #define RTK_PCI_TXBD_DESA_H2CQ	0x1320
43 #define RTK_PCI_TXBD_DESA_MGMTQ	0x310
44 #define RTK_PCI_TXBD_DESA_BKQ	0x330
45 #define RTK_PCI_TXBD_DESA_BEQ	0x328
46 #define RTK_PCI_TXBD_DESA_VIQ	0x320
47 #define RTK_PCI_TXBD_DESA_VOQ	0x318
48 #define RTK_PCI_TXBD_DESA_HI0Q	0x340
49 #define RTK_PCI_RXBD_DESA_MPDUQ	0x338
50 
51 #define TRX_BD_IDX_MASK		GENMASK(11, 0)
52 
53 /* BCNQ is specialized for rsvd page, does not need to specify a number */
54 #define RTK_PCI_TXBD_NUM_H2CQ	0x1328
55 #define RTK_PCI_TXBD_NUM_MGMTQ	0x380
56 #define RTK_PCI_TXBD_NUM_BKQ	0x38A
57 #define RTK_PCI_TXBD_NUM_BEQ	0x388
58 #define RTK_PCI_TXBD_NUM_VIQ	0x386
59 #define RTK_PCI_TXBD_NUM_VOQ	0x384
60 #define RTK_PCI_TXBD_NUM_HI0Q	0x38C
61 #define RTK_PCI_RXBD_NUM_MPDUQ	0x382
62 #define RTK_PCI_TXBD_IDX_H2CQ	0x132C
63 #define RTK_PCI_TXBD_IDX_MGMTQ	0x3B0
64 #define RTK_PCI_TXBD_IDX_BKQ	0x3AC
65 #define RTK_PCI_TXBD_IDX_BEQ	0x3A8
66 #define RTK_PCI_TXBD_IDX_VIQ	0x3A4
67 #define RTK_PCI_TXBD_IDX_VOQ	0x3A0
68 #define RTK_PCI_TXBD_IDX_HI0Q	0x3B8
69 #define RTK_PCI_RXBD_IDX_MPDUQ	0x3B4
70 
71 #define RTK_PCI_TXBD_RWPTR_CLR	0x39C
72 #define RTK_PCI_TXBD_H2CQ_CSR	0x1330
73 
74 #define BIT_CLR_H2CQ_HOST_IDX	BIT(16)
75 #define BIT_CLR_H2CQ_HW_IDX	BIT(8)
76 
77 #define RTK_PCI_HIMR0		0x0B0
78 #define RTK_PCI_HISR0		0x0B4
79 #define RTK_PCI_HIMR1		0x0B8
80 #define RTK_PCI_HISR1		0x0BC
81 #define RTK_PCI_HIMR2		0x10B0
82 #define RTK_PCI_HISR2		0x10B4
83 #define RTK_PCI_HIMR3		0x10B8
84 #define RTK_PCI_HISR3		0x10BC
85 /* IMR 0 */
86 #define IMR_TIMER2		BIT(31)
87 #define IMR_TIMER1		BIT(30)
88 #define IMR_PSTIMEOUT		BIT(29)
89 #define IMR_GTINT4		BIT(28)
90 #define IMR_GTINT3		BIT(27)
91 #define IMR_TBDER		BIT(26)
92 #define IMR_TBDOK		BIT(25)
93 #define IMR_TSF_BIT32_TOGGLE	BIT(24)
94 #define IMR_BCNDMAINT0		BIT(20)
95 #define IMR_BCNDOK0		BIT(16)
96 #define IMR_HSISR_IND_ON_INT	BIT(15)
97 #define IMR_BCNDMAINT_E		BIT(14)
98 #define IMR_ATIMEND		BIT(12)
99 #define IMR_HISR1_IND_INT	BIT(11)
100 #define IMR_C2HCMD		BIT(10)
101 #define IMR_CPWM2		BIT(9)
102 #define IMR_CPWM		BIT(8)
103 #define IMR_HIGHDOK		BIT(7)
104 #define IMR_MGNTDOK		BIT(6)
105 #define IMR_BKDOK		BIT(5)
106 #define IMR_BEDOK		BIT(4)
107 #define IMR_VIDOK		BIT(3)
108 #define IMR_VODOK		BIT(2)
109 #define IMR_RDU			BIT(1)
110 #define IMR_ROK			BIT(0)
111 /* IMR 1 */
112 #define IMR_TXFIFO_TH_INT	BIT(30)
113 #define IMR_BTON_STS_UPDATE	BIT(29)
114 #define IMR_MCUERR		BIT(28)
115 #define IMR_BCNDMAINT7		BIT(27)
116 #define IMR_BCNDMAINT6		BIT(26)
117 #define IMR_BCNDMAINT5		BIT(25)
118 #define IMR_BCNDMAINT4		BIT(24)
119 #define IMR_BCNDMAINT3		BIT(23)
120 #define IMR_BCNDMAINT2		BIT(22)
121 #define IMR_BCNDMAINT1		BIT(21)
122 #define IMR_BCNDOK7		BIT(20)
123 #define IMR_BCNDOK6		BIT(19)
124 #define IMR_BCNDOK5		BIT(18)
125 #define IMR_BCNDOK4		BIT(17)
126 #define IMR_BCNDOK3		BIT(16)
127 #define IMR_BCNDOK2		BIT(15)
128 #define IMR_BCNDOK1		BIT(14)
129 #define IMR_ATIMEND_E		BIT(13)
130 #define IMR_ATIMEND		BIT(12)
131 #define IMR_TXERR		BIT(11)
132 #define IMR_RXERR		BIT(10)
133 #define IMR_TXFOVW		BIT(9)
134 #define IMR_RXFOVW		BIT(8)
135 #define IMR_CPU_MGQ_TXDONE	BIT(5)
136 #define IMR_PS_TIMER_C		BIT(4)
137 #define IMR_PS_TIMER_B		BIT(3)
138 #define IMR_PS_TIMER_A		BIT(2)
139 #define IMR_CPUMGQ_TX_TIMER	BIT(1)
140 /* IMR 3 */
141 #define IMR_H2CDOK		BIT(16)
142 
143 /* one element is reserved to know if the ring is closed */
144 static inline int avail_desc(u32 wp, u32 rp, u32 len)
145 {
146 	if (rp > wp)
147 		return rp - wp - 1;
148 	else
149 		return len - wp + rp - 1;
150 }
151 
152 #define RTK_PCI_TXBD_OWN_OFFSET 15
153 #define RTK_PCI_TXBD_BCN_WORK	0x383
154 
155 struct rtw_pci_tx_buffer_desc {
156 	__le16 buf_size;
157 	__le16 psb_len;
158 	__le32 dma;
159 };
160 
161 struct rtw_pci_tx_data {
162 	dma_addr_t dma;
163 	u8 sn;
164 };
165 
166 struct rtw_pci_ring {
167 	u8 *head;
168 	dma_addr_t dma;
169 
170 	u8 desc_size;
171 
172 	u32 len;
173 	u32 wp;
174 	u32 rp;
175 };
176 
177 struct rtw_pci_tx_ring {
178 	struct rtw_pci_ring r;
179 	struct sk_buff_head queue;
180 	bool queue_stopped;
181 };
182 
183 struct rtw_pci_rx_buffer_desc {
184 	__le16 buf_size;
185 	__le16 total_pkt_size;
186 	__le32 dma;
187 };
188 
189 struct rtw_pci_rx_ring {
190 	struct rtw_pci_ring r;
191 	struct sk_buff *buf[RTK_MAX_RX_DESC_NUM];
192 };
193 
194 #define RX_TAG_MAX	8192
195 
196 struct rtw_pci {
197 	struct pci_dev *pdev;
198 
199 	/* Used for PCI interrupt. */
200 	spinlock_t hwirq_lock;
201 	/* Used for PCI TX queueing. */
202 	spinlock_t irq_lock;
203 	u32 irq_mask[4];
204 	bool irq_enabled;
205 
206 	u16 rx_tag;
207 	DECLARE_BITMAP(tx_queued, RTK_MAX_TX_QUEUE_NUM);
208 	struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM];
209 	struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM];
210 	u16 link_ctrl;
211 
212 	void __iomem *mmap;
213 };
214 
215 static inline u32 max_num_of_tx_queue(u8 queue)
216 {
217 	u32 max_num;
218 
219 	switch (queue) {
220 	case RTW_TX_QUEUE_BE:
221 		max_num = RTK_BEQ_TX_DESC_NUM;
222 		break;
223 	case RTW_TX_QUEUE_BCN:
224 		max_num = 1;
225 		break;
226 	default:
227 		max_num = RTK_DEFAULT_TX_DESC_NUM;
228 		break;
229 	}
230 
231 	return max_num;
232 }
233 
234 static inline struct
235 rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb)
236 {
237 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
238 
239 	BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) >
240 		     sizeof(info->status.status_driver_data));
241 
242 	return (struct rtw_pci_tx_data *)info->status.status_driver_data;
243 }
244 
245 static inline
246 struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring,
247 						  u32 size)
248 {
249 	u8 *buf_desc;
250 
251 	buf_desc = ring->r.head + ring->r.wp * size;
252 	return (struct rtw_pci_tx_buffer_desc *)buf_desc;
253 }
254 
255 #endif
256