1e3037485SYan-Hsuan Chuang /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2e3037485SYan-Hsuan Chuang /* Copyright(c) 2018-2019 Realtek Corporation
3e3037485SYan-Hsuan Chuang */
4e3037485SYan-Hsuan Chuang
5e3037485SYan-Hsuan Chuang #ifndef __RTK_PCI_H_
6e3037485SYan-Hsuan Chuang #define __RTK_PCI_H_
7e3037485SYan-Hsuan Chuang
82e86ef41SLee Jones #include "main.h"
92e86ef41SLee Jones
10e3037485SYan-Hsuan Chuang #define RTK_DEFAULT_TX_DESC_NUM 128
11e3037485SYan-Hsuan Chuang #define RTK_BEQ_TX_DESC_NUM 256
12e3037485SYan-Hsuan Chuang
13e3037485SYan-Hsuan Chuang #define RTK_MAX_RX_DESC_NUM 512
14ee755732STzu-En Huang /* 11K + rx desc size */
15ee755732STzu-En Huang #define RTK_PCI_RX_BUF_SIZE (11454 + 24)
16e3037485SYan-Hsuan Chuang
17e3037485SYan-Hsuan Chuang #define RTK_PCI_CTRL 0x300
18e3037485SYan-Hsuan Chuang #define BIT_RST_TRXDMA_INTF BIT(20)
19e3037485SYan-Hsuan Chuang #define BIT_RX_TAG_EN BIT(15)
20e3037485SYan-Hsuan Chuang #define REG_DBI_WDATA_V1 0x03E8
21d2e2c47eSYan-Hsuan Chuang #define REG_DBI_RDATA_V1 0x03EC
22e3037485SYan-Hsuan Chuang #define REG_DBI_FLAG_V1 0x03F0
2383a5a2d7SYan-Hsuan Chuang #define BIT_DBI_RFLAG BIT(17)
2483a5a2d7SYan-Hsuan Chuang #define BIT_DBI_WFLAG BIT(16)
2583a5a2d7SYan-Hsuan Chuang #define BITS_DBI_WREN GENMASK(15, 12)
2683a5a2d7SYan-Hsuan Chuang #define BITS_DBI_ADDR_MASK GENMASK(11, 2)
2783a5a2d7SYan-Hsuan Chuang
28e3037485SYan-Hsuan Chuang #define REG_MDIO_V1 0x03F4
29e3037485SYan-Hsuan Chuang #define REG_PCIE_MIX_CFG 0x03F8
3083a5a2d7SYan-Hsuan Chuang #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
31e3037485SYan-Hsuan Chuang #define BIT_MDIO_WFLAG_V1 BIT(5)
3283a5a2d7SYan-Hsuan Chuang #define RTW_PCI_MDIO_PG_SZ BIT(5)
3383a5a2d7SYan-Hsuan Chuang #define RTW_PCI_MDIO_PG_OFFS_G1 0
3483a5a2d7SYan-Hsuan Chuang #define RTW_PCI_MDIO_PG_OFFS_G2 2
3583a5a2d7SYan-Hsuan Chuang #define RTW_PCI_WR_RETRY_CNT 20
36e3037485SYan-Hsuan Chuang
37d2e2c47eSYan-Hsuan Chuang #define RTK_PCIE_LINK_CFG 0x0719
38d2e2c47eSYan-Hsuan Chuang #define BIT_CLKREQ_SW_EN BIT(4)
393dff7c6eSYan-Hsuan Chuang #define BIT_L1_SW_EN BIT(3)
408d52b46cSChin-Yen Lee #define BIT_CLKREQ_N_PAD BIT(0)
412a422555SYan-Hsuan Chuang #define RTK_PCIE_CLKDLY_CTRL 0x0725
42d2e2c47eSYan-Hsuan Chuang
43e3037485SYan-Hsuan Chuang #define BIT_PCI_BCNQ_FLAG BIT(4)
44e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_BCNQ 0x308
45e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_H2CQ 0x1320
46e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_MGMTQ 0x310
47e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_BKQ 0x330
48e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_BEQ 0x328
49e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_VIQ 0x320
50e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_VOQ 0x318
51e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_DESA_HI0Q 0x340
52e3037485SYan-Hsuan Chuang #define RTK_PCI_RXBD_DESA_MPDUQ 0x338
53e3037485SYan-Hsuan Chuang
54a5697a65SYan-Hsuan Chuang #define TRX_BD_IDX_MASK GENMASK(11, 0)
559e2fd298SPo-Hao Huang #define TRX_BD_HW_IDX_MASK GENMASK(27, 16)
56a5697a65SYan-Hsuan Chuang
57e3037485SYan-Hsuan Chuang /* BCNQ is specialized for rsvd page, does not need to specify a number */
58e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_NUM_H2CQ 0x1328
59e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_NUM_MGMTQ 0x380
60e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_NUM_BKQ 0x38A
61e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_NUM_BEQ 0x388
62e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_NUM_VIQ 0x386
63e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_NUM_VOQ 0x384
64e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_NUM_HI0Q 0x38C
65e3037485SYan-Hsuan Chuang #define RTK_PCI_RXBD_NUM_MPDUQ 0x382
66e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_IDX_H2CQ 0x132C
67e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_IDX_MGMTQ 0x3B0
68e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_IDX_BKQ 0x3AC
69e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_IDX_BEQ 0x3A8
70e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_IDX_VIQ 0x3A4
71e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_IDX_VOQ 0x3A0
72e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_IDX_HI0Q 0x3B8
73e3037485SYan-Hsuan Chuang #define RTK_PCI_RXBD_IDX_MPDUQ 0x3B4
74e3037485SYan-Hsuan Chuang
75e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_RWPTR_CLR 0x39C
76e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_H2CQ_CSR 0x1330
77e3037485SYan-Hsuan Chuang
78e3037485SYan-Hsuan Chuang #define BIT_CLR_H2CQ_HOST_IDX BIT(16)
79e3037485SYan-Hsuan Chuang #define BIT_CLR_H2CQ_HW_IDX BIT(8)
80e3037485SYan-Hsuan Chuang
81e3037485SYan-Hsuan Chuang #define RTK_PCI_HIMR0 0x0B0
82e3037485SYan-Hsuan Chuang #define RTK_PCI_HISR0 0x0B4
83e3037485SYan-Hsuan Chuang #define RTK_PCI_HIMR1 0x0B8
84e3037485SYan-Hsuan Chuang #define RTK_PCI_HISR1 0x0BC
85e3037485SYan-Hsuan Chuang #define RTK_PCI_HIMR2 0x10B0
86e3037485SYan-Hsuan Chuang #define RTK_PCI_HISR2 0x10B4
87e3037485SYan-Hsuan Chuang #define RTK_PCI_HIMR3 0x10B8
88e3037485SYan-Hsuan Chuang #define RTK_PCI_HISR3 0x10BC
89e3037485SYan-Hsuan Chuang /* IMR 0 */
90e3037485SYan-Hsuan Chuang #define IMR_TIMER2 BIT(31)
91e3037485SYan-Hsuan Chuang #define IMR_TIMER1 BIT(30)
92e3037485SYan-Hsuan Chuang #define IMR_PSTIMEOUT BIT(29)
93e3037485SYan-Hsuan Chuang #define IMR_GTINT4 BIT(28)
94e3037485SYan-Hsuan Chuang #define IMR_GTINT3 BIT(27)
95e3037485SYan-Hsuan Chuang #define IMR_TBDER BIT(26)
96e3037485SYan-Hsuan Chuang #define IMR_TBDOK BIT(25)
97e3037485SYan-Hsuan Chuang #define IMR_TSF_BIT32_TOGGLE BIT(24)
98e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT0 BIT(20)
99e3037485SYan-Hsuan Chuang #define IMR_BCNDOK0 BIT(16)
100e3037485SYan-Hsuan Chuang #define IMR_HSISR_IND_ON_INT BIT(15)
101e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT_E BIT(14)
102e3037485SYan-Hsuan Chuang #define IMR_ATIMEND BIT(12)
103e3037485SYan-Hsuan Chuang #define IMR_HISR1_IND_INT BIT(11)
104e3037485SYan-Hsuan Chuang #define IMR_C2HCMD BIT(10)
105e3037485SYan-Hsuan Chuang #define IMR_CPWM2 BIT(9)
106e3037485SYan-Hsuan Chuang #define IMR_CPWM BIT(8)
107e3037485SYan-Hsuan Chuang #define IMR_HIGHDOK BIT(7)
108e3037485SYan-Hsuan Chuang #define IMR_MGNTDOK BIT(6)
109e3037485SYan-Hsuan Chuang #define IMR_BKDOK BIT(5)
110e3037485SYan-Hsuan Chuang #define IMR_BEDOK BIT(4)
111e3037485SYan-Hsuan Chuang #define IMR_VIDOK BIT(3)
112e3037485SYan-Hsuan Chuang #define IMR_VODOK BIT(2)
113e3037485SYan-Hsuan Chuang #define IMR_RDU BIT(1)
114e3037485SYan-Hsuan Chuang #define IMR_ROK BIT(0)
115e3037485SYan-Hsuan Chuang /* IMR 1 */
116e3037485SYan-Hsuan Chuang #define IMR_TXFIFO_TH_INT BIT(30)
117e3037485SYan-Hsuan Chuang #define IMR_BTON_STS_UPDATE BIT(29)
118e3037485SYan-Hsuan Chuang #define IMR_MCUERR BIT(28)
119e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT7 BIT(27)
120e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT6 BIT(26)
121e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT5 BIT(25)
122e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT4 BIT(24)
123e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT3 BIT(23)
124e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT2 BIT(22)
125e3037485SYan-Hsuan Chuang #define IMR_BCNDMAINT1 BIT(21)
126e3037485SYan-Hsuan Chuang #define IMR_BCNDOK7 BIT(20)
127e3037485SYan-Hsuan Chuang #define IMR_BCNDOK6 BIT(19)
128e3037485SYan-Hsuan Chuang #define IMR_BCNDOK5 BIT(18)
129e3037485SYan-Hsuan Chuang #define IMR_BCNDOK4 BIT(17)
130e3037485SYan-Hsuan Chuang #define IMR_BCNDOK3 BIT(16)
131e3037485SYan-Hsuan Chuang #define IMR_BCNDOK2 BIT(15)
132e3037485SYan-Hsuan Chuang #define IMR_BCNDOK1 BIT(14)
133e3037485SYan-Hsuan Chuang #define IMR_ATIMEND_E BIT(13)
134e3037485SYan-Hsuan Chuang #define IMR_ATIMEND BIT(12)
135e3037485SYan-Hsuan Chuang #define IMR_TXERR BIT(11)
136e3037485SYan-Hsuan Chuang #define IMR_RXERR BIT(10)
137e3037485SYan-Hsuan Chuang #define IMR_TXFOVW BIT(9)
138e3037485SYan-Hsuan Chuang #define IMR_RXFOVW BIT(8)
139e3037485SYan-Hsuan Chuang #define IMR_CPU_MGQ_TXDONE BIT(5)
140e3037485SYan-Hsuan Chuang #define IMR_PS_TIMER_C BIT(4)
141e3037485SYan-Hsuan Chuang #define IMR_PS_TIMER_B BIT(3)
142e3037485SYan-Hsuan Chuang #define IMR_PS_TIMER_A BIT(2)
143e3037485SYan-Hsuan Chuang #define IMR_CPUMGQ_TX_TIMER BIT(1)
144e3037485SYan-Hsuan Chuang /* IMR 3 */
145e3037485SYan-Hsuan Chuang #define IMR_H2CDOK BIT(16)
146e3037485SYan-Hsuan Chuang
1479e2fd298SPo-Hao Huang enum rtw_pci_flags {
1489e2fd298SPo-Hao Huang RTW_PCI_FLAG_NAPI_RUNNING,
1499e2fd298SPo-Hao Huang
1509e2fd298SPo-Hao Huang NUM_OF_RTW_PCI_FLAGS,
1519e2fd298SPo-Hao Huang };
1529e2fd298SPo-Hao Huang
153e3037485SYan-Hsuan Chuang /* one element is reserved to know if the ring is closed */
avail_desc(u32 wp,u32 rp,u32 len)154e3037485SYan-Hsuan Chuang static inline int avail_desc(u32 wp, u32 rp, u32 len)
155e3037485SYan-Hsuan Chuang {
156e3037485SYan-Hsuan Chuang if (rp > wp)
157e3037485SYan-Hsuan Chuang return rp - wp - 1;
158e3037485SYan-Hsuan Chuang else
159e3037485SYan-Hsuan Chuang return len - wp + rp - 1;
160e3037485SYan-Hsuan Chuang }
161e3037485SYan-Hsuan Chuang
162e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_OWN_OFFSET 15
163e3037485SYan-Hsuan Chuang #define RTK_PCI_TXBD_BCN_WORK 0x383
164e3037485SYan-Hsuan Chuang
165e3037485SYan-Hsuan Chuang struct rtw_pci_tx_buffer_desc {
166e3037485SYan-Hsuan Chuang __le16 buf_size;
167e3037485SYan-Hsuan Chuang __le16 psb_len;
168e3037485SYan-Hsuan Chuang __le32 dma;
169e3037485SYan-Hsuan Chuang };
170e3037485SYan-Hsuan Chuang
171e3037485SYan-Hsuan Chuang struct rtw_pci_tx_data {
172e3037485SYan-Hsuan Chuang dma_addr_t dma;
173e3037485SYan-Hsuan Chuang u8 sn;
174e3037485SYan-Hsuan Chuang };
175e3037485SYan-Hsuan Chuang
176e3037485SYan-Hsuan Chuang struct rtw_pci_ring {
177e3037485SYan-Hsuan Chuang u8 *head;
178e3037485SYan-Hsuan Chuang dma_addr_t dma;
179e3037485SYan-Hsuan Chuang
180e3037485SYan-Hsuan Chuang u8 desc_size;
181e3037485SYan-Hsuan Chuang
182e3037485SYan-Hsuan Chuang u32 len;
183e3037485SYan-Hsuan Chuang u32 wp;
184e3037485SYan-Hsuan Chuang u32 rp;
185e3037485SYan-Hsuan Chuang };
186e3037485SYan-Hsuan Chuang
187e3037485SYan-Hsuan Chuang struct rtw_pci_tx_ring {
188e3037485SYan-Hsuan Chuang struct rtw_pci_ring r;
189e3037485SYan-Hsuan Chuang struct sk_buff_head queue;
190e3037485SYan-Hsuan Chuang bool queue_stopped;
191e3037485SYan-Hsuan Chuang };
192e3037485SYan-Hsuan Chuang
193e3037485SYan-Hsuan Chuang struct rtw_pci_rx_buffer_desc {
194e3037485SYan-Hsuan Chuang __le16 buf_size;
195e3037485SYan-Hsuan Chuang __le16 total_pkt_size;
196e3037485SYan-Hsuan Chuang __le32 dma;
197e3037485SYan-Hsuan Chuang };
198e3037485SYan-Hsuan Chuang
199e3037485SYan-Hsuan Chuang struct rtw_pci_rx_ring {
200e3037485SYan-Hsuan Chuang struct rtw_pci_ring r;
201e3037485SYan-Hsuan Chuang struct sk_buff *buf[RTK_MAX_RX_DESC_NUM];
202e3037485SYan-Hsuan Chuang };
203e3037485SYan-Hsuan Chuang
204e3037485SYan-Hsuan Chuang #define RX_TAG_MAX 8192
205e3037485SYan-Hsuan Chuang
206e3037485SYan-Hsuan Chuang struct rtw_pci {
207e3037485SYan-Hsuan Chuang struct pci_dev *pdev;
208e3037485SYan-Hsuan Chuang
20957fb39e2SBrian Norris /* Used for PCI interrupt. */
21057fb39e2SBrian Norris spinlock_t hwirq_lock;
2119e2fd298SPo-Hao Huang /* Used for PCI TX ring/queueing, and enable INT. */
212e3037485SYan-Hsuan Chuang spinlock_t irq_lock;
213e3037485SYan-Hsuan Chuang u32 irq_mask[4];
214e3037485SYan-Hsuan Chuang bool irq_enabled;
2157bd3760cSPo-Hao Huang bool running;
216e3037485SYan-Hsuan Chuang
2179e2fd298SPo-Hao Huang /* napi structure */
2189e2fd298SPo-Hao Huang struct net_device netdev;
2199e2fd298SPo-Hao Huang struct napi_struct napi;
2209e2fd298SPo-Hao Huang
221e3037485SYan-Hsuan Chuang u16 rx_tag;
222aaab5d0eSYan-Hsuan Chuang DECLARE_BITMAP(tx_queued, RTK_MAX_TX_QUEUE_NUM);
223e3037485SYan-Hsuan Chuang struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM];
224e3037485SYan-Hsuan Chuang struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM];
225d2e2c47eSYan-Hsuan Chuang u16 link_ctrl;
226*61733946SKai-Heng Feng atomic_t link_usage;
227*61733946SKai-Heng Feng bool rx_no_aspm;
2289e2fd298SPo-Hao Huang DECLARE_BITMAP(flags, NUM_OF_RTW_PCI_FLAGS);
229e3037485SYan-Hsuan Chuang
230e3037485SYan-Hsuan Chuang void __iomem *mmap;
231e3037485SYan-Hsuan Chuang };
232e3037485SYan-Hsuan Chuang
23391aeaf09SPing-Ke Shih extern const struct dev_pm_ops rtw_pm_ops;
2342e86ef41SLee Jones
2352e86ef41SLee Jones int rtw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
2362e86ef41SLee Jones void rtw_pci_remove(struct pci_dev *pdev);
2372e86ef41SLee Jones void rtw_pci_shutdown(struct pci_dev *pdev);
2382e86ef41SLee Jones
max_num_of_tx_queue(u8 queue)239bbdd1d85SZong-Zhe Yang static inline u32 max_num_of_tx_queue(u8 queue)
240e3037485SYan-Hsuan Chuang {
241e3037485SYan-Hsuan Chuang u32 max_num;
242e3037485SYan-Hsuan Chuang
243e3037485SYan-Hsuan Chuang switch (queue) {
244e3037485SYan-Hsuan Chuang case RTW_TX_QUEUE_BE:
245e3037485SYan-Hsuan Chuang max_num = RTK_BEQ_TX_DESC_NUM;
246e3037485SYan-Hsuan Chuang break;
247e3037485SYan-Hsuan Chuang case RTW_TX_QUEUE_BCN:
248e3037485SYan-Hsuan Chuang max_num = 1;
249e3037485SYan-Hsuan Chuang break;
250e3037485SYan-Hsuan Chuang default:
251e3037485SYan-Hsuan Chuang max_num = RTK_DEFAULT_TX_DESC_NUM;
252e3037485SYan-Hsuan Chuang break;
253e3037485SYan-Hsuan Chuang }
254e3037485SYan-Hsuan Chuang
255e3037485SYan-Hsuan Chuang return max_num;
256e3037485SYan-Hsuan Chuang }
257e3037485SYan-Hsuan Chuang
258e3037485SYan-Hsuan Chuang static inline struct
rtw_pci_get_tx_data(struct sk_buff * skb)259e3037485SYan-Hsuan Chuang rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb)
260e3037485SYan-Hsuan Chuang {
261e3037485SYan-Hsuan Chuang struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
262e3037485SYan-Hsuan Chuang
263e3037485SYan-Hsuan Chuang BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) >
264e3037485SYan-Hsuan Chuang sizeof(info->status.status_driver_data));
265e3037485SYan-Hsuan Chuang
266e3037485SYan-Hsuan Chuang return (struct rtw_pci_tx_data *)info->status.status_driver_data;
267e3037485SYan-Hsuan Chuang }
268e3037485SYan-Hsuan Chuang
269e3037485SYan-Hsuan Chuang static inline
get_tx_buffer_desc(struct rtw_pci_tx_ring * ring,u32 size)270e3037485SYan-Hsuan Chuang struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring,
271e3037485SYan-Hsuan Chuang u32 size)
272e3037485SYan-Hsuan Chuang {
273e3037485SYan-Hsuan Chuang u8 *buf_desc;
274e3037485SYan-Hsuan Chuang
275e3037485SYan-Hsuan Chuang buf_desc = ring->r.head + ring->r.wp * size;
276e3037485SYan-Hsuan Chuang return (struct rtw_pci_tx_buffer_desc *)buf_desc;
277e3037485SYan-Hsuan Chuang }
278e3037485SYan-Hsuan Chuang
279e3037485SYan-Hsuan Chuang #endif
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