1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include "main.h" 8 #include "pci.h" 9 #include "reg.h" 10 #include "tx.h" 11 #include "rx.h" 12 #include "fw.h" 13 #include "ps.h" 14 #include "debug.h" 15 16 static bool rtw_disable_msi; 17 static bool rtw_pci_disable_aspm; 18 module_param_named(disable_msi, rtw_disable_msi, bool, 0644); 19 module_param_named(disable_aspm, rtw_pci_disable_aspm, bool, 0644); 20 MODULE_PARM_DESC(disable_msi, "Set Y to disable MSI interrupt support"); 21 MODULE_PARM_DESC(disable_aspm, "Set Y to disable PCI ASPM support"); 22 23 static u32 rtw_pci_tx_queue_idx_addr[] = { 24 [RTW_TX_QUEUE_BK] = RTK_PCI_TXBD_IDX_BKQ, 25 [RTW_TX_QUEUE_BE] = RTK_PCI_TXBD_IDX_BEQ, 26 [RTW_TX_QUEUE_VI] = RTK_PCI_TXBD_IDX_VIQ, 27 [RTW_TX_QUEUE_VO] = RTK_PCI_TXBD_IDX_VOQ, 28 [RTW_TX_QUEUE_MGMT] = RTK_PCI_TXBD_IDX_MGMTQ, 29 [RTW_TX_QUEUE_HI0] = RTK_PCI_TXBD_IDX_HI0Q, 30 [RTW_TX_QUEUE_H2C] = RTK_PCI_TXBD_IDX_H2CQ, 31 }; 32 33 static u8 rtw_pci_get_tx_qsel(struct sk_buff *skb, u8 queue) 34 { 35 switch (queue) { 36 case RTW_TX_QUEUE_BCN: 37 return TX_DESC_QSEL_BEACON; 38 case RTW_TX_QUEUE_H2C: 39 return TX_DESC_QSEL_H2C; 40 case RTW_TX_QUEUE_MGMT: 41 return TX_DESC_QSEL_MGMT; 42 case RTW_TX_QUEUE_HI0: 43 return TX_DESC_QSEL_HIGH; 44 default: 45 return skb->priority; 46 } 47 }; 48 49 static u8 rtw_pci_read8(struct rtw_dev *rtwdev, u32 addr) 50 { 51 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 52 53 return readb(rtwpci->mmap + addr); 54 } 55 56 static u16 rtw_pci_read16(struct rtw_dev *rtwdev, u32 addr) 57 { 58 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 59 60 return readw(rtwpci->mmap + addr); 61 } 62 63 static u32 rtw_pci_read32(struct rtw_dev *rtwdev, u32 addr) 64 { 65 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 66 67 return readl(rtwpci->mmap + addr); 68 } 69 70 static void rtw_pci_write8(struct rtw_dev *rtwdev, u32 addr, u8 val) 71 { 72 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 73 74 writeb(val, rtwpci->mmap + addr); 75 } 76 77 static void rtw_pci_write16(struct rtw_dev *rtwdev, u32 addr, u16 val) 78 { 79 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 80 81 writew(val, rtwpci->mmap + addr); 82 } 83 84 static void rtw_pci_write32(struct rtw_dev *rtwdev, u32 addr, u32 val) 85 { 86 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 87 88 writel(val, rtwpci->mmap + addr); 89 } 90 91 static inline void *rtw_pci_get_tx_desc(struct rtw_pci_tx_ring *tx_ring, u8 idx) 92 { 93 int offset = tx_ring->r.desc_size * idx; 94 95 return tx_ring->r.head + offset; 96 } 97 98 static void rtw_pci_free_tx_ring_skbs(struct rtw_dev *rtwdev, 99 struct rtw_pci_tx_ring *tx_ring) 100 { 101 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 102 struct rtw_pci_tx_data *tx_data; 103 struct sk_buff *skb, *tmp; 104 dma_addr_t dma; 105 106 /* free every skb remained in tx list */ 107 skb_queue_walk_safe(&tx_ring->queue, skb, tmp) { 108 __skb_unlink(skb, &tx_ring->queue); 109 tx_data = rtw_pci_get_tx_data(skb); 110 dma = tx_data->dma; 111 112 dma_unmap_single(&pdev->dev, dma, skb->len, DMA_TO_DEVICE); 113 dev_kfree_skb_any(skb); 114 } 115 } 116 117 static void rtw_pci_free_tx_ring(struct rtw_dev *rtwdev, 118 struct rtw_pci_tx_ring *tx_ring) 119 { 120 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 121 u8 *head = tx_ring->r.head; 122 u32 len = tx_ring->r.len; 123 int ring_sz = len * tx_ring->r.desc_size; 124 125 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 126 127 /* free the ring itself */ 128 dma_free_coherent(&pdev->dev, ring_sz, head, tx_ring->r.dma); 129 tx_ring->r.head = NULL; 130 } 131 132 static void rtw_pci_free_rx_ring_skbs(struct rtw_dev *rtwdev, 133 struct rtw_pci_rx_ring *rx_ring) 134 { 135 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 136 struct sk_buff *skb; 137 int buf_sz = RTK_PCI_RX_BUF_SIZE; 138 dma_addr_t dma; 139 int i; 140 141 for (i = 0; i < rx_ring->r.len; i++) { 142 skb = rx_ring->buf[i]; 143 if (!skb) 144 continue; 145 146 dma = *((dma_addr_t *)skb->cb); 147 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 148 dev_kfree_skb(skb); 149 rx_ring->buf[i] = NULL; 150 } 151 } 152 153 static void rtw_pci_free_rx_ring(struct rtw_dev *rtwdev, 154 struct rtw_pci_rx_ring *rx_ring) 155 { 156 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 157 u8 *head = rx_ring->r.head; 158 int ring_sz = rx_ring->r.desc_size * rx_ring->r.len; 159 160 rtw_pci_free_rx_ring_skbs(rtwdev, rx_ring); 161 162 dma_free_coherent(&pdev->dev, ring_sz, head, rx_ring->r.dma); 163 } 164 165 static void rtw_pci_free_trx_ring(struct rtw_dev *rtwdev) 166 { 167 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 168 struct rtw_pci_tx_ring *tx_ring; 169 struct rtw_pci_rx_ring *rx_ring; 170 int i; 171 172 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 173 tx_ring = &rtwpci->tx_rings[i]; 174 rtw_pci_free_tx_ring(rtwdev, tx_ring); 175 } 176 177 for (i = 0; i < RTK_MAX_RX_QUEUE_NUM; i++) { 178 rx_ring = &rtwpci->rx_rings[i]; 179 rtw_pci_free_rx_ring(rtwdev, rx_ring); 180 } 181 } 182 183 static int rtw_pci_init_tx_ring(struct rtw_dev *rtwdev, 184 struct rtw_pci_tx_ring *tx_ring, 185 u8 desc_size, u32 len) 186 { 187 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 188 int ring_sz = desc_size * len; 189 dma_addr_t dma; 190 u8 *head; 191 192 if (len > TRX_BD_IDX_MASK) { 193 rtw_err(rtwdev, "len %d exceeds maximum TX entries\n", len); 194 return -EINVAL; 195 } 196 197 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 198 if (!head) { 199 rtw_err(rtwdev, "failed to allocate tx ring\n"); 200 return -ENOMEM; 201 } 202 203 skb_queue_head_init(&tx_ring->queue); 204 tx_ring->r.head = head; 205 tx_ring->r.dma = dma; 206 tx_ring->r.len = len; 207 tx_ring->r.desc_size = desc_size; 208 tx_ring->r.wp = 0; 209 tx_ring->r.rp = 0; 210 211 return 0; 212 } 213 214 static int rtw_pci_reset_rx_desc(struct rtw_dev *rtwdev, struct sk_buff *skb, 215 struct rtw_pci_rx_ring *rx_ring, 216 u32 idx, u32 desc_sz) 217 { 218 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 219 struct rtw_pci_rx_buffer_desc *buf_desc; 220 int buf_sz = RTK_PCI_RX_BUF_SIZE; 221 dma_addr_t dma; 222 223 if (!skb) 224 return -EINVAL; 225 226 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); 227 if (dma_mapping_error(&pdev->dev, dma)) 228 return -EBUSY; 229 230 *((dma_addr_t *)skb->cb) = dma; 231 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 232 idx * desc_sz); 233 memset(buf_desc, 0, sizeof(*buf_desc)); 234 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 235 buf_desc->dma = cpu_to_le32(dma); 236 237 return 0; 238 } 239 240 static void rtw_pci_sync_rx_desc_device(struct rtw_dev *rtwdev, dma_addr_t dma, 241 struct rtw_pci_rx_ring *rx_ring, 242 u32 idx, u32 desc_sz) 243 { 244 struct device *dev = rtwdev->dev; 245 struct rtw_pci_rx_buffer_desc *buf_desc; 246 int buf_sz = RTK_PCI_RX_BUF_SIZE; 247 248 dma_sync_single_for_device(dev, dma, buf_sz, DMA_FROM_DEVICE); 249 250 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 251 idx * desc_sz); 252 memset(buf_desc, 0, sizeof(*buf_desc)); 253 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 254 buf_desc->dma = cpu_to_le32(dma); 255 } 256 257 static int rtw_pci_init_rx_ring(struct rtw_dev *rtwdev, 258 struct rtw_pci_rx_ring *rx_ring, 259 u8 desc_size, u32 len) 260 { 261 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 262 struct sk_buff *skb = NULL; 263 dma_addr_t dma; 264 u8 *head; 265 int ring_sz = desc_size * len; 266 int buf_sz = RTK_PCI_RX_BUF_SIZE; 267 int i, allocated; 268 int ret = 0; 269 270 if (len > TRX_BD_IDX_MASK) { 271 rtw_err(rtwdev, "len %d exceeds maximum RX entries\n", len); 272 return -EINVAL; 273 } 274 275 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 276 if (!head) { 277 rtw_err(rtwdev, "failed to allocate rx ring\n"); 278 return -ENOMEM; 279 } 280 rx_ring->r.head = head; 281 282 for (i = 0; i < len; i++) { 283 skb = dev_alloc_skb(buf_sz); 284 if (!skb) { 285 allocated = i; 286 ret = -ENOMEM; 287 goto err_out; 288 } 289 290 memset(skb->data, 0, buf_sz); 291 rx_ring->buf[i] = skb; 292 ret = rtw_pci_reset_rx_desc(rtwdev, skb, rx_ring, i, desc_size); 293 if (ret) { 294 allocated = i; 295 dev_kfree_skb_any(skb); 296 goto err_out; 297 } 298 } 299 300 rx_ring->r.dma = dma; 301 rx_ring->r.len = len; 302 rx_ring->r.desc_size = desc_size; 303 rx_ring->r.wp = 0; 304 rx_ring->r.rp = 0; 305 306 return 0; 307 308 err_out: 309 for (i = 0; i < allocated; i++) { 310 skb = rx_ring->buf[i]; 311 if (!skb) 312 continue; 313 dma = *((dma_addr_t *)skb->cb); 314 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 315 dev_kfree_skb_any(skb); 316 rx_ring->buf[i] = NULL; 317 } 318 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 319 320 rtw_err(rtwdev, "failed to init rx buffer\n"); 321 322 return ret; 323 } 324 325 static int rtw_pci_init_trx_ring(struct rtw_dev *rtwdev) 326 { 327 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 328 struct rtw_pci_tx_ring *tx_ring; 329 struct rtw_pci_rx_ring *rx_ring; 330 struct rtw_chip_info *chip = rtwdev->chip; 331 int i = 0, j = 0, tx_alloced = 0, rx_alloced = 0; 332 int tx_desc_size, rx_desc_size; 333 u32 len; 334 int ret; 335 336 tx_desc_size = chip->tx_buf_desc_sz; 337 338 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 339 tx_ring = &rtwpci->tx_rings[i]; 340 len = max_num_of_tx_queue(i); 341 ret = rtw_pci_init_tx_ring(rtwdev, tx_ring, tx_desc_size, len); 342 if (ret) 343 goto out; 344 } 345 346 rx_desc_size = chip->rx_buf_desc_sz; 347 348 for (j = 0; j < RTK_MAX_RX_QUEUE_NUM; j++) { 349 rx_ring = &rtwpci->rx_rings[j]; 350 ret = rtw_pci_init_rx_ring(rtwdev, rx_ring, rx_desc_size, 351 RTK_MAX_RX_DESC_NUM); 352 if (ret) 353 goto out; 354 } 355 356 return 0; 357 358 out: 359 tx_alloced = i; 360 for (i = 0; i < tx_alloced; i++) { 361 tx_ring = &rtwpci->tx_rings[i]; 362 rtw_pci_free_tx_ring(rtwdev, tx_ring); 363 } 364 365 rx_alloced = j; 366 for (j = 0; j < rx_alloced; j++) { 367 rx_ring = &rtwpci->rx_rings[j]; 368 rtw_pci_free_rx_ring(rtwdev, rx_ring); 369 } 370 371 return ret; 372 } 373 374 static void rtw_pci_deinit(struct rtw_dev *rtwdev) 375 { 376 rtw_pci_free_trx_ring(rtwdev); 377 } 378 379 static int rtw_pci_init(struct rtw_dev *rtwdev) 380 { 381 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 382 int ret = 0; 383 384 rtwpci->irq_mask[0] = IMR_HIGHDOK | 385 IMR_MGNTDOK | 386 IMR_BKDOK | 387 IMR_BEDOK | 388 IMR_VIDOK | 389 IMR_VODOK | 390 IMR_ROK | 391 IMR_BCNDMAINT_E | 392 IMR_C2HCMD | 393 0; 394 rtwpci->irq_mask[1] = IMR_TXFOVW | 395 0; 396 rtwpci->irq_mask[3] = IMR_H2CDOK | 397 0; 398 spin_lock_init(&rtwpci->irq_lock); 399 spin_lock_init(&rtwpci->hwirq_lock); 400 ret = rtw_pci_init_trx_ring(rtwdev); 401 402 return ret; 403 } 404 405 static void rtw_pci_reset_buf_desc(struct rtw_dev *rtwdev) 406 { 407 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 408 u32 len; 409 u8 tmp; 410 dma_addr_t dma; 411 412 tmp = rtw_read8(rtwdev, RTK_PCI_CTRL + 3); 413 rtw_write8(rtwdev, RTK_PCI_CTRL + 3, tmp | 0xf7); 414 415 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BCN].r.dma; 416 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BCNQ, dma); 417 418 if (!rtw_chip_wcpu_11n(rtwdev)) { 419 len = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.len; 420 dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma; 421 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0; 422 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; 423 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK); 424 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma); 425 } 426 427 len = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.len; 428 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.dma; 429 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.rp = 0; 430 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; 431 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BKQ, len & TRX_BD_IDX_MASK); 432 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BKQ, dma); 433 434 len = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.len; 435 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.dma; 436 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.rp = 0; 437 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; 438 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BEQ, len & TRX_BD_IDX_MASK); 439 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BEQ, dma); 440 441 len = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.len; 442 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.dma; 443 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.rp = 0; 444 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; 445 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VOQ, len & TRX_BD_IDX_MASK); 446 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VOQ, dma); 447 448 len = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.len; 449 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.dma; 450 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.rp = 0; 451 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; 452 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VIQ, len & TRX_BD_IDX_MASK); 453 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VIQ, dma); 454 455 len = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.len; 456 dma = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.dma; 457 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.rp = 0; 458 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; 459 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_MGMTQ, len & TRX_BD_IDX_MASK); 460 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_MGMTQ, dma); 461 462 len = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.len; 463 dma = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.dma; 464 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.rp = 0; 465 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; 466 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_HI0Q, len & TRX_BD_IDX_MASK); 467 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_HI0Q, dma); 468 469 len = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.len; 470 dma = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.dma; 471 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.rp = 0; 472 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0; 473 rtw_write16(rtwdev, RTK_PCI_RXBD_NUM_MPDUQ, len & TRX_BD_IDX_MASK); 474 rtw_write32(rtwdev, RTK_PCI_RXBD_DESA_MPDUQ, dma); 475 476 /* reset read/write point */ 477 rtw_write32(rtwdev, RTK_PCI_TXBD_RWPTR_CLR, 0xffffffff); 478 479 /* reset H2C Queue index in a single write */ 480 if (rtw_chip_wcpu_11ac(rtwdev)) 481 rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR, 482 BIT_CLR_H2CQ_HOST_IDX | BIT_CLR_H2CQ_HW_IDX); 483 } 484 485 static void rtw_pci_reset_trx_ring(struct rtw_dev *rtwdev) 486 { 487 rtw_pci_reset_buf_desc(rtwdev); 488 } 489 490 static void rtw_pci_enable_interrupt(struct rtw_dev *rtwdev, 491 struct rtw_pci *rtwpci, bool exclude_rx) 492 { 493 unsigned long flags; 494 u32 imr0_unmask = exclude_rx ? IMR_ROK : 0; 495 496 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 497 498 rtw_write32(rtwdev, RTK_PCI_HIMR0, rtwpci->irq_mask[0] & ~imr0_unmask); 499 rtw_write32(rtwdev, RTK_PCI_HIMR1, rtwpci->irq_mask[1]); 500 if (rtw_chip_wcpu_11ac(rtwdev)) 501 rtw_write32(rtwdev, RTK_PCI_HIMR3, rtwpci->irq_mask[3]); 502 503 rtwpci->irq_enabled = true; 504 505 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 506 } 507 508 static void rtw_pci_disable_interrupt(struct rtw_dev *rtwdev, 509 struct rtw_pci *rtwpci) 510 { 511 unsigned long flags; 512 513 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 514 515 if (!rtwpci->irq_enabled) 516 goto out; 517 518 rtw_write32(rtwdev, RTK_PCI_HIMR0, 0); 519 rtw_write32(rtwdev, RTK_PCI_HIMR1, 0); 520 if (rtw_chip_wcpu_11ac(rtwdev)) 521 rtw_write32(rtwdev, RTK_PCI_HIMR3, 0); 522 523 rtwpci->irq_enabled = false; 524 525 out: 526 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 527 } 528 529 static void rtw_pci_dma_reset(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 530 { 531 /* reset dma and rx tag */ 532 rtw_write32_set(rtwdev, RTK_PCI_CTRL, 533 BIT_RST_TRXDMA_INTF | BIT_RX_TAG_EN); 534 rtwpci->rx_tag = 0; 535 } 536 537 static int rtw_pci_setup(struct rtw_dev *rtwdev) 538 { 539 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 540 541 rtw_pci_reset_trx_ring(rtwdev); 542 rtw_pci_dma_reset(rtwdev, rtwpci); 543 544 return 0; 545 } 546 547 static void rtw_pci_dma_release(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 548 { 549 struct rtw_pci_tx_ring *tx_ring; 550 u8 queue; 551 552 rtw_pci_reset_trx_ring(rtwdev); 553 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 554 tx_ring = &rtwpci->tx_rings[queue]; 555 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 556 } 557 } 558 559 static void rtw_pci_napi_start(struct rtw_dev *rtwdev) 560 { 561 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 562 563 if (test_and_set_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 564 return; 565 566 napi_enable(&rtwpci->napi); 567 } 568 569 static void rtw_pci_napi_stop(struct rtw_dev *rtwdev) 570 { 571 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 572 573 if (!test_and_clear_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 574 return; 575 576 napi_synchronize(&rtwpci->napi); 577 napi_disable(&rtwpci->napi); 578 } 579 580 static int rtw_pci_start(struct rtw_dev *rtwdev) 581 { 582 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 583 584 spin_lock_bh(&rtwpci->irq_lock); 585 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 586 spin_unlock_bh(&rtwpci->irq_lock); 587 588 rtw_pci_napi_start(rtwdev); 589 590 return 0; 591 } 592 593 static void rtw_pci_stop(struct rtw_dev *rtwdev) 594 { 595 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 596 597 rtw_pci_napi_stop(rtwdev); 598 599 spin_lock_bh(&rtwpci->irq_lock); 600 rtw_pci_disable_interrupt(rtwdev, rtwpci); 601 rtw_pci_dma_release(rtwdev, rtwpci); 602 spin_unlock_bh(&rtwpci->irq_lock); 603 } 604 605 static void rtw_pci_deep_ps_enter(struct rtw_dev *rtwdev) 606 { 607 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 608 struct rtw_pci_tx_ring *tx_ring; 609 bool tx_empty = true; 610 u8 queue; 611 612 lockdep_assert_held(&rtwpci->irq_lock); 613 614 /* Deep PS state is not allowed to TX-DMA */ 615 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 616 /* BCN queue is rsvd page, does not have DMA interrupt 617 * H2C queue is managed by firmware 618 */ 619 if (queue == RTW_TX_QUEUE_BCN || 620 queue == RTW_TX_QUEUE_H2C) 621 continue; 622 623 tx_ring = &rtwpci->tx_rings[queue]; 624 625 /* check if there is any skb DMAing */ 626 if (skb_queue_len(&tx_ring->queue)) { 627 tx_empty = false; 628 break; 629 } 630 } 631 632 if (!tx_empty) { 633 rtw_dbg(rtwdev, RTW_DBG_PS, 634 "TX path not empty, cannot enter deep power save state\n"); 635 return; 636 } 637 638 set_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags); 639 rtw_power_mode_change(rtwdev, true); 640 } 641 642 static void rtw_pci_deep_ps_leave(struct rtw_dev *rtwdev) 643 { 644 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 645 646 lockdep_assert_held(&rtwpci->irq_lock); 647 648 if (test_and_clear_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 649 rtw_power_mode_change(rtwdev, false); 650 } 651 652 static void rtw_pci_deep_ps(struct rtw_dev *rtwdev, bool enter) 653 { 654 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 655 656 spin_lock_bh(&rtwpci->irq_lock); 657 658 if (enter && !test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 659 rtw_pci_deep_ps_enter(rtwdev); 660 661 if (!enter && test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 662 rtw_pci_deep_ps_leave(rtwdev); 663 664 spin_unlock_bh(&rtwpci->irq_lock); 665 } 666 667 static u8 ac_to_hwq[] = { 668 [IEEE80211_AC_VO] = RTW_TX_QUEUE_VO, 669 [IEEE80211_AC_VI] = RTW_TX_QUEUE_VI, 670 [IEEE80211_AC_BE] = RTW_TX_QUEUE_BE, 671 [IEEE80211_AC_BK] = RTW_TX_QUEUE_BK, 672 }; 673 674 static u8 rtw_hw_queue_mapping(struct sk_buff *skb) 675 { 676 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 677 __le16 fc = hdr->frame_control; 678 u8 q_mapping = skb_get_queue_mapping(skb); 679 u8 queue; 680 681 if (unlikely(ieee80211_is_beacon(fc))) 682 queue = RTW_TX_QUEUE_BCN; 683 else if (unlikely(ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))) 684 queue = RTW_TX_QUEUE_MGMT; 685 else if (WARN_ON_ONCE(q_mapping >= ARRAY_SIZE(ac_to_hwq))) 686 queue = ac_to_hwq[IEEE80211_AC_BE]; 687 else 688 queue = ac_to_hwq[q_mapping]; 689 690 return queue; 691 } 692 693 static void rtw_pci_release_rsvd_page(struct rtw_pci *rtwpci, 694 struct rtw_pci_tx_ring *ring) 695 { 696 struct sk_buff *prev = skb_dequeue(&ring->queue); 697 struct rtw_pci_tx_data *tx_data; 698 dma_addr_t dma; 699 700 if (!prev) 701 return; 702 703 tx_data = rtw_pci_get_tx_data(prev); 704 dma = tx_data->dma; 705 dma_unmap_single(&rtwpci->pdev->dev, dma, prev->len, DMA_TO_DEVICE); 706 dev_kfree_skb_any(prev); 707 } 708 709 static void rtw_pci_dma_check(struct rtw_dev *rtwdev, 710 struct rtw_pci_rx_ring *rx_ring, 711 u32 idx) 712 { 713 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 714 struct rtw_chip_info *chip = rtwdev->chip; 715 struct rtw_pci_rx_buffer_desc *buf_desc; 716 u32 desc_sz = chip->rx_buf_desc_sz; 717 u16 total_pkt_size; 718 719 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 720 idx * desc_sz); 721 total_pkt_size = le16_to_cpu(buf_desc->total_pkt_size); 722 723 /* rx tag mismatch, throw a warning */ 724 if (total_pkt_size != rtwpci->rx_tag) 725 rtw_warn(rtwdev, "pci bus timeout, check dma status\n"); 726 727 rtwpci->rx_tag = (rtwpci->rx_tag + 1) % RX_TAG_MAX; 728 } 729 730 static void rtw_pci_tx_kick_off_queue(struct rtw_dev *rtwdev, u8 queue) 731 { 732 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 733 struct rtw_pci_tx_ring *ring; 734 u32 bd_idx; 735 736 ring = &rtwpci->tx_rings[queue]; 737 bd_idx = rtw_pci_tx_queue_idx_addr[queue]; 738 739 spin_lock_bh(&rtwpci->irq_lock); 740 rtw_pci_deep_ps_leave(rtwdev); 741 rtw_write16(rtwdev, bd_idx, ring->r.wp & TRX_BD_IDX_MASK); 742 spin_unlock_bh(&rtwpci->irq_lock); 743 } 744 745 static void rtw_pci_tx_kick_off(struct rtw_dev *rtwdev) 746 { 747 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 748 u8 queue; 749 750 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) 751 if (test_and_clear_bit(queue, rtwpci->tx_queued)) 752 rtw_pci_tx_kick_off_queue(rtwdev, queue); 753 } 754 755 static int rtw_pci_tx_write_data(struct rtw_dev *rtwdev, 756 struct rtw_tx_pkt_info *pkt_info, 757 struct sk_buff *skb, u8 queue) 758 { 759 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 760 struct rtw_chip_info *chip = rtwdev->chip; 761 struct rtw_pci_tx_ring *ring; 762 struct rtw_pci_tx_data *tx_data; 763 dma_addr_t dma; 764 u32 tx_pkt_desc_sz = chip->tx_pkt_desc_sz; 765 u32 tx_buf_desc_sz = chip->tx_buf_desc_sz; 766 u32 size; 767 u32 psb_len; 768 u8 *pkt_desc; 769 struct rtw_pci_tx_buffer_desc *buf_desc; 770 771 ring = &rtwpci->tx_rings[queue]; 772 773 size = skb->len; 774 775 if (queue == RTW_TX_QUEUE_BCN) 776 rtw_pci_release_rsvd_page(rtwpci, ring); 777 else if (!avail_desc(ring->r.wp, ring->r.rp, ring->r.len)) 778 return -ENOSPC; 779 780 pkt_desc = skb_push(skb, chip->tx_pkt_desc_sz); 781 memset(pkt_desc, 0, tx_pkt_desc_sz); 782 pkt_info->qsel = rtw_pci_get_tx_qsel(skb, queue); 783 rtw_tx_fill_tx_desc(pkt_info, skb); 784 dma = dma_map_single(&rtwpci->pdev->dev, skb->data, skb->len, 785 DMA_TO_DEVICE); 786 if (dma_mapping_error(&rtwpci->pdev->dev, dma)) 787 return -EBUSY; 788 789 /* after this we got dma mapped, there is no way back */ 790 buf_desc = get_tx_buffer_desc(ring, tx_buf_desc_sz); 791 memset(buf_desc, 0, tx_buf_desc_sz); 792 psb_len = (skb->len - 1) / 128 + 1; 793 if (queue == RTW_TX_QUEUE_BCN) 794 psb_len |= 1 << RTK_PCI_TXBD_OWN_OFFSET; 795 796 buf_desc[0].psb_len = cpu_to_le16(psb_len); 797 buf_desc[0].buf_size = cpu_to_le16(tx_pkt_desc_sz); 798 buf_desc[0].dma = cpu_to_le32(dma); 799 buf_desc[1].buf_size = cpu_to_le16(size); 800 buf_desc[1].dma = cpu_to_le32(dma + tx_pkt_desc_sz); 801 802 tx_data = rtw_pci_get_tx_data(skb); 803 tx_data->dma = dma; 804 tx_data->sn = pkt_info->sn; 805 806 spin_lock_bh(&rtwpci->irq_lock); 807 808 skb_queue_tail(&ring->queue, skb); 809 810 if (queue == RTW_TX_QUEUE_BCN) 811 goto out_unlock; 812 813 /* update write-index, and kick it off later */ 814 set_bit(queue, rtwpci->tx_queued); 815 if (++ring->r.wp >= ring->r.len) 816 ring->r.wp = 0; 817 818 out_unlock: 819 spin_unlock_bh(&rtwpci->irq_lock); 820 821 return 0; 822 } 823 824 static int rtw_pci_write_data_rsvd_page(struct rtw_dev *rtwdev, u8 *buf, 825 u32 size) 826 { 827 struct sk_buff *skb; 828 struct rtw_tx_pkt_info pkt_info = {0}; 829 u8 reg_bcn_work; 830 int ret; 831 832 skb = rtw_tx_write_data_rsvd_page_get(rtwdev, &pkt_info, buf, size); 833 if (!skb) 834 return -ENOMEM; 835 836 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_BCN); 837 if (ret) { 838 rtw_err(rtwdev, "failed to write rsvd page data\n"); 839 return ret; 840 } 841 842 /* reserved pages go through beacon queue */ 843 reg_bcn_work = rtw_read8(rtwdev, RTK_PCI_TXBD_BCN_WORK); 844 reg_bcn_work |= BIT_PCI_BCNQ_FLAG; 845 rtw_write8(rtwdev, RTK_PCI_TXBD_BCN_WORK, reg_bcn_work); 846 847 return 0; 848 } 849 850 static int rtw_pci_write_data_h2c(struct rtw_dev *rtwdev, u8 *buf, u32 size) 851 { 852 struct sk_buff *skb; 853 struct rtw_tx_pkt_info pkt_info = {0}; 854 int ret; 855 856 skb = rtw_tx_write_data_h2c_get(rtwdev, &pkt_info, buf, size); 857 if (!skb) 858 return -ENOMEM; 859 860 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_H2C); 861 if (ret) { 862 rtw_err(rtwdev, "failed to write h2c data\n"); 863 return ret; 864 } 865 866 rtw_pci_tx_kick_off_queue(rtwdev, RTW_TX_QUEUE_H2C); 867 868 return 0; 869 } 870 871 static int rtw_pci_tx_write(struct rtw_dev *rtwdev, 872 struct rtw_tx_pkt_info *pkt_info, 873 struct sk_buff *skb) 874 { 875 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 876 struct rtw_pci_tx_ring *ring; 877 u8 queue = rtw_hw_queue_mapping(skb); 878 int ret; 879 880 ret = rtw_pci_tx_write_data(rtwdev, pkt_info, skb, queue); 881 if (ret) 882 return ret; 883 884 ring = &rtwpci->tx_rings[queue]; 885 if (avail_desc(ring->r.wp, ring->r.rp, ring->r.len) < 2) { 886 ieee80211_stop_queue(rtwdev->hw, skb_get_queue_mapping(skb)); 887 ring->queue_stopped = true; 888 } 889 890 return 0; 891 } 892 893 static void rtw_pci_tx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 894 u8 hw_queue) 895 { 896 struct ieee80211_hw *hw = rtwdev->hw; 897 struct ieee80211_tx_info *info; 898 struct rtw_pci_tx_ring *ring; 899 struct rtw_pci_tx_data *tx_data; 900 struct sk_buff *skb; 901 u32 count; 902 u32 bd_idx_addr; 903 u32 bd_idx, cur_rp; 904 u16 q_map; 905 906 ring = &rtwpci->tx_rings[hw_queue]; 907 908 bd_idx_addr = rtw_pci_tx_queue_idx_addr[hw_queue]; 909 bd_idx = rtw_read32(rtwdev, bd_idx_addr); 910 cur_rp = bd_idx >> 16; 911 cur_rp &= TRX_BD_IDX_MASK; 912 if (cur_rp >= ring->r.rp) 913 count = cur_rp - ring->r.rp; 914 else 915 count = ring->r.len - (ring->r.rp - cur_rp); 916 917 while (count--) { 918 skb = skb_dequeue(&ring->queue); 919 if (!skb) { 920 rtw_err(rtwdev, "failed to dequeue %d skb TX queue %d, BD=0x%08x, rp %d -> %d\n", 921 count, hw_queue, bd_idx, ring->r.rp, cur_rp); 922 break; 923 } 924 tx_data = rtw_pci_get_tx_data(skb); 925 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 926 DMA_TO_DEVICE); 927 928 /* just free command packets from host to card */ 929 if (hw_queue == RTW_TX_QUEUE_H2C) { 930 dev_kfree_skb_irq(skb); 931 continue; 932 } 933 934 if (ring->queue_stopped && 935 avail_desc(ring->r.wp, ring->r.rp, ring->r.len) > 4) { 936 q_map = skb_get_queue_mapping(skb); 937 ieee80211_wake_queue(hw, q_map); 938 ring->queue_stopped = false; 939 } 940 941 skb_pull(skb, rtwdev->chip->tx_pkt_desc_sz); 942 943 info = IEEE80211_SKB_CB(skb); 944 945 /* enqueue to wait for tx report */ 946 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 947 rtw_tx_report_enqueue(rtwdev, skb, tx_data->sn); 948 continue; 949 } 950 951 /* always ACK for others, then they won't be marked as drop */ 952 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 953 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 954 else 955 info->flags |= IEEE80211_TX_STAT_ACK; 956 957 ieee80211_tx_info_clear_status(info); 958 ieee80211_tx_status_irqsafe(hw, skb); 959 } 960 961 ring->r.rp = cur_rp; 962 } 963 964 static void rtw_pci_rx_isr(struct rtw_dev *rtwdev) 965 { 966 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 967 struct napi_struct *napi = &rtwpci->napi; 968 969 napi_schedule(napi); 970 } 971 972 static int rtw_pci_get_hw_rx_ring_nr(struct rtw_dev *rtwdev, 973 struct rtw_pci *rtwpci) 974 { 975 struct rtw_pci_rx_ring *ring; 976 int count = 0; 977 u32 tmp, cur_wp; 978 979 ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 980 tmp = rtw_read32(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ); 981 cur_wp = u32_get_bits(tmp, TRX_BD_HW_IDX_MASK); 982 if (cur_wp >= ring->r.wp) 983 count = cur_wp - ring->r.wp; 984 else 985 count = ring->r.len - (ring->r.wp - cur_wp); 986 987 return count; 988 } 989 990 static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 991 u8 hw_queue, u32 limit) 992 { 993 struct rtw_chip_info *chip = rtwdev->chip; 994 struct napi_struct *napi = &rtwpci->napi; 995 struct rtw_pci_rx_ring *ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 996 struct rtw_rx_pkt_stat pkt_stat; 997 struct ieee80211_rx_status rx_status; 998 struct sk_buff *skb, *new; 999 u32 cur_rp = ring->r.rp; 1000 u32 count, rx_done = 0; 1001 u32 pkt_offset; 1002 u32 pkt_desc_sz = chip->rx_pkt_desc_sz; 1003 u32 buf_desc_sz = chip->rx_buf_desc_sz; 1004 u32 new_len; 1005 u8 *rx_desc; 1006 dma_addr_t dma; 1007 1008 count = rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci); 1009 count = min(count, limit); 1010 1011 while (count--) { 1012 rtw_pci_dma_check(rtwdev, ring, cur_rp); 1013 skb = ring->buf[cur_rp]; 1014 dma = *((dma_addr_t *)skb->cb); 1015 dma_sync_single_for_cpu(rtwdev->dev, dma, RTK_PCI_RX_BUF_SIZE, 1016 DMA_FROM_DEVICE); 1017 rx_desc = skb->data; 1018 chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status); 1019 1020 /* offset from rx_desc to payload */ 1021 pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz + 1022 pkt_stat.shift; 1023 1024 /* allocate a new skb for this frame, 1025 * discard the frame if none available 1026 */ 1027 new_len = pkt_stat.pkt_len + pkt_offset; 1028 new = dev_alloc_skb(new_len); 1029 if (WARN_ONCE(!new, "rx routine starvation\n")) 1030 goto next_rp; 1031 1032 /* put the DMA data including rx_desc from phy to new skb */ 1033 skb_put_data(new, skb->data, new_len); 1034 1035 if (pkt_stat.is_c2h) { 1036 rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, new); 1037 } else { 1038 /* remove rx_desc */ 1039 skb_pull(new, pkt_offset); 1040 1041 rtw_rx_stats(rtwdev, pkt_stat.vif, new); 1042 memcpy(new->cb, &rx_status, sizeof(rx_status)); 1043 ieee80211_rx_napi(rtwdev->hw, NULL, new, napi); 1044 rx_done++; 1045 } 1046 1047 next_rp: 1048 /* new skb delivered to mac80211, re-enable original skb DMA */ 1049 rtw_pci_sync_rx_desc_device(rtwdev, dma, ring, cur_rp, 1050 buf_desc_sz); 1051 1052 /* host read next element in ring */ 1053 if (++cur_rp >= ring->r.len) 1054 cur_rp = 0; 1055 } 1056 1057 ring->r.rp = cur_rp; 1058 /* 'rp', the last position we have read, is seen as previous posistion 1059 * of 'wp' that is used to calculate 'count' next time. 1060 */ 1061 ring->r.wp = cur_rp; 1062 rtw_write16(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ, ring->r.rp); 1063 1064 return rx_done; 1065 } 1066 1067 static void rtw_pci_irq_recognized(struct rtw_dev *rtwdev, 1068 struct rtw_pci *rtwpci, u32 *irq_status) 1069 { 1070 unsigned long flags; 1071 1072 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 1073 1074 irq_status[0] = rtw_read32(rtwdev, RTK_PCI_HISR0); 1075 irq_status[1] = rtw_read32(rtwdev, RTK_PCI_HISR1); 1076 if (rtw_chip_wcpu_11ac(rtwdev)) 1077 irq_status[3] = rtw_read32(rtwdev, RTK_PCI_HISR3); 1078 else 1079 irq_status[3] = 0; 1080 irq_status[0] &= rtwpci->irq_mask[0]; 1081 irq_status[1] &= rtwpci->irq_mask[1]; 1082 irq_status[3] &= rtwpci->irq_mask[3]; 1083 rtw_write32(rtwdev, RTK_PCI_HISR0, irq_status[0]); 1084 rtw_write32(rtwdev, RTK_PCI_HISR1, irq_status[1]); 1085 if (rtw_chip_wcpu_11ac(rtwdev)) 1086 rtw_write32(rtwdev, RTK_PCI_HISR3, irq_status[3]); 1087 1088 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 1089 } 1090 1091 static irqreturn_t rtw_pci_interrupt_handler(int irq, void *dev) 1092 { 1093 struct rtw_dev *rtwdev = dev; 1094 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1095 1096 /* disable RTW PCI interrupt to avoid more interrupts before the end of 1097 * thread function 1098 * 1099 * disable HIMR here to also avoid new HISR flag being raised before 1100 * the HISRs have been Write-1-cleared for MSI. If not all of the HISRs 1101 * are cleared, the edge-triggered interrupt will not be generated when 1102 * a new HISR flag is set. 1103 */ 1104 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1105 1106 return IRQ_WAKE_THREAD; 1107 } 1108 1109 static irqreturn_t rtw_pci_interrupt_threadfn(int irq, void *dev) 1110 { 1111 struct rtw_dev *rtwdev = dev; 1112 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1113 u32 irq_status[4]; 1114 bool rx = false; 1115 1116 spin_lock_bh(&rtwpci->irq_lock); 1117 rtw_pci_irq_recognized(rtwdev, rtwpci, irq_status); 1118 1119 if (irq_status[0] & IMR_MGNTDOK) 1120 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_MGMT); 1121 if (irq_status[0] & IMR_HIGHDOK) 1122 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_HI0); 1123 if (irq_status[0] & IMR_BEDOK) 1124 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BE); 1125 if (irq_status[0] & IMR_BKDOK) 1126 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BK); 1127 if (irq_status[0] & IMR_VODOK) 1128 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VO); 1129 if (irq_status[0] & IMR_VIDOK) 1130 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VI); 1131 if (irq_status[3] & IMR_H2CDOK) 1132 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_H2C); 1133 if (irq_status[0] & IMR_ROK) { 1134 rtw_pci_rx_isr(rtwdev); 1135 rx = true; 1136 } 1137 if (unlikely(irq_status[0] & IMR_C2HCMD)) 1138 rtw_fw_c2h_cmd_isr(rtwdev); 1139 1140 /* all of the jobs for this interrupt have been done */ 1141 rtw_pci_enable_interrupt(rtwdev, rtwpci, rx); 1142 spin_unlock_bh(&rtwpci->irq_lock); 1143 1144 return IRQ_HANDLED; 1145 } 1146 1147 static int rtw_pci_io_mapping(struct rtw_dev *rtwdev, 1148 struct pci_dev *pdev) 1149 { 1150 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1151 unsigned long len; 1152 u8 bar_id = 2; 1153 int ret; 1154 1155 ret = pci_request_regions(pdev, KBUILD_MODNAME); 1156 if (ret) { 1157 rtw_err(rtwdev, "failed to request pci regions\n"); 1158 return ret; 1159 } 1160 1161 len = pci_resource_len(pdev, bar_id); 1162 rtwpci->mmap = pci_iomap(pdev, bar_id, len); 1163 if (!rtwpci->mmap) { 1164 pci_release_regions(pdev); 1165 rtw_err(rtwdev, "failed to map pci memory\n"); 1166 return -ENOMEM; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev, 1173 struct pci_dev *pdev) 1174 { 1175 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1176 1177 if (rtwpci->mmap) { 1178 pci_iounmap(pdev, rtwpci->mmap); 1179 pci_release_regions(pdev); 1180 } 1181 } 1182 1183 static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data) 1184 { 1185 u16 write_addr; 1186 u16 remainder = addr & ~(BITS_DBI_WREN | BITS_DBI_ADDR_MASK); 1187 u8 flag; 1188 u8 cnt; 1189 1190 write_addr = addr & BITS_DBI_ADDR_MASK; 1191 write_addr |= u16_encode_bits(BIT(remainder), BITS_DBI_WREN); 1192 rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data); 1193 rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr); 1194 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_WFLAG >> 16); 1195 1196 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1197 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1198 if (flag == 0) 1199 return; 1200 1201 udelay(10); 1202 } 1203 1204 WARN(flag, "failed to write to DBI register, addr=0x%04x\n", addr); 1205 } 1206 1207 static int rtw_dbi_read8(struct rtw_dev *rtwdev, u16 addr, u8 *value) 1208 { 1209 u16 read_addr = addr & BITS_DBI_ADDR_MASK; 1210 u8 flag; 1211 u8 cnt; 1212 1213 rtw_write16(rtwdev, REG_DBI_FLAG_V1, read_addr); 1214 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_RFLAG >> 16); 1215 1216 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1217 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1218 if (flag == 0) { 1219 read_addr = REG_DBI_RDATA_V1 + (addr & 3); 1220 *value = rtw_read8(rtwdev, read_addr); 1221 return 0; 1222 } 1223 1224 udelay(10); 1225 } 1226 1227 WARN(1, "failed to read DBI register, addr=0x%04x\n", addr); 1228 return -EIO; 1229 } 1230 1231 static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1) 1232 { 1233 u8 page; 1234 u8 wflag; 1235 u8 cnt; 1236 1237 rtw_write16(rtwdev, REG_MDIO_V1, data); 1238 1239 page = addr < RTW_PCI_MDIO_PG_SZ ? 0 : 1; 1240 page += g1 ? RTW_PCI_MDIO_PG_OFFS_G1 : RTW_PCI_MDIO_PG_OFFS_G2; 1241 rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & BITS_MDIO_ADDR_MASK); 1242 rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page); 1243 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1); 1244 1245 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1246 wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, 1247 BIT_MDIO_WFLAG_V1); 1248 if (wflag == 0) 1249 return; 1250 1251 udelay(10); 1252 } 1253 1254 WARN(wflag, "failed to write to MDIO register, addr=0x%02x\n", addr); 1255 } 1256 1257 static void rtw_pci_clkreq_set(struct rtw_dev *rtwdev, bool enable) 1258 { 1259 u8 value; 1260 int ret; 1261 1262 if (rtw_pci_disable_aspm) 1263 return; 1264 1265 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1266 if (ret) { 1267 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret); 1268 return; 1269 } 1270 1271 if (enable) 1272 value |= BIT_CLKREQ_SW_EN; 1273 else 1274 value &= ~BIT_CLKREQ_SW_EN; 1275 1276 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1277 } 1278 1279 static void rtw_pci_aspm_set(struct rtw_dev *rtwdev, bool enable) 1280 { 1281 u8 value; 1282 int ret; 1283 1284 if (rtw_pci_disable_aspm) 1285 return; 1286 1287 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1288 if (ret) { 1289 rtw_err(rtwdev, "failed to read ASPM, ret=%d", ret); 1290 return; 1291 } 1292 1293 if (enable) 1294 value |= BIT_L1_SW_EN; 1295 else 1296 value &= ~BIT_L1_SW_EN; 1297 1298 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1299 } 1300 1301 static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter) 1302 { 1303 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1304 1305 /* Like CLKREQ, ASPM is also implemented by two HW modules, and can 1306 * only be enabled when host supports it. 1307 * 1308 * And ASPM mechanism should be enabled when driver/firmware enters 1309 * power save mode, without having heavy traffic. Because we've 1310 * experienced some inter-operability issues that the link tends 1311 * to enter L1 state on the fly even when driver is having high 1312 * throughput. This is probably because the ASPM behavior slightly 1313 * varies from different SOC. 1314 */ 1315 if (rtwpci->link_ctrl & PCI_EXP_LNKCTL_ASPM_L1) 1316 rtw_pci_aspm_set(rtwdev, enter); 1317 } 1318 1319 static void rtw_pci_link_cfg(struct rtw_dev *rtwdev) 1320 { 1321 struct rtw_chip_info *chip = rtwdev->chip; 1322 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1323 struct pci_dev *pdev = rtwpci->pdev; 1324 u16 link_ctrl; 1325 int ret; 1326 1327 /* RTL8822CE has enabled REFCLK auto calibration, it does not need 1328 * to add clock delay to cover the REFCLK timing gap. 1329 */ 1330 if (chip->id == RTW_CHIP_TYPE_8822C) 1331 rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0); 1332 1333 /* Though there is standard PCIE configuration space to set the 1334 * link control register, but by Realtek's design, driver should 1335 * check if host supports CLKREQ/ASPM to enable the HW module. 1336 * 1337 * These functions are implemented by two HW modules associated, 1338 * one is responsible to access PCIE configuration space to 1339 * follow the host settings, and another is in charge of doing 1340 * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes 1341 * the host does not support it, and due to some reasons or wrong 1342 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device 1343 * loss if HW misbehaves on the link. 1344 * 1345 * Hence it's designed that driver should first check the PCIE 1346 * configuration space is sync'ed and enabled, then driver can turn 1347 * on the other module that is actually working on the mechanism. 1348 */ 1349 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); 1350 if (ret) { 1351 rtw_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); 1352 return; 1353 } 1354 1355 if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) 1356 rtw_pci_clkreq_set(rtwdev, true); 1357 1358 rtwpci->link_ctrl = link_ctrl; 1359 } 1360 1361 static void rtw_pci_interface_cfg(struct rtw_dev *rtwdev) 1362 { 1363 struct rtw_chip_info *chip = rtwdev->chip; 1364 1365 switch (chip->id) { 1366 case RTW_CHIP_TYPE_8822C: 1367 if (rtwdev->hal.cut_version >= RTW_CHIP_VER_CUT_D) 1368 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG, 1369 BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK, 1); 1370 break; 1371 default: 1372 break; 1373 } 1374 } 1375 1376 static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev) 1377 { 1378 struct rtw_chip_info *chip = rtwdev->chip; 1379 const struct rtw_intf_phy_para *para; 1380 u16 cut; 1381 u16 value; 1382 u16 offset; 1383 int i; 1384 1385 cut = BIT(0) << rtwdev->hal.cut_version; 1386 1387 for (i = 0; i < chip->intf_table->n_gen1_para; i++) { 1388 para = &chip->intf_table->gen1_para[i]; 1389 if (!(para->cut_mask & cut)) 1390 continue; 1391 if (para->offset == 0xffff) 1392 break; 1393 offset = para->offset; 1394 value = para->value; 1395 if (para->ip_sel == RTW_IP_SEL_PHY) 1396 rtw_mdio_write(rtwdev, offset, value, true); 1397 else 1398 rtw_dbi_write8(rtwdev, offset, value); 1399 } 1400 1401 for (i = 0; i < chip->intf_table->n_gen2_para; i++) { 1402 para = &chip->intf_table->gen2_para[i]; 1403 if (!(para->cut_mask & cut)) 1404 continue; 1405 if (para->offset == 0xffff) 1406 break; 1407 offset = para->offset; 1408 value = para->value; 1409 if (para->ip_sel == RTW_IP_SEL_PHY) 1410 rtw_mdio_write(rtwdev, offset, value, false); 1411 else 1412 rtw_dbi_write8(rtwdev, offset, value); 1413 } 1414 1415 rtw_pci_link_cfg(rtwdev); 1416 } 1417 1418 static int __maybe_unused rtw_pci_suspend(struct device *dev) 1419 { 1420 return 0; 1421 } 1422 1423 static int __maybe_unused rtw_pci_resume(struct device *dev) 1424 { 1425 return 0; 1426 } 1427 1428 SIMPLE_DEV_PM_OPS(rtw_pm_ops, rtw_pci_suspend, rtw_pci_resume); 1429 EXPORT_SYMBOL(rtw_pm_ops); 1430 1431 static int rtw_pci_claim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1432 { 1433 int ret; 1434 1435 ret = pci_enable_device(pdev); 1436 if (ret) { 1437 rtw_err(rtwdev, "failed to enable pci device\n"); 1438 return ret; 1439 } 1440 1441 pci_set_master(pdev); 1442 pci_set_drvdata(pdev, rtwdev->hw); 1443 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); 1444 1445 return 0; 1446 } 1447 1448 static void rtw_pci_declaim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1449 { 1450 pci_clear_master(pdev); 1451 pci_disable_device(pdev); 1452 } 1453 1454 static int rtw_pci_setup_resource(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1455 { 1456 struct rtw_pci *rtwpci; 1457 int ret; 1458 1459 rtwpci = (struct rtw_pci *)rtwdev->priv; 1460 rtwpci->pdev = pdev; 1461 1462 /* after this driver can access to hw registers */ 1463 ret = rtw_pci_io_mapping(rtwdev, pdev); 1464 if (ret) { 1465 rtw_err(rtwdev, "failed to request pci io region\n"); 1466 goto err_out; 1467 } 1468 1469 ret = rtw_pci_init(rtwdev); 1470 if (ret) { 1471 rtw_err(rtwdev, "failed to allocate pci resources\n"); 1472 goto err_io_unmap; 1473 } 1474 1475 return 0; 1476 1477 err_io_unmap: 1478 rtw_pci_io_unmapping(rtwdev, pdev); 1479 1480 err_out: 1481 return ret; 1482 } 1483 1484 static void rtw_pci_destroy(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1485 { 1486 rtw_pci_deinit(rtwdev); 1487 rtw_pci_io_unmapping(rtwdev, pdev); 1488 } 1489 1490 static struct rtw_hci_ops rtw_pci_ops = { 1491 .tx_write = rtw_pci_tx_write, 1492 .tx_kick_off = rtw_pci_tx_kick_off, 1493 .setup = rtw_pci_setup, 1494 .start = rtw_pci_start, 1495 .stop = rtw_pci_stop, 1496 .deep_ps = rtw_pci_deep_ps, 1497 .link_ps = rtw_pci_link_ps, 1498 .interface_cfg = rtw_pci_interface_cfg, 1499 1500 .read8 = rtw_pci_read8, 1501 .read16 = rtw_pci_read16, 1502 .read32 = rtw_pci_read32, 1503 .write8 = rtw_pci_write8, 1504 .write16 = rtw_pci_write16, 1505 .write32 = rtw_pci_write32, 1506 .write_data_rsvd_page = rtw_pci_write_data_rsvd_page, 1507 .write_data_h2c = rtw_pci_write_data_h2c, 1508 }; 1509 1510 static int rtw_pci_request_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1511 { 1512 unsigned int flags = PCI_IRQ_LEGACY; 1513 int ret; 1514 1515 if (!rtw_disable_msi) 1516 flags |= PCI_IRQ_MSI; 1517 1518 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); 1519 if (ret < 0) { 1520 rtw_err(rtwdev, "failed to alloc PCI irq vectors\n"); 1521 return ret; 1522 } 1523 1524 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, 1525 rtw_pci_interrupt_handler, 1526 rtw_pci_interrupt_threadfn, 1527 IRQF_SHARED, KBUILD_MODNAME, rtwdev); 1528 if (ret) { 1529 rtw_err(rtwdev, "failed to request irq %d\n", ret); 1530 pci_free_irq_vectors(pdev); 1531 } 1532 1533 return ret; 1534 } 1535 1536 static void rtw_pci_free_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1537 { 1538 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); 1539 pci_free_irq_vectors(pdev); 1540 } 1541 1542 static int rtw_pci_napi_poll(struct napi_struct *napi, int budget) 1543 { 1544 struct rtw_pci *rtwpci = container_of(napi, struct rtw_pci, napi); 1545 struct rtw_dev *rtwdev = container_of((void *)rtwpci, struct rtw_dev, 1546 priv); 1547 int work_done = 0; 1548 1549 while (work_done < budget) { 1550 u32 work_done_once; 1551 1552 work_done_once = rtw_pci_rx_napi(rtwdev, rtwpci, RTW_RX_QUEUE_MPDU, 1553 budget - work_done); 1554 if (work_done_once == 0) 1555 break; 1556 work_done += work_done_once; 1557 } 1558 if (work_done < budget) { 1559 napi_complete_done(napi, work_done); 1560 spin_lock_bh(&rtwpci->irq_lock); 1561 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 1562 spin_unlock_bh(&rtwpci->irq_lock); 1563 /* When ISR happens during polling and before napi_complete 1564 * while no further data is received. Data on the dma_ring will 1565 * not be processed immediately. Check whether dma ring is 1566 * empty and perform napi_schedule accordingly. 1567 */ 1568 if (rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci)) 1569 napi_schedule(napi); 1570 } 1571 1572 return work_done; 1573 } 1574 1575 static void rtw_pci_napi_init(struct rtw_dev *rtwdev) 1576 { 1577 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1578 1579 init_dummy_netdev(&rtwpci->netdev); 1580 netif_napi_add(&rtwpci->netdev, &rtwpci->napi, rtw_pci_napi_poll, 1581 RTW_NAPI_WEIGHT_NUM); 1582 } 1583 1584 static void rtw_pci_napi_deinit(struct rtw_dev *rtwdev) 1585 { 1586 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1587 1588 rtw_pci_napi_stop(rtwdev); 1589 netif_napi_del(&rtwpci->napi); 1590 } 1591 1592 int rtw_pci_probe(struct pci_dev *pdev, 1593 const struct pci_device_id *id) 1594 { 1595 struct ieee80211_hw *hw; 1596 struct rtw_dev *rtwdev; 1597 int drv_data_size; 1598 int ret; 1599 1600 drv_data_size = sizeof(struct rtw_dev) + sizeof(struct rtw_pci); 1601 hw = ieee80211_alloc_hw(drv_data_size, &rtw_ops); 1602 if (!hw) { 1603 dev_err(&pdev->dev, "failed to allocate hw\n"); 1604 return -ENOMEM; 1605 } 1606 1607 rtwdev = hw->priv; 1608 rtwdev->hw = hw; 1609 rtwdev->dev = &pdev->dev; 1610 rtwdev->chip = (struct rtw_chip_info *)id->driver_data; 1611 rtwdev->hci.ops = &rtw_pci_ops; 1612 rtwdev->hci.type = RTW_HCI_TYPE_PCIE; 1613 1614 ret = rtw_core_init(rtwdev); 1615 if (ret) 1616 goto err_release_hw; 1617 1618 rtw_dbg(rtwdev, RTW_DBG_PCI, 1619 "rtw88 pci probe: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 1620 pdev->vendor, pdev->device, pdev->revision); 1621 1622 ret = rtw_pci_claim(rtwdev, pdev); 1623 if (ret) { 1624 rtw_err(rtwdev, "failed to claim pci device\n"); 1625 goto err_deinit_core; 1626 } 1627 1628 ret = rtw_pci_setup_resource(rtwdev, pdev); 1629 if (ret) { 1630 rtw_err(rtwdev, "failed to setup pci resources\n"); 1631 goto err_pci_declaim; 1632 } 1633 1634 rtw_pci_napi_init(rtwdev); 1635 1636 ret = rtw_chip_info_setup(rtwdev); 1637 if (ret) { 1638 rtw_err(rtwdev, "failed to setup chip information\n"); 1639 goto err_destroy_pci; 1640 } 1641 1642 rtw_pci_phy_cfg(rtwdev); 1643 1644 ret = rtw_register_hw(rtwdev, hw); 1645 if (ret) { 1646 rtw_err(rtwdev, "failed to register hw\n"); 1647 goto err_destroy_pci; 1648 } 1649 1650 ret = rtw_pci_request_irq(rtwdev, pdev); 1651 if (ret) { 1652 ieee80211_unregister_hw(hw); 1653 goto err_destroy_pci; 1654 } 1655 1656 return 0; 1657 1658 err_destroy_pci: 1659 rtw_pci_napi_deinit(rtwdev); 1660 rtw_pci_destroy(rtwdev, pdev); 1661 1662 err_pci_declaim: 1663 rtw_pci_declaim(rtwdev, pdev); 1664 1665 err_deinit_core: 1666 rtw_core_deinit(rtwdev); 1667 1668 err_release_hw: 1669 ieee80211_free_hw(hw); 1670 1671 return ret; 1672 } 1673 EXPORT_SYMBOL(rtw_pci_probe); 1674 1675 void rtw_pci_remove(struct pci_dev *pdev) 1676 { 1677 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1678 struct rtw_dev *rtwdev; 1679 struct rtw_pci *rtwpci; 1680 1681 if (!hw) 1682 return; 1683 1684 rtwdev = hw->priv; 1685 rtwpci = (struct rtw_pci *)rtwdev->priv; 1686 1687 rtw_unregister_hw(rtwdev, hw); 1688 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1689 rtw_pci_napi_deinit(rtwdev); 1690 rtw_pci_destroy(rtwdev, pdev); 1691 rtw_pci_declaim(rtwdev, pdev); 1692 rtw_pci_free_irq(rtwdev, pdev); 1693 rtw_core_deinit(rtwdev); 1694 ieee80211_free_hw(hw); 1695 } 1696 EXPORT_SYMBOL(rtw_pci_remove); 1697 1698 void rtw_pci_shutdown(struct pci_dev *pdev) 1699 { 1700 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1701 struct rtw_dev *rtwdev; 1702 struct rtw_chip_info *chip; 1703 1704 if (!hw) 1705 return; 1706 1707 rtwdev = hw->priv; 1708 chip = rtwdev->chip; 1709 1710 if (chip->ops->shutdown) 1711 chip->ops->shutdown(rtwdev); 1712 1713 pci_set_power_state(pdev, PCI_D3hot); 1714 } 1715 EXPORT_SYMBOL(rtw_pci_shutdown); 1716 1717 MODULE_AUTHOR("Realtek Corporation"); 1718 MODULE_DESCRIPTION("Realtek 802.11ac wireless PCI driver"); 1719 MODULE_LICENSE("Dual BSD/GPL"); 1720