1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include "main.h" 8 #include "pci.h" 9 #include "reg.h" 10 #include "tx.h" 11 #include "rx.h" 12 #include "fw.h" 13 #include "ps.h" 14 #include "debug.h" 15 16 static bool rtw_disable_msi; 17 static bool rtw_pci_disable_aspm; 18 module_param_named(disable_msi, rtw_disable_msi, bool, 0644); 19 module_param_named(disable_aspm, rtw_pci_disable_aspm, bool, 0644); 20 MODULE_PARM_DESC(disable_msi, "Set Y to disable MSI interrupt support"); 21 MODULE_PARM_DESC(disable_aspm, "Set Y to disable PCI ASPM support"); 22 23 static u32 rtw_pci_tx_queue_idx_addr[] = { 24 [RTW_TX_QUEUE_BK] = RTK_PCI_TXBD_IDX_BKQ, 25 [RTW_TX_QUEUE_BE] = RTK_PCI_TXBD_IDX_BEQ, 26 [RTW_TX_QUEUE_VI] = RTK_PCI_TXBD_IDX_VIQ, 27 [RTW_TX_QUEUE_VO] = RTK_PCI_TXBD_IDX_VOQ, 28 [RTW_TX_QUEUE_MGMT] = RTK_PCI_TXBD_IDX_MGMTQ, 29 [RTW_TX_QUEUE_HI0] = RTK_PCI_TXBD_IDX_HI0Q, 30 [RTW_TX_QUEUE_H2C] = RTK_PCI_TXBD_IDX_H2CQ, 31 }; 32 33 static u8 rtw_pci_get_tx_qsel(struct sk_buff *skb, 34 enum rtw_tx_queue_type queue) 35 { 36 switch (queue) { 37 case RTW_TX_QUEUE_BCN: 38 return TX_DESC_QSEL_BEACON; 39 case RTW_TX_QUEUE_H2C: 40 return TX_DESC_QSEL_H2C; 41 case RTW_TX_QUEUE_MGMT: 42 return TX_DESC_QSEL_MGMT; 43 case RTW_TX_QUEUE_HI0: 44 return TX_DESC_QSEL_HIGH; 45 default: 46 return skb->priority; 47 } 48 }; 49 50 static u8 rtw_pci_read8(struct rtw_dev *rtwdev, u32 addr) 51 { 52 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 53 54 return readb(rtwpci->mmap + addr); 55 } 56 57 static u16 rtw_pci_read16(struct rtw_dev *rtwdev, u32 addr) 58 { 59 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 60 61 return readw(rtwpci->mmap + addr); 62 } 63 64 static u32 rtw_pci_read32(struct rtw_dev *rtwdev, u32 addr) 65 { 66 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 67 68 return readl(rtwpci->mmap + addr); 69 } 70 71 static void rtw_pci_write8(struct rtw_dev *rtwdev, u32 addr, u8 val) 72 { 73 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 74 75 writeb(val, rtwpci->mmap + addr); 76 } 77 78 static void rtw_pci_write16(struct rtw_dev *rtwdev, u32 addr, u16 val) 79 { 80 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 81 82 writew(val, rtwpci->mmap + addr); 83 } 84 85 static void rtw_pci_write32(struct rtw_dev *rtwdev, u32 addr, u32 val) 86 { 87 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 88 89 writel(val, rtwpci->mmap + addr); 90 } 91 92 static inline void *rtw_pci_get_tx_desc(struct rtw_pci_tx_ring *tx_ring, u8 idx) 93 { 94 int offset = tx_ring->r.desc_size * idx; 95 96 return tx_ring->r.head + offset; 97 } 98 99 static void rtw_pci_free_tx_ring_skbs(struct rtw_dev *rtwdev, 100 struct rtw_pci_tx_ring *tx_ring) 101 { 102 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 103 struct rtw_pci_tx_data *tx_data; 104 struct sk_buff *skb, *tmp; 105 dma_addr_t dma; 106 107 /* free every skb remained in tx list */ 108 skb_queue_walk_safe(&tx_ring->queue, skb, tmp) { 109 __skb_unlink(skb, &tx_ring->queue); 110 tx_data = rtw_pci_get_tx_data(skb); 111 dma = tx_data->dma; 112 113 dma_unmap_single(&pdev->dev, dma, skb->len, DMA_TO_DEVICE); 114 dev_kfree_skb_any(skb); 115 } 116 } 117 118 static void rtw_pci_free_tx_ring(struct rtw_dev *rtwdev, 119 struct rtw_pci_tx_ring *tx_ring) 120 { 121 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 122 u8 *head = tx_ring->r.head; 123 u32 len = tx_ring->r.len; 124 int ring_sz = len * tx_ring->r.desc_size; 125 126 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 127 128 /* free the ring itself */ 129 dma_free_coherent(&pdev->dev, ring_sz, head, tx_ring->r.dma); 130 tx_ring->r.head = NULL; 131 } 132 133 static void rtw_pci_free_rx_ring_skbs(struct rtw_dev *rtwdev, 134 struct rtw_pci_rx_ring *rx_ring) 135 { 136 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 137 struct sk_buff *skb; 138 int buf_sz = RTK_PCI_RX_BUF_SIZE; 139 dma_addr_t dma; 140 int i; 141 142 for (i = 0; i < rx_ring->r.len; i++) { 143 skb = rx_ring->buf[i]; 144 if (!skb) 145 continue; 146 147 dma = *((dma_addr_t *)skb->cb); 148 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 149 dev_kfree_skb(skb); 150 rx_ring->buf[i] = NULL; 151 } 152 } 153 154 static void rtw_pci_free_rx_ring(struct rtw_dev *rtwdev, 155 struct rtw_pci_rx_ring *rx_ring) 156 { 157 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 158 u8 *head = rx_ring->r.head; 159 int ring_sz = rx_ring->r.desc_size * rx_ring->r.len; 160 161 rtw_pci_free_rx_ring_skbs(rtwdev, rx_ring); 162 163 dma_free_coherent(&pdev->dev, ring_sz, head, rx_ring->r.dma); 164 } 165 166 static void rtw_pci_free_trx_ring(struct rtw_dev *rtwdev) 167 { 168 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 169 struct rtw_pci_tx_ring *tx_ring; 170 struct rtw_pci_rx_ring *rx_ring; 171 int i; 172 173 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 174 tx_ring = &rtwpci->tx_rings[i]; 175 rtw_pci_free_tx_ring(rtwdev, tx_ring); 176 } 177 178 for (i = 0; i < RTK_MAX_RX_QUEUE_NUM; i++) { 179 rx_ring = &rtwpci->rx_rings[i]; 180 rtw_pci_free_rx_ring(rtwdev, rx_ring); 181 } 182 } 183 184 static int rtw_pci_init_tx_ring(struct rtw_dev *rtwdev, 185 struct rtw_pci_tx_ring *tx_ring, 186 u8 desc_size, u32 len) 187 { 188 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 189 int ring_sz = desc_size * len; 190 dma_addr_t dma; 191 u8 *head; 192 193 if (len > TRX_BD_IDX_MASK) { 194 rtw_err(rtwdev, "len %d exceeds maximum TX entries\n", len); 195 return -EINVAL; 196 } 197 198 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 199 if (!head) { 200 rtw_err(rtwdev, "failed to allocate tx ring\n"); 201 return -ENOMEM; 202 } 203 204 skb_queue_head_init(&tx_ring->queue); 205 tx_ring->r.head = head; 206 tx_ring->r.dma = dma; 207 tx_ring->r.len = len; 208 tx_ring->r.desc_size = desc_size; 209 tx_ring->r.wp = 0; 210 tx_ring->r.rp = 0; 211 212 return 0; 213 } 214 215 static int rtw_pci_reset_rx_desc(struct rtw_dev *rtwdev, struct sk_buff *skb, 216 struct rtw_pci_rx_ring *rx_ring, 217 u32 idx, u32 desc_sz) 218 { 219 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 220 struct rtw_pci_rx_buffer_desc *buf_desc; 221 int buf_sz = RTK_PCI_RX_BUF_SIZE; 222 dma_addr_t dma; 223 224 if (!skb) 225 return -EINVAL; 226 227 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); 228 if (dma_mapping_error(&pdev->dev, dma)) 229 return -EBUSY; 230 231 *((dma_addr_t *)skb->cb) = dma; 232 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 233 idx * desc_sz); 234 memset(buf_desc, 0, sizeof(*buf_desc)); 235 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 236 buf_desc->dma = cpu_to_le32(dma); 237 238 return 0; 239 } 240 241 static void rtw_pci_sync_rx_desc_device(struct rtw_dev *rtwdev, dma_addr_t dma, 242 struct rtw_pci_rx_ring *rx_ring, 243 u32 idx, u32 desc_sz) 244 { 245 struct device *dev = rtwdev->dev; 246 struct rtw_pci_rx_buffer_desc *buf_desc; 247 int buf_sz = RTK_PCI_RX_BUF_SIZE; 248 249 dma_sync_single_for_device(dev, dma, buf_sz, DMA_FROM_DEVICE); 250 251 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 252 idx * desc_sz); 253 memset(buf_desc, 0, sizeof(*buf_desc)); 254 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 255 buf_desc->dma = cpu_to_le32(dma); 256 } 257 258 static int rtw_pci_init_rx_ring(struct rtw_dev *rtwdev, 259 struct rtw_pci_rx_ring *rx_ring, 260 u8 desc_size, u32 len) 261 { 262 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 263 struct sk_buff *skb = NULL; 264 dma_addr_t dma; 265 u8 *head; 266 int ring_sz = desc_size * len; 267 int buf_sz = RTK_PCI_RX_BUF_SIZE; 268 int i, allocated; 269 int ret = 0; 270 271 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 272 if (!head) { 273 rtw_err(rtwdev, "failed to allocate rx ring\n"); 274 return -ENOMEM; 275 } 276 rx_ring->r.head = head; 277 278 for (i = 0; i < len; i++) { 279 skb = dev_alloc_skb(buf_sz); 280 if (!skb) { 281 allocated = i; 282 ret = -ENOMEM; 283 goto err_out; 284 } 285 286 memset(skb->data, 0, buf_sz); 287 rx_ring->buf[i] = skb; 288 ret = rtw_pci_reset_rx_desc(rtwdev, skb, rx_ring, i, desc_size); 289 if (ret) { 290 allocated = i; 291 dev_kfree_skb_any(skb); 292 goto err_out; 293 } 294 } 295 296 rx_ring->r.dma = dma; 297 rx_ring->r.len = len; 298 rx_ring->r.desc_size = desc_size; 299 rx_ring->r.wp = 0; 300 rx_ring->r.rp = 0; 301 302 return 0; 303 304 err_out: 305 for (i = 0; i < allocated; i++) { 306 skb = rx_ring->buf[i]; 307 if (!skb) 308 continue; 309 dma = *((dma_addr_t *)skb->cb); 310 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 311 dev_kfree_skb_any(skb); 312 rx_ring->buf[i] = NULL; 313 } 314 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 315 316 rtw_err(rtwdev, "failed to init rx buffer\n"); 317 318 return ret; 319 } 320 321 static int rtw_pci_init_trx_ring(struct rtw_dev *rtwdev) 322 { 323 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 324 struct rtw_pci_tx_ring *tx_ring; 325 struct rtw_pci_rx_ring *rx_ring; 326 const struct rtw_chip_info *chip = rtwdev->chip; 327 int i = 0, j = 0, tx_alloced = 0, rx_alloced = 0; 328 int tx_desc_size, rx_desc_size; 329 u32 len; 330 int ret; 331 332 tx_desc_size = chip->tx_buf_desc_sz; 333 334 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 335 tx_ring = &rtwpci->tx_rings[i]; 336 len = max_num_of_tx_queue(i); 337 ret = rtw_pci_init_tx_ring(rtwdev, tx_ring, tx_desc_size, len); 338 if (ret) 339 goto out; 340 } 341 342 rx_desc_size = chip->rx_buf_desc_sz; 343 344 for (j = 0; j < RTK_MAX_RX_QUEUE_NUM; j++) { 345 rx_ring = &rtwpci->rx_rings[j]; 346 ret = rtw_pci_init_rx_ring(rtwdev, rx_ring, rx_desc_size, 347 RTK_MAX_RX_DESC_NUM); 348 if (ret) 349 goto out; 350 } 351 352 return 0; 353 354 out: 355 tx_alloced = i; 356 for (i = 0; i < tx_alloced; i++) { 357 tx_ring = &rtwpci->tx_rings[i]; 358 rtw_pci_free_tx_ring(rtwdev, tx_ring); 359 } 360 361 rx_alloced = j; 362 for (j = 0; j < rx_alloced; j++) { 363 rx_ring = &rtwpci->rx_rings[j]; 364 rtw_pci_free_rx_ring(rtwdev, rx_ring); 365 } 366 367 return ret; 368 } 369 370 static void rtw_pci_deinit(struct rtw_dev *rtwdev) 371 { 372 rtw_pci_free_trx_ring(rtwdev); 373 } 374 375 static int rtw_pci_init(struct rtw_dev *rtwdev) 376 { 377 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 378 int ret = 0; 379 380 rtwpci->irq_mask[0] = IMR_HIGHDOK | 381 IMR_MGNTDOK | 382 IMR_BKDOK | 383 IMR_BEDOK | 384 IMR_VIDOK | 385 IMR_VODOK | 386 IMR_ROK | 387 IMR_BCNDMAINT_E | 388 IMR_C2HCMD | 389 0; 390 rtwpci->irq_mask[1] = IMR_TXFOVW | 391 0; 392 rtwpci->irq_mask[3] = IMR_H2CDOK | 393 0; 394 spin_lock_init(&rtwpci->irq_lock); 395 spin_lock_init(&rtwpci->hwirq_lock); 396 ret = rtw_pci_init_trx_ring(rtwdev); 397 398 return ret; 399 } 400 401 static void rtw_pci_reset_buf_desc(struct rtw_dev *rtwdev) 402 { 403 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 404 u32 len; 405 u8 tmp; 406 dma_addr_t dma; 407 408 tmp = rtw_read8(rtwdev, RTK_PCI_CTRL + 3); 409 rtw_write8(rtwdev, RTK_PCI_CTRL + 3, tmp | 0xf7); 410 411 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BCN].r.dma; 412 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BCNQ, dma); 413 414 if (!rtw_chip_wcpu_11n(rtwdev)) { 415 len = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.len; 416 dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma; 417 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0; 418 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; 419 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK); 420 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma); 421 } 422 423 len = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.len; 424 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.dma; 425 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.rp = 0; 426 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; 427 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BKQ, len & TRX_BD_IDX_MASK); 428 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BKQ, dma); 429 430 len = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.len; 431 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.dma; 432 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.rp = 0; 433 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; 434 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BEQ, len & TRX_BD_IDX_MASK); 435 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BEQ, dma); 436 437 len = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.len; 438 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.dma; 439 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.rp = 0; 440 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; 441 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VOQ, len & TRX_BD_IDX_MASK); 442 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VOQ, dma); 443 444 len = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.len; 445 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.dma; 446 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.rp = 0; 447 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; 448 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VIQ, len & TRX_BD_IDX_MASK); 449 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VIQ, dma); 450 451 len = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.len; 452 dma = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.dma; 453 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.rp = 0; 454 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; 455 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_MGMTQ, len & TRX_BD_IDX_MASK); 456 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_MGMTQ, dma); 457 458 len = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.len; 459 dma = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.dma; 460 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.rp = 0; 461 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; 462 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_HI0Q, len & TRX_BD_IDX_MASK); 463 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_HI0Q, dma); 464 465 len = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.len; 466 dma = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.dma; 467 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.rp = 0; 468 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0; 469 rtw_write16(rtwdev, RTK_PCI_RXBD_NUM_MPDUQ, len & TRX_BD_IDX_MASK); 470 rtw_write32(rtwdev, RTK_PCI_RXBD_DESA_MPDUQ, dma); 471 472 /* reset read/write point */ 473 rtw_write32(rtwdev, RTK_PCI_TXBD_RWPTR_CLR, 0xffffffff); 474 475 /* reset H2C Queue index in a single write */ 476 if (rtw_chip_wcpu_11ac(rtwdev)) 477 rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR, 478 BIT_CLR_H2CQ_HOST_IDX | BIT_CLR_H2CQ_HW_IDX); 479 } 480 481 static void rtw_pci_reset_trx_ring(struct rtw_dev *rtwdev) 482 { 483 rtw_pci_reset_buf_desc(rtwdev); 484 } 485 486 static void rtw_pci_enable_interrupt(struct rtw_dev *rtwdev, 487 struct rtw_pci *rtwpci, bool exclude_rx) 488 { 489 unsigned long flags; 490 u32 imr0_unmask = exclude_rx ? IMR_ROK : 0; 491 492 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 493 494 rtw_write32(rtwdev, RTK_PCI_HIMR0, rtwpci->irq_mask[0] & ~imr0_unmask); 495 rtw_write32(rtwdev, RTK_PCI_HIMR1, rtwpci->irq_mask[1]); 496 if (rtw_chip_wcpu_11ac(rtwdev)) 497 rtw_write32(rtwdev, RTK_PCI_HIMR3, rtwpci->irq_mask[3]); 498 499 rtwpci->irq_enabled = true; 500 501 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 502 } 503 504 static void rtw_pci_disable_interrupt(struct rtw_dev *rtwdev, 505 struct rtw_pci *rtwpci) 506 { 507 unsigned long flags; 508 509 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 510 511 if (!rtwpci->irq_enabled) 512 goto out; 513 514 rtw_write32(rtwdev, RTK_PCI_HIMR0, 0); 515 rtw_write32(rtwdev, RTK_PCI_HIMR1, 0); 516 if (rtw_chip_wcpu_11ac(rtwdev)) 517 rtw_write32(rtwdev, RTK_PCI_HIMR3, 0); 518 519 rtwpci->irq_enabled = false; 520 521 out: 522 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 523 } 524 525 static void rtw_pci_dma_reset(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 526 { 527 /* reset dma and rx tag */ 528 rtw_write32_set(rtwdev, RTK_PCI_CTRL, 529 BIT_RST_TRXDMA_INTF | BIT_RX_TAG_EN); 530 rtwpci->rx_tag = 0; 531 } 532 533 static int rtw_pci_setup(struct rtw_dev *rtwdev) 534 { 535 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 536 537 rtw_pci_reset_trx_ring(rtwdev); 538 rtw_pci_dma_reset(rtwdev, rtwpci); 539 540 return 0; 541 } 542 543 static void rtw_pci_dma_release(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 544 { 545 struct rtw_pci_tx_ring *tx_ring; 546 enum rtw_tx_queue_type queue; 547 548 rtw_pci_reset_trx_ring(rtwdev); 549 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 550 tx_ring = &rtwpci->tx_rings[queue]; 551 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 552 } 553 } 554 555 static void rtw_pci_napi_start(struct rtw_dev *rtwdev) 556 { 557 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 558 559 if (test_and_set_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 560 return; 561 562 napi_enable(&rtwpci->napi); 563 } 564 565 static void rtw_pci_napi_stop(struct rtw_dev *rtwdev) 566 { 567 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 568 569 if (!test_and_clear_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 570 return; 571 572 napi_synchronize(&rtwpci->napi); 573 napi_disable(&rtwpci->napi); 574 } 575 576 static int rtw_pci_start(struct rtw_dev *rtwdev) 577 { 578 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 579 580 rtw_pci_napi_start(rtwdev); 581 582 spin_lock_bh(&rtwpci->irq_lock); 583 rtwpci->running = true; 584 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 585 spin_unlock_bh(&rtwpci->irq_lock); 586 587 return 0; 588 } 589 590 static void rtw_pci_stop(struct rtw_dev *rtwdev) 591 { 592 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 593 struct pci_dev *pdev = rtwpci->pdev; 594 595 spin_lock_bh(&rtwpci->irq_lock); 596 rtwpci->running = false; 597 rtw_pci_disable_interrupt(rtwdev, rtwpci); 598 spin_unlock_bh(&rtwpci->irq_lock); 599 600 synchronize_irq(pdev->irq); 601 rtw_pci_napi_stop(rtwdev); 602 603 spin_lock_bh(&rtwpci->irq_lock); 604 rtw_pci_dma_release(rtwdev, rtwpci); 605 spin_unlock_bh(&rtwpci->irq_lock); 606 } 607 608 static void rtw_pci_deep_ps_enter(struct rtw_dev *rtwdev) 609 { 610 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 611 struct rtw_pci_tx_ring *tx_ring; 612 enum rtw_tx_queue_type queue; 613 bool tx_empty = true; 614 615 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE)) 616 goto enter_deep_ps; 617 618 lockdep_assert_held(&rtwpci->irq_lock); 619 620 /* Deep PS state is not allowed to TX-DMA */ 621 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 622 /* BCN queue is rsvd page, does not have DMA interrupt 623 * H2C queue is managed by firmware 624 */ 625 if (queue == RTW_TX_QUEUE_BCN || 626 queue == RTW_TX_QUEUE_H2C) 627 continue; 628 629 tx_ring = &rtwpci->tx_rings[queue]; 630 631 /* check if there is any skb DMAing */ 632 if (skb_queue_len(&tx_ring->queue)) { 633 tx_empty = false; 634 break; 635 } 636 } 637 638 if (!tx_empty) { 639 rtw_dbg(rtwdev, RTW_DBG_PS, 640 "TX path not empty, cannot enter deep power save state\n"); 641 return; 642 } 643 enter_deep_ps: 644 set_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags); 645 rtw_power_mode_change(rtwdev, true); 646 } 647 648 static void rtw_pci_deep_ps_leave(struct rtw_dev *rtwdev) 649 { 650 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 651 652 lockdep_assert_held(&rtwpci->irq_lock); 653 654 if (test_and_clear_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 655 rtw_power_mode_change(rtwdev, false); 656 } 657 658 static void rtw_pci_deep_ps(struct rtw_dev *rtwdev, bool enter) 659 { 660 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 661 662 spin_lock_bh(&rtwpci->irq_lock); 663 664 if (enter && !test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 665 rtw_pci_deep_ps_enter(rtwdev); 666 667 if (!enter && test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 668 rtw_pci_deep_ps_leave(rtwdev); 669 670 spin_unlock_bh(&rtwpci->irq_lock); 671 } 672 673 static void rtw_pci_release_rsvd_page(struct rtw_pci *rtwpci, 674 struct rtw_pci_tx_ring *ring) 675 { 676 struct sk_buff *prev = skb_dequeue(&ring->queue); 677 struct rtw_pci_tx_data *tx_data; 678 dma_addr_t dma; 679 680 if (!prev) 681 return; 682 683 tx_data = rtw_pci_get_tx_data(prev); 684 dma = tx_data->dma; 685 dma_unmap_single(&rtwpci->pdev->dev, dma, prev->len, DMA_TO_DEVICE); 686 dev_kfree_skb_any(prev); 687 } 688 689 static void rtw_pci_dma_check(struct rtw_dev *rtwdev, 690 struct rtw_pci_rx_ring *rx_ring, 691 u32 idx) 692 { 693 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 694 const struct rtw_chip_info *chip = rtwdev->chip; 695 struct rtw_pci_rx_buffer_desc *buf_desc; 696 u32 desc_sz = chip->rx_buf_desc_sz; 697 u16 total_pkt_size; 698 699 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 700 idx * desc_sz); 701 total_pkt_size = le16_to_cpu(buf_desc->total_pkt_size); 702 703 /* rx tag mismatch, throw a warning */ 704 if (total_pkt_size != rtwpci->rx_tag) 705 rtw_warn(rtwdev, "pci bus timeout, check dma status\n"); 706 707 rtwpci->rx_tag = (rtwpci->rx_tag + 1) % RX_TAG_MAX; 708 } 709 710 static u32 __pci_get_hw_tx_ring_rp(struct rtw_dev *rtwdev, u8 pci_q) 711 { 712 u32 bd_idx_addr = rtw_pci_tx_queue_idx_addr[pci_q]; 713 u32 bd_idx = rtw_read16(rtwdev, bd_idx_addr + 2); 714 715 return FIELD_GET(TRX_BD_IDX_MASK, bd_idx); 716 } 717 718 static void __pci_flush_queue(struct rtw_dev *rtwdev, u8 pci_q, bool drop) 719 { 720 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 721 struct rtw_pci_tx_ring *ring = &rtwpci->tx_rings[pci_q]; 722 u32 cur_rp; 723 u8 i; 724 725 /* Because the time taked by the I/O in __pci_get_hw_tx_ring_rp is a 726 * bit dynamic, it's hard to define a reasonable fixed total timeout to 727 * use read_poll_timeout* helper. Instead, we can ensure a reasonable 728 * polling times, so we just use for loop with udelay here. 729 */ 730 for (i = 0; i < 30; i++) { 731 cur_rp = __pci_get_hw_tx_ring_rp(rtwdev, pci_q); 732 if (cur_rp == ring->r.wp) 733 return; 734 735 udelay(1); 736 } 737 738 if (!drop) 739 rtw_warn(rtwdev, "timed out to flush pci tx ring[%d]\n", pci_q); 740 } 741 742 static void __rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 pci_queues, 743 bool drop) 744 { 745 u8 q; 746 747 for (q = 0; q < RTK_MAX_TX_QUEUE_NUM; q++) { 748 /* It may be not necessary to flush BCN and H2C tx queues. */ 749 if (q == RTW_TX_QUEUE_BCN || q == RTW_TX_QUEUE_H2C) 750 continue; 751 752 if (pci_queues & BIT(q)) 753 __pci_flush_queue(rtwdev, q, drop); 754 } 755 } 756 757 static void rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 758 { 759 u32 pci_queues = 0; 760 u8 i; 761 762 /* If all of the hardware queues are requested to flush, 763 * flush all of the pci queues. 764 */ 765 if (queues == BIT(rtwdev->hw->queues) - 1) { 766 pci_queues = BIT(RTK_MAX_TX_QUEUE_NUM) - 1; 767 } else { 768 for (i = 0; i < rtwdev->hw->queues; i++) 769 if (queues & BIT(i)) 770 pci_queues |= BIT(rtw_tx_ac_to_hwq(i)); 771 } 772 773 __rtw_pci_flush_queues(rtwdev, pci_queues, drop); 774 } 775 776 static void rtw_pci_tx_kick_off_queue(struct rtw_dev *rtwdev, 777 enum rtw_tx_queue_type queue) 778 { 779 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 780 struct rtw_pci_tx_ring *ring; 781 u32 bd_idx; 782 783 ring = &rtwpci->tx_rings[queue]; 784 bd_idx = rtw_pci_tx_queue_idx_addr[queue]; 785 786 spin_lock_bh(&rtwpci->irq_lock); 787 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE)) 788 rtw_pci_deep_ps_leave(rtwdev); 789 rtw_write16(rtwdev, bd_idx, ring->r.wp & TRX_BD_IDX_MASK); 790 spin_unlock_bh(&rtwpci->irq_lock); 791 } 792 793 static void rtw_pci_tx_kick_off(struct rtw_dev *rtwdev) 794 { 795 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 796 enum rtw_tx_queue_type queue; 797 798 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) 799 if (test_and_clear_bit(queue, rtwpci->tx_queued)) 800 rtw_pci_tx_kick_off_queue(rtwdev, queue); 801 } 802 803 static int rtw_pci_tx_write_data(struct rtw_dev *rtwdev, 804 struct rtw_tx_pkt_info *pkt_info, 805 struct sk_buff *skb, 806 enum rtw_tx_queue_type queue) 807 { 808 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 809 const struct rtw_chip_info *chip = rtwdev->chip; 810 struct rtw_pci_tx_ring *ring; 811 struct rtw_pci_tx_data *tx_data; 812 dma_addr_t dma; 813 u32 tx_pkt_desc_sz = chip->tx_pkt_desc_sz; 814 u32 tx_buf_desc_sz = chip->tx_buf_desc_sz; 815 u32 size; 816 u32 psb_len; 817 u8 *pkt_desc; 818 struct rtw_pci_tx_buffer_desc *buf_desc; 819 820 ring = &rtwpci->tx_rings[queue]; 821 822 size = skb->len; 823 824 if (queue == RTW_TX_QUEUE_BCN) 825 rtw_pci_release_rsvd_page(rtwpci, ring); 826 else if (!avail_desc(ring->r.wp, ring->r.rp, ring->r.len)) 827 return -ENOSPC; 828 829 pkt_desc = skb_push(skb, chip->tx_pkt_desc_sz); 830 memset(pkt_desc, 0, tx_pkt_desc_sz); 831 pkt_info->qsel = rtw_pci_get_tx_qsel(skb, queue); 832 rtw_tx_fill_tx_desc(pkt_info, skb); 833 dma = dma_map_single(&rtwpci->pdev->dev, skb->data, skb->len, 834 DMA_TO_DEVICE); 835 if (dma_mapping_error(&rtwpci->pdev->dev, dma)) 836 return -EBUSY; 837 838 /* after this we got dma mapped, there is no way back */ 839 buf_desc = get_tx_buffer_desc(ring, tx_buf_desc_sz); 840 memset(buf_desc, 0, tx_buf_desc_sz); 841 psb_len = (skb->len - 1) / 128 + 1; 842 if (queue == RTW_TX_QUEUE_BCN) 843 psb_len |= 1 << RTK_PCI_TXBD_OWN_OFFSET; 844 845 buf_desc[0].psb_len = cpu_to_le16(psb_len); 846 buf_desc[0].buf_size = cpu_to_le16(tx_pkt_desc_sz); 847 buf_desc[0].dma = cpu_to_le32(dma); 848 buf_desc[1].buf_size = cpu_to_le16(size); 849 buf_desc[1].dma = cpu_to_le32(dma + tx_pkt_desc_sz); 850 851 tx_data = rtw_pci_get_tx_data(skb); 852 tx_data->dma = dma; 853 tx_data->sn = pkt_info->sn; 854 855 spin_lock_bh(&rtwpci->irq_lock); 856 857 skb_queue_tail(&ring->queue, skb); 858 859 if (queue == RTW_TX_QUEUE_BCN) 860 goto out_unlock; 861 862 /* update write-index, and kick it off later */ 863 set_bit(queue, rtwpci->tx_queued); 864 if (++ring->r.wp >= ring->r.len) 865 ring->r.wp = 0; 866 867 out_unlock: 868 spin_unlock_bh(&rtwpci->irq_lock); 869 870 return 0; 871 } 872 873 static int rtw_pci_write_data_rsvd_page(struct rtw_dev *rtwdev, u8 *buf, 874 u32 size) 875 { 876 struct sk_buff *skb; 877 struct rtw_tx_pkt_info pkt_info = {0}; 878 u8 reg_bcn_work; 879 int ret; 880 881 skb = rtw_tx_write_data_rsvd_page_get(rtwdev, &pkt_info, buf, size); 882 if (!skb) 883 return -ENOMEM; 884 885 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_BCN); 886 if (ret) { 887 rtw_err(rtwdev, "failed to write rsvd page data\n"); 888 return ret; 889 } 890 891 /* reserved pages go through beacon queue */ 892 reg_bcn_work = rtw_read8(rtwdev, RTK_PCI_TXBD_BCN_WORK); 893 reg_bcn_work |= BIT_PCI_BCNQ_FLAG; 894 rtw_write8(rtwdev, RTK_PCI_TXBD_BCN_WORK, reg_bcn_work); 895 896 return 0; 897 } 898 899 static int rtw_pci_write_data_h2c(struct rtw_dev *rtwdev, u8 *buf, u32 size) 900 { 901 struct sk_buff *skb; 902 struct rtw_tx_pkt_info pkt_info = {0}; 903 int ret; 904 905 skb = rtw_tx_write_data_h2c_get(rtwdev, &pkt_info, buf, size); 906 if (!skb) 907 return -ENOMEM; 908 909 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_H2C); 910 if (ret) { 911 rtw_err(rtwdev, "failed to write h2c data\n"); 912 return ret; 913 } 914 915 rtw_pci_tx_kick_off_queue(rtwdev, RTW_TX_QUEUE_H2C); 916 917 return 0; 918 } 919 920 static int rtw_pci_tx_write(struct rtw_dev *rtwdev, 921 struct rtw_tx_pkt_info *pkt_info, 922 struct sk_buff *skb) 923 { 924 enum rtw_tx_queue_type queue = rtw_tx_queue_mapping(skb); 925 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 926 struct rtw_pci_tx_ring *ring; 927 int ret; 928 929 ret = rtw_pci_tx_write_data(rtwdev, pkt_info, skb, queue); 930 if (ret) 931 return ret; 932 933 ring = &rtwpci->tx_rings[queue]; 934 spin_lock_bh(&rtwpci->irq_lock); 935 if (avail_desc(ring->r.wp, ring->r.rp, ring->r.len) < 2) { 936 ieee80211_stop_queue(rtwdev->hw, skb_get_queue_mapping(skb)); 937 ring->queue_stopped = true; 938 } 939 spin_unlock_bh(&rtwpci->irq_lock); 940 941 return 0; 942 } 943 944 static void rtw_pci_tx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 945 u8 hw_queue) 946 { 947 struct ieee80211_hw *hw = rtwdev->hw; 948 struct ieee80211_tx_info *info; 949 struct rtw_pci_tx_ring *ring; 950 struct rtw_pci_tx_data *tx_data; 951 struct sk_buff *skb; 952 u32 count; 953 u32 bd_idx_addr; 954 u32 bd_idx, cur_rp, rp_idx; 955 u16 q_map; 956 957 ring = &rtwpci->tx_rings[hw_queue]; 958 959 bd_idx_addr = rtw_pci_tx_queue_idx_addr[hw_queue]; 960 bd_idx = rtw_read32(rtwdev, bd_idx_addr); 961 cur_rp = bd_idx >> 16; 962 cur_rp &= TRX_BD_IDX_MASK; 963 rp_idx = ring->r.rp; 964 if (cur_rp >= ring->r.rp) 965 count = cur_rp - ring->r.rp; 966 else 967 count = ring->r.len - (ring->r.rp - cur_rp); 968 969 while (count--) { 970 skb = skb_dequeue(&ring->queue); 971 if (!skb) { 972 rtw_err(rtwdev, "failed to dequeue %d skb TX queue %d, BD=0x%08x, rp %d -> %d\n", 973 count, hw_queue, bd_idx, ring->r.rp, cur_rp); 974 break; 975 } 976 tx_data = rtw_pci_get_tx_data(skb); 977 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 978 DMA_TO_DEVICE); 979 980 /* just free command packets from host to card */ 981 if (hw_queue == RTW_TX_QUEUE_H2C) { 982 dev_kfree_skb_irq(skb); 983 continue; 984 } 985 986 if (ring->queue_stopped && 987 avail_desc(ring->r.wp, rp_idx, ring->r.len) > 4) { 988 q_map = skb_get_queue_mapping(skb); 989 ieee80211_wake_queue(hw, q_map); 990 ring->queue_stopped = false; 991 } 992 993 if (++rp_idx >= ring->r.len) 994 rp_idx = 0; 995 996 skb_pull(skb, rtwdev->chip->tx_pkt_desc_sz); 997 998 info = IEEE80211_SKB_CB(skb); 999 1000 /* enqueue to wait for tx report */ 1001 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 1002 rtw_tx_report_enqueue(rtwdev, skb, tx_data->sn); 1003 continue; 1004 } 1005 1006 /* always ACK for others, then they won't be marked as drop */ 1007 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1008 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 1009 else 1010 info->flags |= IEEE80211_TX_STAT_ACK; 1011 1012 ieee80211_tx_info_clear_status(info); 1013 ieee80211_tx_status_irqsafe(hw, skb); 1014 } 1015 1016 ring->r.rp = cur_rp; 1017 } 1018 1019 static void rtw_pci_rx_isr(struct rtw_dev *rtwdev) 1020 { 1021 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1022 struct napi_struct *napi = &rtwpci->napi; 1023 1024 napi_schedule(napi); 1025 } 1026 1027 static int rtw_pci_get_hw_rx_ring_nr(struct rtw_dev *rtwdev, 1028 struct rtw_pci *rtwpci) 1029 { 1030 struct rtw_pci_rx_ring *ring; 1031 int count = 0; 1032 u32 tmp, cur_wp; 1033 1034 ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 1035 tmp = rtw_read32(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ); 1036 cur_wp = u32_get_bits(tmp, TRX_BD_HW_IDX_MASK); 1037 if (cur_wp >= ring->r.wp) 1038 count = cur_wp - ring->r.wp; 1039 else 1040 count = ring->r.len - (ring->r.wp - cur_wp); 1041 1042 return count; 1043 } 1044 1045 static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 1046 u8 hw_queue, u32 limit) 1047 { 1048 const struct rtw_chip_info *chip = rtwdev->chip; 1049 struct napi_struct *napi = &rtwpci->napi; 1050 struct rtw_pci_rx_ring *ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 1051 struct rtw_rx_pkt_stat pkt_stat; 1052 struct ieee80211_rx_status rx_status; 1053 struct sk_buff *skb, *new; 1054 u32 cur_rp = ring->r.rp; 1055 u32 count, rx_done = 0; 1056 u32 pkt_offset; 1057 u32 pkt_desc_sz = chip->rx_pkt_desc_sz; 1058 u32 buf_desc_sz = chip->rx_buf_desc_sz; 1059 u32 new_len; 1060 u8 *rx_desc; 1061 dma_addr_t dma; 1062 1063 count = rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci); 1064 count = min(count, limit); 1065 1066 while (count--) { 1067 rtw_pci_dma_check(rtwdev, ring, cur_rp); 1068 skb = ring->buf[cur_rp]; 1069 dma = *((dma_addr_t *)skb->cb); 1070 dma_sync_single_for_cpu(rtwdev->dev, dma, RTK_PCI_RX_BUF_SIZE, 1071 DMA_FROM_DEVICE); 1072 rx_desc = skb->data; 1073 chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status); 1074 1075 /* offset from rx_desc to payload */ 1076 pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz + 1077 pkt_stat.shift; 1078 1079 /* allocate a new skb for this frame, 1080 * discard the frame if none available 1081 */ 1082 new_len = pkt_stat.pkt_len + pkt_offset; 1083 new = dev_alloc_skb(new_len); 1084 if (WARN_ONCE(!new, "rx routine starvation\n")) 1085 goto next_rp; 1086 1087 /* put the DMA data including rx_desc from phy to new skb */ 1088 skb_put_data(new, skb->data, new_len); 1089 1090 if (pkt_stat.is_c2h) { 1091 rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, new); 1092 } else { 1093 /* remove rx_desc */ 1094 skb_pull(new, pkt_offset); 1095 1096 rtw_rx_stats(rtwdev, pkt_stat.vif, new); 1097 memcpy(new->cb, &rx_status, sizeof(rx_status)); 1098 ieee80211_rx_napi(rtwdev->hw, NULL, new, napi); 1099 rx_done++; 1100 } 1101 1102 next_rp: 1103 /* new skb delivered to mac80211, re-enable original skb DMA */ 1104 rtw_pci_sync_rx_desc_device(rtwdev, dma, ring, cur_rp, 1105 buf_desc_sz); 1106 1107 /* host read next element in ring */ 1108 if (++cur_rp >= ring->r.len) 1109 cur_rp = 0; 1110 } 1111 1112 ring->r.rp = cur_rp; 1113 /* 'rp', the last position we have read, is seen as previous posistion 1114 * of 'wp' that is used to calculate 'count' next time. 1115 */ 1116 ring->r.wp = cur_rp; 1117 rtw_write16(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ, ring->r.rp); 1118 1119 return rx_done; 1120 } 1121 1122 static void rtw_pci_irq_recognized(struct rtw_dev *rtwdev, 1123 struct rtw_pci *rtwpci, u32 *irq_status) 1124 { 1125 unsigned long flags; 1126 1127 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 1128 1129 irq_status[0] = rtw_read32(rtwdev, RTK_PCI_HISR0); 1130 irq_status[1] = rtw_read32(rtwdev, RTK_PCI_HISR1); 1131 if (rtw_chip_wcpu_11ac(rtwdev)) 1132 irq_status[3] = rtw_read32(rtwdev, RTK_PCI_HISR3); 1133 else 1134 irq_status[3] = 0; 1135 irq_status[0] &= rtwpci->irq_mask[0]; 1136 irq_status[1] &= rtwpci->irq_mask[1]; 1137 irq_status[3] &= rtwpci->irq_mask[3]; 1138 rtw_write32(rtwdev, RTK_PCI_HISR0, irq_status[0]); 1139 rtw_write32(rtwdev, RTK_PCI_HISR1, irq_status[1]); 1140 if (rtw_chip_wcpu_11ac(rtwdev)) 1141 rtw_write32(rtwdev, RTK_PCI_HISR3, irq_status[3]); 1142 1143 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 1144 } 1145 1146 static irqreturn_t rtw_pci_interrupt_handler(int irq, void *dev) 1147 { 1148 struct rtw_dev *rtwdev = dev; 1149 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1150 1151 /* disable RTW PCI interrupt to avoid more interrupts before the end of 1152 * thread function 1153 * 1154 * disable HIMR here to also avoid new HISR flag being raised before 1155 * the HISRs have been Write-1-cleared for MSI. If not all of the HISRs 1156 * are cleared, the edge-triggered interrupt will not be generated when 1157 * a new HISR flag is set. 1158 */ 1159 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1160 1161 return IRQ_WAKE_THREAD; 1162 } 1163 1164 static irqreturn_t rtw_pci_interrupt_threadfn(int irq, void *dev) 1165 { 1166 struct rtw_dev *rtwdev = dev; 1167 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1168 u32 irq_status[4]; 1169 bool rx = false; 1170 1171 spin_lock_bh(&rtwpci->irq_lock); 1172 rtw_pci_irq_recognized(rtwdev, rtwpci, irq_status); 1173 1174 if (irq_status[0] & IMR_MGNTDOK) 1175 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_MGMT); 1176 if (irq_status[0] & IMR_HIGHDOK) 1177 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_HI0); 1178 if (irq_status[0] & IMR_BEDOK) 1179 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BE); 1180 if (irq_status[0] & IMR_BKDOK) 1181 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BK); 1182 if (irq_status[0] & IMR_VODOK) 1183 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VO); 1184 if (irq_status[0] & IMR_VIDOK) 1185 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VI); 1186 if (irq_status[3] & IMR_H2CDOK) 1187 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_H2C); 1188 if (irq_status[0] & IMR_ROK) { 1189 rtw_pci_rx_isr(rtwdev); 1190 rx = true; 1191 } 1192 if (unlikely(irq_status[0] & IMR_C2HCMD)) 1193 rtw_fw_c2h_cmd_isr(rtwdev); 1194 1195 /* all of the jobs for this interrupt have been done */ 1196 if (rtwpci->running) 1197 rtw_pci_enable_interrupt(rtwdev, rtwpci, rx); 1198 spin_unlock_bh(&rtwpci->irq_lock); 1199 1200 return IRQ_HANDLED; 1201 } 1202 1203 static int rtw_pci_io_mapping(struct rtw_dev *rtwdev, 1204 struct pci_dev *pdev) 1205 { 1206 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1207 unsigned long len; 1208 u8 bar_id = 2; 1209 int ret; 1210 1211 ret = pci_request_regions(pdev, KBUILD_MODNAME); 1212 if (ret) { 1213 rtw_err(rtwdev, "failed to request pci regions\n"); 1214 return ret; 1215 } 1216 1217 len = pci_resource_len(pdev, bar_id); 1218 rtwpci->mmap = pci_iomap(pdev, bar_id, len); 1219 if (!rtwpci->mmap) { 1220 pci_release_regions(pdev); 1221 rtw_err(rtwdev, "failed to map pci memory\n"); 1222 return -ENOMEM; 1223 } 1224 1225 return 0; 1226 } 1227 1228 static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev, 1229 struct pci_dev *pdev) 1230 { 1231 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1232 1233 if (rtwpci->mmap) { 1234 pci_iounmap(pdev, rtwpci->mmap); 1235 pci_release_regions(pdev); 1236 } 1237 } 1238 1239 static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data) 1240 { 1241 u16 write_addr; 1242 u16 remainder = addr & ~(BITS_DBI_WREN | BITS_DBI_ADDR_MASK); 1243 u8 flag; 1244 u8 cnt; 1245 1246 write_addr = addr & BITS_DBI_ADDR_MASK; 1247 write_addr |= u16_encode_bits(BIT(remainder), BITS_DBI_WREN); 1248 rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data); 1249 rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr); 1250 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_WFLAG >> 16); 1251 1252 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1253 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1254 if (flag == 0) 1255 return; 1256 1257 udelay(10); 1258 } 1259 1260 WARN(flag, "failed to write to DBI register, addr=0x%04x\n", addr); 1261 } 1262 1263 static int rtw_dbi_read8(struct rtw_dev *rtwdev, u16 addr, u8 *value) 1264 { 1265 u16 read_addr = addr & BITS_DBI_ADDR_MASK; 1266 u8 flag; 1267 u8 cnt; 1268 1269 rtw_write16(rtwdev, REG_DBI_FLAG_V1, read_addr); 1270 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_RFLAG >> 16); 1271 1272 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1273 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1274 if (flag == 0) { 1275 read_addr = REG_DBI_RDATA_V1 + (addr & 3); 1276 *value = rtw_read8(rtwdev, read_addr); 1277 return 0; 1278 } 1279 1280 udelay(10); 1281 } 1282 1283 WARN(1, "failed to read DBI register, addr=0x%04x\n", addr); 1284 return -EIO; 1285 } 1286 1287 static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1) 1288 { 1289 u8 page; 1290 u8 wflag; 1291 u8 cnt; 1292 1293 rtw_write16(rtwdev, REG_MDIO_V1, data); 1294 1295 page = addr < RTW_PCI_MDIO_PG_SZ ? 0 : 1; 1296 page += g1 ? RTW_PCI_MDIO_PG_OFFS_G1 : RTW_PCI_MDIO_PG_OFFS_G2; 1297 rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & BITS_MDIO_ADDR_MASK); 1298 rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page); 1299 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1); 1300 1301 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1302 wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, 1303 BIT_MDIO_WFLAG_V1); 1304 if (wflag == 0) 1305 return; 1306 1307 udelay(10); 1308 } 1309 1310 WARN(wflag, "failed to write to MDIO register, addr=0x%02x\n", addr); 1311 } 1312 1313 static void rtw_pci_clkreq_set(struct rtw_dev *rtwdev, bool enable) 1314 { 1315 u8 value; 1316 int ret; 1317 1318 if (rtw_pci_disable_aspm) 1319 return; 1320 1321 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1322 if (ret) { 1323 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret); 1324 return; 1325 } 1326 1327 if (enable) 1328 value |= BIT_CLKREQ_SW_EN; 1329 else 1330 value &= ~BIT_CLKREQ_SW_EN; 1331 1332 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1333 } 1334 1335 static void rtw_pci_clkreq_pad_low(struct rtw_dev *rtwdev, bool enable) 1336 { 1337 u8 value; 1338 int ret; 1339 1340 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1341 if (ret) { 1342 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret); 1343 return; 1344 } 1345 1346 if (enable) 1347 value &= ~BIT_CLKREQ_N_PAD; 1348 else 1349 value |= BIT_CLKREQ_N_PAD; 1350 1351 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1352 } 1353 1354 static void rtw_pci_aspm_set(struct rtw_dev *rtwdev, bool enable) 1355 { 1356 u8 value; 1357 int ret; 1358 1359 if (rtw_pci_disable_aspm) 1360 return; 1361 1362 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1363 if (ret) { 1364 rtw_err(rtwdev, "failed to read ASPM, ret=%d", ret); 1365 return; 1366 } 1367 1368 if (enable) 1369 value |= BIT_L1_SW_EN; 1370 else 1371 value &= ~BIT_L1_SW_EN; 1372 1373 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1374 } 1375 1376 static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter) 1377 { 1378 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1379 1380 /* Like CLKREQ, ASPM is also implemented by two HW modules, and can 1381 * only be enabled when host supports it. 1382 * 1383 * And ASPM mechanism should be enabled when driver/firmware enters 1384 * power save mode, without having heavy traffic. Because we've 1385 * experienced some inter-operability issues that the link tends 1386 * to enter L1 state on the fly even when driver is having high 1387 * throughput. This is probably because the ASPM behavior slightly 1388 * varies from different SOC. 1389 */ 1390 if (!(rtwpci->link_ctrl & PCI_EXP_LNKCTL_ASPM_L1)) 1391 return; 1392 1393 if ((enter && atomic_dec_if_positive(&rtwpci->link_usage) == 0) || 1394 (!enter && atomic_inc_return(&rtwpci->link_usage) == 1)) 1395 rtw_pci_aspm_set(rtwdev, enter); 1396 } 1397 1398 static void rtw_pci_link_cfg(struct rtw_dev *rtwdev) 1399 { 1400 const struct rtw_chip_info *chip = rtwdev->chip; 1401 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1402 struct pci_dev *pdev = rtwpci->pdev; 1403 u16 link_ctrl; 1404 int ret; 1405 1406 /* RTL8822CE has enabled REFCLK auto calibration, it does not need 1407 * to add clock delay to cover the REFCLK timing gap. 1408 */ 1409 if (chip->id == RTW_CHIP_TYPE_8822C) 1410 rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0); 1411 1412 /* Though there is standard PCIE configuration space to set the 1413 * link control register, but by Realtek's design, driver should 1414 * check if host supports CLKREQ/ASPM to enable the HW module. 1415 * 1416 * These functions are implemented by two HW modules associated, 1417 * one is responsible to access PCIE configuration space to 1418 * follow the host settings, and another is in charge of doing 1419 * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes 1420 * the host does not support it, and due to some reasons or wrong 1421 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device 1422 * loss if HW misbehaves on the link. 1423 * 1424 * Hence it's designed that driver should first check the PCIE 1425 * configuration space is sync'ed and enabled, then driver can turn 1426 * on the other module that is actually working on the mechanism. 1427 */ 1428 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); 1429 if (ret) { 1430 rtw_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); 1431 return; 1432 } 1433 1434 if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) 1435 rtw_pci_clkreq_set(rtwdev, true); 1436 1437 rtwpci->link_ctrl = link_ctrl; 1438 } 1439 1440 static void rtw_pci_interface_cfg(struct rtw_dev *rtwdev) 1441 { 1442 const struct rtw_chip_info *chip = rtwdev->chip; 1443 1444 switch (chip->id) { 1445 case RTW_CHIP_TYPE_8822C: 1446 if (rtwdev->hal.cut_version >= RTW_CHIP_VER_CUT_D) 1447 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG, 1448 BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK, 1); 1449 break; 1450 default: 1451 break; 1452 } 1453 } 1454 1455 static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev) 1456 { 1457 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1458 const struct rtw_chip_info *chip = rtwdev->chip; 1459 struct pci_dev *pdev = rtwpci->pdev; 1460 const struct rtw_intf_phy_para *para; 1461 u16 cut; 1462 u16 value; 1463 u16 offset; 1464 int i; 1465 int ret; 1466 1467 cut = BIT(0) << rtwdev->hal.cut_version; 1468 1469 for (i = 0; i < chip->intf_table->n_gen1_para; i++) { 1470 para = &chip->intf_table->gen1_para[i]; 1471 if (!(para->cut_mask & cut)) 1472 continue; 1473 if (para->offset == 0xffff) 1474 break; 1475 offset = para->offset; 1476 value = para->value; 1477 if (para->ip_sel == RTW_IP_SEL_PHY) 1478 rtw_mdio_write(rtwdev, offset, value, true); 1479 else 1480 rtw_dbi_write8(rtwdev, offset, value); 1481 } 1482 1483 for (i = 0; i < chip->intf_table->n_gen2_para; i++) { 1484 para = &chip->intf_table->gen2_para[i]; 1485 if (!(para->cut_mask & cut)) 1486 continue; 1487 if (para->offset == 0xffff) 1488 break; 1489 offset = para->offset; 1490 value = para->value; 1491 if (para->ip_sel == RTW_IP_SEL_PHY) 1492 rtw_mdio_write(rtwdev, offset, value, false); 1493 else 1494 rtw_dbi_write8(rtwdev, offset, value); 1495 } 1496 1497 rtw_pci_link_cfg(rtwdev); 1498 1499 /* Disable 8821ce completion timeout by default */ 1500 if (chip->id == RTW_CHIP_TYPE_8821C) { 1501 ret = pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 1502 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 1503 if (ret) 1504 rtw_err(rtwdev, "failed to set PCI cap, ret = %d\n", 1505 ret); 1506 } 1507 } 1508 1509 static int __maybe_unused rtw_pci_suspend(struct device *dev) 1510 { 1511 struct ieee80211_hw *hw = dev_get_drvdata(dev); 1512 struct rtw_dev *rtwdev = hw->priv; 1513 const struct rtw_chip_info *chip = rtwdev->chip; 1514 struct rtw_efuse *efuse = &rtwdev->efuse; 1515 1516 if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6) 1517 rtw_pci_clkreq_pad_low(rtwdev, true); 1518 return 0; 1519 } 1520 1521 static int __maybe_unused rtw_pci_resume(struct device *dev) 1522 { 1523 struct ieee80211_hw *hw = dev_get_drvdata(dev); 1524 struct rtw_dev *rtwdev = hw->priv; 1525 const struct rtw_chip_info *chip = rtwdev->chip; 1526 struct rtw_efuse *efuse = &rtwdev->efuse; 1527 1528 if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6) 1529 rtw_pci_clkreq_pad_low(rtwdev, false); 1530 return 0; 1531 } 1532 1533 SIMPLE_DEV_PM_OPS(rtw_pm_ops, rtw_pci_suspend, rtw_pci_resume); 1534 EXPORT_SYMBOL(rtw_pm_ops); 1535 1536 static int rtw_pci_claim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1537 { 1538 int ret; 1539 1540 ret = pci_enable_device(pdev); 1541 if (ret) { 1542 rtw_err(rtwdev, "failed to enable pci device\n"); 1543 return ret; 1544 } 1545 1546 pci_set_master(pdev); 1547 pci_set_drvdata(pdev, rtwdev->hw); 1548 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); 1549 1550 return 0; 1551 } 1552 1553 static void rtw_pci_declaim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1554 { 1555 pci_clear_master(pdev); 1556 pci_disable_device(pdev); 1557 } 1558 1559 static int rtw_pci_setup_resource(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1560 { 1561 struct rtw_pci *rtwpci; 1562 int ret; 1563 1564 rtwpci = (struct rtw_pci *)rtwdev->priv; 1565 rtwpci->pdev = pdev; 1566 1567 /* after this driver can access to hw registers */ 1568 ret = rtw_pci_io_mapping(rtwdev, pdev); 1569 if (ret) { 1570 rtw_err(rtwdev, "failed to request pci io region\n"); 1571 goto err_out; 1572 } 1573 1574 ret = rtw_pci_init(rtwdev); 1575 if (ret) { 1576 rtw_err(rtwdev, "failed to allocate pci resources\n"); 1577 goto err_io_unmap; 1578 } 1579 1580 return 0; 1581 1582 err_io_unmap: 1583 rtw_pci_io_unmapping(rtwdev, pdev); 1584 1585 err_out: 1586 return ret; 1587 } 1588 1589 static void rtw_pci_destroy(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1590 { 1591 rtw_pci_deinit(rtwdev); 1592 rtw_pci_io_unmapping(rtwdev, pdev); 1593 } 1594 1595 static struct rtw_hci_ops rtw_pci_ops = { 1596 .tx_write = rtw_pci_tx_write, 1597 .tx_kick_off = rtw_pci_tx_kick_off, 1598 .flush_queues = rtw_pci_flush_queues, 1599 .setup = rtw_pci_setup, 1600 .start = rtw_pci_start, 1601 .stop = rtw_pci_stop, 1602 .deep_ps = rtw_pci_deep_ps, 1603 .link_ps = rtw_pci_link_ps, 1604 .interface_cfg = rtw_pci_interface_cfg, 1605 1606 .read8 = rtw_pci_read8, 1607 .read16 = rtw_pci_read16, 1608 .read32 = rtw_pci_read32, 1609 .write8 = rtw_pci_write8, 1610 .write16 = rtw_pci_write16, 1611 .write32 = rtw_pci_write32, 1612 .write_data_rsvd_page = rtw_pci_write_data_rsvd_page, 1613 .write_data_h2c = rtw_pci_write_data_h2c, 1614 }; 1615 1616 static int rtw_pci_request_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1617 { 1618 unsigned int flags = PCI_IRQ_LEGACY; 1619 int ret; 1620 1621 if (!rtw_disable_msi) 1622 flags |= PCI_IRQ_MSI; 1623 1624 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); 1625 if (ret < 0) { 1626 rtw_err(rtwdev, "failed to alloc PCI irq vectors\n"); 1627 return ret; 1628 } 1629 1630 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, 1631 rtw_pci_interrupt_handler, 1632 rtw_pci_interrupt_threadfn, 1633 IRQF_SHARED, KBUILD_MODNAME, rtwdev); 1634 if (ret) { 1635 rtw_err(rtwdev, "failed to request irq %d\n", ret); 1636 pci_free_irq_vectors(pdev); 1637 } 1638 1639 return ret; 1640 } 1641 1642 static void rtw_pci_free_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1643 { 1644 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); 1645 pci_free_irq_vectors(pdev); 1646 } 1647 1648 static int rtw_pci_napi_poll(struct napi_struct *napi, int budget) 1649 { 1650 struct rtw_pci *rtwpci = container_of(napi, struct rtw_pci, napi); 1651 struct rtw_dev *rtwdev = container_of((void *)rtwpci, struct rtw_dev, 1652 priv); 1653 int work_done = 0; 1654 1655 if (rtwpci->rx_no_aspm) 1656 rtw_pci_link_ps(rtwdev, false); 1657 1658 while (work_done < budget) { 1659 u32 work_done_once; 1660 1661 work_done_once = rtw_pci_rx_napi(rtwdev, rtwpci, RTW_RX_QUEUE_MPDU, 1662 budget - work_done); 1663 if (work_done_once == 0) 1664 break; 1665 work_done += work_done_once; 1666 } 1667 if (work_done < budget) { 1668 napi_complete_done(napi, work_done); 1669 spin_lock_bh(&rtwpci->irq_lock); 1670 if (rtwpci->running) 1671 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 1672 spin_unlock_bh(&rtwpci->irq_lock); 1673 /* When ISR happens during polling and before napi_complete 1674 * while no further data is received. Data on the dma_ring will 1675 * not be processed immediately. Check whether dma ring is 1676 * empty and perform napi_schedule accordingly. 1677 */ 1678 if (rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci)) 1679 napi_schedule(napi); 1680 } 1681 if (rtwpci->rx_no_aspm) 1682 rtw_pci_link_ps(rtwdev, true); 1683 1684 return work_done; 1685 } 1686 1687 static void rtw_pci_napi_init(struct rtw_dev *rtwdev) 1688 { 1689 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1690 1691 init_dummy_netdev(&rtwpci->netdev); 1692 netif_napi_add(&rtwpci->netdev, &rtwpci->napi, rtw_pci_napi_poll); 1693 } 1694 1695 static void rtw_pci_napi_deinit(struct rtw_dev *rtwdev) 1696 { 1697 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1698 1699 rtw_pci_napi_stop(rtwdev); 1700 netif_napi_del(&rtwpci->napi); 1701 } 1702 1703 int rtw_pci_probe(struct pci_dev *pdev, 1704 const struct pci_device_id *id) 1705 { 1706 struct pci_dev *bridge = pci_upstream_bridge(pdev); 1707 struct ieee80211_hw *hw; 1708 struct rtw_dev *rtwdev; 1709 struct rtw_pci *rtwpci; 1710 int drv_data_size; 1711 int ret; 1712 1713 drv_data_size = sizeof(struct rtw_dev) + sizeof(struct rtw_pci); 1714 hw = ieee80211_alloc_hw(drv_data_size, &rtw_ops); 1715 if (!hw) { 1716 dev_err(&pdev->dev, "failed to allocate hw\n"); 1717 return -ENOMEM; 1718 } 1719 1720 rtwdev = hw->priv; 1721 rtwdev->hw = hw; 1722 rtwdev->dev = &pdev->dev; 1723 rtwdev->chip = (struct rtw_chip_info *)id->driver_data; 1724 rtwdev->hci.ops = &rtw_pci_ops; 1725 rtwdev->hci.type = RTW_HCI_TYPE_PCIE; 1726 1727 rtwpci = (struct rtw_pci *)rtwdev->priv; 1728 atomic_set(&rtwpci->link_usage, 1); 1729 1730 ret = rtw_core_init(rtwdev); 1731 if (ret) 1732 goto err_release_hw; 1733 1734 rtw_dbg(rtwdev, RTW_DBG_PCI, 1735 "rtw88 pci probe: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 1736 pdev->vendor, pdev->device, pdev->revision); 1737 1738 ret = rtw_pci_claim(rtwdev, pdev); 1739 if (ret) { 1740 rtw_err(rtwdev, "failed to claim pci device\n"); 1741 goto err_deinit_core; 1742 } 1743 1744 ret = rtw_pci_setup_resource(rtwdev, pdev); 1745 if (ret) { 1746 rtw_err(rtwdev, "failed to setup pci resources\n"); 1747 goto err_pci_declaim; 1748 } 1749 1750 rtw_pci_napi_init(rtwdev); 1751 1752 ret = rtw_chip_info_setup(rtwdev); 1753 if (ret) { 1754 rtw_err(rtwdev, "failed to setup chip information\n"); 1755 goto err_destroy_pci; 1756 } 1757 1758 /* Disable PCIe ASPM L1 while doing NAPI poll for 8821CE */ 1759 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821C && bridge->vendor == PCI_VENDOR_ID_INTEL) 1760 rtwpci->rx_no_aspm = true; 1761 1762 rtw_pci_phy_cfg(rtwdev); 1763 1764 ret = rtw_register_hw(rtwdev, hw); 1765 if (ret) { 1766 rtw_err(rtwdev, "failed to register hw\n"); 1767 goto err_destroy_pci; 1768 } 1769 1770 ret = rtw_pci_request_irq(rtwdev, pdev); 1771 if (ret) { 1772 ieee80211_unregister_hw(hw); 1773 goto err_destroy_pci; 1774 } 1775 1776 return 0; 1777 1778 err_destroy_pci: 1779 rtw_pci_napi_deinit(rtwdev); 1780 rtw_pci_destroy(rtwdev, pdev); 1781 1782 err_pci_declaim: 1783 rtw_pci_declaim(rtwdev, pdev); 1784 1785 err_deinit_core: 1786 rtw_core_deinit(rtwdev); 1787 1788 err_release_hw: 1789 ieee80211_free_hw(hw); 1790 1791 return ret; 1792 } 1793 EXPORT_SYMBOL(rtw_pci_probe); 1794 1795 void rtw_pci_remove(struct pci_dev *pdev) 1796 { 1797 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1798 struct rtw_dev *rtwdev; 1799 struct rtw_pci *rtwpci; 1800 1801 if (!hw) 1802 return; 1803 1804 rtwdev = hw->priv; 1805 rtwpci = (struct rtw_pci *)rtwdev->priv; 1806 1807 rtw_unregister_hw(rtwdev, hw); 1808 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1809 rtw_pci_napi_deinit(rtwdev); 1810 rtw_pci_destroy(rtwdev, pdev); 1811 rtw_pci_declaim(rtwdev, pdev); 1812 rtw_pci_free_irq(rtwdev, pdev); 1813 rtw_core_deinit(rtwdev); 1814 ieee80211_free_hw(hw); 1815 } 1816 EXPORT_SYMBOL(rtw_pci_remove); 1817 1818 void rtw_pci_shutdown(struct pci_dev *pdev) 1819 { 1820 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1821 struct rtw_dev *rtwdev; 1822 const struct rtw_chip_info *chip; 1823 1824 if (!hw) 1825 return; 1826 1827 rtwdev = hw->priv; 1828 chip = rtwdev->chip; 1829 1830 if (chip->ops->shutdown) 1831 chip->ops->shutdown(rtwdev); 1832 1833 pci_set_power_state(pdev, PCI_D3hot); 1834 } 1835 EXPORT_SYMBOL(rtw_pci_shutdown); 1836 1837 MODULE_AUTHOR("Realtek Corporation"); 1838 MODULE_DESCRIPTION("Realtek 802.11ac wireless PCI driver"); 1839 MODULE_LICENSE("Dual BSD/GPL"); 1840